AS91L1003E10F100IG
更新时间:2024-09-18 02:12:59
品牌:ETC
描述:The AS91L1006BU is a one to 6-port JTAG gateway
AS91L1003E10F100IG 概述
The AS91L1006BU is a one to 6-port JTAG gateway 该AS91L1006BU是一到6端口的JTAG网关
AS91L1003E10F100IG 数据手册
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PDF下载July 2004
AS91L1006BU
6-Port JTAG Gateway
Description
The AS91L1006BU is a one to 6-port
control. Partitioning the IEEE1149.1 chains on the
JTAG gateway. It partitions a single JTAG chain
into six separate chains. These separate chains
can be optionally configured to operate as a single
chain.
PCB has several benefits which include easier
fault diagnostics capabilities as a fault on one of
the IEEE1149.1 Local Scan Ports (LSPs) does
not render the PCB untestable, faster flash
programming on the PCBs, and removal of
IEEE1149.1 signal loading issues.
The AS91L1006BU device is used to
provide enhanced capabilities to the standard
IEEE1149.1. It enables the IEEE1149.1 interface
to be used in a true Multi-Drop environment without
any additional signals. This Multi-Drop capability
enables the standard IEEE1149.1 interface to be
used not just for stand alone PCB (Printed Circuit
Board) testing, but also for complete system
testing including all PCBs within a system back
plane environment.
All of the protocols required for
addressing the AS91L1006BU device via the
Multi-Drop capability and the protocols for
configuring which of the six IEEE1149.1 LSPs on
the AS91L1006BU are to be used, is handled via
3rd party ATPG tools from vendors like Asset-
Intertech and JTAG Technologies. In a Multi-Drop
environment it is also possible to perform
interconnect tests between multiple PCBs within a
system thus extending the interconnect tests to
the back plane itself.
The AS91L1006BU provides the capability
of partitioning the PCB, into multiple smaller
IEEE1149.1 scan chains totally under software
Key Features
ꢀDevice Multi-Drop addressable via the IEEE ꢀProvides the ability to initiate Self-Test on a
1149.1 protocol
remote PCB via a standard IEEE 1149.1
command
ꢀSupport for 6 local scan chains addressable via
the IEEE 1149.1 interface
ꢀSupport for JTAG Technologies AutoWR™
feature
ꢀSupport for Pass-Through™
ꢀPinout and feature set compatible (complete
second source) with the Firecron JTS06BU
device
ꢀSupport for the IEEE 1149.1 USERCODE
instruction
ꢀSupport for Status instruction enabling non-
intrusive monitoring of the system card
ꢀAvailable in a 100-pin LQFP or a 100-pin
FPBGA lead free package
ꢀLocal Scan Port (LSP) enable signal provides the
ability to use non IEEE 1149.1 compliant devices
that require JTAG enable signal
Device Block Diagram
P a s s T h ro u g h E n a b le
P rim a ry 1 1 4 9 .1
J T A G In te rfa c e
L S P 1
L S P 2
S ta tu s D a ta
1 1 4 9 .1 T A P C o n tro lle r
U s e rc o d e
a n d
P a s s T h ro u g h
L S P 3
D a ta
L o g ic
& L o c a l
B o u n d a ry R e g is te r S e le c tio n L o g ic
S c a n P o rt
C o n n e c tio n /
C o n fig
L S P 4
L S P 5
L S P 6
lo g ic
D e v ic e
a d d re s s
D e v ic e
S e le c tio n
L o g ic
L o c a l S c a n P o rt
P a rk /U n -p a rk
S y n c L o g ic
Figure 1 - AS91L1006BU Device Block Diagram
Alliance Semiconductor
2575 Augustine Drive • Santa Clara, CA 95054 • T: 408-855-4900 • F: 408-855-4999 • www.alsc.com
July 2004
AS91L1006BU
AS91L1006BU Gateway Functional Description
The basic structure of the AS91L1006BU
device is shown in Figure-1. The core of the device
is the 16-state IEEE1149.1 TAP controller state
machine. All accesses to the internal registers of
the AS91L1006BU device are controlled via this
state machine during normal operation as per the
IEEE1149.1 standard. The address selection logic
enables the AS91L1006BU to operate in a Multi-
Drop environment within system backplane.
device also supports a Pass-Through mode which
enables the primary IEEE1149.1 signals to be
routed to any of the LSPs. This signal routing is
selectable via I/O pins on the AS91L1006BU
device.
Figure-2 shows the device selection state
machine. The AS91L1006BU will perform an
address compare on the slot address presented
at its I/O and the value scanned in via the
IEEE1149.1. If the value matches then the
AS91L1006BU becomes selected and is ready for
normal access via IEEE1149.1 commands. If the
address does not match then the device will
proceed to the unselected mode, where it will
remain until the AS91L1006BU is issued a
GOTOWAIT instruction or a reset occurs via
TRST or the LSP_RESET pin.
The address selection logic compares the
scanned address to the slot address value
presented on the I/O of the AS91L1006BU device.
The LSP park/unpark logic provides control
through instructions scanned in under the
IEEE1149.1 protocol, to select, which LSP will be
placed into the active, scan chain. The pass-
through and LSP connection logic selects the
signal paths for the LSP IEEE1149.1 signals. The
Selected Single
Device
Device
Unselected
Parked-RTI
Parked-
Parked-TLR
UnParked
Wait for
Selection
PauseDR
Parked-
PauseIR
Select Group
of Devices
Select All
Devices
Figure 2 - AS91L1006BU
Figure 3 - The LSP
Selection Logic State machine
Park/Unpark State Machine
The LSP Park/Unpark State Machine controls the insertion of the LSPs into the current active scan
chain. The ability to park the LSP in certain IEEE1149.1 states, enable the AS91L1006BU to perform
several functions including backplane interconnect testing and IC BIST.
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AS91L1006BU
AS91L1006BU Detailed Mode of Operation
Addressing the AS91L1006BU device
The AS91L1006BU device should be in
the Wait-for-Selection mode, which can be
entered into by issuing an asynchronous reset
(through the deassertion of TRST) or by issuing a
synchronous reset (through the assertion of TMS
for five cycles of TCK). After the device has been
After a Test-Logic-Reset or power-up, the
AS91L1006BU device will be in its Wait-for-
Selection state with its TDO pin tri-stated, thus
avoiding contention in a Multi-Drop environment.
The AS91L1006BU device will respond to a
device-select sequence for a particular address
that is auto generated by third party test tools with
respect to the address that is pre-loaded on its
S(5..0). Once this sequence has been completed,
the AS91L1006BU device will respond to normal
IEEE 1149.1 instructions. Note that addresses 60-
63 have been reserved and the AS91L1006BU
device will not respond if the user selects these
addresses.
selected, it can be issued
instruction.
a
GOTOWAIT
The internal IEEE1149.1 state machine of
the AS91L1006BU device is taken to the Shift-IR
phase and the required Device-ID is shifted into
the Instruction register. As the IEEE1149.1 state
machine passes through the Update-IR phase,
the address is matched to the value on the S(5-0)
pins on the AS91L1006BU device; if the values
match, then the AS91L1006BU device is selected
and is ready to receive any normal IEEE1149.1
command.
S(5-0) value
IR (7 – 0) value
< 3A hex or 60
decimal
XXVVVVVV
Table 1 - AS91L1006BU
Device Selection Table
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AS91L1006BU
Table 2 - AS91L1006BU Multi Cast Group
Selection Table
Table 3 - AS91L1006BU Device
Register Description
Selection Binary
Mode Address
Single XX000000 to Single AS91L1006BU
Function
Register
Name
Instruction
Register
Description
AS91L1006BU device
addressing and instruction-
decode
IEEE Std. 1149.1 required
register
Address XX111010
Mode
selected the TDO of
the device will be
active
Broad
XX111011
All accessible
Boundary-
Scan
Register
Bypass
Register
IEEE Std. 1149.1 required
register
Cast Mode
AS91L1006BU
devices are selected
for operation. TDO on
all devices will be in
HighZ
IEEE Std. 1149.1 required
register
Device
Identification register
Register
User Code IEEE Std. 1149.1 optional
Register
IEEE Std. 1149.1 optional
Multi-Cast XX111100
Group 0
Access all
AS91L1006BU
devices that have
been placed in GRP0
by their MCGR
contents
register
Status
Register
AS91L1006BU device non
intrusive 8-bit register pre load
able from the I/O pins
Multi-Cast XX111101
Group 1
Access all
AS91L1006BU
devices that have
been placed in GRP1
by their MCGR
contents
Self Test
Register
AS91L1006BU device specific
single bit register for initiating
self testing on a PCB
Multi-Cast XX111110
Group 2
Access all
Mode
Register
AS91L1006BU device local-port
configuration and control bits
AS91L1006BU
devices that have
been placed in GRP2
by their MCGR
contents
Auto Write
Register
AS91L1006BU device Auto
Write feature enable register
Multi-Cast XX111111
Group 3
Access all
LSP Async AS91L1006BU device Async
AS91L1006BU
devices that have
been placed in GRP3
by their MCGR
contents
Reset
reset register for the LSPs
Register
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AS91L1006BU
Instructions
Hex Op- Binary Op- Data Register
Code
Code
BYPASS
FF
11111111 Bypass Register
EXTEST
00
81
AA
E7
C5
84
C6
C3
8E
03
88
97
00000000 Boundary-Scan Register
10000001 Boundary-Scan Register
10101010 Device Identification Register
11100111 Device Identification Register
11000101 Device Identification Register
10000100 Device Identification Register
11000110 Device Identification Register
11000011 Device Identification Register
10001110 Mode Register
SAMPLE/PRELOAD
IDCODE
UNPARK
PARKTLR
PARKRTI
PARKPAUSE
GOTOWAIT*
MODESELECT
MCGRSELECT
SOFTRESET
USERCODE
00000011 Multi-Cast Group Register.
10001000 Device Identification Register
10010111 User Programmable 32 Bit Identification Register
10011000 Auto Write Feature Enable Register
AUTOWR
98
99
STEST_PCB
10011001 Single bit low pulse, used to initiate function on PCB
(SELF_TEST pin)
STATUS_BYTE
9A
9B
10011010 User programmable status byte (USER_STATUS_DATA
pins)
LSP_ASYNC_RESET
10011011 Toggles LSP TRST while maintaining the AS91L1006BU
in the selected state.
Other Undefined
TBD
TBD
Device Identification Register
Table 4 - AS91L1006BU Device Instruction Register OpCodes
ꢁNote: All instructions act on a single selected AS91L1006BU device only.
* This instruction causes the AS91L1006BU to become unselected and revert to the Wait-for-
Selection state.
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AS91L1006BU
AS91L1006BU device Register descriptions
Bypass Register
It is a mandatory single bit register that can
Multi-Cast Group Register
This 2-bit data register enables the host
be connected between PRIM_TDI and PRIM_TDO
of the AS91L1006BU device.
system to place the AS91L1006BU into one of
four distinct addressable groups.
MCGR Register Bits Binary Selection Address
MCGR GROUP
GRP0
[1..0]
00
01
10
11
XX111100
XX111101
XX111110
XX111111
GRP1
GRP2
GRP3
Table 5 - Multicast Group Register Mapping
ꢁNote: The MCGR is reset to 00 upon receiving TRST or the entering of the Test-Logic-Reset
state.
Bits 12 to 27 indicate the part number of the
device: “0000000000010000”
IDCODE Register
It is an optional 32-bit register that can be
Bits 28 to 31 indicate the revision of the device:
“0000”
connected between PRIM_TDI and PRIM_TDO of
the AS91L1006BU device. The contents of the
IDCODE register will be loaded with the following
data when the AS91L1006BU enters Test-Logic-
Reset or passes through Capture-IR:
USERCODE Register
The USERCODE is an 8-bit register that can
be addressed via standard IEEE1149.1
commands, which are automatically generated by
third party test tools. AS91L1006BU returns all
zeroes if read from this registerUSERUSER and
does have the ability to write into this register.
"00000000000000001000001101101111"
Bits 0 to 11 indicate ALSC Jedec ID value of:
“001101101111”
ꢁ
* The AS91L1006BU is a complete second source and pin for pin replacement of the
Firecron JTS06BU device.
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AS91L1006BU
internal registers to be reset. In order to enable
SELF_TEST Register
The AS91L1006BU device supports a
async reset tests on LSPs, the test tool should
instruct the device to toggle the LSP reset pins
while maintaining the set up information in the
AS91L1006BU. When the instruction is loaded
into the AS91L1006BU instruction register, a
single bit data register is connected as the data
register which is always reset to logic zero when
the TAP state machine enters Capture-DR. This
will cause the LSP TRST pins to pulse low for one
TCK cycle, during the Update-DR phase.
single output pin that can be controlled via the
IEEE1149.1 interface. When the instruction is
loaded into the AS91L1006BU instruction register,
a single bit data register is connected which is
always reset to logic zero when the TAP state
machine enters Capture-DR. This will cause the
SELF_TEST pin to pulse low for one cycle of TCK,
during the Update-DR phase. This low going pulse
can be used to initiate self-tests on PCB’s in a rack
via the JTAG interface.
AUTOWR Register
This is a 6-bit register that controls the pass-
through of the JTAG Technologies AutoWR™
signal to any LSP. The register is reset to all
zeros when entering the Test-Logic-Reset state.
LSP_ASYNC_RST Register
The AS91L1006BU device supports async
reset tests on the devices connected to the LSPs.
The standard method of performing these tests by
utilizing the primary TRST pin cannot be used as it
will cause the AS91L1006BU to deselect and its
ꢁNote: The MCGR is reset to 00 upon receiving TRST or the entering of the
Test-Logic-Reset state
AutoWr
Register AutoWr
(Bit 2 –
Bit 0)
000
LSP 3
LSP 2
AutoWr
Signal
LSP 1
AutoWr
Signal
AutoWr
Register
(Bit 5 – Bit
3)
LSP 6
AutoWr
Signal
LSP 5
AutoWr
Signal
LSP 4
AutoWr
Signal
Signal
High Z
High Z
High Z
Active
High Z
High Z
Active
Active
High Z
Active
Active
High Z
Active
High Z
Active
000
High Z
High Z
High Z
Active
Active
Active
Active
High Z
High Z
Active
High Z
High Z
Active
Active
High Z
Active
Active
High Z
Active
High Z
Active
001
011
100
101
110
111
High Z
High Z
Active
Active
Active
Active
001
011
100
101
110
111
Table 6 - AUTOWR Register Mapping
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AS91L1006BU
If the LSP is not parked in a stable state,
MODE_SELECT Register
The Mode_Select register allows the LSP
of the AS91L1006BU to be connected in various
different configurations. A LSP is selected for
connection within the scan chain by the contents of
the Mode_Select register.
i.e.: Pause-DR, Pause-IR, Run-Test-Idle or Test-
Logic-Reset, it will be connected into the active
scan chain. If all LSPs are parked in a stable
state, then the AS91L1006BU will perform a
bypass of the 6-LSP chain section. In this way if
both sections are in the bypass mode then the
AS91L1006BU is performing a loopback of TDI-
>Register->TDO to the host device.
Mode_Select
LSP Configuration (If Port
Register (Bit 15
Unparked)
Mode_Select
LSP Configuration (If Port
Register (Bit 7 ->
Unparked)
-> Bit 8)
Bit 0)
XXX0X000
XXX0X001
XXX0X010
XXX0X011
TDI ->Register->LSP_Data
XXX0X000
XXX0X001
XXX0X010
XXX0X011
LSP_Data ->TDO
TDI ->Register->LSP1->PAD->
LSP_Data
LSP_Data ->LSP4->PAD-
>TDO
TDI ->Register->LSP2->PAD->
LSP_Data
LSP_Data ->LSP5->PAD-
>TDO
TDI ->Register->LSP1->PAD-
>LSP2->PAD-> LSP_Data
LSP_Data ->LSP4->PAD-
>LSP5->PAD->TDO
XXX0X100
XXX0X101
TDI ->Register->LSP3->PAD->
LSP_Data
XXX0X100
XXX0X101
LSP_Data ->LSP6->PAD-
>TDO
TDI ->Register->LSP1->PAD-
>LSP3->PAD-> LSP_Data
LSP_Data ->LSP4->PAD-
>LSP6->PAD->TDO
XXX0X110
XXX0X111
TDI ->Register->LSP2->PAD-
>LSP3->PAD-> LSP_Data
XXX0X110
XXX0X111
LSP_Data ->LSP5->PAD-
>LSP6->PAD->TDO
TDI ->Register->LSP1->PAD-
>LSP2->PAD->LSP3->PAD->
LSP_Data
LSP_Data ->LSP4->PAD-
>LSP5->PAD->LSP6->PAD-
>TDO
Table 7 - Mode Select Register Mapping
X = Don’t care
Register = AS91L1006BU device instruction register or any of the AS91L1006BU device test
data registers.
PAD = Insertion of a 1-bit register for data synchronization.
Upon entering Test-Logic-Reset, the register bits will be loaded with “0000000”.
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AS91L1006BU
Pass Through Support within the AS91L1006BU Device
The AS91L1006BU device supports a
Pass-Through mode where the primary or master
IEEE1149.1 JTAG signals can be routed to any
one of the LSPs. When this mode is activated, the
“Debug Enable” signal for that LSP will go active,
which can be used to place a processor such as
the MPC8260 into BDM (Background Debug
mode), if required. If no processors are present in
the LSP, the Pass-Through mode can be used to
assist in the generation of the test vectors or
memory tests for the devices that are linked into
the selected LSP. The pass-through feature has
the effect of simplifying the test vector generation
for the LSP, as it also has the effect of removing
the AS91L1006BU device from the test vector
generation process.
PASS_THRU_Enable PASS_THRU_SEL(2) PASS_THRU_SEL(1) PASS_THRU_SEL(0) Active LSP
High
Low
Low
Low
Low
Low
Low
X
X
X
Normal
Operation
Low
Low
Low
Low
High
High
Low
Low
High
High
Low
Low
Low
High
Low
High
Low
High
LSP1
LSP2
LSP3
LSP4
LSP5
LSP6
Table 8 - Pass through mode in AS91L1006BU
ꢁNote: When PASS_THRU_ENABLE is deasserted (logic “1”), then the LSPs are under
control of the AS91L1006BU device logic. When PASS_THRU_ENABLE is asserted (logic
“0”) and if an invalid combination is presented on the PASS_THRU_SEL lines, then all LSPs
are tri-stated.
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AS91L1006BU
Signal Description
PIN
PIN
PIN
TYPE
Stable state
after port/reset
PIN NAME
NUMBER NUMBER
LQFP
DESCRIPTION
FPBGA
LSP1_TCK
OUT
OUT
OUT
31
H4
IEEE1149.1 Test Clock on LSP 1
when PASS_THRU_ENABLE is
HIGH.
Buffered version
of signal present
on primary TCK
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 000.
This pin is tri-stated for all other
combinations.
IEEE1149.1 Test Mode Select on
LSP 1 when PASS_THRU_ENABLE
is HIGH.
LSP1_TMS
32
J4
Logic '1'
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 000.
This pin is tri-stated for all other
combinations.
IEEE1149.1 Test Data Out on LSP 1 Logic '1'
when PASS_THRU_ENABLE is
HIGH.
LSP1_TDO
35
H5
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 000.
This pin is tri-stated for all other
combinations.
LSP1_TDI
IN
33
29
K4
K3
IEEE1149.1 Test Data In on LSP 1
when PASS_THRU_ENABLE is
HIGH.
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 000.
IEEE1149.1 Test Reset on LSP 1
when PASS_THRU_ENABLE is
HIGH.
LSP1_TRST
OUT
Buffered version
of signal present
on primary TRST
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 000.
This pin is tri-stated for all other
combinations.
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AS91L1006BU
PIN
PIN
PIN
TYPE
Stable state
after port/reset
PIN NAME
NUMBER NUMBER
LQFP
DESCRIPTION
FPBGA
LSP1_AutoWR
OUT
30
J3
Flash, Memory Auto-Write on LSP 1 Logic '1'
when PASS_THRU_ENABLE is
HIGH.
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 000;
PRIM_AutoWR is routed to output.
This pin is tri-stated for all other
combinations.
LSP1_DE
OUT
OUT
28
41
J2
J6
Pass-Through Debug Enable Output Logic '1'
on Local Scan Port 1.
Active low output when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 000.
This pin is high for all other
combinations.
LSP2_TCK
IEEE1149.1 Test Clock on LSP 2
when PASS_THRU_ENABLE is
HIGH.
Buffered version
of signal present
on primary TCK
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 001.
This pin is tri-stated for all other
combinations.
LSP2_TMS
OUT
42
H6
IEEE1149.1 Test Mode Select on
LSP 2 when PASS_THRU_ENABLE
is HIGH.
Logic '1'
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 001.
This pin is tri-stated for all other
combinations.
LSP2_TDO
OUT
45
J7
IEEE1149.1 Test Data Out on LSP 2 Logic '1'
when PASS_THRU_ENABLE is
HIGH.
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 001.
This pin is tri-stated for all other
combinations.
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AS91L1006BU
PIN
PIN
PIN
TYPE
Stable state
after port/reset
PIN NAME
LSP2_TDI
NUMBER NUMBER
LQFP
DESCRIPTION
FPBGA
IN
44
K7
IEEE1149.1 Test Data In on LSP 2
when PASS_THRU_ENABLE is
HIGH.
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 001.
LSP2_TRST
OUT
37
K5
IEEE1149.1 Test Reset on LSP 2
when PASS_THRU_ENABLE is
HIGH.
Buffered version
of signal present
on primary TRST
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 001.
This pin is tri-stated for all other
combinations.
LSP2_AutoWR
OUT
40
K6
Flash, Memory Auto-Write on LSP 2 Logic '1'
when PASS_THRU_ENABLE is
HIGH.
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 001;
PRIM_AutoWR is routed to output.
This pin is tri-stated for all other
combinations.
LSP2_DE
OUT
OUT
36
49
J5
PASS_THRU Debug Enable Output Logic '1'
on LSP 2.
Active low output when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 001.
This pin is high for all other
combinations.
LSP3_TCK
K9
IEEE1149.1 Test Clock on LSP 3
when PASS_THRU_ENABLE is
HIGH.
Buffered version
of signal present
on primary TCK
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 010.
This pin is tri-stated for all other
combinations.
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AS91L1006BU
PIN
PIN
PIN
TYPE
Stable state
after port/reset
PIN NAME
LSP3_TMS
NUMBER NUMBER
LQFP
DESCRIPTION
FPBGA
OUT
50
K10
IEEE1149.1 Test Mode Select on
Logic '1'
LSP 3 when PASS_THRU_ENABLE
is HIGH.
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 010.
This pin is tri-stated for all other
combinations.
LSP3_TDO
OUT
53
H10
IEEE1149.1 Test Data Out on LSP 3 Logic '1'
when PASS_THRU_ENABLE is
HIGH.
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 010.
This pin is tri-stated for all other
combinations.
LSP3_TDI
IN
52
47
J10
IEEE1149.1 Test Data In on LSP 3
when PASS_THRU_ENABLE is
HIGH.
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 010.
IEEE1149.1 Test Reset on LSP 3
when PASS_THRU_ENABLE is
HIGH.
LSP3_TRST
OUT
J8
Buffered version
of signal present
on primary TRST
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 010.
This pin is tri-stated for all other
combinations.
LSP3_LSP_
AutoWR
OUT
48
K8
Flash, Memory Auto-Write on LSP 3 Logic '1'
when PASS_THRU_ENABLE is
HIGH.
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 010;
PRIM_AutoWR is routed to output.
This pin is tri-stated for all other
combinations.
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AS91L1006BU
PIN
PIN
PIN
TYPE
Stable state
after port/reset
PIN NAME
LSP3_DE
NUMBER NUMBER
LQFP
DESCRIPTION
FPBGA
OUT
46
H7
PASS_THRU Debug Enable Output Logic '1'
on LSP 3.
Active low output when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 010.
This pin is high for all other
combinations.
LSP4_TCK
LSP4_TMS
LSP4_TDO
LSP4_TDI
OUT
79
78
76
77
A8
IEEE1149.1 Test Clock on LSP 4
when PASS_THRU_ENABLE is
HIGH.
Buffered version
of signal present
on primary TCK
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 011.
This pin is tri-stated for all other
combinations.
IEEE1149.1 Test Mode Select on
LSP 4 when PASS_THRU_ENABLE
is HIGH.
OUT
OUT
IN
A9
Logic '1'
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 011.
This pin is tri-stated for all other
combinations.
IEEE1149.1 Test Data Out on LSP 4 Logic '1'
when PASS_THRU_ENABLE is
HIGH.
B10
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 011.
This pin is tri-stated for all other
combinations.
IEEE1149.1 Test Data In on LSP 4
when PASS_THRU_ENABLE is
HIGH.
B9
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 011.
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AS91L1006BU
PIN
PIN
PIN
TYPE
Stable state
after port/reset
PIN NAME
NUMBER NUMBER
LQFP
DESCRIPTION
FPBGA
LSP4_TRST
OUT
81
A7
IEEE1149.1 Test Reset on LSP 4
when PASS_THRU_ENABLE is
HIGH.
Buffered version
of signal present
on primary TRST
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 011.
This pin is tri-stated for all other
combinations.
LSP4_AutoWR
OUT
80
B8
Flash, Memory Auto-Write on LSP 4 Logic '1'
when PASS_THRU_ENABLE is
HIGH.
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 011;
PRIM_AutoWR is routed to output.
This pin is tri-stated for all other
combinations.
LSP4_DE
OUT
OUT
83
70
B7
PASS_THRU Debug Enable Output Logic '1'
on LSP 4.
Active low output when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 011.
This pin is high for all other
combinations.
LSP5_TCK
D10
IEEE1149.1 Test Clock on LSP 5
when PASS_THRU_ENABLE is
HIGH.
Buffered version
of signal present
on primary TCK
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 100.
This pin is tri-stated for all other
combinations.
LSP5_TMS
OUT
69
D9
IEEE1149.1 Test Mode Select on
LSP 5 when PASS_THRU_ENABLE
is HIGH.
Logic '1'
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 100.
This pin is tri-stated for all other
combinations.
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AS91L1006BU
PIN
PIN
PIN
TYPE
Stable state
after port/reset
PIN NAME
NUMBER NUMBER
LQFP
DESCRIPTION
FPBGA
LSP5_TDO
OUT
67
E8
IEEE1149.1 Test Data Out on LSP 5 Logic '1'
when PASS_THRU_ENABLE is
HIGH.
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 100.
This pin is tri-stated for all other
combinations.
LSP5_TDI
IN
68
72
E7
C9
IEEE1149.1 Test Data In on LSP 5
when PASS_THRU_ENABLE is
HIGH.
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 100.
IEEE1149.1 Test Reset on LSP 5
when PASS_THRU_ENABLE is
HIGH.
LSP5_TRST
OUT
Buffered version
of signal present
on primary TRST
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 100.
This pin is tri-stated for all other
combinations.
LSP5_AutoWR
OUT
71
D8
Flash, Memory Auto-Write on LSP 5 Logic '1'
when PASS_THRU_ENABLE is
HIGH.
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 100;
PRIM_AutoWR is routed to output.
This pin is tri-stated for all other
combinations.
LSP5_DE
75
C10
PASS_THRU Debug Enable Output Logic '1'
on LSP 5.
Active low output when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 100.
This pin is high for all other
combinations.
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AS91L1006BU
PIN
PIN
PIN
TYPE
Stable state
after port/reset
PIN NAME
NUMBER NUMBER
LQFP
DESCRIPTION
FPBGA
LSP6_TCK
LSP6_TMS
LSP6_TDO
OUT
OUT
OUT
61
F10
IEEE1149.1 Test Clock on LSP 6
when PASS_THRU_ENABLE is
HIGH.
Buffered version
of signal present
on primary TCK
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 101.
This pin is tri-stated for all other
combinations.
IEEE1149.1 Test Mode Select on
LSP 6 when PASS_THRU_ENABLE
is HIGH.
60
F9
Logic '1'
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 101.
This pin is tri-stated for all other
combinations.
IEEE1149.1 Test Data Out on LSP 6 Logic '1'
when PASS_THRU_ENABLE is
HIGH.
57
G10
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 101.
This pin is tri-stated for all other
combinations.
LSP6_TDI
IN
58
64
G8
E9
IEEE1149.1 Test Data In on LSP 6
when PASS_THRU_ENABLE is
HIGH.
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 101.
IEEE1149.1 Test Reset on LSP 5
when PASS_THRU_ENABLE is
HIGH.
LSP6_TRST
OUT
Buffered version
of signal present
on primary TRST
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 101.
This pin is tri-stated for all other
combinations.
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AS91L1006BU
PIN
PIN
PIN
TYPE
Stable state
after port/reset
PIN NAME
LSP6_AutoWR
NUMBER NUMBER
LQFP
DESCRIPTION
FPBGA
OUT
63
F7
Flash, Memory Auto-Write on LSP 6 Logic '1'
when PASS_THRU_ENABLE is
HIGH.
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 101;
PRIM_AutoWR is routed to output.
This pin is tri-stated for all other
combinations.
LSP6_DE
OUT
65
E10
PASS_THRU Debug Enable Output Logic '1'
on LSP 6.
Active low output when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 101.
This pin is high for all other
combinations.
IEEE1149.1 Primary Test Clock
Input.
IEEE1149.1 Primary Test Mode
Select Input.
PRIM_TCK
PRIM_TMS
IN
IN
87
21
A6
G2
PRIM_TDO
OUT
20
G1
IEEE1149.1 Primary Test Data
Output. This pin is tri-stated when
AS91L1006BUis not selected.
HighZ
PRIM_TDI
IN
IN
19
22
G3
H2
IEEE1149.1 Primary Test Data Input
PRIM_TRST
IEEE1149.1 Primary Test Reset
Input.
This active low asynchronous reset
input signal places AS91L1006U in
Wait-for-Selection state.
PRIM_AutoWR
S[5:0]
IN
IN
16
F1
Primary Auto-Write Input controlled
by test equipment to shorten Flash
memory programming.
8,7,6,5,100, D2,D1,D3,C AS91L1006BU Slot Address[5:0]
99
2,B2,A2 Inputs.
Used to set address at which
AS91L1006BU will respond; typically
set by hardwired connection on the
backplane.
*TOE
IN
88
B6
Test Output Enable Input.
Tri-states all LSPs, when asserted
low.
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July 2004
AS91L1006BU
PIN
PIN
PIN
TYPE
Stable state
after port/reset
PIN NAME
NUMBER NUMBER
LQFP
DESCRIPTION
LSP Reset Input.
FPBGA
LSP_RESET_n
IN
14
F4
Active low resets AS91L1006BU to
“Wait-for-Selection” state and pulses
all LSP TRST output pins to low.
This resets all devices with TRST
function; typically this signal would be
connected to a power-on-reset
function.
AS91L1006BU_
SELECTED
OUT
OUT
25
24
K1
J1
AS91L1006BU_Selected Output.
Logic '1'
Logic '1'
Active low when AS91L1006BU is
selected; typically used to control off
board buffering.
LSP_ENABLE
LSP Enabled Output.
Active low when AS91L1006BU is
selected; typically used to set
IEEE1149.1 compliance enable pins
on devices.
USER_STATUS
_BYTE[7:0]
IN
84, 85, 92, C7,C6,C5,C AS91L1006BU Status_Byte Inputs.
93, 94, 96, 4,B4,A4,B3,
97, 98
A3(MSB- Used to provide status information of
(MSB-LSB)
LSB)
the PCB under test back to the test
master via the IEEE1149.1 bus. Eight
signals levels can be monitored and
then reported via the IEEE1149.1 bus
in a non intrusive manner.
SELF_TEST
OUT
IN
27
9
K2
E4
Provides a low going output pulse
under command from the
IEEE1149.1 bus, which can be used
to start self-test functions on a PCB.
Logic '1'
PASS_THRU_
ENABLE
PASS_THRU Enable Input.
Active high disables Pass-Through
mode.
Active low enables Pass-Through
mode.
PASS_THRU_
SEL12:0]
IN
13,12,10
(MSB-LSB) (MSB-LSB)
E2,E1,E3 PASS_THRU Select Inputs.
Used to select active routing of Pass-
Through ports enabled by active low
on PASS_THRU_ENABLE pin.
000 = LSP1
001 = LSP2
010 = LSP3
011 = LSP4
100 = LSP5
101 = LSP6
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AS91L1006BU
PIN
NUMBER NUMBER
LQFP FPBGA
PIN
PIN
TYPE
Stable state
after port/reset
PIN NAME
DESCRIPTION
GND
POWER 38, 86, 11, D6, G5, C3, Ground pins.
26, 43, 59, D7, E5, F6,
74, 95, 2, G4,H8, H9,
17, 54, 55 J9,B1, A5,
90
F2
VCC
POWER
IN
39, 91, 3, D5, G6, C8, VCC pins.
18, 34, 51, D4, E6, F5,
66,
G7,
82,23,56 H3,G9,H1
ASIC_TEST_
EN
89
B5
Factory Test_Enable Input.
This pin should be left unconnected.
IEEE1149.1 ASIC Test Clock Input.
ASIC_TCK
ASIC_TMS
ASIC_TDO
IN
IN
62
15
73
F8
F3
IEEE1149.1 ASIC Test Mode Select.
Input
IEEE1149.1 ASIC Test Clock Output.
OUT
A10
ASIC_TDI
IN
4
1
A1
C1
IEEE1149.1 ASIC Test Clock Input.
No Connects
Table 9 - AS91L0006BU Signal Description
Absolute Maximum Ratings
Parameter
Supply Voltage (Vcc)
Maximum Range
-0.3V to 5.5V
DC Input Voltage (Vi)
-0.5V to Vcc +0.5V
-20mA
Max sink current when Vi = -0.5V
Max source current when Vi = Vcc + 0.5V
Max Junction Temperature with power applied Tj
Max Storage temperature
+20mA
+125 degrees C
-55 to +150 degree C
Table 10 - Absolute Maximum Ratings
ꢁNote: Stress above the stated maximum values may cause irreparable damage to the device.
Correct operation of the device at these values is not guaranteed.
Recommended Operating Conditions
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AS91L1006BU
Parameter
Operating Range
3.0V to 3.6V
0V to Vcc
Supply Voltage (Vcc)
Input Voltage (Vi)
Output Voltage (Vo)
0V to Vcc
Operating Temperature (Ta)
Commercial
0 C to 70 C
Industrial (Ta)
-40 deg C to +85 deg C, 3.00V to 3.6V
Table 11 - Recommended Operating Conditions
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AS91L1006BU
AC Electrical Characteristics
Tch
Tcl
Tcw
TCK
Tsu
Th
TMS
TDI
Toe
Tco
TDO
High Z
High Z
Tpd
Lsp Signal
Figure 4 - AS91L1006BU AC Timing Diagram
MIN
SYMBOL Parameter
MAX
UNITS
Tcw
TCK clock pulse width
TCK pulse width high
100
50
-
-
ns
ns
Tch
Tcl
TCK pulse width low
50
-
ns
Tsu
Th
TCK Setup time
30
40
20
-
-
-
ns
ns
ns
TCK Hold time
Toe
Neg Edge TCK to valid data enable
Tco
Tpd
Neg Edge TCK to valid data
15
-
-
ns
ns
Pass through Mode Primary/Lsp Delay
10
Table 12 - AS91L1006BU AC Timing Information
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AS91L1006BU
DC Electrical Characteristics
Parameter
Max
Min
Condition
Symbol
VIH
Minimum High Input
Voltage
5.25
2.0
VIL
Maximum Low Input
Voltage
0.8V
-0.3V
Parameter
Value
Condition
Symbol
VOH
Minimum High Output
Voltage
2.4V
Ioh=24mA or 8mA as defined
by pin
VOL
Minimum LowOutput
Voltage
0.4V
Iol=24mA or 8mA as defined
by pin
Ioz
Icc
Tristate output leakage -10 or 10 mA
Maximum quiecennt
supply current
2mA
Iccd
Maximum dynamic
supply current
80mA
TCK freq equal to 10 MHz
Table 13 - AS91L1006BU DC Electrical Characteristics
Packaging Information
The AS91L1006BU is available in a 100-pin LQFP or a 100-pin FPBGA lead free package.
L E A D S
S Y M B O
A
L
1 0 0 L E A D
1 . 6 0
T O L .
M
A X .
M
1
A
A
1
2
M
IN
A X
M
0 . 0 5
1 . 3 5
0 . 1 5
1 . 4 5
D
M
IN N O
M
A X
1 . 4 0
1 8 . 0 0
1 4 . 0 0
0 . 6 0
Square
D
B A S I C
B A S I C
0 .1 5
D
1
L
D1
Square
L 1
b
R E F
1 . 0 0
M
IN
B A S I C
A X
N O
J E D E C R E F
M
A X
0 . 1 7
0 . 2 7
e
0 . 5 0
0 . 0 8
0 . 0 8
c c c
d d d
M
M
#
M S - 0 2 6
NOTES:
3
1. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.
2. PLASTIC BODY DIMENSIONS DO NOT INCLUDE FLASH OR PROTUSION.
MAX ALLOWABLE 0.25 PER SIDE.
3.
LEAD COUNT ON DRAWING NOT REPRESENTATIVE OF ACTUAL PACKAGE.
12 NOM
0 - 7
TYP
A1
A
A
A2
- C -
0.09/0.20 TYP
e
CCC
LEAD COPLANARITY
L1
b
0.25
L
12 NOM
al al al A-B
M
S
D S
Figure 5 - LQFP-100
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AS91L1006BU
Revisions
DESCRIPTION
Initial document release.
Updated ball coplanarity limits from
0.20mm to 0.15mm.
D
A
REV.
A
ECN
91253
DATE
12-04-01
2
B
E
B
C
0.15 C
D1
DIMENSIONS
SYMBOL
MIN.
--
0.30
0.25
0.50
NOM.
--
--
--
0.60
MAX.
1.70
--
1.10
0.70
A
A1
A2
b
K
I
H
G
F
D
D1
E
E1
e
11.00 BSC
9.00 BSC
11.00 BSC
9.00 BSC
1.00
E1
E
D
C
B
PACKAGE NUMBER
JEDEC REF #
FBGA0100-11F
MO-192 VAR. AAC-1
A
1
2
3
4
5
6
7
8
9 10
0.25
0.25
M
C
C
A B
b
M
Figure 6 - FPBGA-100
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AS91L1006BU
Device Selector Guide and Ordering Information
AS91L XXXX UU - CC PP - TEMP - L
Aliance Semiconductor
system solution
Blank = leaded
F = lead free
G = green
Device family
1001
1002
C = Commercial (0 to 70 degrees C)
I = Industrial (-40 to 85 degrees C)
1003
1006
Package
L100 = 100 pin LQFP
F100 = 100 pin FPBGA
Product version
S = standard
Clock speed
10 = 10 MHz TCK
40 = 40 MHz TCK
U = 16-bit user code
BU = 8-bit status/user code
E = enhanced
Figure 7 - Part Numbering Guide
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AS91L1006BU
Part Number
Description
AS91L1006BU – 10L100-C
JTAG 6-Port Gateway, 100-pin LQFP
package, commercial
AS91L1006BU – 10L100-CF
AS91L1006BU – 10L100-I
AS91L1006BU – 10L100-IF
AS91L1006BU – 10F100-C
AS91L1006BU – 10F100-CG
AS91L1006BU – 10F100-I
AS91L1006BU – 10F100-IG
AS91L1006BU – 40L100-CF
JTAG 6-Port Gateway, 100-pin LQFP
package, commercial, lead free
JTAG 6-Port Gateway, 100-pin LQFP
package, industrial
JTAG 6-Port Gateway, 100-pin LQFP
package, industrial, lead free
JTAG 6-Port Gateway 100-pin FPBGA
package, commercial
JTAG 6-Port Gateway 100-pin FPBGA,
commercial, green package
JTAG 6-Port Gateway 100-pin FPBGA
package, industrial
JTAG 6-Port Gateway 100-pin FPBGA,
industrial, green package
JTAG 6-Port Gateway, 100-pin LQFP
package, commercial, lead free, 40 MHz
TCK
AS91L1006BU – 40L100-IF
JTAG 6-Port Gateway, 100-pin LQFP
package, industrial, lead free, 40 MHz
TCK
AS91L1006BU – 40F100-CG
AS91L1006BU – 40F100-IG
JTAG 6-Port Gateway 100-pin FPBGA,
commercial, green package, 40 MHz TCK
JTAG 6-Port Gateway 100-pin FPBGA,
industrial, green package, 40 MHz TCK
Table 14 - Valid Part Number Combinations
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AS91L1006BU
Package Options
Device
Master
Description
FPBGA-100
(1mm pitch)
LQFP-100
AS91L1001
AS91L1002
JTAG Test Controller
JTAG Test Sequencer
3-Port Gateway
x
x
x
x
x
x
x
x
AS91L1003U
AS91L1006BU
6-Port Gateway
Table 15 - JTAG Controller Product Family
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AS91L1006BU
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AS91L1003E10F100IG 相关器件
型号 | 制造商 | 描述 | 价格 | 文档 |
AS91L1003E10L100C | ETC | The AS91L1006BU is a one to 6-port JTAG gateway | 获取价格 | |
AS91L1003E10L100CF | ETC | The AS91L1006BU is a one to 6-port JTAG gateway | 获取价格 | |
AS91L1003E10L100CG | ETC | The AS91L1006BU is a one to 6-port JTAG gateway | 获取价格 | |
AS91L1003E10L100I | ETC | The AS91L1006BU is a one to 6-port JTAG gateway | 获取价格 | |
AS91L1003E10L100IF | ETC | The AS91L1006BU is a one to 6-port JTAG gateway | 获取价格 | |
AS91L1003E10L100IG | ETC | The AS91L1006BU is a one to 6-port JTAG gateway | 获取价格 | |
AS91L1003E40F100C | ETC | The AS91L1006BU is a one to 6-port JTAG gateway | 获取价格 | |
AS91L1003E40F100CF | ETC | The AS91L1006BU is a one to 6-port JTAG gateway | 获取价格 | |
AS91L1003E40F100CG | ETC | The AS91L1006BU is a one to 6-port JTAG gateway | 获取价格 | |
AS91L1003E40F100I | ETC | The AS91L1006BU is a one to 6-port JTAG gateway | 获取价格 |
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