AS7C1024-10JC [ETC]
x8 SRAM ; X8 SRAM\n
| 型号： | AS7C1024-10JC |
| 厂家： | 
ETC |
| 描述： | x8 SRAM
|
| 文件： | 总10页 (文件大小：180K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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• Organization: 131,072 words × 8 bits
• High speed
- 10/ 12/ 15/ 20 ns address access time
- 3/ 3/ 4/ 5 ns output enable access time
• Low power consumption available
- Active: 180 mW max (3V, 15 ns)
- Standby: 1.8 mW max, CMOS I/ O
- Very low DC component in active power
• 2.0V data retention
• TTL/ LVTTL-compatible, three-state I/ O
• 32-pin JEDEC standard packages
- 300 mil PDIP and SOJ
Socket compatible with 7C512 (64K×8)
- 400 mil SOJ
- 8mm × 20mm TSOP
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
• 3.3V and 5.0V versions available
• Industrial and commercial temperature available
• Equal access and cycle times
• Easy memory expansion with CE1, CE2, OE inputs
• Intelliwatttm low power and CPG versions available
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TSOP
DIP, SOJ
Vcc
GND
A11
A9
1
OE
Input buffer
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A15
CE2
NC
A16
A14
A12
A7
1
32
2
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
2
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
3
A8
3
4
A13
WE
CE2
A15
A0
A1
A2
4
5
WE
6
5
I/O7
I/O0
A13
7
A6
6
A8
8
512×256×8
Vcc
NC
A16
A14
A12
A7
A5
7
A9
A3
9
A11
A4
8
A4
A5
A6
A7
A8
10
11
12
13
14
15
16
Array
A3
9
OE
A10
A2
10
11
12
13
14
15
16
(1,048,576)
A1
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
A0
A6
A1
I/O0
I/O1
I/O2
GND
A5
A2
A4
A3
WE
OE
CE1
CE2
Column decoder
Control
circuit
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-10
-12
12
-15
-20
20
5
Unit
ns
Maximum address access time
10
3
15
4
Maximum output enable access time
3
ns
AS7C1024
175
–
160
120
100
60
120
95
70
50
0.1
110
80
65
45
0.1
mA
mA
mA
mA
mA
AS7C1024L
AS7C31024
AS7C31024L
Maximum operating current
150
–
Maximum static standby current (L)
0.1
0.1
Shaded areas contain advance information.
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The AS7C1024 and AS7C31024 are high performance CMOS 1,048,576-bit Static Random Access Memories (SRAM) organized as 131,072
words × 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 10/ 12/ 15/ 20 ns with output enable access times (tOE) of 3/ 3/ 4/ 5 ns are ideal for
high performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion with multiple-bank systems.
When CE1 is HIGH or CE2 is LOW the device enters standby mode. If inputs are still toggling, the devices will consume ISB power. If the bus
is static, then full standby power is reached (ISB1 or ISB2). The 31024L for example, is guaranteed not to exceed 0.33mW under nominal full
standby conditions. All devices in this family will retain data when VCC is reduced as low as 2.0V.
A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/ O0-I/ O7 is written
on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2). To avoid bus contention, external
devices should drive I/ O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) HIGH. The chip
drives I/ O pins with the data word referenced by the input address. When either chip enable is inactive, output enable is inactive, or write
enable is active, output drivers stay in high-impedance mode.
All chip inputs and outputs are TTL/ LVTTL-compatible, and operation is from a single 5V supply or 3.3V supply. 128Kx8 and 64Kx16
SRAMs are also available in ultra-low power Intelliwatttm versions. For Intelliwatt specifications, please see the AS7C31024LL and
AS7C31026LL datasheets respectively. The revolutionary pinout (CPG) version of the 128Kx8 may be found as AS7C1025, AS7C31025.
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Parameter
Symbol
Min
–0.5
–
Max
+7.0
1.0
Unit
V
Voltage on any pin relative to GND
Power dissipation
V
t
PD
W
Storage temperature (plastic)
Temperature under bias
DC output current
Tstg
Tbias
Iout
–55
–10
–
+150
+85
20
oC
oC
mA
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute max-
imum rating conditions for extended periods may affect reliability.
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CE1
H
CE2
X
WE
X
OE
X
Data
Mode
High Z
High Z
High Z
Dout
Standby (ISB, ISB1
Standby (ISB, ISB1
Output disable
Read
)
)
X
L
X
X
L
H
H
H
L
H
H
L
L
H
L
X
D
Write
in
Key: X = Don’t Care, L = LOW, H = HIGH
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Parameter
Symbol
VCC
Min
4.5
3.0
0.0
2.2
2.0
–0.5
Nominal
Max
5.5
3.6
0.0
Unit
V
5V devices
5.0
3.3
0.0
–
Supply voltage
3.3V devices
VCC
V
GND
V
AS7C1024
V
VCC + 0.5
VCC + 0.5
0.8
V
V
V
IH
Input voltage
AS7C31024
V
–
IH
†
V
–
IL
†
V
min = –3.0V for pulse width less than t / 2.
RC
IL
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-10
-12
-15
-20
Parameter
Symbol
Test conditions
CC = Max,
V = GND to VCC
Min Max Min Max Min Max Min Max Unit
Input leakage
current
V
| ILI
|
–
1
–
1
–
1
–
1
µA
in
CE1 = VIH or CE2 = V ,
IL
Output leakage
current
| ILO
|
VCC = Max,
–
1
–
1
–
1
–
1
µA
Vout = GND to VCC
V
IOL = 8 mA, VCC = Min
IOH = –4 mA, VCC = Min
–
0.4
–
–
0.4
–
–
0.4
–
–
0.4
–
V
V
OL
Output voltage
V
2.4
2.4
2.4
2.4
OH
Shaded areas contain advance information.
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-10
-12
-15
-20
Parameter
Symbol
ICC
Test conditions
CE1 = V , CE2 = V ,
Min Max Min Max Min Max Min Max Unit
Operating
power supply
current
–
–
175
–
–
–
160
120
–
–
120
95
–
–
110 mA
IL
IH
f = fmax, Iout = 0 mA
L
L
80
mA
–
–
–
–
55
–
–
–
–
–
50
35
5
–
–
–
–
40
25
5
–
–
–
–
40
25
5
mA
mA
mA
CE1 = VIH or CE2 = V ,
IL
ISB
f = fmax, all inputs toggling
Standby
power supply
current
5
Chip disabled, f = 0,
ISB1
ISB2
V ≤ 0.2V or V ≥ VCC–0.2V
in
in
L
L
–
0.5
0.5
0.5 mA
Chip disabled, f = 0,tA = 25°C
V ≤ 0.2V or V ≥ VCC–0.2V,
–
–
–
0.1
–
0.1
–
0.1 mA
in
Shaded areas contain advance information.
in
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-10
-12
-15
-20
Parameter
Operating
power supply
current
Symbol
ICC
Test conditions
CE1 = V , CE2 = V ,
Min Max Min Max Min Max Min Max Unit
–
–
150
–
–
–
100
60
–
–
70
50
–
–
65
45
mA
mA
IL
IH
f = fmax, Iout = 0 mA
L
L
–
–
–
–
55
–
–
–
–
–
50
35
5
–
–
–
–
40
25
5
–
–
–
–
40
25
5
mA
mA
mA
CE1 = VIH or CE2 = V ,
IL
ISB
f = fmax
Standby
power supply
current
5
Chip disabled, f = 0,
ISB1
ISB2
V ≤ 0.2V or V ≥ VCC–0.2V
in
in
L
L
–
0.5
0.5
0.5 mA
Chip disabled, f = 0,tA = 25C
–
–
–
0.1
–
0.1
–
0.1 mA
V ≤ 0.2V or V ≥ VCC–0.2V,
in
in
Shaded areas contain advance information.
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Parameter
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Symbol
Signals
Test conditions
V = 0V
Max
5
Unit
pF
Input capacitance
I/ O capacitance
C
A, CE1, CE2, WE, OE
I/ O
IN
in
C
V = Vout = 0V
7
pF
I/ O
in
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-10
-12
-15
-20
Parameter
Symbol Min Max Min Max Min Max Min Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Read cycle time
tRC
10
–
–
–
–
2
3
3
–
–
0
–
0
–
–
10
10
10
3
12
–
–
–
–
3
3
3
–
–
0
–
0
–
–
12
12
12
3
15
–
–
–
–
3
3
3
–
–
0
–
0
–
–
15
15
15
4
20
–
–
–
–
3
3
3
–
–
0
–
0
–
–
20
20
20
5
Address access time
tAA
3
Chip enable (CE1) access time
Chip enable (CE2) access time
Output enable (OE) access time
Output hold from address change
CE1 LOW to output in Low Z
CE2 HIGH to output in Low Z
CE1 HIGH to output in High Z
CE2 LOW to output in High Z
OE LOW to output in Low Z
OE HIGH to output in High Z
Power up time
tACE1
tACE2
tOE
3, 12
3, 12
tOH
–
–
–
–
5
tCLZ1
tCLZ2
tCHZ1
tCHZ2
tOLZ
tOHZ
tPU
–
–
–
–
4, 5, 12
4, 5, 12
4, 5, 12
4, 5, 12
4, 5
–
–
–
–
3
3
4
5
3
3
4
5
–
–
–
–
3
3
4
5
4, 5
–
–
–
–
4, 5, 12
4, 5, 12
Power down time
tPD
10
12
15
20
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Rising input
Falling input
tRC
Undefined output/don’t care
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Address
Dout
tAA
t
O H
Data valid
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1
tRC
CE1
CE2
OE
tOE
tOLZ
tOHZ
tCHZ1, CHZ2
t
tACE1, ACE2
t
Dout
D ata valid
tCLZ1, tCLZ2
tPD
50%
ICC
ISB
tPU
Current
supply
50%
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-10
-12
-15
-20
Parameter
Symbol Min Max Min Max Min Max Min Max Unit
Notes
Write cycle time
tWC
tCW1
tCW2
tAW
tAS
10
9
9
9
0
7
0
6
0
–
3
–
–
–
–
–
–
–
–
–
5
–
12
10
10
10
0
–
–
–
–
–
–
–
–
–
5
–
15
12
12
12
0
–
–
–
–
–
–
–
–
–
5
–
20
12
12
12
0
–
–
–
–
–
–
–
–
–
5
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip enable (CE1) to write end
Chip enable (CE2) to write end
Address setup to write end
Address setup time
12
12
12
Write pulse width
tWP
tAH
tDW
tDH
8
9
12
0
Address hold from end of write
Data valid to write end
Data hold time
0
0
6
9
10
0
0
0
4, 5
4, 5
4, 5
Write enable to output in High Z tWZ
–
–
–
Output active from write end
tOW
3
3
3
Shaded areas contain advance information.
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tWC
tAW
tAH
Address
tWP
WE
tAS
tDW
Data valid
tDH
Din
tWZ
tOW
Dout
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tWC
tAW
tAH
Address
tAS
tCW1, tCW2
CE1
CE2
tWP
WE
tWZ
tDW
tDH
Din
Data valid
Dout
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Parameter
Symbol
VDR
Test conditions
VCC = 2.0V
Min
2.0
–
Max
–
Unit
V
VCC for data retention
Data retention current
ICCDR
tCDR
tR
500 (100 L) µA
CE1 ≥ VCC–0.2V or
CE2 ≤ 0.2V
Chip deselect to data retention time
Operation recovery time
Input leakage current
0
–
–
1
ns
tRC
–
ns
V ≥ VCC–0.2V or
in
V ≤ 0.2V
in
| ILI
|
µA
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Data retention mode
VCC
4.5V or 2.7V
VDR ≥ 2.0V
4.5V or 2.7V
tR
tCDR
VDR
VIH
VIH
CE
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– 5V output load: see Figure B,
except as noted see Figure C.
– 3.3V output load: see Figure D,
except as noted see Figure E.
Thevenin equivalent:
168Ω
– Input pulse level: GND to 3.0V. See Figure A.
– Input rise and fall times: 5 ns. See Figure A.
– Input and output timing reference levels: 1.5V.
Dout
+1.728V
+5V
+5V
480Ω
480Ω
Dout
Dout
255Ω
+3.0V
90%
10%
90%
10%
255Ω
30 pF*
GND
5 pF*
GND
*including scope
and jig capacitance
GND
Figure B: Output load
Figure C: Output load for tCLZ, tCHZ, tOLZ, tOHZ, tOW
Figure A: Input waveform
+3.3V
+3.3V
320Ω
320Ω
Dout
Dout
*including scope
and jig capacitance
350Ω
30 pF*
GND
350Ω
5 pF*
GND
Figure D: Output load
Figure C: Output load for tCLZ, tCHZ, tOLZ, tOHZ, tOW
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Normalized supply current ICC, ISB
Normalized supply current ICC, ISB
Normalized supply current ISB1
vs. ambient temperature T
vs. supply voltage VCC
1.4
vs. ambient temperature T
a
a
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.2
1.0
0.8
0.6
0.4
0.2
0.0
625
25
5
1
0.2
0.04
4.0
4.5
5.0
5.5
–55
–10
35
80
-55
-10
35
80
6.0
125
125
Supply voltage (V)
Ambient temperature (°C)
Ambient temperature (°C)
Normalized access time tAA
vs. supply voltage VCC
Normalized access time tAA
Normalized supply current ICC
vs. cycle frequency
vs. ambient temperature T
a
1.3
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.2
1.1
1.0
0.9
0.8
0.7
0.6
T = 25°C
a
4.0
4.5
5.0
5.5
–55
–10
35
80
0
1/ (2tRC
)
6.0
125
1/ tRC
Supply voltage (V)
Ambient temperature (°C)
Cycle frequency (MHz)
Output source current IOH
Output sink current IOL
Typical access time change ∆tAA
vs. output capacitive loading
vs. output voltage V
vs. output voltage V
OH
OL
140
120
100
80
140
120
100
80
35
30
25
20
15
10
5
VCC = 5.0V
VCC = 5.0V
T = 25°C
T = 25°C
a
a
60
60
40
40
20
20
0
0.0
0
0.0
0
1.25
2.5
3.75
1.25
2.5
3.75
0
250
500
750
5.0
5.0
1000
Output voltage (V)
Output voltage (V)
Capacitance (pF)
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1RWHV
1
2
3
4
5
6
7
8
9
During V power-up, a pull-up resistor to V on CE1 is required to meet I specification.
CC CC SB
This parameter is sampled and not 100% tested.
For test conditions, see AC Test Conditions, Figures A, B, C.
t
and t
are specified with CL = 5pF as in Figure C. Transition is measured ±500mV from steady-state voltage.
CHZ
CLZ
This parameter is guaranteed but not tested.
WEis HIGH for read cycle.
CE1 and OE are LOW and CE2 is HIGH for read cycle.
Address valid prior to or coincident with CE transition LOW.
All read cycle timings are referenced from the last valid address to the first transitioning address.
10 CE1 or WE must be HIGH or CE2 LOW during address transitions.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 CE1 and CE2 have identical timing.
13 This data applicable to the AS7C1024. The AS7C31024 functions similarly.
14 2V data retention applies to commercial temperature operating range only.
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Package \ Access time
10 ns
12 ns
15 ns
20 ns
Plastic DIP, 300 mil
New designs using PDIP are discouraged. Contact Alliance Sales for PDIP availability of limited production.
AS7C1024-10TJC
AS7C1024-12TJC
AS7C1024L-12TJC
AS7C1024-15TJC
AS7C1024L-15TJC
AS7C1024-20TJC
AS7C1024L-20TJC
Plastic SOJ, 300 mil
AS7C31024-15TJC
AS7C31024-15TJI
AS7C31024-20TJC
AS7C31024-20TJI
AS7C31024-10TJC
AS7C31024-12TJC
AS7C31024L-12TJC
AS7C1024-12JC
AS7C31024L-15TJC
AS7C31024L-20TJC
AS7C1024-15JC
AS7C1024-15JI
AS7C1024-20JC
AS7C1024-20JI
AS7C1024-10JC
AS7C31024-10JC
AS7C1024L-12JC
AS7C31024-12JC
AS7C1024L-15JC
AS7C1024L-20JC
Plastic SOJ, 400 mil
AS7C31024-15JC
AS7C31024-15JI
AS7C31024-20JC
AS7C31024-20JI
AS7C31024L-12JC
AS7C1024-12TC
AS7C1024L-12TC
AS7C31024-12TC
AS7C31024L-12TC
AS7C31024L-15JC
AS7C1024-15TC
AS7C1024L-15TC
AS7C31024-15TC
AS7C31024L-15TC
AS7C31024L-20JC
AS7C1024-20TC
AS7C1024L-20TC
AS7C31024-20TC
AS7C31024L-20TC
TSOP 8×20
Shaded areas contain advance information.
$6ꢃ&ꢄꢅꢆꢇꢀIDPLO\ꢀSDUWꢀQXPEHULQJꢀV\VWHP
–XX
AS7C
X
1024
X
X
X
Temperature range
C = Commercial, 0°C to 70°C
I = Industrial, -40°C to 85°C
SRAM
prefix
Blank=5V CMOS
3=3.3V CMOS
Device
number
L = low
power
Access
time
Package:TP =PDIP 300 mil T =TSOP 8×20
J =SOJ 400 mil TJ =SOJ 300 mil
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