AN22022 [ETC]
; - 12号的铝制车身绘（ RAL 7032 ）
| 型号： | AN22022 |
| 厂家： | 
ETC |
| 描述： |
|
| 文件： | 总16页 (文件大小：259K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXA2022S
I2C Bus Sound Processor for TV
Description
30 pin SDIP (Plastic)
The CXA2022S is a bipolar IC designed as an I2C
bus control sound processor for TV. This IC has
simulate stereo, surround, tone control, balance,
volume, muting, AGC and other functions.
Features
• Allows control by I2C bus
• Employs a special surround system to prevent
"vocal missing" in the surround mode
• Adopts an AGC circuit to absorb the difference in
sound level between input sources and improves
S/N ratio of hearing characteristics
Structure
Bipolar silicon monolithic IC
Applications
TVs
Absolute Maximum Ratings
• Supply voltage
VCC
14
V
• Operating temperature
• Storage temperature
Topr –20 to +75 °C
Tstg –65 to +150 °C
• Allowable power dissipation PD
1.25
W
Recommended Operating Condition
Supply voltage
8 to 13
V
Pin Configuration
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E95Y17A7X
CXA2022S
L C S
A D S
L O V
L A B
E R T
S S A B
L L C
L H C
R L C
R H C
L C C
R C C
B 3 S P
A 3 S P
B 2 S P
A 2 S P
B 1 S P
A 1 S P
C C V
D N G
I F V M
O F V M
S R V
2 T E D
1 T E D
– 2 –
CXA2022S
Pin Description
(Ta = 25°C, VCC = 12V)
Description
Pin
Symbol
Pin voltage
Equivalent circuit
No.
VCC
10µ
130 10k
1
R IN
6V
Input pins.
1
30 L IN
30k
30
VCC/2
2
3
GND
CL R
0V
6V
GND
VCC
250µ
250µ
5.4k
External pins for LPF
capacitance (BASS).
11k
11k
28 CL L
3
130
28
VCC/2
VCC
250µ
250µ
6k
4
CH R
External pins for HPF
capacitance (TREBLE).
5.7k
5.7k
130
6V
27 CH L
4
27
VCC
40k
20k
DAC output pins.
Connect LPF
capacitance of DAC.
Internal impedance is
approximetely 20kΩ.
5
6
7
8
BAL
7.5V
5
6
7
8
2k
TRE
BASS
VOL
4.5V
2k
75µ
– 3 –
CXA2022S
Pin
No.
Symbol
Pin voltage
Equivalent circuit
Description
VCC
1k
1k
500
20k
DC-cut pins for L and R.
Internal impedance is
approximately 20kΩ.
9
CC R
20k
1k
6V
22 CC L
9
22
500
VCC
5P
500
500
130
10 ROUT
21 LOUT
10
21
6V
Output pins.
84k
VCC
10µ
11 PS1A
17 PS2A
18 PS2B
19 PS1B
20 PS3A
23 PS3B
11
External capacitance
pins for surround phase-
shifter. Internal
impedance is
approximately 18kΩ.
18k
18k
17
18
19
20
23
130
6V
VCC
200
10k
200
AGC detector output and
control pin.
12
12 DET2
130
100k
100k
– 4 –
CXA2022S
Pin
No.
Symbol
Pin voltage
Equivalent circuit
Description
10µ
500
130
10k
HPF external capacitance
pin of AGC.
13 HPF
14 SCL
15 SDA
6V
13
500
16k
16k
VCC
50µ
100µ
14
I2C bus clock line pin.
4k
3k
11k
56k
VCC
100µ
50µ
I2C bus data line pin.
15
4k
3k
4.5k
56k
VCC
40k
16
AGC detector output pin.
Connect capacitance for
setting time constant.
16 DET1
7.8V
2k
– 5 –
CXA2022S
Pin
No.
Symbol
Pin voltage
Equivalent circuit
Description
VCC
5µ
5µ
22k
10k
22k
10k
External pin for surround
filter.
24 MVFI
25 MVFO
26 VRS
6V
24
130
18k
39k
VCC
500
130
External pin for surround
filter.
6V
25
500
VCC
16k
16k
30k
VCC/2 reference voltage
pin.
6V
1k
26
30k
30µ
29
VCC
12V
Power supply.
– 6 –
CXA2022S
A D S
L C S
1 T E D
A 2 S P
B 2 S P
B 1 S P
A 3 S P
T U O L
L C C
B 3 S P
I F V M
O F V M
S R V
F P H
2 T E D
A 1 S P
T U O R
R C C
L O V
S S A B
E R T
L A B
R H C
R L C
D N G
N I R
L H C
L L C
C C V
N I L
– 7 –
CXA2022S
Control Register Table
(SLAVE ADDRESS = 82H)
(Power ON setting value)
DATA
bit 4 bit 3
bit 7
bit 6
bit 5
bit 2
bit 1
MUTE AGC
(0) (0)
MODE (00)
bit 0
AGC : 0 = OFF/1 = ON
MUTE : 0 = OFF/1 = ON
VOLUME (00)
BASS (00)
TREBLE (00)
BALANCE (00)
SURR-EFFECT (00)
VOCAL-MIX (00)
MONO-EFFECT (00)
MODE : 00 = Surround OFF
: 01 = Simulate Stereo
: 10 = Stereo Surround 1
: 11 = Stereo Surround 2
Undefined
Description of Register
• VOLUME: Common to both L and R channels
0 = Minimum
3F = Maximum
• MUTE: MUTE switch
0 = Mute OFF
1 = Mute ON (muting state)
• AGC: AGC switch
0 = AGC OFF
1 = AGC ON
• BASS: Low frequency control
0 = Minimum
10 = Typical
1F = Maximum
• MODE: Surround mode setting
00 = Surround OFF
01 = Simulate Stereo (Monaural Surround)
10 = Stereo Surround 1
11 = Stereo Surround 2
• TREBLE: High frequency control
00 = Minimum
10 = Typical
1F = Maximum
– 8 –
CXA2022S
• BALANCE: Balance control for L and R channels
00 = L channel (Minimum), R channel (Maximum)
20 = Typical
3F = L channel (Maximum), R channel (Minimum)
• SURR-EFFECT: Effect setting for Stereo Surround 1 and 2
0 = Minimum
8 = Typical
F = Maximum
• MONO-EFFECT: Effect setting for Simulate Stereo (Monaural Surround)
0 = Minimum
F = Maximum
• VOCAL-MIX: Addition amount setting of middle frequency for Stereo Surround 1 and 2
0 = Minimum
8 = Typical
F = Maximum
Application Circuit
L IN
L OUT
VCC
C10
0.1µ
C2
4.7µ
C4
0.1µ
C6
4700P
C8
47µ
C13
8200P
C15
4.7µ
C17
10µ
C19
8200P
C21
4700P
C24
0.1µ
C25
4.7µ
R1
820k
C23
0.022µ
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CXA2022S
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
C20
10µ
R3
220
R4
220
C1
4.7µ
C3
0.1µ
C5
4700P
C7
4.7µ
C9
4.7µ
C11
4.7µ
C12
4.7µ
C14
4.7µ
C16
10µ
C18
4700P
C22
0.1µ
R2
1MEG
R IN
R OUT
SCL
SDA
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 9 –
CXA2022S
– 10 –
CXA2022S
– 11 –
CXA2022S
– 12 –
CXA2022S
Description of Operation
• AGC circuit
The AGC circuit is provided at the input. When AGC is set to ON, this circuit is 0dB for small signal input,
boosts for medium signal input, and achieves gain reduction for large signal input. The sound level
defference between input sources can be absorbed at this circuit.
• Surround circuit
The surround circuit provides three modes; MONO (Simulate Stereo), STEREO-1 and STEREO-2.
MONO mode
L + R signals, passed through the mono filter and then through four stages of phase shifters (PS1A, PS1B,
PS2A, PS2B) and 9kHz LPF, are added to L and R channels at opposite phase to each other.
The surround effect can be changed by the MONO-EFFECT.
STEREO-1 mode
L-R signals, passed through two stages of phase shifters (PS1A, PS1B) and 9kHz LPF, are added to L and R
channels at opposite phase to each other. The surround effect can be changed by the SURR-EFFECT. In
addition, L + R signals passed through the middle frequency BPF (1kHz BPF) are added to L and R channels at
in-phase to each other to prevent "vocal missing" in the surround mode. The addition amount of middle
frequency can be changed by the VOCAL-MIX.
STEREO-2 mode
L-R signals, passed through two stages of phase shifters (PS1A, PS1B) and 9kHz LPF, are added to L and R
channels at opposite phase to each other. The surround effect can be changed by the SURR-EFFECT. In
addition, L + R signals passed through the middle frequency BPF (1kHz BPF) are added to R channel, and the
middle frequency signals passed further through two stages of phase shifters (PS3A, PS3B) are added to the L
channel. The addition amount of middle frequency (L and R) can be changed by the VOCAL-MIX.
Phase Shifter
Each of the phase shifters PS1, PS2 and PS3 consists of two stages of phase shifters (A, B). The transfer
function for a stage of phase shifter is expressed by the following equation.
1 – SCR
1 + SCR
VO =
Vin
R: Internal resistance ≈ 18kΩ, C: External capacitance
• TONE circuit
Provides tone controls for BASS and TREBLE. The external capacitance of CL for BASS and CH for TREBLE
can determine the characteristics. The number of steps is 32.
• BALANCE and VOLUME circuit
Provides controls for BALANCE and VOLUME. the number of steps is 64 each.
• DAC circuit
Provides controls for BASS, TREBLE, VOLUME and BALANCE. The internal impedance is approximately
20kΩ and the LPF capacitance is used externally.
– 13 –
CXA2022S
Example of Representative Characteristics
TONE characteristics
20
10
BASS-TREBLE MAX.
BASS-TREBLE MIN.
0
–10
–20
10
100
1k
10k
100k
Frequency [Hz]
CH. vs. TREBLE-CONTROL (MAX)
17.5
15.0
12.5
10.0
7.5
0.047µ
0.022µ
2200p
470p
4700p
5.0
2.5
0.0
–2.5
10
100
Frequency [Hz]
1k
10k
100k
CH. vs. BASS-CONTROL (MAX)
17.5
15.0
12.5
10.0
7.5
0.01µ
0.1µ
0.047µ
1µ
5.0
0.47µ
2.5
0.0
–2.5
10
100
Frequency [Hz]
1k
10k
100k
– 14 –
CXA2022S
VOL CONTROL characteristics
BALANCE CONTROL characteristics
0
–10
–20
–30
–40
–50
–60
–70
–80
0
–10
–20
–30
–40
–50
–60
–70
–80
OUT R
OUT L
10
20
30
3F
0
10
20
30
3F
BUS Data (VOL)
BUS Data (BALANCE)
BASS CONTROL characteristics
TREBLE CONTROL characteristics
12
10
8
12
10
8
Input = 100Hz
Input = 10kHz
6
6
4
4
2
2
0
0
–2
–4
–6
–8
–10
–12
–2
–4
–6
–8
–10
–12
0
4
8
C
10 14 18 1C 1F
0
4
8
C
10 14 18 1C 1F
BUS Data (BASS)
BUS Data (TREBLE)
AGC characteristics
1V
AGC = OFF
AGC = ON
100mV
10
10
100mV
1V
IN [rms]
– 15 –
CXA2022S
Package Outline
Unit : mm
30PIN SDIP (PLASTIC)
+ 0.4
26.9 – 0.1
30
16
0° to 15°
15
1
1.778
Two kinds of package surface:
1.All mat surface type.
2.All mirror surface type.
0.5 ± 0.1
0.9 ± 0.15
PACKAGE STRUCTURE
EPOXY RESIN
MOLDING COMPOUND
LEAD TREATMENT
LEAD MATERIAL
SOLDER/PALLADIUM
SONY CODE
EIAJ CODE
SDIP-30P-01
PLATING
COPPER ALLOY
1.8g
SDIP030-P-0400
JEDEC CODE
PACKAGE MASS
NOTE : PALLADIUM PLATING
This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
– 16 –
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