AM29LV400BB-120FC_技术文档

Am29LV400B

4 Megabit (512 K x 8-Bit/256 K x 16-Bit)

CMOS 3.0 Volt-only Boot Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

■ Single power supply operation

■ Top or bottom boot block configurations

available

— Full voltage range: 2.7 to 3.6 volt read and write

operations for battery-powered applications

■ Embedded Algorithms

— Regulated voltage range: 3.0 to 3.6 volt read and

write operations for compatibility with high

performance 3.3 volt microprocessors

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any

combination of designated sectors

■ Manufactured on 0.32 µm process technology

— Embedded Program algorithm automatically

writes and verifies data at specified addresses

— Compatible with 0.5 µm Am29LV400 device

■ Minimum 1,000,000 write cycle guarantee per sector

■ 20-year data retention at 125°C

— Reliable operation for the life of the system

■ Package option

■ High performance

— Full voltage range: access times as fast as 70 ns

— Regulated voltage range: access times as fast as

55 ns

— 48-ball FBGA

■ Ultra low power consumption (typical values at

5 MHz)

— 48-pin TSOP

— 200 nA Automatic Sleep mode current

— 200 nA standby mode current

— 7 mA read current

— 44-pin SO

■ Compatibility with JEDEC standards

— Pinout and software compatible with single-

power supply Flash

— 15 mA program/erase current

— Superior inadvertent write protection

■ Flexible sector architecture

— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and

seven 64 Kbyte sectors (byte mode)

■ Data# Polling and toggle bits

— Provides a software method of detecting program

or erase operation completion

— One 8 Kword, two 4 Kword, one 16 Kword, and

seven 32 Kword sectors (word mode)

■ Ready/Busy# pin (RY/BY#)

— Supports full chip erase

— Provides a hardware method of detecting

program or erase cycle completion

— Sector Protection features:

A hardware method of locking a sector to prevent

any program or erase operations within that sector

■ Erase Suspend/Erase Resume

— Suspends an erase operation to read data from,

or program data to, a sector that is not being

erased, then resumes the erase operation

Sectors can be locked in-system or via

programming equipment

Temporary Sector Unprotect feature allows code

changes in previously locked sectors

■ Hardware reset pin (RESET#)

— Hardware method to reset the device to reading

array data

■ Unlock Bypass Program Command

— Reduces overall programming time when issuing

multiple program command sequences

This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data

Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.

Publication# 21523 Rev: D Amendment/+1

Issue Date: November 8, 2000

GENERAL DESCRIPTION

The Am29LV400B is a 4 Mbit, 3.0 volt-only Flash

memory organized as 524,288 bytes or 262,144 words.

The device is offered in 48-ball FBGA, 44-pin SO, and

48-pin TSOP packages. The word-wide data (x16)

appears on DQ15–DQ0; the byte-wide (x8) data

appears on DQ7–DQ0. This device is designed to be

programmed in-system using only a single 3.0 volt V_CC

supply. No V_PPis required for write or erase opera-

tions. The device can also be programmed in standard

EPROM programmers.

pre-programs the array (if it is not already programmed)

before executing the erase operation. During erase, the

device automatically times the erase pulse widths and

verifies proper cell margin.

The host system can detect whether a program or

erase operation is complete by observing the RY/BY#

pin, or by reading the DQ7 (Data# Polling) and DQ6

(toggle) status bits. After a program or erase cycle has

been completed, the device is ready to read array data

or accept another command.

This device is manufactured using AMD’s 0.32 µm

process technology, and offers all the features and ben-

efits of the Am29LV400, which was manufactured using

0.5 µm process technology. In addition, the

Am29LV400B features unlock bypass programming

and in-system sector protection/unprotection.

The sector erase architecture allows memory sectors

to be erased and reprogrammed without affecting the

data contents of other sectors. The device is fully

erased when shipped from the factory.

Hardware data protection measures include a low

V_CCdetector that automatically inhibits write opera-

tions during power transitions. The hardware sector

protection feature disables both program and erase

operations in any combination of the sectors of

memory. This can be achieved in-system or via pro-

gramming equipment.

The standard device offers access times of 55, 70, 90

and 120 ns, allowing high speed microprocessors to

operate without wait states. To eliminate bus contention

the device has separate chip enable (CE#), write

enable (WE#) and output enable (OE#) controls.

The device requires only a single 3.0 volt power

supply for both read and write functions. Internally

generated and regulated voltages are provided for the

program and erase operations.

The Erase Suspend feature enables the user to put

erase on hold for any period of time to read data from,

or program data to, any sector that is not selected for

erasure. True background erase can thus be achieved.

The device is entirely command set compatible with the

JEDEC single-power-supply Flash standard. Com-

mands are written to the command register using

standard microprocessor write timings. Register con-

tents serve as input to an internal state-machine that

controls the erase and programming circuitry. Write

cycles also internally latch addresses and data needed

for the programming and erase operations. Reading

data out of the device is similar to reading from other

Flash or EPROM devices.

The hardware RESET# pin terminates any operation

in progress and resets the internal state machine to

reading array data. The RESET# pin may be tied to the

system reset circuitry. A system reset would thus also

reset the device, enabling the system microprocessor

to read the boot-up firmware from the Flash memory.

The device offers two power-saving features. When

addresses have been stable for a specified amount of

time, the device enters the automatic sleep mode.

The system can also place the device into the standby

mode. Power consumption is greatly reduced in both

these modes.

Device programming occurs by executing the program

command sequence. This initiates the Embedded

Program algorithm—an internal algorithm that auto-

matically times the program pulse widths and verifies

proper cell margin. The Unlock Bypass mode facili-

tates faster programming times by requiring only two

write cycles to program data instead of four.

AMD’s Flash technology combines years of Flash

memory manufacturing experience to produce the

highest levels of quality, reliability and cost effectiveness.

The device electrically erases all bits within a sector simul-

taneously via Fowler-Nordheim tunneling. The data is

programmed using hot electron injection.

Device erasure occurs by executing the erase

command sequence. This initiates the Embedded

Erase algorithm—an internal algorithm that automatically

2

Am29LV400B

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5

Special Handling Instructions for Fine Pitch Ball Grid

Reading Toggle Bits DQ6/DQ2 ............................................... 21

DQ5: Exceeded Timing Limits ................................................ 22

DQ3: Sector Erase Timer ....................................................... 22

Figure 6. Toggle Bit Algorithm........................................................ 22

Table 6. Write Operation Status ..................................................... 23

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 24

Figure 7. Maximum Negative Overshoot Waveform ...................... 24

Figure 8. Maximum Positive Overshoot Waveform........................ 24

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 24

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 25

Array (FBGA) ............................................................................ 7

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9

Table 1. Am29LV400B Device Bus Operations ................................9

Word/Byte Configuration .......................................................... 9

Requirements for Reading Array Data ..................................... 9

Writing Commands/Command Sequences ............................ 10

Program and Erase Operation Status .................................... 10

Standby Mode ........................................................................ 10

Automatic Sleep Mode ........................................................... 10

RESET#: Hardware Reset Pin ............................................... 10

Output Disable Mode .............................................................. 11

Table 2. Am29LV400BT Top Boot Sector Address Table ...............11

Table 3. Am29LV400BB Bottom Boot Sector Address Table .........11

Autoselect Mode ..................................................................... 12

Table 4. Am29LV400B Autoselect Codes (High Voltage Method) ..12

Sector Protection/Unprotection ............................................... 12

Figure 1. In-System Sector Protect/Unprotect Algorithms .............. 13

Temporary Sector Unprotect .................................................. 14

Figure 2. Temporary Sector Unprotect Operation........................... 14

Hardware Data Protection ...................................................... 14

Figure 9. I

Current vs. Time (Showing Active and Automatic

CC1

Sleep Currents).............................................................................. 26

Figure 10. Typical I vs. Frequency ........................................... 26

CC1

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 11. Test Setup..................................................................... 27

Table 7. Test Specifications ........................................................... 27

Figure 12. Input Waveforms and Measurement Levels ................. 27

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 28

Read Operations .................................................................... 28

Figure 13. Read Operations Timings ............................................. 28

Hardware Reset (RESET#) .................................................... 29

Figure 14. RESET# Timings .......................................................... 29

Word/Byte Configuration (BYTE#) ........................................ 30

Figure 15. BYTE# Timings for Read Operations............................ 30

Figure 16. BYTE# Timings for Write Operations............................ 30

Erase/Program Operations ..................................................... 31

Figure 17. Program Operation Timings.......................................... 32

Figure 18. Chip/Sector Erase Operation Timings .......................... 33

Figure 19. Data# Polling Timings (During Embedded Algorithms). 34

Figure 20. Toggle Bit Timings (During Embedded Algorithms)...... 34

Figure 21. DQ2 vs. DQ6................................................................. 35

Figure 22. Temporary Sector Unprotect Timing Diagram .............. 35

Figure 23. Sector Protect/Unprotect Timing Diagram .................... 36

Figure 24. Alternate CE# Controlled Write Operation Timings ...... 38

Erase And Programming Performance . . . . . . . 39

Latchup Characteristics . . . . . . . . . . . . . . . . . . . 39

TSOP And SO Pin Capacitance . . . . . . . . . . . . . 39

Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 40

TS 048—48-Pin Standard TSOP ............................................ 40

TSR048—48-Pin Reverse TSOP ........................................... 41

FBA048—48-ball Fine-Pitch Ball Grid Array (FBGA)

6 x 8 mm package .................................................................. 42

SO 044—44-Pin Small Outline Package ............................... 43

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 44

Revision A (January 1998) ..................................................... 44

Revision B (July 1998) ............................................................ 44

Revision B+1 (August 1998) ................................................... 44

Revision C (January 1999) ..................................................... 44

Revision C+1 (July 2, 1999) ................................................... 44

Revision D (January 3, 1999) ................................................. 44

Revision D+1 (November 8, 2000) ......................................... 44

Low V Write Inhibit .............................................................. 14

CC

Write Pulse “Glitch” Protection ............................................... 14

Logical Inhibit .......................................................................... 14

Power-Up Write Inhibit ............................................................ 14

Command Definitions . . . . . . . . . . . . . . . . . . . . . . 15

Reading Array Data ................................................................ 15

Reset Command ..................................................................... 15

Autoselect Command Sequence ............................................ 15

Word/Byte Program Command Sequence ............................. 15

Unlock Bypass Command Sequence ..................................... 16

Figure 3. Program Operation .......................................................... 16

Chip Erase Command Sequence ........................................... 16

Sector Erase Command Sequence ........................................ 17

Erase Suspend/Erase Resume Commands ........................... 17

Figure 4. Erase Operation............................................................... 18

Command Definitions ............................................................. 19

Table 5. Am29LV400B Command Definitions .................................19

Write Operation Status . . . . . . . . . . . . . . . . . . . . . 20

DQ7: Data# Polling ................................................................. 20

Figure 5. Data# Polling Algorithm ................................................... 20

RY/BY#: Ready/Busy# ........................................................... 21

DQ6: Toggle Bit I .................................................................... 21

DQ2: Toggle Bit II ................................................................... 21

Am29LV400B

3

PRODUCT SELECTOR GUIDE

Family Part Number

Am29LV400B

Regulated Voltage Range: 3.0 – 3.6 V

Full Voltage Range: 2.7 – 3.6 V

55R

Speed Options

70

90

35

120

50

Max access time, ns (t

)

55

30

70

30

ACC

Max CE# access time, ns (t

)

CE

Max OE# access time, ns (t

)

OE

Note: See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

DQ0–DQ15 (A-1)

RY/BY#

V

CC

Sector Switches

V

SS

Erase Voltage

Generator

Input/Output

Buffers

RESET#

State

Control

WE#

BYTE#

Command

Register

PGM Voltage

Generator

Data

Latch

Chip Enable

Output Enable

Logic

STB

CE#

OE#

Y-Decoder

Y-Gating

STB

V

Detector

Timer

CC

Cell Matrix

X-Decoder

A0–A17

4

Am29LV400B

CONNECTION DIAGRAMS

A15

A14

A13

A12

A11

A10

A9

A8

NC

1

2

3

4

5

6

7

8

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A16

BYTE#

V_SS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

DQ12

DQ4

V_CC

WE#

RESET#

NC

RY/BY#

NC

Standard TSOP

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

V_SS

CE#

A0

A17

A7

A6

A5

A4

A3

A2

A1

1

2

3

4

5

6

7

8

A15

A14

A13

A12

A11

A10

A9

A8

NC

WE#

RESET#

NC

RY/BY#

NC

A17

A7

A6

A5

A4

48

A16

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

BYTE#

V_SS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

V_CC

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

Reverse TSOP

OE#

V_SS

CE#

A0

A3

A2

A1

Am29LV400B

5

CONNECTION DIAGRAMS

NC

RY/BY#

A17

A7

1

2

3

4

5

6

7

8

9

44 RESET#

43 WE#

42 A8

41 A9

A6

40 A10

A5

39 A11

A4

38 A12

A3

37 A13

A2

36 A14

A1 10

A0 11

35 A15

34 A16

SO

CE# 12

V_SS13

33 BYTE#

32 V_SS

OE# 14

DQ0 15

DQ8 16

DQ1 17

DQ9 18

DQ2 19

DQ10 20

DQ3 21

DQ11 22

31 DQ15/A-1

30 DQ7

29 DQ14

28 DQ6

27 DQ13

26 DQ5

25 DQ12

24 DQ4

23 V_CC

FBGA

Top View, Balls Facing Down

A6

B6

C6

D6

E6

F6

G6

H6

A13

A12

A14

A15

A16

BYTE# DQ15/A-1 V_SS

A5

A9

B5

A8

C5

D5

E5

F5

G5

H5

A10

A11

DQ7

DQ14

DQ13

DQ6

A4

B4

C4

D4

E4

F4

G4

H4

WE# RESET#

NC

DQ5

DQ12

V_CC

DQ4

A3

B3

C3

D3

E3

F3

G3

H3

RY/BY#

NC

DQ2

DQ10

DQ11

DQ3

A2

A7

B2

C2

A6

D2

A5

E2

F2

G2

H2

A17

DQ0

DQ8

DQ9

DQ1

A1

A3

B1

A4

C1

A2

D1

A1

E1

A0

F1

G1

H1

CE#

OE#

V_SS

6

Am29LV400B

Flash memory devices in FBGA packages may be

damaged if exposed to ultrasonic cleaning methods.

The package and/or data integrity may be compro-

mised if the package body is exposed to temperatures

above 150°C for prolonged periods of time.

Special Handling Instructions for Fine

Pitch Ball Grid Array (FBGA)

Special handling is required for Flash Memory products

in FBGA packages.

PIN CONFIGURATION

LOGIC SYMBOL

A0–A17

=

18 addresses

18

DQ0–DQ14 = 15 data inputs/outputs

A0–A17

16 or 8

DQ15/A-1

=

DQ15 (data input/output, word mode),

A-1 (LSB address input, byte mode)

DQ0–DQ15

(A-1)

BYTE#

CE#

=

Selects 8-bit or 16-bit mode

Chip enable

CE#

OE#

Output enable

WE#

Write enable

RESET#

BYTE#

RESET#

RY/BY#

V_CC

Hardware reset pin, active low

Ready/Busy# output

RY/BY#

3.0 volt-only single power supply

(see Product Selector Guide for speed

options and voltage supply tolerances)

V_SS

NC

=

Device ground

Pin not connected internally

Am29LV400B

7

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-

nation) is formed by a combination of the elements below.

Am29LV400B

T

-55R

E

C

TEMPERATURE RANGE

C

I

=

Commercial (0°C to +70°C)

Industrial (–40°C to +85°C)

Extended (–55°C to +125°C)

E

PACKAGE TYPE

E

=

48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048)

48-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR048)

44-Pin Small Outline Package (SO 044)

F

S

WA

48-Ball Fine Pitch Ball Grid Array (FBGA)

0.80 mm pitch, 6 x 8 mm package (FBA048)

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T

B

=

Top sector

Bottom sector

DEVICE NUMBER/DESCRIPTION

Am29LV400B

4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program, and Erase

Valid Combinations for TSOP and SO Packages

Valid Combinations for FBGA Packages

AM29LV400BT55R,

AM29LV400BB55R

EC, EI, FC,

FI, SC, SI

Order Number

Package Marking

AM29LV400BT55R,

AM29LV400BB55R

WAC, L400BT55R,

WAI L400BB55R

C, I

AM29LV400BT70,

AM29LV400BB70

AM29LV400BT70,

AM29LV400BB70

L400BT70V,

L400BB70V

EC, EI, EE,

FC, FI, FE,

SC, SI, SE

AM29LV400BT90,

AM29LV400BB90

WAC,

AM29LV400BT90,

AM29LV400BB90

L400BT90V,

WAI,

C, I, E

AM29LV400BT120,

AM29LV400BB120

L400BB90V

WAE

AM29LV400BT120,

AM29LV400BB120

L400BT12V,

L400BB12V

Valid Combinations

Valid Combinations list configurations planned to be sup-

ported in volume for this device. Consult the local AMD sales

office to confirm availability of specific valid combinations and

to check on newly released combinations.

8

Am29LV400B

DEVICE BUS OPERATIONS

This section describes the requirements and use of the

device bus operations, which are initiated through the

internal command register. The command register

itself does not occupy any addressable memory loca-

tion. The register is composed of latches that store the

commands, along with the address and data informa-

tion needed to execute the command. The contents of

the register serve as inputs to the internal state

machine. The state machine outputs dictate the func-

tion of the device. Table 1 lists the device bus

operations, the inputs and control levels they require,

and the resulting output. The following subsections

describe each of these operations in further detail.

Table 1. Am29LV400B Device Bus Operations

DQ8–DQ15

BYTE#

= V

Addresses

(Note 1)

DQ0– BYTE#

Operation

CE# OE# WE# RESET#

DQ7

= V

IH

IL

Read

L

H

A

D

DQ8–DQ14 = High-Z,

DQ15 = A-1

IN

OUT

Write

L

H

L

H

A

D

IN

V

0.3 V

±

V

0.3 V

±

CC

Standby

X

High-Z High-Z

High-Z

Output Disable

Reset

L

H

X

H

X

H

L

X

High-Z High-Z

High-Z

X

Sector Address, A6 = L,

A1 = H, A0 = L

Sector Protect (Note 2)

L

H

X

L

V

D

X

ID

IN

Sector Address, A6 = H,

A1 = H, A0 = L

Sector Unprotect (Note 2)

Temporary Sector

Unprotect

X

A

D

High-Z

IN

Legend:

L = Logic Low = V , H = Logic High = V , V = 12.0 ± 0.5 V, X = Don’t Care, A = Addresses In, D = Data In, D = Data Out

IL

IH ID

IN

OUT

Notes:

1. Addresses are A17:A0 in word mode (BYTE# = V ), A17:A-1 in byte mode (BYTE# = V ).

IH

IL

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector

Protection/Unprotection” section.

The internal state machine is set for reading array data

Word/Byte Configuration

upon device power-up, or after a hardware reset. This

The BYTE# pin controls whether the device data I/O

ensures that no spurious alteration of the memory

pins DQ15–DQ0 operate in the byte or word configura-

content occurs during the power transition. No

tion. If the BYTE# pin is set at logic ‘1’, the device is in

command is necessary in this mode to obtain array

word configuration, DQ15–DQ0 are active and con-

data. Standard microprocessor read cycles that assert

trolled by CE# and OE#.

valid addresses on the device address inputs produce

If the BYTE# pin is set at logic ‘0’, the device is in byte

configuration, and only data I/O pins DQ0–DQ7 are

active and controlled by CE# and OE#. The data I/O

pins DQ8–DQ14 are tri-stated, and the DQ15 pin is

used as an input for the LSB (A-1) address function.

valid data on the device data outputs. The device

remains enabled for read access until the command

register contents are altered.

Address access time (t_ACC) is the delay from stable

addresses to valid output data. The chip enable access

time (t_CE) is the delay from stable addresses and stable

CE# to valid data at the output pins. The output enable

access time (t_OE) is the delay from the falling edge of

OE# to valid data at the output pins (assuming the

addresses have been stable for at least t_ACC–t_OEtime).

Requirements for Reading Array Data

To read array data from the outputs, the system must

drive the CE# and OE# pins to V_IL. CE# is the power

control and selects the device. OE# is the output

control and gates array data to the output pins. WE#

should remain at V_IH. The BYTE# pin determines

whether the device outputs array data in words or

bytes.

See “Reading Array Data” for more information. Refer

to the AC Read Operations table for timing specifica-

tions and to Figure 13 for the timing diagram. I_CC1in the

Am29LV400B

9

DC Characteristics table represents the active current

specification for reading array data.

The device enters the CMOS standby mode when the

CE# and RESET# pins are both held at V_CC± 0.3 V.

(Note that this is a more restricted voltage range than

V_IH.) If CE# and RESET# are held at V_IH, but not within

Writing Commands/Command Sequences

V

_CC± 0.3 V, the device will be in the standby mode, but

To write a command or command sequence (which

includes programming data to the device and erasing

sectors of memory), the system must drive WE# and

CE# to V_IL, and OE# to V_IH.

the standby current will be greater. The device requires

standard access time (t_CE) for read access when the

device is in either of these standby modes, before it is

ready to read data.

For program operations, the BYTE# pin determines

whether the device accepts program data in bytes or

words. Refer to “Word/Byte Configuration” for more

information.

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

I_CC3in the DC Characteristics table represents the

standby current specification.

The device features an Unlock Bypass mode to facili-

tate faster programming. Once the device enters the

Unlock Bypass mode, only two write cycles are

required to program a word or byte, instead of four. The

“Word/Byte Program Command Sequence” section

has details on programming data to the device using

both standard and Unlock Bypass command

sequences.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device

energy consumption. The device automatically enables

this mode when addresses remain stable for t_ACC+ 30

ns. The automatic sleep mode is independent of the

CE#, WE#, and OE# control signals. Standard address

access timings provide new data when addresses are

changed. While in sleep mode, output data is latched

and always available to the system. I_CC4in the DC

Characteristics table represents the automatic sleep

mode current specification.

An erase operation can erase one sector, multiple sec-

tors, or the entire device. Tables 2 and 3 indicate the

address space that each sector occupies. A “sector

address” consists of the address bits required to

uniquely select a sector. The “Command Definitions”

section has details on erasing a sector or the entire

chip, or suspending/resuming the erase operation.

RESET#: Hardware Reset Pin

After the system writes the autoselect command

sequence, the device enters the autoselect mode. The

system can then read autoselect codes from the

internal register (which is separate from the memory

array) on DQ7–DQ0. Standard read cycle timings apply

in this mode. Refer to the Autoselect Mode and Autose-

lect Command Sequence sections for more

information.

The RESET# pin provides a hardware method of reset-

ting the device to reading array data. When the

RESET# pin is driven low for at least a period of t_RP, the

device immediately terminates any operation in

progress, tristates all output pins, and ignores all

read/write commands for the duration of the RESET#

pulse. The device also resets the internal state

machine to reading array data. The operation that was

interrupted should be reinitiated once the device is

ready to accept another command sequence, to

ensure data integrity.

I_CC2in the DC Characteristics table represents the

active current specification for the write mode. The “AC

Characteristics” section contains timing specification

tables and timing diagrams for write operations.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at V_SS±0.3 V, the device

draws CMOS standby current (I_CC4). If RESET# is held

at V_ILbut not within V_SS±0.3 V, the standby current will

be greater.

Program and Erase Operation Status

During an erase or program operation, the system may

check the status of the operation by reading the status

bits on DQ7–DQ0. Standard read cycle timings and I_CC

read specifications apply. Refer to “Write Operation

Status” for more information, and to “AC Characteris-

tics” for timing diagrams.

If RESET# is asserted during a program or erase oper-

ation, the RY/BY# pin remains a “0” (busy) until the

internal reset operation is complete, which requires a

time of t_READY(during Embedded Algorithms). The

system can thus monitor RY/BY# to determine whether

the reset operation is complete. If RESET# is asserted

when a program or erase operation is not executing

(RY/BY# pin is “1”), the reset operation is completed

within a time of t_READY(not during Embedded Algo-

rithms). The system can read data t_RHafter the

RESET# pin returns to V_IH.

Standby Mode

When the system is not reading or writing to the device,

it can place the device in the standby mode. In this

mode, current consumption is greatly reduced, and the

outputs are placed in the high impedance state, inde-

pendent of the OE# input.

10

Am29LV400B

Refer to the AC Characteristics tables for RESET#

parameters and to Figure 14 for the timing diagram.

Output Disable Mode

When the OE# input is at V_IH, output from the device is

disabled. The output pins are placed in the high imped-

ance state.

Table 2. Am29LV400BT Top Boot Sector Address Table

Address Range (in hexadecimal)

Sector Size

(Kbytes/

(x8)

(x16)

Sector

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

A17

0

A16

0

A15

0

A14

X

0

A13

X

A12

X

Kwords)

Address Range

64/32

32/16

8/4

00000h–0FFFFh

10000h–1FFFFh

20000h–2FFFFh

30000h–3FFFFh

40000h–4FFFFh

50000h–5FFFFh

60000h–6FFFFh

70000h–77FFFh

78000h–79FFFh

7A000h–7BFFFh

7C000h–7FFFFh

00000h–07FFFh

08000h–0FFFFh

10000h–17FFFh

18000h–1FFFFh

20000h–27FFFh

28000h–2FFFFh

30000h–37FFFh

38000h–3BFFFh

3C000h–3CFFFh

3D000h–3DFFFh

3E000h–3FFFFh

0

1

X

0

1

0

X

0

1

X

1

0

X

1

0

1

X

1

0

X

1

X

1

0

1

0

1

8/4

1

X

16/8

Table 3. Am29LV400BB Bottom Boot Sector Address Table

Address Range (in hexadecimal)

Sector Size

(Kbytes/

(x8)

(x16)

Sector

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

A17

0

A16

0

A15

0

A14

0

A13

0

A12

X

Kwords)

Address Range

16/8

8/4

00000h–03FFFh

04000h–05FFFh

06000h–07FFFh

08000h–0FFFFh

10000h–1FFFFh

20000h–2FFFFh

30000h–3FFFFh

40000h–4FFFFh

50000h–5FFFFh

60000h–6FFFFh

70000h–7FFFFh

00000h–01FFFh

02000h–02FFFh

03000h–03FFFh

04000h–07FFFh

08000h–0FFFFh

10000h–17FFFh

18000h–1FFFFh

20000h–27FFFh

28000h–2FFFFh

30000h–37FFFh

38000h–3FFFFh

0

1

0

1

8/4

0

1

X

32/16

64/32

0

1

X

0

1

0

X

0

1

X

1

0

X

1

0

1

X

1

0

X

1

X

Note for Tables 2 and 3: Address range is A17:A-1 in byte mode and A17:A0 in word mode. See “Word/Byte Configuration”

section.

Am29LV400B

11

Table 4. In addition, when verifying sector protection,

the sector address must appear on the appropriate

highest order address bits (see Tables 2 and 3). Table

4 shows the remaining address bits that are don’t care.

When all necessary bits have been set as required, the

programming equipment may then read the corre-

sponding identifier code on DQ7–DQ0.

Autoselect Mode

The autoselect mode provides manufacturer and

device identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This

mode is primarily intended for programming equipment

to automatically match a device to be programmed with

its corresponding programming algorithm. However,

the autoselect codes can also be accessed in-system

through the command register.

To access the autoselect codes in-system, the host

system can issue the autoselect command via the

command register, as shown in Table 5. This method

does not require V_ID. See “Command Definitions” for

details on using the autoselect mode.

When using programming equipment, the autoselect

mode requires V_ID(11.5 V to 12.5 V) on address pin

A9. Address pins A6, A1, and A0 must be as shown in

Table 4. Am29LV400B Autoselect Codes (High Voltage Method)

A17 A11

to to

Mode CE# OE# WE# A12 A10 A9

A8

to

A7

A5

to

A2

DQ8

to

A0 DQ15

DQ7

to

DQ0

Description

A6

A1

Manufacturer ID: AMD

L

H

X

V

X

L

X

L

X

01h

B9h

ID

Device ID:

Am29LV400B

(Top Boot Block)

Word

Byte

Word

Byte

22h

X

V

L

H

ID

L

H

X

22h

X

B9h

BAh

Device ID:

Am29LV400B

(Bottom Boot Block)

X

V

X

H

L

ID

01h

(protected)

X

Sector Protection Verification

L

H

SA

L

H

ID

00h

(unprotected)

L = Logic Low = V , H = Logic High = V , SA = Sector Address, X = Don’t care.

IL

IH

The alternate method intended only for programming

equipment requires V_IDon address pin A9 and OE#.

This method is compatible with programmer routines

written for earlier 3.0 volt-only AMD flash devices. Pub-

lication number 20873 contains further details; contact

an AMD representative to request a copy.

Sector Protection/Unprotection

The hardware sector protection feature disables both

program and erase operations in any sector. The hard-

ware sector unprotection feature re-enables both

program and erase operations in previously protected

sectors. Sector protection/unprotection can be imple-

mented via two methods.

The device is shipped with all sectors unprotected.

AMD offers the option of programming and protecting

sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Service. Contact an

AMD representative for details.

The primary method requires V_IDon the RESET# pin

only, and can be implemented either in-system or via

programming equipment. Figure 1 shows the algo-

rithms and Figure 23 shows the timing diagram. This

method uses standard microprocessor bus cycle

timing. For sector unprotect, all unprotected sectors

must first be protected prior to the first sector unprotect

write cycle.

It is possible to determine whether a sector is protected

or unprotected. See “Autoselect Mode” for details.

12

Am29LV400B

START

Protect all sectors:

The indicated portion

of the sector protect

algorithm must be

performed for all

PLSCNT = 1

RESET# = V_ID

unprotected sectors

prior to issuing the

first sector

Wait 1 µs

unprotect address

No

First Write

No

First Write

Cycle = 60h?

Temporary Sector

Unprotect Mode

Temporary Sector

Unprotect Mode

Cycle = 60h?

Yes

Set up sector

address

No

All sectors

protected?

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Yes

Set up first sector

address

Sector Unprotect:

Wait 150 µs

Write 60h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

Reset

PLSCNT = 1

Increment

PLSCNT

Wait 15 ms

A1 = 1, A0 = 0

Verify Sector

Unprotect: Write

40h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

Increment

PLSCNT

No

PLSCNT

= 25?

Read from

sector address

with A6 = 1,

Data = 01h?

Yes

A1 = 1, A0 = 0

No

Yes

Set up

next sector

address

Yes

No

PLSCNT

= 1000?

Protect another

sector?

Data = 00h?

Yes

Device failed

No

Yes

Remove V_ID

from RESET#

No

Last sector

verified?

Device failed

Write reset

command

Yes

Remove V_ID

Sector Unprotect

Algorithm

from RESET#

Sector Protect

Algorithm

Sector Protect

complete

Write reset

command

Sector Unprotect

complete

Figure 1. In-System Sector Protect/Unprotect Algorithms

Am29LV400B

13

Temporary Sector Unprotect

Hardware Data Protection

This feature allows temporary unprotection of previ-

ously protected sectors to change data in-system. The

Sector Unprotect mode is activated by setting the

RESET# pin to V_ID. During this mode, formerly pro-

tected sectors can be programmed or erased by

selecting the sector addresses. Once V_IDis removed

from the RESET# pin, all the previously protected

sectors are protected again. Figure 2 shows the algo-

rithm, and Figure 22 shows the timing diagrams, for this

feature.

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes (refer to Table 5 for

command definitions). In addition, the following hard-

ware data protection measures prevent accidental

erasure or programming, which might otherwise be

caused by spurious system level signals during V_CC

power-up and power-down transitions, or from system

noise.

Low V

Write Inhibit

CC

When V_CCis less than V_LKO, the device does not

accept any write cycles. This protects data during V_CC

power-up and power-down. The command register and

all internal program/erase circuits are disabled, and the

device resets. Subsequent writes are ignored until V_CC

is greater than V_LKO. The system must provide the

proper signals to the control pins to prevent uninten-

START

RESET# = V

(Note 1)

ID

tional writes when V_CCis greater than V_LKO

.

Write Pulse “Glitch” Protection

Perform Erase or

Program Operations

Noise pulses of less than 5 ns (typical) on OE#, CE# or

WE# do not initiate a write cycle.

Logical Inhibit

RESET# = V

IH

Write cycles are inhibited by holding any one of OE# =

V_IL, CE# = V_IHor WE# = V_IH. To initiate a write cycle,

CE# and WE# must be a logical zero while OE# is a

logical one.

Temporary Sector

Unprotect Completed

(Note 2)

Power-Up Write Inhibit

If WE# = CE# = V_ILand OE# = V_IHduring power up, the

device does not accept commands on the rising edge

of WE#. The internal state machine is automatically

reset to reading array data on power-up.

Notes:

1. All protected sectors unprotected.

2. All previously protected sectors are protected once

again.

Figure 2. Temporary Sector Unprotect Operation

14

Am29LV400B

COMMAND DEFINITIONS

Writing specific address and data commands or

sequences into the command register initiates device

operations. Table 5 defines the valid register command

sequences. Writing incorrect address and data

values or writing them in the improper sequence

resets the device to reading array data.

however, the device ignores reset commands until the

operation is complete.

The reset command may be written between the

sequence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command must

be written to return to reading array data (also applies

to autoselect during Erase Suspend).

All addresses are latched on the falling edge of WE# or

CE#, whichever happens later. All data is latched on

the rising edge of WE# or CE#, whichever happens

first. Refer to the appropriate timing diagrams in the

“AC Characteristics” section.

If DQ5 goes high during a program or erase operation,

writing the reset command returns the device to

reading array data (also applies during Erase

Suspend).

Reading Array Data

Autoselect Command Sequence

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data. The device is also ready to read array

data after completing an Embedded Program or

Embedded Erase algorithm.

The autoselect command sequence allows the host

system to access the manufacturer and devices codes,

and determine whether or not a sector is protected.

Table 5 shows the address and data requirements. This

method is an alternative to that shown in Table 4, which

is intended for PROM programmers and requires V_ID

on address bit A9.

After the device accepts an Erase Suspend command,

the device enters the Erase Suspend mode. The

system can read array data using the standard read

timings, except that if it reads at an address within

erase-suspended sectors, the device outputs status

data. After completing a programming operation in the

Erase Suspend mode, the system may once again

read array data with the same exception. See “Erase

Suspend/Erase Resume Commands” for more infor-

mation on this mode.

The autoselect command sequence is initiated by

writing two unlock cycles, followed by the autoselect

command. The device then enters the autoselect

mode, and the system may read at any address any

number of times, without initiating another command

sequence. A read cycle at address XX00h retrieves the

manufacturer code. A read cycle at address XX01h in

word mode (or 02h in byte mode) returns the device

code. A read cycle containing a sector address (SA)

and the address 02h in word mode (or 04h in byte

mode) returns 01h if that sector is protected, or 00h if it

is unprotected. Refer to Tables 2 and 3 for valid sector

addresses.

The system must issue the reset command to re-

enable the device for reading array data if DQ5 goes

high, or while in the autoselect mode. See the “Reset

Command” section, next.

See also “Requirements for Reading Array Data” in the

“Device Bus Operations” section for more information.

The Read Operations table provides the read parame-

ters, and Figure 13 shows the timing diagram.

The system must write the reset command to exit the

autoselect mode and return to reading array data.

Word/Byte Program Command Sequence

Reset Command

The system may program the device by word or byte,

depending on the state of the BYTE# pin. Program-

ming is a four-bus-cycle operation. The program

command sequence is initiated by writing two unlock

write cycles, followed by the program set-up command.

The program address and data are written next, which

in turn initiate the Embedded Program algorithm. The

system is not required to provide further controls or tim-

ings. The device automatically generates the program

pulses and verifies the programmed cell margin. Table

5 shows the address and data requirements for the

byte program command sequence.

Writing the reset command to the device resets the

device to reading array data. Address bits are don’t

care for this command.

The reset command may be written between the

sequence cycles in an erase command sequence

before erasing begins. This resets the device to reading

array data. Once erasure begins, however, the device

ignores reset commands until the operation is

complete.

The reset command may be written between the

sequence cycles in a program command sequence

before programming begins. This resets the device to

reading array data (also applies to programming in

Erase Suspend mode). Once programming begins,

When the Embedded Program algorithm is complete,

the device then returns to reading array data and

addresses are no longer latched. The system can

determine the status of the program operation by using

Am29LV400B

15

DQ7, DQ6, or RY/BY#. See “Write Operation Status”

for information on these status bits.

START

Any commands written to the device during the

Embedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the program-

ming operation. The Byte Program command

sequence should be reinitiated once the device has

reset to reading array data, to ensure data integrity.

Write Program

Command Sequence

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

from a “0” back to a “1”. Attempting to do so may halt

the operation and set DQ5 to “1”, or cause the Data#

Polling algorithm to indicate the operation was suc-

cessful. However, a succeeding read will show that the

data is still “0”. Only erase operations can convert a “0”

to a “1”.

Data Poll

from System

Embedded

Program

algorithm

in progress

Verify Data?

Yes

No

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to

program bytes or words to the device faster than using

the standard program command sequence. The unlock

bypass command sequence is initiated by first writing

two unlock cycles. This is followed by a third write cycle

containing the unlock bypass command, 20h. The

device then enters the unlock bypass mode. A two-

cycle unlock bypass program command sequence is all

that is required to program in this mode. The first cycle

in this sequence contains the unlock bypass program

command, A0h; the second cycle contains the program

address and data. Additional data is programmed in

the same manner. This mode dispenses with the initial

two unlock cycles required in the standard program

command sequence, resulting in faster total program-

ming time. Table 5 shows the requirements for the

command sequence.

No

Increment Address

Last Address?

Yes

Programming

Completed

Note: See Table 5 for program command sequence.

Figure 3. Program Operation

During the unlock bypass mode, only the Unlock

Bypass Program and Unlock Bypass Reset commands

are valid. To exit the unlock bypass mode, the system

must issue the two-cycle unlock bypass reset

command sequence. The first cycle must contain the

program address and the data 90h. The second cycle

need only contain the data 00h. The device then

returns to reading array data.

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does not require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the entire

memory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operations. Table 5 shows

the address and data requirements for the chip erase

command sequence.

Figure 3 illustrates the algorithm for the program oper-

ation. See the Erase/Program Operations table in “AC

Characteristics” for parameters, and to Figure 17 for

timing diagrams.

Any commands written to the chip during the

Embedded Erase algorithm are ignored. Note that a

hardware reset during the chip erase operation imme-

diately terminates the operation. The Chip Erase

command sequence should be reinitiated once the

16

Am29LV400B

device has returned to reading array data, to ensure

data integrity.

operation. The Sector Erase command sequence

should be reinitiated once the device has returned to

reading array data, to ensure data integrity.

The system can determine the status of the erase oper-

ation by using DQ7, DQ6, DQ2, or RY/BY#. See “Write

Operation Status” for information on these status bits.

When the Embedded Erase algorithm is complete, the

device returns to reading array data and addresses are

no longer latched.

When the Embedded Erase algorithm is complete, the

device returns to reading array data and addresses are

no longer latched. The system can determine the

status of the erase operation by using DQ7, DQ6, DQ2,

or RY/BY#. (Refer to “Write Operation Status” for infor-

mation on these status bits.)

Figure 4 illustrates the algorithm for the erase opera-

tion. See the Erase/Program Operations tables in “AC

Characteristics” for parameters, and to Figure 18 for

timing diagrams.

Figure 4 illustrates the algorithm for the erase opera-

tion. Refer to the Erase/Program Operations tables in

the “AC Characteristics” section for parameters, and to

Figure 18 for timing diagrams.

Sector Erase Command Sequence

Erase Suspend/Erase Resume Commands

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two

additional unlock write cycles are then followed by the

address of the sector to be erased, and the sector

erase command. Table 5 shows the address and data

requirements for the sector erase command sequence.

The Erase Suspend command allows the system to

interrupt a sector erase operation and then read data

from, or program data to, any sector not selected for

erasure. This command is valid only during the sector

erase operation, including the 50 µs time-out period

during the sector erase command sequence. The

Erase Suspend command is ignored if written during

the chip erase operation or Embedded Program algo-

rithm. Writing the Erase Suspend command during the

Sector Erase time-out immediately terminates the

time-out period and suspends the erase operation.

Addresses are “don’t-cares” when writing the Erase

Suspend command.

The device does not require the system to preprogram

the memory prior to erase. The Embedded Erase algo-

rithm automatically programs and verifies the sector for

an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or

timings during these operations.

After the command sequence is written, a sector erase

time-out of 50 µs begins. During the time-out period,

additional sector addresses and sector erase com-

mands may be written. Loading the sector erase buffer

may be done in any sequence, and the number of

sectors may be from one sector to all sectors. The time

between these additional cycles must be less than 50

µs, otherwise the last address and command might not

be accepted, and erasure may begin. It is recom-

mended that processor interrupts be disabled during

this time to ensure all commands are accepted. The

interrupts can be re-enabled after the last Sector Erase

command is written. If the time between additional

sector erase commands can be assumed to be less

than 50 µs, the system need not monitor DQ3. Any

command other than Sector Erase or Erase

Suspend during the time-out period resets the

device to reading array data. The system must

rewrite the command sequence and any additional

sector addresses and commands.

When the Erase Suspend command is written during a

sector erase operation, the device requires a maximum

of 20 µs to suspend the erase operation. However,

when the Erase Suspend command is written during

the sector erase time-out, the device immediately ter-

minates the time-out period and suspends the erase

operation.

After the erase operation has been suspended, the

system can read array data from or program data to

any sector not selected for erasure. (The device “erase

suspends” all sectors selected for erasure.) Normal

read and write timings and command definitions apply.

Reading at any address within erase-suspended

sectors produces status data on DQ7–DQ0. The

system can use DQ7, or DQ6 and DQ2 together, to

determine if a sector is actively erasing or is erase-sus-

pended. See “Write Operation Status” for information

on these status bits.

After an erase-suspended program operation is com-

plete, the system can once again read array data within

non-suspended sectors. The system can determine

the status of the program operation using the DQ7 or

DQ6 status bits, just as in the standard program oper-

ation. See “Write Operation Status” for more

information.

The system can monitor DQ3 to determine if the sector

erase timer has timed out. (See the “DQ3: Sector Erase

Timer” section.) The time-out begins from the rising

edge of the final WE# pulse in the command sequence.

Once the sector erase operation has begun, only the

Erase Suspend command is valid. All other commands

are ignored. Note that a hardware reset during the

sector erase operation immediately terminates the

The system may also write the autoselect command

sequence when the device is in the Erase Suspend

Am29LV400B

17

mode. The device allows reading autoselect codes

even at addresses within erasing sectors, since the

codes are not stored in the memory array. When the

device exits the autoselect mode, the device reverts to

the Erase Suspend mode, and is ready for another

valid operation. See “Autoselect Command Sequence”

for more information.

START

Write Erase

Command Sequence

The system must write the Erase Resume command

(address bits are “don’t care”) to exit the erase suspend

mode and continue the sector erase operation. Further

writes of the Resume command are ignored. Another

Erase Suspend command can be written after the

device has resumed erasing.

Data Poll

from System

Embedded

Erase

algorithm

in progress

No

Data = FFh?

Yes

Erasure Completed

Notes:

1. See Table 5 for erase command sequence.

2. See “DQ3: Sector Erase Timer” for more information.

Figure 4. Erase Operation

18

Am29LV400B

Command Definitions

Table 5. Am29LV400B Command Definitions

Bus Cycles (Notes 2–5)

Command

Sequence

(Note 1)

First

Second

Third

Addr

Fourth

Fifth

Sixth

Addr Data Addr Data

Data Addr Data Addr Data Addr Data

Read (Note 6)

Reset (Note 7)

1

RA

XXX

555

RD

F0

Word

2AA

555

2AA

555

2AA

555

AAA

555

Manufacturer ID

4

AA

55

90

X00

01

Byte

Word

Byte

Word

Byte

AAA

555

X01 22B9

X02

B9

X01 22BA

Device ID,

Top Boot Block

AAA

555

AAA

555

Device ID,

Bottom Boot Block

AAA

X02

BA

XX00

XX01

00

(SA)

X02

Word

Byte

555

2AA

555

Sector Protect Verify

(Note 9)

4

AA

55

90

(SA)

X04

AAA

01

Word

Byte

Word

Byte

555

AAA

555

2AA

555

2AA

555

PA

555

AAA

555

Program

Unlock Bypass

4

3

AA

55

A0

20

PA

PD

AAA

XXX

555

AAA

Unlock Bypass Program (Note 10)

Unlock Bypass Reset (Note 11)

2

A0

90

PD

00

XXX

2AA

555

2AA

555

Word

555

AAA

555

AAA

555

2AA

555

2AA

555

Chip Erase

Byte

6

AA

55

80

AA

55

10

30

AAA

555

AAA

Word

Sector Erase

Byte

SA

AAA

XXX

AAA

Erase Suspend (Note 12)

Erase Resume (Note 13)

1

B0

30

Legend:

X = Don’t care

PD = Data to be programmed at location PA. Data latches on the

rising edge of WE# or CE# pulse, whichever happens first.

RA = Address of the memory location to be read.

SA = Address of the sector to be verified (in autoselect mode) or

erased. Address bits A17–A12 uniquely select any sector.

RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed.

Addresses latch on the falling edge of the WE# or CE# pulse,

whichever happens later.

Notes:

1. See Table 1 for description of bus operations.

9. The data is 00h for an unprotected sector and 01h for a

protected sector. See “Autoselect Command Sequence” for

more information.

2. All values are in hexadecimal.

3. Except when reading array or autoselect data, all bus cycles

are write operations.

10. The Unlock Bypass command is required prior to the Unlock

Bypass Program command.

4. Data bits DQ15–DQ8 are don’t cares for unlock and

command cycles.

11. The Unlock Bypass Reset command is required to return to

reading array data when the device is in the unlock bypass

mode.

5. Address bits A17–A11 are don’t cares for unlock and

command cycles, except when SA or PA required.

12. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend

mode. The Erase Suspend command is valid only during a

sector erase operation.

6. No unlock or command cycles required when reading array

data.

7. The Reset command is required to return to reading array

data when device is in the autoselect mode, or if DQ5 goes

high (while the device is providing status data).

13. The Erase Resume command is valid only during the Erase

Suspend mode.

8. The fourth cycle of the autoselect command sequence is a

read cycle.

Am29LV400B

19

WRITE OPERATION STATUS

The device provides several bits to determine the

status of a write operation: DQ2, DQ3, DQ5, DQ6,

DQ7, and RY/BY#. Table 6 and the following subsec-

tions describe the functions of these bits. DQ7,

RY/BY#, and DQ6 each offer a method for determining

whether a program or erase operation is complete or in

progress. These three bits are discussed first.

Table 6 shows the outputs for Data# Polling on DQ7.

Figure 5 shows the Data# Polling algorithm.

START

DQ7: Data# Polling

Read DQ7–DQ0

Addr = VA

The Data# Polling bit, DQ7, indicates to the host

system whether an Embedded Algorithm is in progress

or completed, or whether the device is in Erase Sus-

pend. Data# Polling is valid after the rising edge of the

final WE# pulse in the program or erase command

sequence.

Yes

DQ7 = Data?

During the Embedded Program algorithm, the device

outputs on DQ7 the complement of the datum pro-

grammed to DQ7. This DQ7 status also applies to

programming during Erase Suspend. When the

Embedded Program algorithm is complete, the device

outputs the datum programmed to DQ7. The system

must provide the program address to read valid status

information on DQ7. If a program address falls within a

protected sector, Data# Polling on DQ7 is active for

approximately 1 µs, then the device returns to reading

array data.

No

DQ5 = 1?

Yes

Read DQ7–DQ0

Addr = VA

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase

algorithm is complete, or if the device enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7.

This is analogous to the complement/true datum output

described for the Embedded Program algorithm: the

erase function changes all the bits in a sector to “1”;

prior to this, the device outputs the “complement,” or

“0.” The system must provide an address within any of

the sectors selected for erasure to read valid status

information on DQ7.

Yes

DQ7 = Data?

No

PASS

FAIL

After an erase command sequence is written, if all

sectors selected for erasing are protected, Data#

Polling on DQ7 is active for approximately 100 µs, then

the device returns to reading array data. If not all

selected sectors are protected, the Embedded Erase

algorithm erases the unprotected sectors, and ignores

the selected sectors that are protected.

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is an address within any

sector selected for erasure. During chip erase, a valid

address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

When the system detects DQ7 has changed from the

complement to true data, it can read valid data at DQ7–

DQ0 on the following read cycles. This is because DQ7

may change asynchronously with DQ0–DQ6 while

Output Enable (OE#) is asserted low. Figure 19, Data#

Polling Timings (During Embedded Algorithms), in the

“AC Characteristics” section illustrates this.

Figure 5. Data# Polling Algorithm

20

Am29LV400B

Table 6 shows the outputs for Toggle Bit I on DQ6.

Figure 6 shows the toggle bit algorithm. Figure 20 in the

“AC Characteristics” section shows the toggle bit timing

diagrams. Figure 21 shows the differences between

DQ2 and DQ6 in graphical form. See also the subsec-

tion on DQ2: Toggle Bit II.

RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin that

indicates whether an Embedded Algorithm is in

progress or complete. The RY/BY# status is valid after

the rising edge of the final WE# pulse in the command

sequence. Since RY/BY# is an open-drain output,

several RY/BY# pins can be tied together in parallel

DQ2: Toggle Bit II

with a pull-up resistor to V_CC

.

The “Toggle Bit II” on DQ2, when used with DQ6, indi-

cates whether a particular sector is actively erasing

(that is, the Embedded Erase algorithm is in progress),

or whether that sector is erase-suspended. Toggle Bit

II is valid after the rising edge of the final WE# pulse in

the command sequence.

If the output is low (Busy), the device is actively erasing

or programming. (This includes programming in the

Erase Suspend mode.) If the output is high (Ready),

the device is ready to read array data (including during

the Erase Suspend mode), or is in the standby mode.

Table 6 shows the outputs for RY/BY#. Figures 14, 17

and 18 shows RY/BY# for reset, program, and erase

operations, respectively.

DQ2 toggles when the system reads at addresses

within those sectors that have been selected for era-

sure. (The system may use either OE# or CE# to

control the read cycles.) But DQ2 cannot distinguish

whether the sector is actively erasing or is erase-sus-

pended. DQ6, by comparison, indicates whether the

device is actively erasing, or is in Erase Suspend, but

cannot distinguish which sectors are selected for era-

sure. Thus, both status bits are required for sector and

mode information. Refer to Table 6 to compare outputs

for DQ2 and DQ6.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded

Program or Erase algorithm is in progress or complete,

or whether the device has entered the Erase Suspend

mode. Toggle Bit I may be read at any address, and is

valid after the rising edge of the final WE# pulse in the

command sequence (prior to the program or erase

operation), and during the sector erase time-out.

Figure 6 shows the toggle bit algorithm in flowchart

form, and the section “DQ2: Toggle Bit II” explains the

algorithm. See also the DQ6: Toggle Bit I subsection.

Figure 20 shows the toggle bit timing diagram. Figure

21 shows the differences between DQ2 and DQ6 in

graphical form.

During an Embedded Program or Erase algorithm

operation, successive read cycles to any address

cause DQ6 to toggle. The system may use either OE#

or CE# to control the read cycles. When the operation

is complete, DQ6 stops toggling.

After an erase command sequence is written, if all

sectors selected for erasing are protected, DQ6 toggles

for approximately 100 µs, then returns to reading array

data. If not all selected sectors are protected, the

Embedded Erase algorithm erases the unprotected

sectors, and ignores the selected sectors that are

protected.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 6 for the following discussion. When-

ever the system initially begins reading toggle bit

status, it must read DQ7–DQ0 at least twice in a row to

determine whether a toggle bit is toggling. Typically, the

system would note and store the value of the toggle bit

after the first read. After the second read, the system

would compare the new value of the toggle bit with the

first. If the toggle bit is not toggling, the device has com-

pleted the program or erase operation. The system can

read array data on DQ7–DQ0 on the following read

cycle.

The system can use DQ6 and DQ2 together to deter-

mine whether a sector is actively erasing or is erase-

suspended. When the device is actively erasing (that is,

the Embedded Erase algorithm is in progress), DQ6

toggles. When the device enters the Erase Suspend

mode, DQ6 stops toggling. However, the system must

also use DQ2 to determine which sectors are erasing

or erase-suspended. Alternatively, the system can use

DQ7 (see the subsection on DQ7: Data# Polling).

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the

system also should note whether the value of DQ5 is

high (see the section on DQ5). If it is, the system

should then determine again whether the toggle bit is

toggling, since the toggle bit may have stopped tog-

gling just as DQ5 went high. If the toggle bit is no longer

toggling, the device has successfully completed the

program or erase operation. If it is still toggling, the

device did not completed the operation successfully,

and the system must write the reset command to return

to reading array data.

If a program address falls within a protected sector,

DQ6 toggles for approximately 2 µs after the program

command sequence is written, then returns to reading

array data.

DQ6 also toggles during the erase-suspend-program

mode, and stops toggling once the Embedded

Program algorithm is complete.

Am29LV400B

21

The remaining scenario is that the system initially

determines that the toggle bit is toggling and DQ5 has

not gone high. The system may continue to monitor the

toggle bit and DQ5 through successive read cycles,

determining the status as described in the previous

paragraph. Alternatively, it may choose to perform

other system tasks. In this case, the system must start

at the beginning of the algorithm when it returns to

determine the status of the operation (top of Figure 6).

START

Read DQ7–DQ0

(Note 1)

Read DQ7–DQ0

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has

exceeded a specified internal pulse count limit. Under

these conditions DQ5 produces a “1.” This is a failure

condition that indicates the program or erase cycle was

not successfully completed.

No

Toggle Bit

= Toggle?

Yes

The DQ5 failure condition may appear if the system

tries to program a “1” to a location that is previously pro-

grammed to “0.” Only an erase operation can change

a “0” back to a “1.” Under this condition, the device

halts the operation, and when the operation has

exceeded the timing limits, DQ5 produces a “1.”

No

DQ5 = 1?

Yes

Under both these conditions, the system must issue the

reset command to return the device to reading array

data.

(Notes

1, 2)

Read DQ7–DQ0

Twice

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not an

erase operation has begun. (The sector erase timer

does not apply to the chip erase command.) If addi-

tional sectors are selected for erasure, the entire time-

out also applies after each additional sector erase com-

mand. When the time-out is complete, DQ3 switches

from “0” to “1.” If the time between additional sector

erase commands from the system can be assumed to

be less than 50 µs, the system need not monitor DQ3.

See also the “Sector Erase Command Sequence”

section.

Toggle Bit

= Toggle?

No

Yes

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Notes:

1. Read toggle bit twice to determine whether or not it is

toggling. See text.

After the sector erase command sequence is written,

the system should read the status on DQ7 (Data#

Polling) or DQ6 (Toggle Bit I) to ensure the device has

accepted the command sequence, and then read DQ3.

If DQ3 is “1”, the internally controlled erase cycle has

begun; all further commands (other than Erase Sus-

pend) are ignored until the erase operation is complete.

If DQ3 is “0”, the device will accept additional sector

erase commands. To ensure the command has been

accepted, the system software should check the status

of DQ3 prior to and following each subsequent sector

erase command. If DQ3 is high on the second status

check, the last command might not have been

accepted. Table 6 shows the outputs for DQ3.

2. Recheck toggle bit because it may stop toggling as DQ5

changes to “1” . See text.

Figure 6. Toggle Bit Algorithm

22

Am29LV400B

Table 6. Write Operation Status

DQ7

DQ5

DQ2

Operation

(Note 2)

DQ6

(Note 1)

DQ3

N/A

1

(Note 2)

RY/BY#

Embedded Program Algorithm

Embedded Erase Algorithm

DQ7#

0

Toggle

0

No toggle

Toggle

0

Standard

Mode

Reading within Erase

Suspended Sector

1

No toggle

0

N/A

Toggle

1

Erase

Suspend Reading within Non-Erase

Data

0

Data

N/A

Data

N/A

1

0

Mode

Suspended Sector

Erase-Suspend-Program

DQ7#

Toggle

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “DQ5: Exceeded Timing Limits” for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

Am29LV400B

23

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

20 ns

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –65°C to +125°C

+0.8 V

Voltage with Respect to Ground

–0.5 V

–2.0 V

V_CC(Note 1) . . . . . . . . . . . . . . . .–0.5 V to +4.0 V

A9, OE#, and

RESET# (Note 2). . . . . . . . . . . .–0.5 V to +12.5 V

20 ns

All other pins (Note 1) . . . . . –0.5 V to V_CC+0.5 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Figure 7. Maximum Negative

Overshoot Waveform

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During

voltage transitions, input or I/O pins may overshoot V to

SS

–2.0 V for periods of up to 20 ns. See Figure 7. Maximum

DC voltage on input or I/O pins is V +0.5 V. During

voltage transitions, input or I/O pins may overshoot to V

+2.0 V for periods up to 20 ns. See Figure 8.

CC

20 ns

CC

V

CC

2. Minimum DC input voltage on pins A9, OE#, and RESET#

is –0.5 V. During voltage transitions, A9, OE#, and

+2.0 V

V

CC

RESET# may overshoot V to –2.0 V for periods of up to

+0.5 V

SS

20 ns. See Figure 7. Maximum DC input voltage on pin A9

is +12.5 V which may overshoot to 14.0 V for periods up

to 20 ns.

2.0 V

20 ns

3. No more than one output may be shorted to ground at a

time. Duration of the short circuit should not be greater

than one second.

Figure 8. Maximum Positive

Overshoot Waveform

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This is

a stress rating only; functional operation of the device at

these or any other conditions above those indicated in the

operational sections of this data sheet is not implied.

Exposure of the device to absolute maximum rating

conditions for extended periods may affect device reliability.

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (T_A) . . . . . . . . . . . 0°C to +70°C

Industrial (I) Devices

Ambient Temperature (T_A) . . . . . . . . . –40°C to +85°C

Extended (E) Devices

Ambient Temperature (T_A) . . . . . . . . –55°C to +125°C

V_CCSupply Voltages

V_CCfor regulated voltage range. . . . .+3.0 V to +3.6 V

V_CCfor full voltage range . . . . . . . . .+2.7 V to +3.6 V

Operating ranges define those limits between which the

functionality of the device is guaranteed.

24

Am29LV400B

DC CHARACTERISTICS

CMOS Compatible

Parameter

Description

Test Conditions

= V to V

Min

Typ

Max

±1.0

35

Unit

µA

V

,

CC

IN

SS

I

Input Load Current

LI

= V

CC

CC max

I

A9 Input Load Current

Output Leakage Current

V

= V

; A9 = 12.5 V

µA

LIT

CC

CC max

V

= V to V

,

CC

OUT

SS

I

±1.0

µA

LO

= V

CC

CC max

5 MHz

1 MHz

5 MHz

1 MHz

7

2

7

2

12

4

CE# = V OE#

Byte Mode

V

IL,

=

IH,

V

Active Read Current

CC

I

mA

CC1

(Note 1)

12

4

CE# = V OE#

V

IL,

Word Mode

V

Active Write Current

CC

CE# = V OE#

V

15

30

CC2

IL,

=

IH

(Notes 2, 3, 5)

I

V

Standby Current (Note 2)

Reset Current (Note 2)

CE#, RESET# = V ±0.3 V

0.2

5

µA

CC3

CC

RESET# = V ± 0.3 V

CC4

SS

Automatic Sleep Mode

(Notes 2, 4)

I

V

= V ± 0.3 V; V = V ± 0.3 V

0.2

5

µA

CC5

IH

CC

IL

SS

V

Input Low Voltage

Input High Voltage

–0.5

0.8

V

IL

V

0.7 x V

V

+ 0.3

CC

IH

CC

Voltage for Autoselect and

Temporary Sector Unprotect

V

= 3.3 V

11.5

12.5

0.45

V

ID

CC

V

Output Low Voltage

I

= 4.0 mA, V = V

V

OL

OH

CC

CC min

V

= –2.0 mA, V = V

0.85 V

OH1

OH2

CC

CC min

CC

Output High Voltage

V

= –100 µA, V = V

V

–0.4

CC

Low V Lock-Out Voltage

(Note 4)

CC

V

2.3

2.5

V

LKO

Notes:

1. The I current listed is typically less than 2 mA/MHz, with OE# at V . Typical V is 3.0 V.

CC

IH

CC

2. Maximum I specifications are tested with V = V .

CCmax

CC

3. I active while Embedded Erase or Embedded Program is in progress.

CC

4. Automatic sleep mode enables the low power mode when addresses remain stable for t

5. Not 100% tested.

+ 30 ns.

ACC

Am29LV400B

25

DC CHARACTERISTICS

Zero Power Flash

20

15

10

5

0

500

1000

1500

2000

2500

3000

3500

4000

Time in ns

Note: Addresses are switching at 1 MHz

Figure 9. I_CC1Current vs. Time (Showing Active and Automatic Sleep Currents)

10

8

3.6 V

2.7 V

6

4

2

0

1

2

3

4

5

Frequency in MHz

Note: T = 25 °C

Figure 10. Typical I_CC1vs. Frequency

26

Am29LV400B

TEST CONDITIONS

Table 7. Test Specifications

3.3 V

55R,

70,

90,

120

Test Condition

Output Load

Unit

2.7 kΩ

Device

Under

Test

1 TTL gate

Output Load Capacitance, C

(including jig capacitance)

L

30

100

pF

C

L

6.2 kΩ

Input Rise and Fall Times

Input Pulse Levels

5

0.0–3.0

ns

V

Input timing measurement

reference levels

1.5

V

Note:Diodes are IN3064 or equivalent

Output timing measurement

reference levels

Figure 11. Test Setup

Key To Switching Waveforms

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

3.0 V

0.0 V

1.5 V

Input

Measurement Level

Output

Figure 12. Input Waveforms and Measurement Levels

Am29LV400B

27

AC CHARACTERISTICS

Read Operations

Parameter

Speed Options

JEDEC

Std

Description

Test Setup

Min

55R

70

90

120

Unit

t

Read Cycle Time (Note 1)

55

70

90

120

ns

AVAV

RC

CE# = V

OE# = V

IL

t

Address to Output Delay

Max

55

70

90

120

ns

AVQV

ACC

t

Chip Enable to Output Delay

OE# = V

Max

Min

55

30

25

0

70

30

25

90

35

30

120

50

ns

ELQV

GLQV

EHQZ

GHQZ

CE

IL

t

Output Enable to Output Delay

OE

t

Chip Enable to Output High Z (Note 1)

Output Enable to Output High Z (Note 1)

30

DF

t

30

Read

Output Enable

t

OEH

Toggle and

Data# Polling

Hold Time (Note 1)

Min

10

0

ns

Output Hold Time From Addresses, CE# or

OE#, Whichever Occurs First (Note 1)

t

OH

AXQX

Notes:

1. Not 100% tested.

2. See Figure 11 and Table 7 for test specifications.

t_RC

Addresses Stable

t_ACC

Addresses

CE#

t_DF

t_OE

OE#

t_OEH

WE#

t_CE

t_OH

HIGH Z

Output Valid

Outputs

RESET#

RY/BY#

0 V

Figure 13. Read Operations Timings

28

Am29LV400B

AC CHARACTERISTICS

Hardware Reset (RESET#)

Parameter

JEDEC

Std Description

RESET# Pin Low (During Embedded

Test Setup

Max

All Speed Options

Unit

t

20

µs

READY

Algorithms) to Read or Write (See Note)

RESET# Pin Low (NOT During Embedded

Algorithms) to Read or Write (See Note)

t

Max

500

ns

READY

t

RESET# Pulse Width

Min

500

50

20

0

ns

µs

ns

RP

RESET# High Time Before Read (See Note)

RESET# Low to Standby Mode

RY/BY# Recovery Time

RH

t

RPD

t

RB

Note: Not 100% tested.

RY/BY#

CE#, OE#

RESET#

t_RH

t_RP

t_Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t_Ready

RY/BY#

t_RB

CE#, OE#

RESET#

t_RP

Figure 14. RESET# Timings

Am29LV400B

29

AC CHARACTERISTICS

Word/Byte Configuration (BYTE#)

Parameter

Speed Options

JEDEC

Std

Description

55R

70

90

120

Unit

ns

t

CE# to BYTE# Switching Low or High

BYTE# Switching Low to Output HIGH Z

BYTE# Switching High to Output Active

Max

Min

5

ELFL/ ELFH

25

55

25

70

30

90

30

ns

FLQZ

FHQV

120

ns

CE#

OE#

BYTE#

t

ELFL

Data Output

(DQ0–DQ14)

Data Output

(DQ0–DQ7)

BYTE#

DQ0–DQ14

DQ15/A-1

Switching

from word

to byte

Address

Input

DQ15

Output

mode

t

FLQZ

t

ELFH

BYTE#

Switching

from byte

to word

Data Output

(DQ0–DQ7)

Data Output

(DQ0–DQ14)

DQ0–DQ14

DQ15/A-1

mode

Address

Input

DQ15

Output

t

FHQV

Figure 15. BYTE# Timings for Read Operations

CE#

The falling edge of the last WE# signal

WE#

BYTE#

t

SET

(t

)

AS

t

(t

)

HOLD AH

Note: Refer to the Erase/Program Operations table for t and t specifications.

AS

AH

Figure 16. BYTE# Timings for Write Operations

30

Am29LV400B

AC CHARACTERISTICS

Erase/Program Operations

Parameter

Speed Options

JEDEC

Std

Description

55R

70

90

120

Unit

ns

t

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

Data Setup Time

Min

55

70

90

120

AVAV

WC

t

0

ns

AVWL

WLAX

AS

AH

DS

DH

t

45

35

45

35

45

50

ns

t

ns

DVWH

WHDX

Data Hold Time

0

ns

t

Output Enable Setup Time

ns

OES

Read Recovery Time Before Write

(OE# High to WE# Low)

t

Min

0

ns

GHWL

t

CE# Setup Time

Min

Typ

Min

0

ns

ELWL

WHEH

WLWH

WHWL

CS

CH

WP

CE# Hold Time

t

Write Pulse Width

Write Pulse Width High

35

50

t

30

9

WPH

Byte

t

Programming Operation (Note 2)

µs

WHWH1

WHWH2

WHWH1

Word

11

0.7

50

0

t

Sector Erase Operation (Note 2)

sec

µs

WHWH2

t

V

Setup Time (Note 1)

VCS

CC

t

Recovery Time from RY/BY#

ns

RB

t

Program/Erase Valid to RY/BY# Delay

90

ns

BUSY

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

Am29LV400B

31

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

t_AS

PA

t_WC

Addresses

555h

PA

t_AH

CE#

OE#

t_CH

t_WHWH1

t_WP

WE#

Data

t_WPH

t_CS

t_DS

t_DH

PD

D_OUT

A0h

Status

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. PA = program address, PD = program data, D

is the true data at the program address.

OUT

2. Illustration shows device in word mode.

Figure 17. Program Operation Timings

32

Am29LV400B

AC CHARACTERISTICS

Erase Command Sequence (last two cycles)

Read Status Data

VA

t_AS

SA

t_WC

VA

Addresses

CE#

2AAh

555h for chip erase

t_AH

t_CH

OE#

t_WP

WE#

t_WPH

t_WHWH2

t_CS

t_DS

t_DH

In

Data

Complete

55h

30h

Progress

10 for Chip Erase

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).

2. Illustration shows device in word mode.

Figure 18. Chip/Sector Erase Operation Timings

Am29LV400B

33

AC CHARACTERISTICS

t_RC

VA

Addresses

VA

t_ACC

t_CE

CE#

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

High Z

DQ7

Valid Data

Complement

True

DQ0–DQ6

Valid Data

Status Data

True

Status Data

t_BUSY

RY/BY#

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.

Figure 19. Data# Polling Timings (During Embedded Algorithms)

t_RC

Addresses

CE#

VA

t_ACC

t_CE

VA

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

High Z

DQ6/DQ2

RY/BY#

Valid Status

(first read)

Valid Status

Valid Data

(second read)

(stops toggling)

t_BUSY

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read

cycle, and array data read cycle.

Figure 20. Toggle Bit Timings (During Embedded Algorithms)

34

Am29LV400B

AC CHARACTERISTICS

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase

Complete

WE#

Erase

Erase Suspend

Read

DQ6

DQ2

Note: The system may use OE# and CE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an

erase-suspended sector.

Figure 21. DQ2 vs. DQ6

Temporary Sector Unprotect

Parameter

JEDEC

Std

Description

Rise and Fall Time (See Note)

All Speed Options

Unit

t

V

Min

500

ns

VIDR

ID

RESET# Setup Time for Temporary Sector

Unprotect

t

4

µs

RSP

Note: Not 100% tested.

12 V

RESET#

0 or 3 V

t_VIDR

Program or Erase Command Sequence

CE#

WE#

t_RSP

RY/BY#

Figure 22. Temporary Sector Unprotect Timing Diagram

Am29LV400B

35

AC CHARACTERISTICS

V_ID

V_IH

RESET#

SA, A6,

A1, A0

Valid*

Sector Protect/Unprotect

60h 60h

Valid*

Status

Verify

40h

Data

Sector Protect: 150 µs

Sector Unprotect: 15 ms

1 µs

CE#

WE#

OE#

* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 23. Sector Protect/Unprotect Timing Diagram

36

Am29LV400B

AC CHARACTERISTICS

Alternate CE# Controlled Erase/Program Operations

Parameter

Speed Options

JEDEC

Std

Description

55R

70

90

120

Unit

ns

t

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

Data Setup Time

Min

55

70

90

120

AVAV

AVEL

ELAX

DVEH

EHDX

WC

t

0

ns

AS

AH

DS

DH

t

45

35

45

35

45

50

ns

t

ns

t

Data Hold Time

0

ns

t

Output Enable Setup Time

ns

OES

Read Recovery Time Before Write

(OE# High to WE# Low)

t

Min

0

ns

GHEL

WLEL

GHEL

t

WE# Setup Time

WE# Hold Time

Min

Typ

0

ns

WS

t

EHWH

WH

t

CE# Pulse Width

CE# Pulse Width High

35

50

ELEH

EHEL

CP

t

30

9

CPH

Byte

Word

Programming Operation

(Note 2)

t

µs

WHWH1

11

0.7

t

Sector Erase Operation (Note 2)

sec

WHWH2

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

Am29LV400B

37

AC CHARACTERISTICS

555 for program

PA for program

2AA for erase

SA for sector erase

555 for chip erase

Data# Polling

Addresses

PA

t_WC

t_WH

t_AS

t_AH

WE#

OE#

t_GHEL

t_{WHWH1 or 2}

t_CP

CE#

Data

t_WS

t_CPH

t_DS

t_BUSY

t_DH

DQ7#

D_OUT

t_RH

A0 for program

55 for erase

PD for program

30 for sector erase

10 for chip erase

RESET#

RY/BY#

Notes:

1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, DOUT = data written to the device.

2. Figure indicates the last two bus cycles of the command sequence.

3. Word mode address used as an example.

Figure 24. Alternate CE# Controlled Write Operation Timings

38

Am29LV400B

ERASE AND PROGRAMMING PERFORMANCE

Parameter

Typ (Note 1)

Max (Note 2)

Unit

s

Comments

Sector Erase Time

Chip Erase Time

0.7

11

9

15

Excludes 00h programming

prior to erasure (Note 4)

s

Byte Programming Time

Word Programming Time

300

360

13.5

8.7

µs

s

11

4.5

2.9

Excludes system level

overhead (Note 5)

Byte Mode

Word Mode

Chip Programming Time

(Note 3)

s

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 3.0 V V , 1,000,000 cycles. Additionally,

CC

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V = 2.7 V (3.0 V for regulated speed options), 1,000,000 cycles.

CC

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See

Table 5 for further information on command definitions.

6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Description

Min

Max

Input voltage with respect to V on all pins except I/O pins

(including A9, OE#, and RESET#)

SS

–1.0 V

12.5 V

Input voltage with respect to V on all I/O pins

–1.0 V

V

+ 1.0 V

CC

SS

V

Current

–100 mA

+100 mA

CC

Includes all pins except V . Test conditions: V = 3.0 V, one pin at a time.

CC

TSOP AND SO PIN CAPACITANCE

Parameter

Symbol

Parameter Description

Input Capacitance

Test Setup

Typ

6

Max

7.5

12

Unit

pF

C

V

= 0

IN

C

Output Capacitance

Control Pin Capacitance

V

= 0

8.5

7.5

pF

OUT

C

V

= 0

IN

9

pF

IN2

Notes:

1. Sampled, not 100% tested.

2. Test conditions T = 25°C, f = 1.0 MHz.

A

DATA RETENTION

Parameter

Test Conditions

150°C

Min

10

Unit

Years

Minimum Pattern Data Retention Time

125°C

20

Am29LV400B

39

PHYSICAL DIMENSIONS*

TS 048—48-Pin Standard TSOP

Dwg rev AA; 10/99

40

Am29LV400B

PHYSICAL DIMENSIONS

TSR048—48-Pin Reverse TSOP

Dwg rev AA; 10/99

* For reference only. BSC is an ANSI standard for Basic Space Centering.

Am29LV400B

41

PHYSICAL DIMENSIONS

FBA048—48-ball Fine-Pitch Ball Grid Array (FBGA)

6 x 8 mm package

Dwg rev AF; 10/99

42

Am29LV400B

PHYSICAL DIMENSIONS

SO 044—44-Pin Small Outline Package

Dwg rev AC; 10/99

43

Am29LV400B

REVISION SUMMARY

Ordering Information

Revision A (January 1998)

Valid Combinations: Deleted the Am29LV400BT80 and

Am29LV400BB80 entries.

First release.

Revision B (July 1998)

Erase and Programming Performance

Expanded data sheet from Advanced Information to

Preliminary version.

Note 2: Changed “(3.0 V for 55R)’ to “(3.0 V for regu-

lated speed options)”.

Distinctive Characteristics

Revision C+1 (July 2, 1999)

Changed “Manufactured on 0.35 µm process technology”

to “Manufactured on 0.32 µm process technology”.

Global

Deleted references to the 50R speed option.

General Description

Second paragraph: Changed “This device is manufac-

tured using AMD’s 0.35 µm process technology” to

“This device is manufactured using AMD’s 0.32 µm

process technology”.

Revision D (January 3, 1999)

AC Characteristics—Figure 17. Program

Operations Timing and Figure 18. Chip/Sector

Erase Operations

Revision B+1 (August 1998)

Deleted t_GHWLand changed OE# waveform to start at

high.

Global

Added the 55 ns speed option.

Physical Dimensions

Connection Diagrams

Replaced figures with more detailed illustrations. The

FBGA package OPN designation is now FBA048.

Corrected the orientation identifiers on the reverse

TSOP package. Changed the FBGA drawing to top

view, balls facing down.

Revision D+1 (November 8, 2000)

Global

Revision C (January 1999)

Added table of contents. Deleted burn-in option from

Ordering Information section.

Global

Added -50R speed option.

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

Am29LV400B

44


型号：	AM29LV400BB-120FC
厂家：	ETC
描述：	x8/x16 Flash EEPROM X8 / X16闪存EEPROM 闪存内存集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件：	总44页 (文件大小：1026K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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