AL1212H [ETC]
AL1212H 6Bit 120MSPS ADC|Data Sheet ; AL1212H 6位120MSPS ADC |数据表\n
| 型号： | AL1212H |
| 厂家： | 
ETC |
| 描述： | AL1212H 6Bit 120MSPS ADC|Data Sheet
|
| 文件： | 总11页 (文件大小：120K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
6BIT 120MSPS ADC
AL1212H
GENERAL DESCRIPTION
FEATURES
The AL1212H is a CMOS 6-Bit A/D converter for a
digital video disk (DVD) partial-response maximum
- Resolution : 6Bit
- Differential Linearity Error : ±1.0 LSB
- Integral Linearity Error : ±1.0 LSB
- Maximum Conversion Rate : 120MSPS
- Digital Output : CMOS Level
likelihood (PRML) system.
It is a flash type A/D
converter which consists of input buffer, comparator
array, digital backend encoder, and output buffer. The
maximum conversion rate of AL1212H is over
120MSPS and supply voltage is 5V single.
- Power Consumption : 300mW
- Power Supply : 5V Single
TYPICAL APPLICATIONS
- Multi-media applications
- Digital video disk (DVD) system
- Digital broadcast satellite (DBS) receiver
- Quadrature phase shift keying (QPSK) demodulator
- Video applications
FUNCTIONAL BLOCK DIAGRAM
4-bit
CML
CML
ROM
Block
Level
Generator
DSL
Block
4-bit
ROM
Block
Flip/
Flop
Array
Flip/
Flop
Array
AINT
Input
Buffer
Comparator
Array
FNAND
Array
INCOM
4-bit
ROM
Block
DO[9:0]
Output
Buffer
Bias
Current
Generator
4-bit
ROM
Block
ITEST
CLKIN
Clock Generator
Ver 1.0 (Mar. 1999)
No responsibility is assumed by SEC for its use nor for any
infringements of patents or other rights of third parties that may
result from its use. The content of this datasheet is subject to
change without any notice.
SAMSUNG ELECTRONICS Co. LTD
AL1212H
6BIT 120MSPS ADC
CORE PIN DESCRIPTION
I/O TYPE ABBR.
NAME
I/O TYPE I/O PAD
PIN DESCRIPTION
- AI : Analog Input
REFTOP
REFBOT
AI
AI
pia_bb
pia_bb
Reference Top Bias (3.0V)
- DI : Digital Input
- AO : Analog Output
- DO : Digital Output
- AB : Analog Bidirectional
- DB : Digital Bidirectional
Reference Bottom Bias (2.0V)
Internal Bias Point
CML
AB
pia_bb
(open=use internal bias circuit)
VDDA
VBBA
VSSA
AP
AG
AG
vdda
vbba
vssa
Analog Power (5.0V)
Analog Sub Bias
Analog Ground
- AP : Analog Power
- DP : Digital Power
- AG : Analog Ground
- DG : Digital Ground
Analog Input
AINT
INCOM
ITEST
AI
piar10_bb
pia_bb
Input Span : 1.5~3.5 V
Internal Bias Point
AB
AB
(open=use internal bias circuit)
Internal Bias Point
pia_bb
(open=use internal bias circuit)
CLKIN
DO[5:0]
VSSD
DI
DO
DG
DP
piar50_bb Clock Input
poa_bb
vssd
Digital Output
Digital Ground
VDDD
vddd
Digital Power (5.0V)
CORE CONFIGURATION
DO[5:0]
AINT
al1212h
CLKIN
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SEC ASIC
ANALOG
AL1212H
6BIT 120MSPS ADC
ABSOLUTE MAXIMUM RATINGS
Characteristics
Supply Voltage
Symbol
VDD
Value
Unit
V
7.0
Analog Input Voltage
Digital Input Voltage
Digital Output Voltage
Reference Voltage
AINT
VSS to VDD
VSS to VDD
VSS to VDD
V
CLKIN
VOH, VOL
V
V
REFTOP/REFBOT 3.0/2.0
Tstg -45 to 125
V
Storage Temperature Range
º C
NOTES
1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently.
Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition
value is applied with the other values kept within the following operating conditions and function operation under any
of these conditions is not implied.
2. All voltages are measured with respect to VSS unless otherwise specified.
3. 100pF capacitor is discharged through a 1.5K resistor (Human body model).
W
RECOMMENDED OPERATING CONDITIONS
Characteristics
Supply Voltage
Symbol
Min
4.5
Typ
5.0
Max
5.5
Unit
V
VDDA - VSSA
VDDD - VSSD
Supply Voltage Difference
Reference Input Voltage
Analog Input Voltage
VDDA - VDDD
-0.1
0.0
0.1
V
REFTOP
REFBOT
-
-
3.0
2.0
-
-
V
AINT
1.5
-
3.5
V
Digital Input 'L' Voltage
Digital Input 'H' Voltage
VIL
VIH
-
-
-
0.5
-
V
4.5
Operating Temperature
NOTES
Topr
0
-
70
º C
1. It is strongly recommended that all the supply pins (VDDA, VDDD, VDDO) be powered from the same source to avoid
power latch-up.
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SEC ASIC
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AL1212H
6BIT 120MSPS ADC
DC ELECTRICAL CHARACTERISTICS
Characteristics
Resolution
Symbol
Min
Typ
Max
Unit
Conditions
-
-
6
-
Bits
-
REFTOP : 3.0V
REFBOT : 2.0V
Reference Current
IREF
DLE
ILE
-
-
-
0.8
-
mA
LSB
LSB
AINT : 1.5V ~ 3.5V
(Ramp Input)
Differential Linearity Error
-
-
±1.0
±1.0
Fs : 120MHz
Integral Linearity Error
Bottom Offset Voltage Error
EOB
EOT
-
-
1
1
3
3
LSB EOB = AINT(0,1)-REFBOT
LSB EOT = REFTOP-AINT(62,63)
Top Offset Voltage Error
NOTES
1. Converter Specifications (unless otherwise specified)
VDDA=5.0V
VSSA=.0.0V
VDDD=5.0V SUBST=0.0V
VSSD=0.0V
REFTOP=3.0V REFBOT=2.0V
Ta=25º C
2. TBD : To Be Determined
AC ELECTRICAL CHARACTERISTICS
Characteristics
Conversion Rate
Symbol
Min
Typ
Max
Unit
Conditions
Fs
-
120
-
MSPS
Is
60
Is = I(VDDA) + I(VDDD)
Fs : 120MHz
Dynamic Supply Current
Digital Output Data Delay
Signal to Noise Ratio
-
-
66
-
mA
ns
(IREF)
(0.8)
See
td
1.1
34
"DELAY TIMING DIAGRAM"
AINT : 20MHz (Sine Input)
Fs : 120MHz
SNDR
32
-
dB
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SEC ASIC
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AL1212H
6BIT 120MSPS ADC
DELAY TIMING DIAGRAM
AIN(1)
AIN(2)
AIN(3)
AINT
CLKIN
td
DO
DO (-1)
DO (0)
DO (1)
DO (2)
Signal Delay
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SEC ASIC
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AL1212H
6BIT 120MSPS ADC
generator generates approximately 1 MHz low
frequency clocks, which are supplied to
preamplifiers and input buffer while digital clock
generator generates a 120 MHz high frequency
clock, which is supplied to latches and digital
backend encoder.
FUNCTIONAL DESCRIPTION
1. AL1212H is a flash A/D converter, which
consists of input buffer, comparator array, digital
backend encoder, and clock generator.
2. The input buffer is used to reduce a relatively
large input capacitance of the A/D converter and
convert single-ended input to differential output,
which is provided to comparator array.
3. Comparator array generates a thermometer code
from analog input and reference levels. As it
has an interpolation factor of 2, this architecture
halves the number of preamplifiers but maintains
the same number of latches without extra
capacitors and resistors.
amplifies the analog input with performing an
auto-zero function simultaneously. Each latch
Each preamplifier
converts analog output of the preamplifier into
fully digital signal by positive feedback
operation.
4. The digital backend part composed of logic gates
and ROM blocks converts the comparator outputs
into 6-bit binary-coded digital words.
The
FNAND array, which converts a thermometer
code of the comparators into a single HIGH
level output, consists of 3-input NAND gates for
sparkle code suppression. The digital backend
encoding block consists of four 4-bit ROMs to
achieve fast encoding, low power consumption,
and small digital area.
Each FROM block
encodes 16-bit input code into 4-bit LSB and
generates extra 1-bit, named a group selection bit
(GSB), which becomes HIGH when the 4-bit
output code is valid. DSL block, which consists
of some logic gates, generates 2-bit MSB from
the 4-bit GSBs. To prevent timing errors, the
digital backend part contains two stage flip/flop
arrays which synchronize propagated signals with
the external clock.
5 Clock generator consists of analog clock generator
and digital clock generator.
Analog clock
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SEC ASIC
ANALOG
AL1212H
6BIT 120MSPS ADC
CORE EVALUATION GUIDE
1. ADC function is evaluated by external check on the bidirectional pads connected to input nodes of HOST
DSP back-end circuit.
2. The reference voltages should be biased externally through REFTOP and REFBOT pins.
VDDA
VSSA
REFTOP
REFBOT
VBBA
CML
VDDD
VSSD
INCOM
ITEST
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SEC ASIC
ANALOG
AL1212H
6BIT 120MSPS ADC
CORE LAYOUT GUIDE
1. The width of all signal and power lines, which are connected to the ports of AL1212H block, must be
same to one of the connected ports.
2. The power lines, which have over 20um width, may be designed by the slit form.
3. Each power line, which has same label, must be tied in front of the I/O pad block.
4. Analog signal lines (AINT, REFTOP, REFBOT, CML, INCOM, and ITEST) must be separated to the
digital lines (CLKIN and DO[5:0]).
5. The lines of AINT and CLKIN may be designed as a straight line and maintain an enough space (over
10um) with other lines as it possible.
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SEC ASIC
ANALOG
AL1212H
6BIT 120MSPS ADC
PACKAGE CONFIGURATION
0.1u
3.0V
2.0V
1
2
REFTOP
REFTOP
REFBOT
REFBOT
CML
VDDD
VDDD
VSSD
VSSD
NC
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
0.1u
10u
10u
1n
1n
5.0V
10u
3
1n
4
0.1u
5
0.1u
1n
6
VDDA
VDDA
VBBA
VSSA
VSSA
AINT
NC
NC
5.0V
10u
7
NC
8
NC
9
DO[5]
DO[4]
DO[3]
DO[2]
DO[1]
DO[0]
NC
0.1u
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
0.1u
6-b ADC
output
Analog
input
50
1K
al1212h_top
INCOM
NC
0.1u
NC
ITEST
NC
NC
0.1u
1n
NC
0.1u
5.0V
10u
VDDO
VSSO
CLKIN
NC
NC
NC
Clock in
NC
NC
50
NC
NC
NC
NC
NC
NC
: Test Pin
No bias forcing, Remain floating
NOTES
1. NC denotes "No Connection".
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SEC ASIC
ANALOG
AL1212H
6BIT 120MSPS ADC
PACKAGE PIN DESCRIPTION
NAME
REFTOP
REFBOT
CML
PIN NO.
1,2
I/O TYPE
AI
PIN DESCRIPTION
Reference Top (3V)
3,4
AI
Reference Bottom (2V)
5
AB
AP
Internal Bias Point (Open=use internal bias circuit)
Analog Power (5V)
VDDA
VBBA
VSSA
6, 7
8
AG
AG
AI
Analog Sub Bias
9, 10
11
Analog Ground
AINT
Analog Input +
INCOM
ITEST
VDDO
VSSO
13
AB
AB
PP
Analog Input - (Open=use internal bias circuit)
Internal Bias Point (Open=use internal bias circuit)
Output Driving Power
16
18
19
PG
Output Driving Ground
Clock Input
CLKIN
DO[5:0]
VSSD
20
DI
35~40
45,46
47,48
DO
DG
DP
Digital Output
Digital Ground
VDDD
Digital Power
NOTES
1. I/O TYPE PP and PG denote PAD Power and PAD Ground respectively.
2. INCOM is the other pin of differential input, which is fixed to 2.5 V internally.
3. CML is the bias pin, which is fixed to 2.5 V internally.
4. ITEST is the test pin of bias generator. When initial bias function is working normally the pin is fixed to 0.9 V.
5. VDDO and VSSO are output driving power pads.
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SEC ASIC
ANALOG
AL1212H
6BIT 120MSPS ADC
FEEDBACK REQUEST
It should be quite helpful to our ADC core development if you specify your system requirements on ADC in
the following characteristic checking table and fill out the additional questions.
We appreciate your interest in our products. Thank you very much.
Characteristic
Analog Power Supply Voltage
Digital Power Supply Voltage
Bit Resolution
Min
Typ
Max
Unit
V
Remarks
V
Bit
V
Reference Input Voltage
Analog Input Voltage
Vpp
Analog Input Bandwidth
MHz
(Maximum Input Frequency)
Operating Temperature
Integral Non-linearity Error
Differential Non-linearity Error
Bottom Offset Voltage Error
Top Offset Voltage Error
Maximum Conversion Rate
Dynamic Supply Current
Power Dissipation
º C
LSB
LSB
mV
mV
MSPS
mA
mW
dB
Signal-to-noise Ratio
Pipeline Delay
CLK
pF
Output Loading Capacitance
Digital Output Format
(Provide detailed description &
timing diagram)
1. Between single input-output and differential input-output configurations, which one is suitable for your
system and why?
2. Please comment on the internal/external pin configurations you want our ADC to have, if you have any
reason to prefer some type of configuration.
3. Freely list those functions you want to be implemented in our ADC, if you have any.
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SEC ASIC
ANALOG
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