AFE1400X [ETC]
AFE1400X 12-Bit 20 MSPS AFE FOR CCD/CIS SIGNAL PROCESSOR|Data Sheet ; AFE1400X 12位20 MSPS模拟前端,用于CCD / CIS信号处理器|数据表\n型号: | AFE1400X |
厂家: | ETC |
描述: | AFE1400X 12-Bit 20 MSPS AFE FOR CCD/CIS SIGNAL PROCESSOR|Data Sheet
|
文件: | 总21页 (文件大小:571K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
AFE_CIP4
12-Bit 20 MSPS AFE FOR CCD/CIS SIGNAL PROCESSOR
GENERAL DESCRIPTION
FEATURES
The samsung analog front end(AFE) for CCD/CIS
image signal is an integrated analog signal
processor for color image signal.
- 12-bit 20 MSPS A/D Converter
- Integrated Triple Correlated Double
Sampler
The AFE converts CCD/CIS output signal to digital
- 3-Channel 2 MSPS Color Mode
- 1 ~ 6.25x Analog Programmable Gain
Amplifier
data.
The
AFE
Double
includes
three-channel
circuit,
CDS(Correlated
Sampling)
PGA(Programmable Gain Amplifier), and 12-bit
analog to digital converter with reference generator.
The 12-bit digital output is multiplexed into an
8-bit output word that is accessed using 8+4
format two read cycles. The internal resgisters are
programmed through a 3-wire serial interface, and
provide adjustment of the gain, offset, and
operating mode.
- Internal Voltage Reference
- No Missing Code Guaranteed
- Multiplexed Byte-Wide Output
(8+4 Format)
- 3-Wire Serial Digital Interface
- Operation by Single 3.3V Supply
- CMOS Low Power Dissipation
- 28-SOP-375 Package
APPLICATIONS
- Color and B/W Scanner
KEY SPECIFICATION
- Resolution: 12-bit
- Digital Copiers
- Conversion Rate: 20 MHz(2 MHz*3)
- Supply Voltage: 3.3 V ± 5%
- Power Dissipation: 415 mW(Typical)
- General Purpose CCD/CIS imager
FUNCTIONAL BLOCK DIAGRAM
R E D
P G A
P G A
P G A
C D S
R E F
D A C
O E B
G R E E N
12
8
12b
A D C
12:8
C D S
D [7:0]
M U X
M U X
D A C
B LU E
C D S
G A I N
R E G I S T E R S
S C L K
M P U
P O R T
S L O A D
S D A T A
D A C
I N P U T O F F S E T
R E G I S T E R S
Ver 1.0 (July, 2001)
This datasheet is
a preliminary version. No responsibility is
assumed by SEC for its use nor for any infringements of patents
or other rights of third parties that may result from its use. The
content of this datasheet is subject to change without any notice.
SAMSUNG ELECTRONICS Co. LTD
AFE_CIP4
12-Bit 20 MSPS AFE FOR CCD/CIS SIGNAL
CORE PIN DESCRIPTION
NAME
AVDDA
AVSSA
AVDDD
AVSSD
AVBBA
AVBBD
REFT
I/O TYPE
AP
I/O PAD
vdda
DESCRIPTION
3.3 V Analog Supply
AG
AP
vssa
Analog Ground
vdda
3.3 V Digital Supply
Digital Ground
AG
AG
AG
AB
AB
AB
AI
vssa
vbba
Analog Substrate
vbba
Digital Substrate
poa_bb
poa_bb
poa_bb
piar10_bb
piar10_bb
piar10_bb
piar10_bb
picc_bb
picc_bb
picc_bb
poa_bb
picc_bb
picc_bb
picc_bb
pot4_bb
Reference Decoupling
Reference Decoupling
Analog Common Voltage
Analog Input; Red
REFB
VCOM
R_VIN
G_VIN
AI
Analog Input; Green
B_VIN
AI
Analog Input; Blue
OFFSET
CDS1_CLK
CDS2_CLK
ADCCLK
SDATA
SCLK
AB
DI
Clamp Bias Level Decoupling
CDS Reset Clock Pulse Input
CDS Data Clock Pulse Input
A/D Converter Sample Clock Input
Serial Interface Data Input/Output
Serial Interface Clock Input
Serial Interface Load Pulse
Output Enable; Active Low
Data Outputs
DI
DI
DB
DI
SLOAD
OEB
DI
DI
D[7:0]
DO
I/O TYPE ABBR.
- DP : Digital Power
- DG : Digital Ground
- AB : Analog Bidirectional Port
- DB : Digital Bidirectional Port
- AI : Analog Input
- DI : Digital Input
- AO : Analog Output
- DO : Analog Output
- AP : Analog Power
- AG : Analog Ground
SEC ASIC
2
MIXED
AFE_CIP4
12-Bit 20 MSPS AFE FOR CCD/CIS SIGNAL
CORE PIN CONFIGURATION
REFT VCOM REFB
AVSSD
AVDDD
AVSSA
AVDDA
OEB
R_VIN
G_VIN
B_VIN
D[7:0]
afe_cip4
SDATA
SCLK
SLOAD
OFFSET
AVBBA
AVBBD
ADCCLK
CDS1_CLK
CDS2_CLK
ABSOLUTE MAXIMUM RATINGS
Characteristic
Supply Voltage
Symbol
Value
Unit
V
VDD
AIN
4.5
Analog Input Voltage
VSS to VDD
VSS to VDD
VSS to VDD
VSS to VDD
-45 to 150
V
Digital Input Voltage
CLK
VOH, VOL
VRT/VRB
Tstg
V
V
Digital Output Voltage
Reference Voltage
V
Storage Temperature Range
Operating Temperature Range
º C
º C
Topr
0 to 70
NOTES
1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged
permanently. Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect
reliability. Each condition value is applied with the other values kept within the following operating
conditions and function operation under any of these conditions is not implied.
2. All voltages are measured with respect to VSS unless otherwise specified.
3. 100pF capacitor is discharged through a 1.5k resistor (Human body model)
W
SEC ASIC
3
MIXED
AFE_CIP4
12-Bit 20 MSPS AFE FOR CCD/CIS SIGNAL
ANALOG SPECIFICATIONS(VDDA1=3.3V, VDDA2=3.3V, ADCCLK=20MHz,
CDS1_CLK=6.666MHz,CDS2_CLK=6.666MHz, PGA Gain=1
unless otherwise noted
)
Characteristics
Symbol
Min
Typ
Max
Unit
Comment
Resolution
12
Bits
Conversion Rate
3-Channel with CDS
1-Channel with CDS
20
20
MSPS
MSPS
Signal-to-Noise & Distortion
Ratio @ 1MHz Input
SNDR
DNL
INL
60
dB
Differential
Nonlinearity
LSB
LSB
±1
Entire
Signal Path
Integral
2
±
Nonlinearity
Unipolar Offset Error
Gain Error
1.0
2.0
%FSR
%FSR
Analog Input
Full-Scale Input
Input Capacitance
Reference Top
Reference Bottom
0.04
2.4
Vp-p
pF
V
8
2.2
1.0
V
Amplifier
PGA Gain
1
-
6
-
6.25
V/V
Bits
mV
Bits
PGA Resolution
OFFSET Range
OFFSET Resolution
-
-200
-
-
+200
-
9
Power Supply
Analog Voltage
Digital Voltage
Analog Current
Digital Current
VDDA1
VDDA2
IDD1
3.3
3.3
120
6
V
V
3.3V 5%
±
3.3V 5%
±
mA
mA
IDD2
Power Consumption
Temperature Range
415
mW
º C
0
70
Operating
DIGITAL SPECIFICATIONS(VDDA1=3.3V, VDDA2=3.3V, ADCCLK=20MHz,
CDS1_CLK=6.666MHz, CDS2_CLK=6.666MHz, CL=20pF
unless otherwise noted)
Characteristics
Symbol
Min
Typ
Max
Unit
V
Comment
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output Voltage
Low Level Output Voltage
VIH
VIL
IIH
2.0
0.7
V
10
10
A
m
IIL
A
m
VoH
VOL
3.0
V
IoH = 0.5mA
IoL = -0.5mA
0.3
V
SEC ASIC
4
MIXED
AFE_CIP4
12-Bit 20 MSPS AFE FOR CCD/CIS SIGNAL
TIMING SPECIFICATIONS
(VDDA1=3.3V, VDDA2=3.3V unless otherwise noted)
Characteristics
CLOCK CHARACTERISTICS
3-Channel Conversion Rate
1-Channel Conversion Rate
CDSCLK1 Pulse Width
Symbol
Min
Typ
Max
Unit
150
50
22
24
24
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tC1CLK
tC2CLK
tC2CLKB
tC1C2A
tC2C1A
tADCLK
tC2ADA
tC2ADB
tADC2A
tAD
CDSCLK2 Pulse Width
CDSCLK2B Pulse Width
CDSCLK1 Falling to CDSCLK2 Rising
CDSCLK2 Falling to CDSCLK1 Rising
ADCCLK Pulse Width
3
22
24
3
CDSCLK2 Rising to ADCCLK Rising
CDSCLK2 Falling to ADCCLK Falling
ADCCLK Rising to CDS2CLK Falling
Aperture Delay
3
2
SERIAL INTERFACE
Maximum SCLK Frequency
SLOAD to SCLK Set-up Time
SCLK to SLOAD Hold Time
SDATA to SCLK Rising Set-up Time
SCLK Rising to SDATA Hold Time
SCLK Falling to SDATA Valid
DATA OUTPUT
fCLK
tLS
10
10
10
10
10
10
MHz
ns
tLH
ns
tDS
ns
tDH
tRDV
ns
ns
ADC Output Delay
tADDT
tDEV
tHZ
10
15
5
ns
ns
ns
Tri-State to Data Valid
Output Enable High to Tri-State
ADCCLK
Cycles
ADC Latency(Pipeline Delay)
3
* Aperture delay is a timing measurement between the sampling clocks and
CDS. It is measured from the falling edge of the CDS2_CLK input to when the
input signal is held for data conversion
SEC ASIC
5
MIXED
AFE_CIP4
12-Bit 20 MSPS AFE FOR CCD/CIS SIGNAL
TIMING DIAGRAM
3-Channel CDS Mode
Analog
Input
R0,G0,B0
R1,G1,B1
R2,G2,B2
tC1C2A
tC2C1A
tC1CLK
CDS1_CLK
CDS2_CLK
ADCCLK
tC2ADA
tADC2A
tC2CLKB
tADCLK
tADDT
R0
OUTPUT
D[7:0]
R-2 R-2
G-2 G-2 B-2
B-2 R-1
R-1 G-1
G-1 B-1 B-1
R0
G0
G0
B0
B0
3-Channel SHA Mode
Analog
Input
R0,G0,B0
R1,G1,B1
R2,G2,B2
tC2ADA
tADC2A
tC2CLKB
CDS2_CLK
ADCCLK
tADCLK
tADDT
R0 R0
OUTPUT
D[7:0]
R-2 R-2
G-2 G-2
B-2
B-2 R-1
R-1
G-1
G-1
B-1
B-1
G0
G0
B0
B0
SEC ASIC
6
MIXED
AFE_CIP4
12-Bit 20 MSPS AFE FOR CCD/CIS SIGNAL
1-Channel CDS Mode
Analog
Input
tC1CLK
tC1C2A
tC2C1A
CDS1_CLK
CDS2_CLK
ADCCLK
tC2CLK
tC2ADA
tADCLK
tC2ADB
1-Channel SHA Mode
Analog
Input
R0,G0,B0
tC2CLK
R1,G1,B1
R2,G2,B2
CDS2_CLK
ADCCLK
tC2ADA
tADCLK
tC2ADB
SEC ASIC
7
MIXED
AFE_CIP4
12-Bit 20 MSPS AFE FOR CCD/CIS SIGNAL
Digital Output Data Timing
ADCCLK
tADDT
tADDT
Byte
High Byte Low
D13-D6
OUTPUT
D[7:0]
High
Low
High
Low
D5-D0
tHZ
tDEV
OEB
Serial Write Operation Timing
SDATA
R/Wb A2
A1 A0
XX XX XX
D8
D7 D6
D5 D4
D3 D2 D1 D0
tDH
tDS
SCLK
tLH
tLS
SLOAD
Serial Read Operation Timing
SDATA
R/Wb A2
A1 A0
XX XX XX
D8
D7 D6
D5 D4
tRDV
D3 D2 D1 D0
tDH
tDS
SCLK
tLH
tLS
SLOAD
'Read' means microcontroller reads SDATA
SEC ASIC
8
MIXED
AFE_CIP4
12-Bit 20 MSPS AFE FOR CCD/CIS SIGNAL
MAIN BLOCK DESCRIPTION
FUNCTIONAL DESCRIPTION
1) 3-Channel Operation with CDS
1) Programmable Gain Amplifier
This mode enables simultaneous sampling of a
triple output CCD. The CCD waveforms are ac
coupled to the R_VIN, G_VIN and B_VIN pins
where they are automatically biased at an
appropriate voltage using the on-chip clamp. The
internal CDSs take two samples of the incoming
pixel data; the first samples are taken during the
reset time while the second samples are taken
during data portion of the input pixels.
The analog programmable gain can accommodate
a wide range of input voltage spans. The transfer
function of the PGA is as follows.
H(X) = 1/12*X + 1,
where the range of X is 0 to 63.
Thus, the minimum gain value is equal to 1, and
the maximum gain value is equal to 6.25. The
transfer function has linearity in linear scale. The
overall gain is equal to analog gain multiplied
by digital gain. So, the multiplier should be
required in back end of AFE.
2) 3-Channel SHA Operation
This mode enables simultaneous sampling of
a
triple output CIS or something like that. The CDS
functions are replaced with the sample and hold
amplifiers. The input waveforms are either dc
coupled or dc restored to the R_VIN, G_VIN and
B_VIN pins. The input reference voltage in this
mode will be defined by external OFFSET pin.
6
5
4
3
2
1
16
14
12
10
8
3) 1-Channel Operation with CDS
6
This mode enables single channel or monochrome
sampling. The CCD waveforms are ac coupled to
the analog input pin where they are automatically
biased at an appropriate voltage using the on-chip
clamp.
4
2
0
PGA Register Value
Bit4, bit5 and bit6 in MUX register select the
desired input among red, green and blue.
4) 1-Channel SHA Operation
This mode enables single-channel or monochrome
sampling. The CDS function is replaced with the
sample and hold amplifier.
The input waveforms are either dc coupled or dc
restored to the analog input pin. The input
reference voltage in this mode will be defined by
clamp level control register.
Bit4, bit5 and bit6 in MUX register select the
desired input among red, green and blue.
SEC ASIC
9
MIXED
AFE_CIP4
12-Bit 20 MSPS AFE FOR CCD/CIS SIGNAL
BLOCK DIAGRAM
VDDA1 VSSA1 VDDA2
VSSDR
VSSA2 VDDDR
VCOM REFB
REFT
RED
R_VIN
CDS
PGA
CLAMP
R_OFFSET[8:0]
REF
DAC
R_GAIN[5:0]
PGA
GREEN
8
G_VIN
12-bit
ADC
12:8
MUX
CDS
MUX
CLAMP
D[7:0]
G_OFFSET[8:0]
DAC
G_GAIN[5:0]
OEB
BLUE
B_VIN
PGA
CDS
CLAMP
Configuration
B_OFFSET[8:0]
Register
DAC
B_GAIN[5:0]
SDATA
SCLK
R_OFFSET[8:0]
Input Offset
Register
MPU
PORT
G_OFFSET[8:0]
B_OFFSET[8:0]
(R,G,B)
SLOAD
OFFSET
R_GAIN[5:0]
G_GAIN[5:0]
PGA Gain
Register
(R,G,B)
B_GAIN[5:0]
CDS2_CLK
ADCCLK
CDS1_CLK
SEC ASIC
10
MIXED
AFE_CIP4
12-Bit 20 MSPS AFE FOR CCD/CIS SIGNAL
2) INTERNAL REGISTER OVERVIEW
The internal register map is accessed through serial data pin SDATA's A0, A1 and A2.
Register Map
Address
A1 A0
Data Bits
D4
Register
A2
0
D8
0
D7
0
D6
0
D5
D3
0
D2
PWR Dn
0
D1
0
D1
0
Configuration
MUX
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
3Ch/1Ch CDS on
0
0
RGB/BGR Red
Green
MSB
MSB
MSB
Blue
0
0
0
Red PGA
0
0
0
0
0
0
0
0
LSB
LSB
LSB
LSB
LSB
LSB
Green PGA
Blue PGA
Red Offset
Green Offset
Blue Offset
0
0
1
0
1
MSB
MSB
MSB
1
1
Configuration Register
D8
D7
D6
D5
D4
D3
D2
D1
D0
# of Channels
CDS Operation
Power Down
Set to
0
1*
X
1*
X
Set to 0
1=3-CH mode*
0=1-CH mode
1=CDS Mode*
0=SHA Mode*
1=On
0=Off (Operation)*
*Power-on Default Value, X: Don't care
MUX Register
D8
D7
D6
D5
D4
D3
D2
D1
D0
3-CH Select
1-CH
1-CH
1-CH
Set to
0
Set to 0
1=R-G-B*
0=B-G-R
1=RED*
0=Off
1=Green
0=Off*
1=Blue
0=Off*
*Power-on Default Value
SEC ASIC
11
MIXED
AFE_CIP4
12-Bit 20 MSPS AFE FOR CCD/CIS SIGNAL
PGA Gain Register
Gain
Gain
(dB)
D8
D7
D6 D5(MSB)
D4
D3
D2
D1
D0(LSB)
(V/V)
0*
0
0*
0
0*
0
0*
0
0*
0
0*
0
0*
0
0*
0
0*
1
1
0
1.083
1.167
0.693
1.341
0
0
0
0
0
0
0
1
0
. . .
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
1
6.167
6.25
15.801
15.918
*Power-on Default Value
Offset Register
D8(MSB)
Offset
(mV)
D7
D6
D5
D4
D3
D2
D1
D0(LSB)
Sign Bit
0*
0*
0
0*
0
0*
0
0*
0
0*
0
0*
0
0*
0
0*
1
0
0
0
0.781
1.563
0
0
0
0
0
0
1
0
. . .
1
0
1
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
1
200
0
-0.781
-1.563
0
. . .
1
1
1
1
1
1
1
1
1
-200
*Power-on Default Value
SEC ASIC
12
MIXED
AFE_CIP4
12-Bit 20 MSPS AFE FOR CCD/CIS SIGNAL
INPUT COUPLING CAPACITOR
OVERALL TRANSFER FUNCTION
Because of the DC offset present at the output of
CCD, some kind of DC restoration is
required. In case of CDS enable mode, to
simplify input level shifting, a DC decoupling
capacitor is used in conjuction with the
internal input circuitry.
The overall transfer function can be calculated as
follows.
ADCout=[(Vin+Input_Offset)* PGA_Gain]/(2*REF)*4096,
where REF is equal to (REFT-REFB) and Input
_Offset means the DAC value of the input offset
register. The analog offset range of the input
offset register is varied between 200mV and -200
mV. The 9-bit data format for the input offset
register is sign magnitude, with D8 as the sign bit.
To maximize the dynamic range of the ADC input,
The capacitor charging or discharging depends on
the clamping time, the analog input resistance of
the AFE and the output resistance of the circuit
driving the coupling capacitor.
it is necessary to program the input offset register
code to move the ADC code corresponding to
the black level towards 'zero'.
The clamping time is typically (n*T), where n is
the number of periods
CDSCLK1 is asserted
and T is the period of assertion. CDSCLK2
should not be asserted during clamping time. The
analog input resistance of the AFE's Clamp is
And also PGA_gain is to maximize the dynamic
range of the 12-bit ADC's input. The PGA_gain
range is varied between 1 and 6.25 by PGA gain
register. The 6-bit data format for the PGA gain
register is straight binary coding.
equal to 1 k . The recommended input coupling
W
capacitor is more than 0.1uF. The time constant
of the input clamp is determined by the internal
1K resistance and the external 0.1uF input
capacitance. Thus, to extend the clamping time,
the time a transport motor moves the scanner
carriage can be available, for example.
SEC ASIC
13
MIXED
AFE_CIP4
12-Bit 20 MSPS AFE FOR CCD/CIS SIGNAL
POWER-ON INITIALIZATION
CALIBRATION
Decide clamp level for SHA mode
(Refer to next page)
Write to configuration register
Set CDS or SHA operation
Set 3 or 1 channel mode
Set color pointer
Set PGA gain
(Input offset = 0 mV)
Set clamp mode
Scan dark line
Compute pixel offsets
Write to PGA gain register
Set to gain of one(000000)
Set input offset
Write to input offset register
Set to 0mV(100000000)
Set odd/even offset in back end
YES
Set another color
YES
Set another color
NO
NO
Set gain/offset bus size
in back end
Set external pixel offset
in back end
Scan white line
Compute pixel gains
in back end
YES
Adjust PGA gain
NO
SEC ASIC
14
MIXED
AFE_CIP4
12-Bit 20 MSPS AFE FOR CCD/CIS SIGNAL
CORE EVALUATION GUIDE
0.1u
0.1u
0.1u
AVSSD
AVDDD
AVSSA
AVDDA
REFT VCOM REFB
OEB
R_VIN
G_VIN
B_VIN
D[7:0]
afe_cip4
SDATA
SCLK
SLOAD
OFFSET
AVBBA
AVBBD
ADCCLK
CDS2_CLK
CDS1_CLK
TIMING GENERATOR
MPU INTERFACE
DSP ASIC
MUX
MUX
Externally forced digital input/output
SEC ASIC
15
MIXED
AFE_CIP4
12-Bit 20 MSPS AFE FOR CCD/CIS SIGNAL
APPLICATIONS INFORMATION
CDS Mode Applications
- The recommended input coupling capacitor value is 0.1uF.
- A single ground plane is recommended for the afe_cip4. Thus the digital pins should be
well decoupled to the analog ground plane.
- If possible, a separate power supply should be used for VDDDR, but this supply pin
should still be decoupled to the same ground plane as the rest of the afe_cip4.
- The loading of digital outputs should be minimized.
- All 0.1uF decoupling capacitors should be located as close as possible to the afe_cip4
pins.
- When operating in single channel mode, the unused analog inputs must be grounded.
1
2
3
28
CDSCLK1
VDDA2
0.1u
27
26
CDSCLK2
ADCCLK
OEB
VSSA2
R_VIN
0.01u
0.01u
4
5
25
24
OFFSET
VDDDR
VSSDR
D7(MSB)
D6
G_VIN
VCOM
B_VIN
REFT
0.1u
1.0u
0.1u
0.1u
6
7
23
22
21
20
0.01u
10u
afe_cip4
8
9
0.1u
0.1u
0.1u
D5
REFB
10
11
19
18
D4
VSSA1
VDDA1
SLOAD
SCLK
0.1u
D3
12
13
14
17
16
15
D2
D1
D0(LSB)
SDATA
Data Outputs
3-Channel CDS Mode Application Circuit Configuration
SEC ASIC
16
MIXED
AFE_CIP4
12-Bit 20 MSPS AFE FOR CCD/CIS SIGNAL
SHA Mode Applications
- All of the CDS mode's considerations also apply for this configuration, except that
analog inputs are directly connected to the afe_cip4 without coupling capacitors.
- The OFFSET pin may be used in a CIS application for DC offset adjustment.
By connecting the appropriate dc voltage to the OFFSET pin, the CIS signal will be
restored to "zero".
1
CDSCLK1
28
VDDA2
0.1u
2
3
27
26
CDSCLK2
ADCCLK
OEB
VSSA2
R_VIN
4
5
25
24
OFFSET
VDDDR
VSSDR
D7(MSB)
D6
G_VIN
VCOM
B_VIN
REFT
0.1u
0.1u
6
7
23
22
21
20
afe_cip4
8
9
0.1u
0.1u
10u
0.1u
D5
REFB
10
11
19
18
D4
VSSA1
VDDA1
SLOAD
SCLK
0.1u
D3
12
13
14
17
16
15
D2
D1
D0(LSB)
SDATA
Data Outputs
3-Channel SHA Mode Application Circuit Configuration
SEC ASIC
17
MIXED
AFE_CIP4
12-Bit 20 MSPS AFE FOR CCD/CIS SIGNAL
PACKAGE PIN DESCRIPTION
PIN NO.
PIN NAME
I/O TYPE
DESCRIPTION
1
2
3
4
5
6
CDS1_CLK
CDS2_CLK
ADCCLK
OEB
DI
DI
CDS Reference Sampling Clock
CDS Data Sampling Clock
A/D Converter Clock
DI
DI
Output Enable (Active Low)
Output Buffer Power
VDDDR
VSSDR
DP
DG
Output Buffer Ground
Digital Output (MSB)
7
D[7]
DO
High Byte: D13, Low Byte: D5
8
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
DO
DO
DO
DO
DO
DO
Digital Output (D12, D4)
Digital Output (D11, D3)
Digital Output (D10, D2)
Digital Output (D9, D1)
Digital Output (D8, D0)
Digital Output (D7, X)
9
10
11
12
13
Digital Output (LSB)
14
D[0]
DO
High Byte: D6, Low Byte: X(Don't care)
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SDATA
SCLK
DB
DI
Serial Interface Data Input/Output
Serial Interface Clock Input
Serial Interface Load Pulse
Analog Power
SLOAD
VDDA1
VSSA1
REFB
DI
AP
AG
AB
AB
AI
Aanlog Ground
Reference Decoupling
Reference Decoupling
Analog Input: Blue
REFT
B_VIN
VCOM
G_VIN
OFFSET
R_VIN
VSSA2
VDDA2
AB
AI
Analog Common Voltage
Analog Input: Green
Clamp Bias Level Decoupling
Analog Input: Red
AB
AI
DG
DP
Digital Ground
Digital Power
SEC ASIC
18
MIXED
AFE_CIP4
12-Bit 20 MSPS AFE FOR CCD/CIS SIGNAL
USER GUIDE
SYSTEM CONFIGURATION
It is necessary that output signal of analog front end be shading-compensated by back end
logic block including subtracter and multiplier.
(Shading-Compensation Block)
Memory
Subtracter
Multiplier
Controller
AFE
CCD/CIS
SEC ASIC
19
MIXED
AFE_CIP4
12-Bit 20 MSPS AFE FOR CCD/CIS SIGNAL
Questionnaire for Analog Core
Characteristics
Symbol
Min
Typ
Max
Unit
Comment
Resolution
Bits
Signal-to-Noise & Distortion
Ratio
SNDR
dB
Conversion Rate
3-Channel with CDS
1-Channel with CDS
MSPS
MSPS
Differential
Nonlinearity
DNL
INL
LSB
LSB
Integral
Nonlinearity
Unipolar Offset Error
Gain Error
%FSR
%FSR
Anlog Input
Vp-p
Full-Scale Input
Power Supply
Analog Voltage
Digital Voltage
VDDA
VDDD
V
V
Power Consumption
Temperature Range
mW
º C
- What do you want to choose as power supply voltages?
For example, the analog VDD needs to be 3.3V. The digital VDD can be 2.5V/3.3V.
- Which modes of AFE do you use for overall system ? (Refer to page 9)
For example: 3channel operation with CDS / 3channel SHI(CIS) operation
1channel operation with CDS / 1channel SHI(CIS) operation
- Would you define the gain range and input offset range ?
Could you explain external/internal pin configurations as required?
-
- If possible, present other requirements below.
SEC ASIC
20
MIXED
AFE_CIP4
12-Bit 20 MSPS AFE FOR CCD/CIS SIGNAL
HISTORY CARD
Version
Date
Modified Items
Comments
ver 1.0
2001.07 Original version published (preliminary)
SEC ASIC
MIXED
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