ADC4345M-500KHZ [ETC]
Analog to Digital Converter ; 模拟数字转换器\n
| 型号： | ADC4345M-500KHZ |
| 厂家： | 
ETC |
| 描述： | Analog to Digital Converter
|
| 文件： | 总6页 (文件大小：184K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADC4344/ADC4345
Very High Speed, 16-Bit, 1 MHz and
500 kHz Sampling A/D Converters
With Built-in Sample-and-Hold Amplifiers
Description
The ADC4344 and ADC4345 are complete 16-bit, 1 MHz and 500 kHz
A/D converter subsystems with a built-in sample-and-hold amplifier in a
space-saving 2.5" x 3.5" x 0.44" package. They offer pin-programmable
input voltage ranges of ±2.5V, ±5V and 0 to +10V. They are designed for
use in applications requiring high speed and high resolution front ends
such as ATE, digital oscilloscopes, medical imaging, radar, sonar, and
analytical instrumentation. The ADC4344 is capable of digitizing a 500
kHz signal at a 1 MHz sampling rate with a guarantee of no missing
codes from 0°C to +60°C. Equally impressive in frequency domain appli-
cations, the ADC4345 features 95 dB signal-to-noise ratio with input sig-
nals from DC to 100 kHz.
Features
❑ Built-in S/H Amplifier
❑ Unique 2-Pass Sub-Ranging
Architecture
❑ 16-Bit Resolution
❑ 1 MHz and 500 kHz Conversion
Rate
❑ 0.003% Maximum Integral
Nonlinearity
❑ No Missing Codes
❑ Peak Distortion: –99 dB
(100 kHz Input)
❑ Signal to Noise Ratio: 100 kHz
Input 92 dB, ADC4344; 95 dB,
ADC4345
❑ Total Harmonic Distortion: –93 dB
(100 kHz Input)
The ADC4344 and ADC4345 utilize the latest surface-mount technolo-
gies to produce a cost effective, high performance part in a 2.5" x 3.5"
fully shielded package. They are designed around a two-pass, sub-rang-
ing architecture that integrates a low distortion sample-and-hold amplifier,
precision voltage reference, ultra-stable 16-bit linear reference D/A con-
verter, all necessary timing circuitry and tri-state CMOS/TTL-compatible
output lines for ease of system integration. The converters also offer an
optional high-speed, low-noise input buffer for applications requiring high
input impedance.
Continued on page 3.
A/D Offset
Adjust
R
R
FB
IN
1
A/D In
P1
S/H
Cont
S/H In 1
S/H In 2
S/H
Amp
Difference
Amplifier
❑ TTL/CMOS Compatibility
❑ Low Noise
❑ Compact Size: 2.5" x 3.5" x 0.44"
❑ Electromagnetic/Electrostatic
Shielding
P1
P2
-
+
9
O/U
Flow
S/H Out
9-Bit Flash
ADC
Summing
Amplifier
+
-
Buffer In
16
B1-B16
Data
B1
S/H Cont
Logic
Buffer Out
P1
∑
Ref
Out
-
-
+
P2
P1
P2
P2
+
Transfer
-5V Ref
+5V Ref
R
FB
2
Reference
Circuit
Gain Adj
En Trig
Applications
9
9-Bit DAC
16-Bit Linear
HI & LO
Byte En
Trigger
+15V
-15V
+15V
2
❑ Digital Signal Processing
❑ Sampling Oscilloscopes
❑ Automatic Test Equipment
❑ High-Resolution Imaging
❑ Analytical Instrumentation
❑ Medical Instrumentation
❑ CCD Detectors
+15V
-15V
+5V
-15V
+5V
Ana Gnd
Dig Gnd
Ana Gnd
Dig Gnd
Figure 1. Functional Block Diagram.
❑ IR Imaging
❑ Sonar
❑ Radar
ADC4344/ADC4345
1
Specifications
ANALOG INPUT
Logic "1"
100 kHz input @ 0 dB
+2.4V Min.
–86 dB Max., –93 dB Typ. (ADC4345)
–86 dB Max., –97 dB Typ. (ADC4344)
Input Voltage Range
Bipolar
Output Coding
±2.5V, ±5V
@ –20 dB
Binary, Offset Binary, 2's Comp.
–82 dB Typ.
Unipolar
Transfer Pulse
0 to +10V
540 kHz input @ -10 dB (ADC4344)
Data valid on positive edge
–79 dB Min., –86 dB Typ.
THD + Noise7
20 kHz input @ 0 dB
89 dB Min., 92 dB Typ. (ADC4345)
87 dB Min., 90 dB Typ. (ADC4344)
Max. Input Without Damage
±15.5V Typ.
Over/Under Flow
Valid = logic "0" (occurs only when ±FS
have been exceeded)
S/H Direct Input Resistance
2.5 kΩ Typ.
DYNAMIC CHARACTERISTICS 4
Ext. Offset and Gain Adj. Sensitivity
2 mV/V
@ –20 dB
75 dB Typ. (ADC4345)
72 dB Typ. (ADC4344)
Maximum Throughput Rate
500 kHz Min. (ADC4345)
1.0 MHz Min. ((ADC4344)
INPUT BUFFER 2
100 kHz input @ 0 dB
86 dB Min., 91 dB Typ. (ADC4345)
84 dB Min., 89 dB Typ. (ADC4344)
A/D Conversion Time
1.2 µs Typ. (ADC4345)
620 ns Typ. (ADC4344)
Input Bias Current
10 nA Max.
Input Resistance
100 MΩ Typ.
@ –20 dB
75 dB Typ. (ADC4345)
72 dB Typ. (ADC4344)
S/H Acquisition Time
800 ns Typ. (ADC4345)
380 ns Typ. (ADC4344)
Input Capacitance
10 pF Typ.
540 kHz input @ -10 dB (ADC4344)
76 dB Min., 81 dB Typ.
Step Response8
800 ns Max. to 1 LSB
S/H Aperture Delay
15 ns Max.
F.S. Settling Time
800 ns Typ. to 0.0015%
S/H Aperture Jitter
10 ps rms Max.
S/H Feedthrough 5
–90 dB Max.; –96 dB Typ.
DIGITAL INPUTS
Compatibility
TTL, HCT, and ACT
TRANSFER CHARACTERISTICS
Resolution
16 bits
Full Power Bandwidth
1.5 MHz Min. (ADC4345)
3.0 MHz Min. (ADC4344
Logic "0"
+0.8V Max.
Quantization Error
Logic "1"
+2.0V Min.
±0.5 LSB Max.
Small Signal Bandwidth
2.8 MHz Typ. (ADC34345)
4.0 MHz Typ. (ADC34344)
Integral Nonlinearity
±0.003% FSR Max.
Trigger
Positive Edge Triggered
Slew Rate
Differential Nonlinearity
Loading
1 TTL Load Min.
50V/µs Typ. (ADC4345)
100V/µs Typ. (ADC4344)
Signal to Noise Ratio 6
100 kHz input @ 0 dB
92 dB Min., 95 dB Typ. (ADC4345)
89 dB Min., 92 dB Typ. (ADC4344)
±0.75 LSB Max.
Monotonicity
Guaranteed
Pulse Width
100 ns Min.
No Missing Codes
Guaranteed 0°C to +60°C
High Byte Enable
Active Low, B1-B8, B1
Offset Error
±0.1% FSR Max. (Adj. to Zero)
540 kHz input @ -10 dB (ADC4344)
79 dB Min., 82 dB Typ.
Peak Distortion6
100 kHz input @ 0 dB
Low Byte Enable
Active Low, B9-B16
Gain Error
±0.1% FSR Max. (Adj. to Zero)
Noise w/o Buffer9
10V p-p FSR
50 µV rms Typ., 56 µV rms Max.
(ADC4345)
INTERNAL REFERENCE
–92 dB Max., –99 dB Typ.
Voltage
±5V, ±0.1% Max
@ –20 dB
–92 dB Typ.
Stability
10 ppm/°C Max.
Available Current 3
0.5 mA Max.
540 kHz input @ -10 dB (ADC4344)
84 dB Min., 91 dB Typ.
Total Harmonic Distortion6
20 kHz input @ 0 dB
–90 dB Max., –97 dB Typ.
70 µV rms Typ., 80 µV rms Max.
(ADC4344)
5V p-p FSR
35 µV rms Typ., 40 µV rms Max.
(ADC4345)
50 µV rms Typ., 55 µV rms Max.
(ADC4344)
DIGITAL OUTPUTS
@ –20 dB
–82 dB Typ.
Fan-Out
1 TTL Load
Logic "0"
+0.4V Max.
Noise including Buffer 9
10V p-p FSR
56 µV rms Typ., 70 µV rms Max.
(ADC4345)
79 µV rms Typ., 100 µV rms Max.
(ADC4344)
Supply Rejection per % change
in any supply
ENVIRONMENTAL & MECHANICAL
Specified Temp. Range
0°C to 60°C
Offset
±10 ppm/% Max., ±2 ppm/% Typ.
Storage Temp. Range
–25°C to 80°C
Gain
±10 ppm/% Max., ±2 ppm/% Typ.
Relative Humidity
5V p-p FSR
85%, non-condensing to 60°C
42 µV rms Typ., 50 µV rms Max.
(ADC4345)
60 µV rms Typ., 70 µV rms Max.
(ADC4344)
POWER REQUIREMENTS
Dimensions
2.5" x 3.5" x 0.44"
(63.5 x 88.9 x 11.18 mm)
±15V Supplies
14.55V Min., 15.45V Max.
+5V Supplies
+4.75V Min., +5.25V Max.
Shielding
Electromagnetic 6 sides
Electrostatic 6 sides
STABILITY (0°C TO 60°C)
Differential Nonlinearity TC
±1 ppm/°C Max.
+15V Current Drain
100 mA Typ.
Case Potential
Ground
Offset TC
±10 ppm/°C Max., ±5 ppm/°C Typ.
–15V Current Drain
100 mA Typ.
Gain TC
±10 ppm/°C Max., ±5 ppm/°C Typ.
+5V Current Drain
80 mA Typ.
Warm-Up Time
5 Min. Max.
Total Power Consumption
3.4W Typ.
NOTES
6. See performance testing.
1. All specifications guaranteed at 25°C unless otherwise
noted and supplies at ±15V and +5V.
7. THD + noise represents the ratio of the rms value of the
signal to the total RMS noise below the Nyquist plus the
total harmonic distortion up to the 100th harmonic with an
analysis bandwidth of DC to the Nyquist rate.
2. The input buffer need only be used when a high im-
pedance input is required.
8. Step response represents the time required to achieve the
specified accuracies after an input full scale step change.
3. Reference Load to remain stable during conversion.
4. Dynamic characteristics on ±5V input range and without
input buffer unless otherwise noted.
9. Includes noise from S/H and A/D converter.
5. Measured with a full scale step input with a 20V/µs rise
time.
Specifications subject to change without notice.
Continued from page 1.
SPECIFICATIONS
Input Scaling
Superior performance and ease-of-use of these con-
verters make an ideal solution for those applications
requiring a sample-and-hold amplifier directly at the
input to the A/D converter. Having the S/H amplifier in-
tegrated with the A/D converter benefits the system de-
signer in two ways. First, the S/H is designed specifi-
cally to complement the performance of the A/D con-
verter; for example, the acquisition time, hold mode
settling, and droop rate are optimized for the A/D con-
verter, resulting in exceptional overall performance.
Second, the designer achieves true 16-bit perfor-
mance, avoiding degradation due to ground loops, sig-
nal coupling, jitter, and digital noise introduced when
separate S/H and A/D converters are interconnected.
Furthermore, the accuracy, speed, and quality of the
ADC4344 and ADC4345 are fully ensured by thor-
ough, computer-controlled factory tests of each unit.
The ADC4344 and ADC4345 can be configured for
three input voltage ranges: 0 to +10V, ±2.5V, and ±5V.
The Analog input range should be scaled as close as
possible to the maximum input to utilize the full dynam-
ic range of the converter. Figure 2 describes the input
connections.
Pin#
A8
S/H In 1
Input
A9
Range
0V to +10V
±5V
S/H In 2
–5V Ref
SIG RTN
Input
Input
±2.5V
Input
Figure 2. Input Scaling Connections.
bipolar ranges and check that the digital code is ±1
LSB of the stated code.
Coding and Trim Procedure
Figure 4 shows the output coding and trim calibration
voltages of the A/D converter. For two's complement
operation, simply use the available B1 (MSB) instead
of B1 (MSB). Refer to Figure 3 for use of external off-
set and gain trim potentiometers. Voltage DACs with a
±10V output can be utilized easily when digital control
is required. The input sensitivity of the external offset
and gain control pins is 2 mV/V. If the external offset
and gain adjust pins are not used, connect to Pin A12.
Layout Considerations
Because of the high resolution of the ADC4344/
ADC4345 A/D converters, it is necessary to pay care-
ful attention to the printed-circuit layout for the device.
It is, for example, important to return analog and digital
grounds separately to their respective power supplies.
Digital grounds are often noisy or “glitchy”, and these
glitches can have adverse effects on the performance
of the ADC4345 if they are introduced to the analog
portions of the A/D converter's circuitry. At 16-bit reso-
lution, the size of the voltage step between one code
transition and the succeeding one for a 5V full scale
range is only 76 µV. It is evident that any noise in the
analog ground return can result in erroneous or miss-
ing codes. It is important in the design of the PC board
to configure a low-impedance ground-plane return on
the printed-circuit board. It is only at this point, where
the analog and digital power returns should be made
common.
To trim the offset of the AD converter, apply the offset
voltage shown in Figure 4 for the appropriate voltage
range. Adjust the offset trim potentiometer such that
the 15 MSBs are "0" and the LSB alternates equally
between “0” and “1” for the unipolar ranges or all 16
bits are in transition for the bipolar ranges.
To trim the gain of the ADC4345, apply the range
(+FS) voltage shown in Figure 4 for the appropriate
range. Adjust the gain trim potentiometer such that the
15 MSBs are “1” and the LSB alternates equally be-
tween “0” and “1”.
To check the trim procedure, apply 1/2 full scale volt-
age for a unipolar range or –full scale voltage for the
Trigger
S/H Cont
(Internal)
Hold
Sample
A/D Clock
(Internal)
*Gain Adj.
+5V REF
*Off Adj.
R 1
=
R
R
C
50K
1
=
=
=
50K
2
1
Transfer
Data
0.1 µF
0.1 µF
N-1 Data
N Data
C2
R 2
25 ns Min.
C1
C2
Ana Gnd.
–5V REF
Time (ns)
0
ADC4344 600 ns
ADC4345 1.2 µs
850 ns 1000 ns
1.45 µs 2.0 µs
*Note: If not required,
connect to Ana Gnd.
Figure 5. Timing Diagram.
Figure 3. Offset and Gain Adjustment Circuit.
PRINCIPLE OF OPERATION
UNIPOLAR BINARY
MSB
0V TO +10V
The ADC4344 and ADC4345 are 16-bit sampling A/D
converters with a throughput rate of up to 1 MHz.
These converters are available in two externally config-
ured full scale ranges of 5V p-p and 10V p-p. Both op-
tions are externally or user-programmable for bipolar
and unipolar inputs of ±2.5V, ±5V and 0 to +10V. Two's
complement format can be obtained by utilizing B1 in-
stead of B1.
LSB
+FS
111111111111111*
=
=
=
+9.99977V
+5.00000V
+0.00008V
1/2 FS 1000000000000000
Offset 000000000000000*
OFFSET BINARY
±2.5V input ±5V input
MSB
111111111111111*
Offset ****************
+FS 000000000000000*
LSB
+FS
=
=
=
+2.49989V
–0.00004V
–2.49996V
+4.99977V
–0.00008V
–4.99992V
To understand the operating principles of the A/D con-
verter, refer to the timing diagram of Figure 5 and the
simplified block diagram of Figure 6. The simplified
block diagram illustrates the two successive passes in
the sub-ranging scheme of the AD converter.
2'S COMPLEMENT
±2.5V input ±5V input
MSB
LSB
+FS
Offset ****************
–FS 100000000000000*
011111111111111*
=
=
=
+2.49989V
–0.00004V
–2.49996V
+4.99977V
–0.00008V
–4.99992V
The A/D converter section of the converters is factory-
trimmed and optimized to operate with a 10V p-p input
Figure 4. Coding and Trim Calibration Table.
10V p-p
2V p-p
S/H In A
S/H In B
S/H Amp
A= -1 or -2
–
+
9
9-Bit
ADC
Logic
A= -0.2
9
To DAC
10V p-p
(2nd Pass)
S/H Amp
A= -1 or -2
S/H In A
S/H In B
1st Pass
DAC In
From
Logic
±2 mA
16-Bit
Linear DAC
9
Σ
–
+
0.5V p-p
9-Bit
ADC
–
9
O/U Flow
B1-B16
B1
16
+
A= 6.4
Logic
A= 4
EOC
2nd Pass
Figure 6. Operating Principle of the ADC4344 and ADC4345.
voltage range. Scaling resistors at the S/H inputs con- might be possible to realize on a laboratory benchtop,
figure the three input ranges and provide a S/H output it clearly would be impractical to achieve on a produc-
voltage to the A/D converter of 10V p-p.
tion basis. The key to the conversion technique used in
the A/D converter is the 16-bit accurate and 16-bit-lin-
ear D/A converter which serves as the reference ele-
ment for the conversion's second pass. The use of pro-
prietary sub-ranging architecture in the A/D converter
results in a sampling A/D converter that offers un-
precedented speed and transfer characteristics at the
16-bit level.
The first pass starts with a low-to-high transition of the
trigger pulse. This signal places the S/H into the Hold
mode and starts the timing logic. At this time, the inter-
nal logic locks out any additional triggers that may in-
advertently occur and corrupt the conversion process
until the routine is complete. The path of the 10V p-p
input signal during the first pass is through a 5:1 atten-
uator circuit to the 9-bit ADC with an input range of 2V The ADC4345 has a 3-state output structure. Users
p-p. At 50 ns, the ADC converts the signal and the 9 can enable the eight MSBs and B1 with HIBYTEN and
bits are latched both into the logic as the MSBs and
into the 16-bit accurate DAC for the second pass.
the eight LSBs with LOBYTEN (both are active low).
This feature makes it possible to transfer data from the
A/D converter to an 8-bit microprocessor bus. However,
to prevent the coupling of high frequency noise from the
microprocessor bus into the A/D converter, the output
data must be buffered (see Figure 7).
The second pass subtracts the 9-bit, 16-bit accurate
DAC output and the S/H output with the result equal to
the 9-bit quantization error of the DAC, or 19.5 mV p-p.
This “error” voltage is then amplified by a gain of 25.6
and is now 0.5V p-p or 1/4 of the full scale range of the Figure 7 shows a typical application circuit for the A/D
ADC allowing a 2-bit overlap safety margin. At approxi- converter: a four channel, high speed, high resolution
mately 1.2 µs, the DAC and the “error” amplifier have A/D conversion system tied into an 8-bit bus structure.
had sufficient time to settle to 16-bit accuracy and the This circuit could be part of the front end of a medical
amplified “error” voltage is then digitized by the ADC
imaging system, an ATE system or a sampling oscillo-
with the 9-bit second pass result latched into the logic. scope. The 16-bit resolution provides 96 dB dynamic
At this time the S/H returns to the Sample mode to range for each channel, and the 500 kHz throughput
begin acquiring the next sample.
rate provides approximately 125 kHz throughput per
channel. (In certain CT imaging applications, it may be
possible to multiplex as many as 24 channels into the
A/D converter.)
The 1/4 full scale range in the second pass produces a
2-bit overlap of the two passes. This is a scheme used
in the A/D converter to provide an output word that is
accurate and linear to 16 bits. This method corrects for For multiplexed inputs, the high input impedance of the
any gain and linearity errors in the amplifying circuitry, on board buffer input is required. By addressing the
as well as the 9-bit flash A/D converter. Without the multiplexer at the time of the ADC trigger (Figure 5),
use of this overlapping correction scheme, it would be the mux and buffer settling times do not add to the sys-
necessary that all the components in the A/D converter tem throughput rates.
be accurate to the 16-bit level. While such a design
For interfacing into a 16-bit bus, the tri-state latch or
digital buffers may still be required to prevent coupling
of high frequency noise from the microprocessor bus
into the A/D converter. Note that in Figure 7 the signal
return is NOT tied to the external common ground-
plane return but instead is common at a strategic point
inside the A/D converter.
All Capacitors are
6.8 µF Bypassed by
0.01 µF caps.
Ana
Gnd
+15V -15V +5V
Sig. Rtn
Buf In
Dig
Gnd
Sig Rtn
Ch 0 In
8
8
8
D0-D7
B1-B8
Buf Out
Tri-State
Buffer
S/H In 1
B9-B16
ADC4344
Ch 1 In
Ch 2 In
Ch 3 In
S/H In 2
-5V Ref
S/H Out
A/D In
O/U Flow
Transfer
O/U Flow
Transfer
Digital
Buffer
Trig
HiBytEn
LoBytEn
Both the ability of the A/D converter Sample-and-Hold
amplifier to acquire new data to within ±1 LSB after a
full-scale step change at the analog input, and the su-
perb dc characteristics exhibited by the A/D converter,
are key factors in establishing this part as the ideal
choice for high speed, high performance data acquisi-
tion systems.
4
Ch Add
Trigger
HiBytEn
LoBytEn
Figure 7. ADC4344 Configured for: 4-CH input, 0V
to +10V input range, true binary data driving an
8-bit bus.
A1
A2
+15V
AGND
–15V
BUFFER IN
BUFFER OUT
A/D IN
S&H OUT
S&HIN1
S&H IN2
SIG RTN
SIG RTN
SIG RTN
+5V REF
OFF-SET ADJ
GAIN ADJ
–5V REF
B1
B3
B5
B7
B9
B11
B13
B15
B17
B19
B21
B23
B25
B27
B29
B31
+5V
B2
B4
B6
B8
B10
B12
B14
B16
B18
B20
B22
B24
B26
B28
B30
B32
+5V
.125 Dia.
(4 Places)
.30 Dia.
Clearance for
Stand-off
DGND
N.C.
N.C.
N.C.
BIT1
BIT3
BIT5
BIT7
BIT9
BIT11
BIT13
BIT15
TRIGGER
LOBYTE ENB
O/U FLOW
DGND
N.C.
N.C.
N.C.
BIT1
BIT2
BIT4
BIT6
BIT8
BIT10
BIT12
BIT14
BIT16
TRANSFER
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
3.50
B32
B2
2.060
A16
B31
B1
.035 Dia.
(48 Places)
15 Equal
Spaces @
100 = 1.500
(Tolerance
2.50
Top View
2.980
Noncumulative)
A1
.280
0
.220
.020
.220
HIBYTE ENB
3.060
3.080
Figure 9. ADC4345 Pin Assignment.
0
.44 max.
4-40 x .16 Dp
(4 Places)
Use 4-40 x .18 screw
.04 typ.
User Board
A1
Figure 8. ADC4344/
ADC4345 Mechanical.
.220
.020
2.980
.220
3.060
3.080
Ordering Guide
Simply Specify
ADC4344M – 1 MHz
ADC4345M – 500 kHz
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