ADC-B207 [ETC]
7- BIT 20MHZ CMOS FLASH A/D CONVERTERS; 7位20MHZ CMOS FLASH A / D转换器
| 型号： | ADC-B207 |
| 厂家： | 
ETC |
| 描述： | 7- BIT 20MHZ CMOS FLASH A/D CONVERTERS |
| 文件： | 总6页 (文件大小：162K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
®
ADC-2 0 7
7-Bit, 20MHz, CMOS
Flash A/D Converters
INN OVATION and E XCELLENCE
FEATURES
• 7-bit flash A/D converter
• 20MHz sampling rate
• Low power (250mW)
• Single +5V supply
• 1.2 micron CMOS technology
• 7-bit latched 3-state output with overflow bit
• Surface-mount versions
• High-reliability version
• No missing codes
GENERAL DESCRIPTION
The ADC-207 has 128 comparators which are auto-balanced
on every conversion to cancel out any offsets due to
temperature and/or dynamic effects. The resistor ladder has a
midpoint tap for use with an external voltage source to improve
integral linearity beyond 7 bits. The ADC-207 also provides the
user with 3-state outputs for easy interfacing to other
components.
The ADC-207 is the industry’s first 7-bit flash converter using an
advanced high-speed VLSI 1.2 micron CMOS process. This
process offers some very distinctive advantages over other
processes, making the ADC-207 unique. The smaller
geometrics of the process achieve high speed, better linearity
and superior temperature performance.
Since the ADC-207 is a CMOS device, it also has very low
power consumption (250mW). The device draws power from
a single +5V supply and is conservatively rated for 20MHz
operation. The ADC-207 allows using sampling apertures as
small as 12ns, making it more closely approach an ideal
sampler. The small sampling apertures also let the device
operate at greater than 20MHz.
There are six models of the ADC-207 covering two operating
temperature ranges, 0 to +70°C and –55 to +125°C. Two high-
reliability "QL" models are also available.
Æ2
Æ1
Æ2
Æ1
INPUT/OUTPUT
CONNECTIONS
CLOCK
1 CLOCK INPUT
GENERATOR
ANALOG INPUT
+REFERENCE
4
6
R/2
Q
Q
D
10 OVERFLOW
DIP
PINS
LCC
PINS
D
G
+VDD
FUNCTION
G
D
+5V SUPPLY 18
R
Q
Q
11 BIT 1 (MSB)
1
2
CLOCK INPUT
DIGITAL GROUND
–REFERENCE
ANALOG INPUT
MIDPOINT
+REFERENCE
ANALOG GROUND
CS1
1
DIGITAL GROUND
ANALOG GROUND
2
7
D
G
G
D
R
4
Q
Q
3
5
12 BIT 2
13 BIT 3
4
6
128-TO-7
ENCODER
G
D
R/2
R/2
5
7
RANGE MIDPOINT
5
6
7
8
9
D
G
G
D
Q
Q
14 BIT 4
8
11
12
13
14
16
17
19
20
21
23
24
9
CS2
G
D
R
R
10
11
12
13
14
15
16
17
18
OVERFLOW
BIT 1 (MSB)
BIT 2
Q
Q
Q
15 BIT 5
D
G
G
D
Q
Q
16 BIT 6
BIT 3
–REFERENCE
3
D
G
BIT 4
G
D
BIT 5
17 BIT 7 (LSB)
BIT 6
G
BIT 7 (LSB)
+5V SUPPLY
8
9
CS1
CS2
Figure 1. ADC-207 Functional Block Diagram (DIP Pinout)
DATEL, Inc., 11 Cabot Boulevard, Mansfield, MA 02048-1151 (U.S.A.) • Tel: (508) 339-3000 Fax: (508) 339-6356 • For immediate assistance (800) 233-2765
®
®
ADC-2 0 7
ABSOLUTE MAXIMUM RATINGS
PHYSICAL/ENVIRONMENTAL
PARAMETERS
LIMITS
UNITS
PARAMETERS
MIN.
TYP.
MAX.
UNITS
Power Supply Voltage (+V
Digital Inputs
Analog Input
Reference Inputs
Digital Outputs
)
–0.5 to +7
–0.5 to +5.5
–0.5 to (+VDD +0.5)
Volts
Volts
Volts
Volts
Volts
Operating Temp. Range, Case:
LC/MC Versions
MM/LM/QL Versions
Storage Temp. Range
Package Type
DIP
DD
0
–55
–65
—
—
—
+70
+125
+150
°C
°C
°C
–0.5 to +V
DD
–0.5 to +5.5
(short circuit protected to ground)
Lead Temperature (10 sec. max.)
18-pin ceramic DIP
24-pin ceramic LCC
+300
°C
LCC
TECHNICAL NOTES
FUNCTIONAL SPECIFICATIONS
(Typical at +5V power, +25°C, 20MHz clock, +REFERENCE = +5V,
–REFERENCE = ground, unless noted)
1. Input Buffer Amplifier – Since the ADC-207 has a switched
capacitor type input, the input impedance of the 207 is
dependent on the clock frequency. At relatively slow
ANALOG INPUT
MIN.
TYP.
MAX.
UNITS
conversion rates, a general purpose type input buffer can be
used; at high conversion rates DATEL recommends either
the HA-5033 or Elantec 2003. See Figure 2 for typical
connections.
InputType
Input Range (dc-20MHz)
Input Impedance
Single-ended, non-isolated
0
—
1000
10
+5
—
—
Volts
Ohms
pF
—
—
Input Capacitance (FullRange)
2. Reference Ladder – Adjusting the voltage at +REFERENCE
adjusts the gain of the ADC-207. Adjusting the voltage at –
REFERENCE adjusts the offset or zero of the ADC-207.
The midpoint pin is usually bypassed to ground through a
0.1µF capacitor, although it can be tied to a precision
voltage halfway between +REFERENCE and
DIGITAL INPUTS
Logic Levels
Logic "1"
Logic "0"
Logic Loading "1"
Logic Loading "0"
Sample Pulse Width
(During Sampling Portion of Clock)
Reference Ladder Resistance
+3.2
—
—
—
—
±1
±1
—
+0.8
±5
Volts
Volts
microamps
microamps
—
±5
–REFERENCE. This would improve integral linearity
beyond 7 bits.
12
225
—
330
—
—
ns
Ohms
3. Clock Pulse Width – To improve performance at Nyquist
bandwidths, the clock duty cycle can be adjusted so that the
low portion of the clock pulse is 12ns wide. The smaller
aperture allows the ADC-207 to closely resemble an ideal
sampler. See Figure 4.
PERFORMANCE
Conversion Rate ➀
Harmonic Distortion ➁
(8MHz 2nd Order Harmonic)
Differential Gain ➂
Differential Phase ➂
Aperture Delay
Aperture Jitter
No Missing Codes
LC/MC grade
LM/MM grade
Integral Linearity ➃
Over Temperature Range
Differential Nonlinearity
Over Temperature Range
Power Supply Rejection
20
25
—
MHz
—
—
—
—
—
–40
3
1.5
8
—
—
—
—
—
dB
%
degrees
ns
4. At sampling rates less than 100kHz, there may be some
degradation in offset and differential nonlinearity.
50
ps
Performance may be improved by increasing the clock duty
cycle (decreasing the time spent in the sample mode).
0
–55
—
—
—
+70
+125
±1
°C
°C
LSB
LSB
LSB
±0.8
±0.8
±0.3
±0.4
±0.02
CAUTION
±1
Since the ADC-207 is a CMOS device, normal precautions
against static electricity should be taken. Use ground straps,
grounded mats, etc. The Absolute Maximum Ratings of the
device MUST NOT BE EXCEEDED as irrevocable damage to
the ADC-207 will occur.
—
—
—
±0.6
±0.6
—
LSB
%FSR/%Vs
DIGITAL OUTPUTS
Data Coding
Data Output Resolution
Logic Levels
Straight binary
—
+5V
7
—
Bits
20MHz
CLOCK
+15
Logic "1"
+2.4
—
–4
+4.5
—
—
—
+0.4
—
Volts
Volts
mA
4.7µF
Logic "0" (at 1.6mA)
Logic Loading "1"
Logic Loading "0"
Output Data Valid Delay
(From Rising Edge)
+
47µF
0.01µF
+5V
+
0.1µF
+4
—
—
mA
1
2
18
17
CLOCK
+VDD
B7
—
15
25
ns
B7 (LSB)
B6
DIGITAL GND
–REFERENCE
VIN
12
3
4
5
16
15
14
13
12
11
10
B6
B5
POWER REQUIREMENTS
11
5
10
W
B5
HA-5033
10
Power Supply Range (+V
Power Supply Current
Power Dissipation
)
DD
+3.0
—
—
+5.0
+50
250
+5.5
+70
385
Volts
mA
mW
MID
B4
B3
B2
B4
6
7
8
9
+REFERENCE
B3
47µF
ANALOG GND
CS1
B2
0.1µF
B1 (MSB)
OF
B1
Footnotes:
➀ At full power input and chip selects enabled.
➁ At 4MHz input and 20MHz clock.
0.1µF
CS2
OF
+
–15
➂For 10-step, 40 IRE NTSC ramp test.
➃Adjustable using reference ladder midpoint tap. See ADC-207 Operation.
Figure 2. Typical Connections for Using the ADC-207
2
®
®
ADC-2 0 7
OUTPUT CODING
(+REFERENCE = +5.12V, –REFERENCE = ground, MIDPOINT = no connection)
TIMING DIAGRAM
NOTE: The reference should be held to ±0.1% accuracy or
better. Do not use the +5V power supply as a
reference input without precision regulation and high
frequency decoupling.
Æ2
Æ1
Æ2
Æ1
Æ2
Æ1
AUTO
ZERO
SAMPLE
N
AUTO
ZERO
SAMPLE
N + 1
AUTO
ZERO
SAMPLE
N + 2
CLOCK
Values shown here are for a +5.12V reference. Scale other
references proportionally. Calibration equipment should test for
code changes at the midpoints between these center values
shown in Table 1. For example, at the half-scale major carry,
set the input to 2.54V and adjust the reference until the code
flickers equally between 63 and 64. Note also that the
weighting for the comparator resistor network leaves the first
and last thresholds within 1/2LSB of the end points to adjust
the code transition to the proper midpoint values.
OUTPUT
DATA
N DATA
N+1 DATA
25ns max.
25ns max.
Table 1. ADC-207 Output Coding
Analog Input
(Center Value)
1
2
3
4
5
6
7
LSB
Hexadecimal
(Incl. 0V)
Code
Overflow
MSB
Decimal
0.00V
+0.04V
+1.28V
+2.52V
+2.56V
+2.60V
+3.84V
+5.08V
+5.12V
Zero
+1LSB
+1/4FS
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
1
0
0
0
1
0
0
0
1
1
0
0
0
1
0
0
0
1
1
0
0
0
1
0
0
0
1
1
0
0
0
1
0
0
0
1
1
0
1
0
1
0
1
0
1
1
0
1
32
63
64
65
96
127
255*
00
01
20
3F
40
41
60
7F
FF
+1/2FS – 1LSB
+1/2FS
+1/2FS + 1LSB
+3/4FS
+FS
Overflow
*Note that the overflow code does not clear the data bits.
ADC-207 OPERATION
The ADC-207 uses a switched capacitor scheme in which
there is an auto-zero phase and a sampling phase. See
Figure 1 and Timing Diagram. The ADC-207 uses a single
clock input. When the clock is at a high state (logic 1), the
Continuous conversion requires one cycle/sample (one positive
pulse and one negative pulse). The 3-state buffer has two
enable lines, CS1 and CS2. Table 2 shows the truth table for
chip select signals. CS1 has the function of enabling/disabling
bits 1 through 7. CS2 has the function of enabling/disabling
bits 1 through 7 and the overflow bit. Also, a full-scale input
produces all ones, including the overflow bit at the output. The
ADC-207 has an adjustable resistor ladder string. The top end,
idle point, and bottom end are brought out for use with
applications circuits.
ADC-207 is in the auto-zero phase (Ø1). When the clock is at
a low state (logic 0), the ADC-207 is in the sampling phase
(Ø2). During phase 1, the 128 comparator outputs are shorted
to their inputs through CMOS switches. This serves the
purpose of bringing the inputs and outputs to the transition
levels of the respective comparators. The inputs to the
comparators are also connected to 128 sampling capacitors.
The other end of the 128 capacitors are also shorted to 128
taps of a resistor ladder, via CMOS switches. Therefore, during
phase 1 the sampling capacitors are charged to the differential
voltage between a resistor tap and its respective comparator
transition voltage.
These pins are called +REFERENCE, MIDPOINT and
–REFERENCE, respectively. In typical operation
+REFERENCE is tied to +5V, –REFERENCE is tied to ground,
and MIDPOINT is bypassed to ground. Such a configuration
results in a 0 to +5V input voltage range. The MIDPOINT pin
can also be tied to a +2.5V source to further improve integral
linearity. This is usually not necessary unless better than 7-bit
linearity is needed.
This eliminates offset differences between comparators and
yields better temperature performance. During phase 2 (Ø2) the
input voltage is applied to the 128 capacitors, via CMOS
switches. This forces the comparators to trip either high or low.
Since the comparators during phase 1 were sitting at their
transition point, they can trip very quickly to the correct state.
Also during phase 2, the outputs of the comparators are loaded
into internal latches which in turn feed a128-to-7 encoder. When
going back into phase 1, the output of the encoder is loaded into
an output latch. This latch then feeds the 3-state output buffer.
Table 2. Chip Select Truth Table
CS1
CS2
Bits 1-7
Overflow Bit
0
1
0
1
0
0
1
1
3-State Mode
3-State Mode
Data Outputed
3-State Mode
3-State Mode
3-State Mode
Data Outputed
Data Outputed
This means that the ADC-207 is of pipeline design. To do a
single conversion, the ADC-207 requires a positive pulse
followed by a negative pulse followed by a positive pulse.
NOTE: Reduce the sample time (sample pulse)
3
®
®
ADC-2 0 7
9
8
13
12
11
CLOCK OUT
CLOCK IN
4
20k
6
1
2
3
5
0.01µF
10pF
to 12ns to improve performance above
20MHz. Such a configuration will closely
resemble an ideal sampler.
GROUND
+5 VOLTS
Figure 3. Optional Pulse Shaping Circuit
USINGTWO ADC-207’S FOR 8-BIT RESOLUTION
BEAT FREQUENCY AND ENVELOPE TESTS
Two ADC-207’s (A and B) are cascadable for applications
requiring 8-bit resolution. The device A provides a typical 7-bit
output. The OVERFLOW signal of device A turns off device A
and turns on the device B. The OVERFLOW signal of device A
is also used as MSB for 8-bit operation. The device B provides
the other seven bits from the input signal. Figure 4 shows the
circuit connections for the application.
Figure 5 shows an actual ADC-207 plot of the Beat Frequency
Test. This test uses a 20MHz clock input to the ADC-207 with
a 20.002MHz full-scale sine wave input. Although the
converter would not normally be used in this mode because
the input frequency violates Nyquist criteria for full recovery of
signal information, the test is an excellent demonstration of the
ADC-207’s high-frequency performance.
The effect of the 2kHz frequency difference between the input
and the clock is that the output will be a 2kHz sinusoidal digital
data array which "walks" along the actual input at the 2kHz
beat note frequency. Any inability to follow the 20.002MHz
input will be immediately obvious by plotting the digital data
array. Further arithmetic analysis may be done on the data
array to determine spectral purity, harmonic distortion, etc.
This test is an excellent indication of:
OVERFLOW
+5V
18
+5.12
BIT 1 (MSB)
REFERENCE
+VDD
6
8
10
11
12
IN
OF
+REFERENCE
CS1
10
BIT2
BIT3
B1
B2
TURN
13
14
4
1
BIT4
BIT5
B3
B4
B5
B6
ANALOG INPUT
CLOCK
OPTIONAL
MIDSCALE
ADJUST
1. Full power input bandwidth of all 128 comparators.
(Any gain loss would show as signal distortion.)
15
16
BIT6
9
3
BIT7
CS2
17
2
BIT8 (LSB)
B7
2. Phase response linearity vs. instantaneous signal
magnitude. (Phase problems would show as
improper codes.)
DIG GND
–REFERENCE
ANALOG GROUND
CLOCK IN
7
3. Comparator slew rate limiting.
7
Figure 6 shows an actual ADC-207 plot of the Envelope Test.
This test is a variation of the previous test but uses a
10.002MHz sinewave input to give two overlapping cycles
when the data is reconstructed by a D/A converter output to an
oscilloscope. The scope is triggered by the 20MHz clock used
by the A/D. Any asymmetry between positive and negative
portions of the signal will be very obvious. This test is an
excellent indication of slew rate capability. At the peaks of the
envelope, consecutive samples swing completely through the
input voltage range.
ANALOG GROUND
10
6
8
OF
B1
B2
+REFERENCE
ANALOG IN
11
12
CS1
1
4
13
14
CLOCK
B3
B4
ANALOG INPUT
15
16
17
2
9
B5
B6
CS2
18
+VDD
+5V
B7
3
–REFERENCE
DIG GND
REFERENCE
GROUND
NOTE: The output data bit numbering is offset
by a bit to the device B’s output.
Figure 4. Using Two ADC-207’s for 8-Bit Operation
®
®
ADC-2 0 7
120
110
100
90
80
70
60
50
40
30
20
10
0
120
110
100
90
80
70
60
50
40
30
20
10
0
OUTPUT
CODES
OUTPUT
CODES
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2 1.3
1.4
1.5
NUMBER OF SAMPLES(X103
)
NUMBER OF SAMPLES(X103
)
Figure 6. 10MHz Envelope Test
Figure 5. Beat Frequency Test at 20MHz
FFTTEST
This test actually produces an amplitude versus frequency graph (Figure 7) which indicates harmonic distortion and signal-to-noise
ratio. The theoretical rms signal-to-noise ration for a 7-bit converter is +43.8dB.
4MHz FUNDAMENTAL
SAMPLE PULSE = 25ns
70
69.2
65
60
55
50
45
40
35
27.3
30
25
20
15
10
0
–5
–10
0
1
2
3
4
5
6
7
8
9
10
FREQUENCY (MHz)
Figure 7. FFT Test Using the ADC-207
®
®
ADC-2 0 7
MECHANICAL DIMENSIONS INCHES (MM)
24-Pin Ceramic LCC
18-Pin Ceramic DIP
+0.010
–0.005
0.400
+0.25
–0.13
(10.16
)
0.960 MAX.
(24.38 MAX.)
16
10
18
0.400 +–00..000105
24
+0.25
1
–0.13
(10.16
)
DATEL
ADC-207MC
0.220/0.310
(5.59/7.87)
10
4
1
9
TOP VIEW
0.090 MAX.
(2.29 MAX.)
PIN 1
IDENTIFIER
0.015/0.060
(0.38/1.52)
0.200 MAX.
(5.1 MAX.)
0.020 ±0.005
(0.51 ±0.13)
0.008/0.015
(0.20/0.38)
0.050
(1.270)
TYP.
PIN 1
INDEX
0.250 ±0.005
(6.35 ±0.13)
0.014/0.023 0.100 TYP.
0.290/0.320
(7.36/8.13)
(0.35/0.58)
(2.540)
SEATING
PLANE
0.035
(0.889)
0.250 ±0.005
(6.35 ±0.13)
ORDERING INFORMATION
MODEL
TEMP. RANGE
PACKAGE
ADC-207MC
ADC-207MM
ADC-207MM-QL
0 to +70°C
–55 to +125°C
–55 to +125°C
18-pin DIP
18-pin DIP
18-pin DIP
ADC-207LC
0 to +70°C
24-pin CLCC
24-pin CLCC
24-pin CLCC
ADC-207LM
ADC-207LM-QL
–55 to +125°C
–55 to +125°C
ACCESSORIES
ADC-B207/208
Evaluation Board for DIP Version
(without ADC-207)
®
®
ISO 9001
R
E
G
I
S
T
E
R
E
D
INN OVAT ION and E XCELLENCE
DS-0038C 12/04
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151
Tel: (508) 339-3000 (800) 233-2765 Fax: (508) 339-6356
Internet: www.datel.com E-mail:sales@datel.com
Data Sheet Fax Back: (508) 261-2857
DATEL (UK) LTD. Tadley, England Tel: (01256)-880444
DATEL S.A.R.L. Montigny Le Bretonneux, France Tel: 1-34-60-01-01
DATEL GmbH München, Germany Tel: 89-544334-0
DATEL KK Tokyo, Japan Tel: 3-3779-1031, Osaka Tel: 6-354-2025
DATEL makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein
do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice. The DATEL logo is a registered DATEL, Inc. trademark.
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