AD8541AKS_技术文档

General-Purpose CMOS

Rail-to-Rail Amplifiers

a

AD8541/AD8542/AD8544

FEATURES

PIN CONFIGURATIONS

Single Supply Operation: 2.7 V to 5.5 V

Low Supply Current: 45 ␮A/Amplifier

Wide Bandwidth: 1 MHz

No Phase Reversal

Low Input Currents: 4 pA

Unity Gain Stable

5-Lead SC70 and SOT-23

(KS and RT Suffixes)

AD8541

V+

OUT A

V؊

1

2

5

4

Rail-to-Rail Input and Output

+IN A

3

؊IN A

APPLICATIONS

ASIC Input or Output Amplifier

Sensor Interface

Piezo Electric Transducer Amplifier

Medical Instrumentation

Mobile Communication

Audio Output

8-Lead SOIC

(R Suffix)

1

8

NC

V+

NC

AD8541

2

7

–IN A

Portable Systems

OUT A

NC

3

4

6

5

+IN A

V–

GENERAL DESCRIPTION

NC = NO CONNECT

The AD8541/AD8542/AD8544 are single, dual and quad rail-

to-rail input and output single supply amplifiers featuring very

low supply current and 1 MHz bandwidth. All are guaranteed to

operate from a 2.7 V single supply as well as a 5 V supply. These

parts provide 1 MHz bandwidth at low current consumption of

45 µA per amplifier.

8-Lead SOIC, MSOP, and TSSOP

(R, RM, and RU Suffixes)

AD8542

OUT A

–IN A

+IN A

V–

8

7

6

5

1

2

3

4

V+

OUT B

Very low input bias currents enable the AD8541/AD8542/AD8544

to be used for integrators, photodiode amplifiers, piezo electric

sensors and other applications with high source impedance. Supply

current is only 45 µA per amplifier, ideal for battery operation.

–IN B

+IN B

Rail-to-rail inputs and outputs are useful to designers buffering

ASICs in single supply systems. The AD8541/AD8542/AD8544

are optimized to maintain high gains at lower supply voltages,

making them useful for active filters and gain stages.

14-Lead SOIC and TSSOP

(R and RU Suffixes)

The AD8541/AD8542/AD8544 are specified over the extended

industrial (–40°C to +125°C) temperature range. The AD8541

is available in 8-lead SOIC, 5-lead SC70, and 5-lead SOT-23

packages. The AD8542 is available in 8-lead SOIC, 8-lead

MSOP, and 8-lead TSSOP surface-mount packages. The AD8544

is available in 14-lead narrow SOIC, and 14-lead TSSOP surface

mount packages. All TSSOP, MSOP, SC70, and SOT versions

are available in tape and reel only.

14

13

12

OUT D

–IN D

OUT A

–IN A

1

2

3

4

5

+IN D

+IN A

V+

AD8544

11 V–

10 +IN C

+IN B

–IN B

9

6

7

–IN C

8

OUT C

OUT B

REV. B

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

AD8541/AD8542/AD8544–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS ^(V_S^{= 2.7 V, V}_CM= 1.35 V, T_A= 25؇C unless otherwise noted)

Parameter

Symbol

Conditions

Min

Typ Max

Unit

INPUT CHARACTERISTICS

Offset Voltage

V_OS

I_B

1

4

6

7

60

mV

pA

–40°C ≤ T_A≤ +125°C

Input Bias Current

–40°C ≤ T_A≤ +85°C

–40°C ≤ T_A≤ +125°C

100

1,000

30

pA

Input Offset Current

I_OS

0.1

–40°C ≤ T_A≤ +85°C

–40°C ≤ T_A≤ +125°C

50

500

2.7

pA

V

Input Voltage Range

0

Common-Mode Rejection Ratio

CMRR

A_VO

V_CM= 0 V to 2.7 V

40

38

100

50

2

45

dB

–40°C ≤ T_A≤ +125°C

R_L= 100 kΩ , V_O= 0.5 V to 2.2 V

–40°C ≤ T_A≤ +85°C

–40°C ≤ T_A≤ +125°C

–40°C ≤ T_A≤ +85°C

–40°C ≤ T_A≤ +125°C

Large Signal Voltage Gain

500

V/mV

µV/°C

fA/°C

Offset Voltage Drift

Bias Current Drift

∆V_OS/∆T

∆I_B/∆T

4

100

2,000

25

Offset Current Drift

∆I_OS/∆T

OUTPUT CHARACTERISTICS

Output Voltage High

V_OH

V_OL

I_L= 1 mA

–40°C ≤ T_A≤ +125°C

I_L= 1 mA

–40°C ≤ T_A≤ +125°C

V_OUT= V_S– 1 V

2.575 2.65

2.550

V

Output Voltage Low

35

100

125

mV

mA

Ω

Output Current

I_OUT

I_SC

Z_OUT

15

20

50

Closed Loop Output Impedance

f = 200 kHz, A_V= 1

POWER SUPPLY

Power Supply Rejection Ratio

PSRR

I_SY

V_S= 2.5 V to 6 V

–40°C ≤ T_A≤ +125°C

V_O= 0 V

65

60

76

38

dB

µA

Supply Current/Amplifier

55

75

–40°C ≤ T_A≤ +125°C

DYNAMIC PERFORMANCE

Slew Rate

Settling Time

Gain Bandwidth Product

Phase Margin

SR

t_S

GBP

Φo

R_L= 100 kΩ

To 0.1% (1 V Step)

0.4

0.75

5

980

63

V/µs

µs

kHz

Degrees

NOISE PERFORMANCE

Voltage Noise Density

e_n

i_n

f = 1 kHz

f = 10 kHz

40

38

<0.1

nV/√Hz

pA/√Hz

Current Noise Density

Specifications subject to change without notice.

–2–

REV. B

AD8541/AD8542/AD8544

ELECTRICAL CHARACTERISTICS ^(V_S^{= 3.0 V, V}_CM= 1.5 V, T_A= 25؇C unless otherwise noted)

Parameter

Symbol

Conditions

Min

Typ Max

Unit

INPUT CHARACTERISTICS

Offset Voltage

V_OS

I_B

1

4

6

7

mV

pA

–40°C ≤ T_A≤ +125°C

Input Bias Current

60

100

1,000

30

50

500

3

–40°C ≤ T_A≤ +85°C

–40°C ≤ T_A≤ +125°C

Input Offset Current

I_OS

0.1

–40°C ≤ T_A≤ +85°C

–40°C ≤ T_A≤ +125°C

Input Voltage Range

0

V

Common-Mode Rejection Ratio

CMRR

A_VO

V

_CM= 0 V to 3 V

40

38

100

50

2

45

dB

–40°C ≤ T_A≤ +125°C

R_L= 100 kΩ , V_O= 0.5 V to 2.2 V

–40°C ≤ T_A≤ +85°C

–40°C ≤ T_A≤ +125°C

–40°C ≤ T_A≤ +85°C

–40°C ≤ T_A≤ +125°C

Large Signal Voltage Gain

500

V/mV

µV/°C

fA/°C

Offset Voltage Drift

Bias Current Drift

∆V_OS/∆T

∆I_B/∆T

4

100

2,000

25

Offset Current Drift

∆I_OS/∆T

OUTPUT CHARACTERISTICS

Output Voltage High

V_OH

V_OL

I_L= 1 mA

–40°C ≤ T_A≤ +125°C

I_L= 1 mA

–40°C ≤ T_A≤ +125°C

V_OUT= V_S– 1 V

2.875 2.955

V

2.850

Output Voltage Low

32

100

125

mV

mA

Ω

Output Current

I_OUT

I_SC

Z_OUT

18

25

50

Closed Loop Output Impedance

f = 200 kHz, A_V= 1

POWER SUPPLY

Power Supply Rejection Ratio

PSRR

I_SY

V_S= 2.5 V to 6 V

–40°C ≤ T_A≤ +125°C

V_O= 0 V

65

60

76

40

dB

µA

Supply Current/Amplifier

60

75

–40°C ≤ T_A≤ +125°C

DYNAMIC PERFORMANCE

Slew Rate

Settling Time

Gain Bandwidth Product

Phase Margin

SR

t_S

GBP

Φo

R_L= 100 kΩ

To 0.01% (1 V Step)

0.4

0.8

5

980

64

V/µs

µs

kHz

Degrees

NOISE PERFORMANCE

Voltage Noise Density

e_n

i_n

f = 1 kHz

f = 10 kHz

42

38

<0.1

nV/√Hz

pA/√Hz

Current Noise Density

Specifications subject to change without notice.

REV. B

–3–

AD8541/AD8542/AD8544–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS ^(V_S^{= 5.0 V, V}_CM= 2.5 V, T_A= 25؇C unless otherwise noted)

Parameter

Symbol

Conditions

Min

Typ Max

Unit

INPUT CHARACTERISTICS

Offset Voltage

V_OS

I_B

1

4

6

7

mV

pA

–40°C ≤ T_A≤ +125°C

Input Bias Current

Input Offset Current

60

100

1,000

30

50

500

5

–40°C ≤ T_A≤ +85°C

–40°C ≤ T_A≤ +125°C

I_OS

0.1

–40°C ≤ T_A≤ +85°C

–40°C ≤ T_A≤ +125°C

Input Voltage Range

0

V

Common-Mode Rejection Ratio

CMRR

A_VO

V_CM= 0 V to 5 V

40

38

20

10

2

48

40

dB

–40°C ≤ T_A≤ +125°C

R_L= 100 kΩ , V_O= 0.5 V to 2.2 V

–40°C ≤ T_A≤ +85°C

–40°C ≤ T_A≤ +125°C

–40°C ≤ T_A≤ +85°C

–40°C ≤ T_A≤ +125°C

Large Signal Voltage Gain

V/mV

µV/°C

fA/°C

Offset Voltage Drift

Bias Current Drift

∆V_OS/∆T

∆I_B/∆T

4

100

2,000

25

Offset Current Drift

∆I_OS/∆T

OUTPUT CHARACTERISTICS

Output Voltage High

V_OH

V_OL

I_L= 1 mA

–40°C ≤ T_A≤ +125°C

I_L= 1 mA

–40°C ≤ T_A≤ +125°C

V_OUT= V_S– 1 V

4.9

4.875

4.965

25

V

Output Voltage Low

100

125

mV

mA

Ω

Output Current

I_OUT

I_SC

Z_OUT

30

60

45

Closed Loop Output Impedance

f = 200 kHz, A_V= 1

POWER SUPPLY

Power Supply Rejection Ratio

PSRR

I_SY

V_S= 2.5 V to 6 V

–40°C ≤ T_A≤ +125°C

V_O= 0 V

65

60

76

45

dB

µA

Supply Current/Amplifier

65

85

–40°C ≤ T_A≤ +125°C

DYNAMIC PERFORMANCE

Slew Rate

Full-Power Bandwidth

Settling Time

Gain Bandwidth Product

Phase Margin

SR

BW_P

t_S

GBP

Φo

R_L= 100 kΩ, C_L= 200 pF

1% Distortion

To 0.1% (1 V Step)

0.45

0.92

70

6

1,000

67

V/µs

kHz

µs

kHz

Degrees

NOISE PERFORMANCE

Voltage Noise Density

e_n

i_n

f = 1 kHz

f = 10 kHz

42

38

<0.1

nV/√Hz

pA/√Hz

Current Noise Density

Specifications subject to change without notice.

–4–

REV. B

AD8541/AD8542/AD8544

PACKAGE INFORMATION

ABSOLUTE MAXIMUM RATINGS¹

Supply Voltage (V_S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND to V_S

Package Type

␪_JA*

␪

Unit

JC

Differential Input Voltage². . . . . . . . . . . . . . . . . . . . . . .

6 V

5-Lead SC70 (KS)

5-Lead SOT-23 (RT)

8-Lead SOIC (R)

8-Lead MSOP (RM)

8-Lead TSSOP (RU)

14-Lead SOIC (R)

14-Lead TSSOP (RU)

376

230

158

210

240

120

240

126

146

43

45

43

36

43

°C/W

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Operating Temperature Range . . . . . . . . . . –40°C to +125°C

Junction Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature Range (Soldering, 60 sec) . . . . . . . 300°C

NOTES

¹Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those listed in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

²For supplies less than 6 V, the differential input voltage is equal to V_S.

*θ_JAis specified for worst-case conditions, i.e., q_JAis specified for device soldered

onto a circuit board for surface mount packages.

ORDERING GUIDE

Temperature

Range

Package

Description

Package

Option

Branding

Information

Model

AD8541AKS*

AD8541AR

AD8541ART*

–40°C to +125°C

5-Lead SC70

KS-5

SO-8

RT-5

SO-8

RM-8

RU-8

SO-14

RU-14

A4B

A4A

AVA

8-Lead SOIC

5-Lead SOT-23

8-Lead SOIC

8-Lead MSOP

8-Lead TSSOP

14-Lead SOIC

14-Lead TSSOP

AD8542AR

AD8542ARM*

AD8542ARU*

AD8544AR

AD8544ARU*

*Available in reels only.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although

the AD8541/AD8542/AD8544 features proprietary ESD protection circuitry, permanent damage

may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. B

–5–

AD8541/AD8542/AD8544–Typical Performance Characteristics

180

160

140

120

100

80

1.0

0.5

0.0

9

8

7

6

5

4

3

2

1

0

V

= 5V

V

= 2.7V AND 5V

= V /2

V

= 2.7V AND 5V

= V /2

S

= 2.5V

CM

S

CM

S

T

= 25؇C

A

؊0.5

؊1.0

؊1.5

؊2.0

؊2.5

؊3.0

؊3.5

؊4.0

60

40

20

0

؊4.5 ؊3.5 ؊2.5 ؊1.5

؊0.5 0.5 1.5 2.5 3.5 4.5

INPUT OFFSET VOLTAGE – mV

؊55 ؊35 ؊15

5

25 45 65 85 105 125 145

؊0.5

0.5

1.5

2.5

3.5

4.5

5.5

TEMPERATURE – ؇C

COMMON-MODE VOLTAGE – V

Figure 2. Input Offset Voltage

vs. Temperature

Figure 1. Input Offset Voltage

Distribution

Figure 3. Input Bias Current vs.

Common-Mode Voltage

7

400

350

300

250

200

150

100

50

160

V

= 2.7V AND 5V

= V /2

V

= 2.7V AND 5V

= V /2

S

V

T

= 2.7V

= 25؇C

S

A

CM

S

CM

S

140

120

100

80

6

5

4

؊PSRR

+PSRR

3

60

40

2

20

1

0

؊20

؊40

؊1

0

؊55 ؊35 ؊15

5

25 45 65 85 105 125 145

؊40 ؊20

0

20 40 60 80 100 120 140

100

1k

10k

100k

1M

10M

TEMPERATURE – ؇C

FREQUENCY – Hz

Figure 5. Input Offset Current vs.

Temperature

Figure 6. Power Supply Rejection

Ratio vs. Frequency

Figure 4. Input Bias Current vs.

Temperature

60

3.0

10k

V

R

= 2.7V

= 2.5Vp-p

= 2k⍀

V

T

= 2.7V

= 25؇C

S

V

R

= 2.7V

=

S

IN

A

2.5

2.0

1.5

1.0

0.5

0

50

40

30

20

L

1k

100

10

L

T

= 25؇C

A

T

= 25؇C

A

+OS

SOURCE

SINK

؊OS

1

10

0

0.1

0.01

0.001

10

100

1k

10k

1k

10k

100k

FREQUENCY – Hz

1M

10M

0.01

0.1

1

10

100

CAPACITANCE – pF

LOAD CURRENT – mA

Figure 9. Small Signal Overshoot vs.

Load Capacitance

Figure 8. Closed-Loop Output

Voltage Swing vs. Frequency

Figure 7. Output Voltage to Supply

Rail vs. Load Current

–6–

REV. B

AD8541/AD8542/AD8544

60

50

40

30

20

10

0

60

50

40

30

20

V

= 2.7V

= 100k⍀

= 300pF

= 1

S

V

R

= 2.7V

= 10k⍀

= 25؇C

V

R

= 2.7V

= 2k⍀

= 25؇C

S

R

C

A

T

L

V

L

T

A

= 25؇C

A

+OS

؊OS

1.35V

؊OS

10

0

10␮s

50mV

10

100

1k

10k

10

100

1k

10k

CAPACITANCE – pF

Figure 10. Small Signal Overshoot

vs. Load Capacitance

Figure 11. Small Signal Overshoot

vs. Load Capacitance

Figure 12. Small Signal Transient

Response

160

V

R

= 2.7V

= NO LOAD

= 25؇C

V

T

= 5V

= 25؇C

S

140

120

100

80

L

A

T

A

80

60

40

20

0

45

90

؊PSRR

+PSRR

135

180

60

1.35V

40

V

= 2.7V

= 2k⍀

= 1

S

20

R

A

L

V

A

0

T

= 25؇C

؊20

؊40

10␮s

500mV

1k

10k

100k

FREQUENCY – Hz

1M

10M

100

1k

10k

100k

1M

10M

FREQUENCY – Hz

Figure 13. Large Signal Transient

Response

Figure 14. Open-Loop Gain and

Phase vs. Frequency

Figure 15. Power Supply Rejection

Ratio vs. Frequency

10k

5.0

90

V

R

= 5V

V

T

= 5V

= 25؇C

V

T

= 5V

= 25؇C

S

4.5

80

70

60

50

= 4.9V p-p

= NO LOAD

= 25؇C

IN

A

1k

100

10

L

4.0

3.5

T

A

3.0

2.5

SOURCE

40

30

20

SINK

2.0

1.5

1

1.0

0.5

0

10

0.1

0

0.01

0.001

؊10

1k

10k

100k

FREQUENCY – Hz

1M

10M

1k

10k

100k

FREQUENCY – Hz

1M

10M

0.01

0.1

1

10

100

LOAD CURRENT – mA

Figure 16. Common-Mode Rejection

Ratio vs. Frequency

Figure 17. Output Voltage to Supply

Rail vs. Frequency

Figure 18. Closed Loop Output

Voltage Swing vs. Frequency

REV. B

–7–

AD8541/AD8542/AD8544

60

50

40

30

20

5.0

60

V

= 5V

= 4.9V p-p

= 2k⍀

S

4.5

V

R

= 5V

= 10k⍀

= 25؇C

S

V

= 5V

= 2k⍀

= 25؇C

S

IN

L

50

40

30

20

10

0

R

T

R

T

L

4.0

3.5

T

A

= 25؇C

A

3.0

2.5

+OS

؊OS

2.0

1.5

1.0

0.5

0

10

0

10

100

1k

10k

10

100

1k

10k

1k

10k

100k

FREQUENCY – Hz

1M

10M

CAPACITANCE – pF

Figure 19. Closed-Loop Output

Voltage Swing vs. Frequency

Figure 20. Small Signal Overshoot

vs. Load Capacitance

Figure 21. Small Signal Overshoot

vs. Load Capacitance

60

50

40

30

20

10

0

V

= 5V

S

V

R

= 5V

=

= 25؇C

S

R

C

A

T

= 100k⍀

= 300pF

= 1

L

V

L

T

A

= 25؇C

A

+OS

2.5V

؊OS

V

= 5V

= 2k⍀

= 1

S

R

A

L

V

A

T

= 25؇C

10␮s

50mV

1V

10

100

1k

10k

CAPACITANCE – pF

Figure 22. Small Signal Overshoot

vs. Load Capacitance

Figure 23. Small Signal Transient

Response

Figure 24. Large Signal Transient

Response

60

V

= 5V

S

V

R

= 5V

= NO LOAD

= 25؇C

T

= 25؇C

S

A

R

A

T

= 10k⍀

= 1

= 25؇C

L

V

A

L

V

IN

50

40

30

20

10

0

T

A

80

60

40

20

0

45

V

OUT

90

135

180

2.5V

20␮s

1V

0

1

2

3

4

5

6

1k

10k

100k

FREQUENCY – Hz

1M

10M

SUPPLY VOLTAGE – V

Figure 25. Open-Loop Gain & Phase

vs. Frequency

Figure 26. No Phase Reversal

Figure 27. Supply Current per

Amplifier vs. Supply Voltage

–8–

REV. B

AD8541/AD8542/AD8544

55

50

45

40

35

30

25

20

1,000

900

800

700

600

500

400

300

200

100

0

V

= 2.7V AND 5V

= 1

= 25؇C

V

A

= 5V

= 1

S

A

T

V

MARKER SET @ 10kHz

V

= 5V

A

S

MARKER READING: 37.6␮V/ Hz

T

= 25؇C

A

V

= 2.7V

S

؊55 ؊35؊15

5

25 45 65 85 105 125 145

0

5

10

15

20

25

1k

10k

100k

1M

10M

100M

TEMPERATURE – ؇C

FREQUENCY – Hz

FREQUENCY – kHz

Figure 28. Supply Current per

Amplifier vs. Temperature

Figure 29. Closed-Loop Output

Impedance vs. Frequency

Figure 30. Voltage Noise

NOTES ON THE AD854x AMPLIFIERS

the circuit to no longer attenuate at the ideal notch frequency.

To achieve desired performance, 1% or better component

tolerances or special component screens are usually required.

One method to desensitize the circuit-to-component mis-

match is to increase R2 with respect to R1, which lowers Q. A

lower Q increases attenuation over a wider frequency range,

but reduces attenuation at the peak notch frequency.

The AD8541/AD8542/AD8544 amplifiers are improved perfor-

mance general-purpose operational amplifiers. Performance has

been improved over previous amplifiers in several ways.

Lower Supply Current for 1 MHz Gain Bandwidth

The AD854x series typically uses 45 microamps of current per

amplifier. This is much less than the 200 µA to 700 µA used in

earlier generation parts with similar performance. This makes

the AD854x series a good choice for upgrading portable designs

for longer battery life. Alternatively, additional functions and

performance can be added at the same current drain.

5.0V

R

8

100k⍀

1/2 AD8542

3

2

U1

V_OUT

C2

1

4

53.6␮F

Higher Output Current

R/2

50k⍀

At 5 V single supply, the short circuit current is typically 60 µA.

Even 1 V from the supply rail, the AD854x amplifiers can provide

30 mA, sourcing or sinking.

R2

2.5k⍀

2.5V

REF

C

1/2 AD8542

26.7nF

5

6

Sourcing and sinking is strong at lower voltages, with 15 mA

available at 2.7 V, and 18 mA at 3.0 V. For even higher output

currents, please see the Analog Devices AD8531/AD8532/AD8534

parts, with output currents to 250 mA. Information on these

parts is available from your Analog Devices representative,

and data sheets are available at the Analog Devices website at

www.analog.com.

7

U2

R1

97.5k⍀

1

f

=

0

2πRC

1

2.5V

REF

f

=

0

R1

1 ؊

4

[

]

R1+R2

Figure 31. 60 Hz Twin-T Notch Filter, Q = 10

Better Performance at Lower Voltages

The AD854x family parts have been designed to provide better ac

performance, at 3.0 V and 2.7 V, than previously available parts.

Typical gain-bandwidth product is close to 1 MHz at 2.7 V. Volt-

age gain at 2.7 V and 3.0 V is typically 500,000. Phase margin is

typically over 60°C, making the part easy to use.

5.0V

7

AD8541

R

3

2

V_OUT

6

4

2C

V

IN

APPLICATIONS

Notch Filter

R/2

2.5V

REF

The AD8542 has very high open loop gain (especially with supply

voltage below 4 V), which makes it useful for active filters of all

types. For example, Figure 31 illustrates the AD8542 in the clas-

sic Twin-T Notch Filter design. The Twin-T Notch is desired for

simplicity, low output impedance and minimal use of op amps. In

fact, this notch filter may be designed with only one op amp if Q

adjustment is not required. Simply remove U2 as illustrated in

Figure 32. However, a major drawback to this circuit topology is

ensuring that all the Rs and Cs closely match. The components

must closely match or notch frequency offset and drift will cause

C

=

Figure 32. 60 Hz Twin-T Notch Filter, Q ∞ (Ideal)

Figure 33 diagrams another example of the AD8542 in a

notch filter circuit. The FNDR notch filter has several

unique features as compared to the Twin-T Notch including:

less critical matching requirements; Q is directly proportional

to a single resistor R1. While matching component values is

still important, it is also much easier and/or less expensive to

REV. B

–9–

AD8541/AD8542/AD8544

accomplish in the FNDR circuit. For example, the Twin-T

Notch uses three capacitors with two unique values, whereas the

FNDR circuit uses only two capacitors, which may be of the

same value. U3 is simply a buffer that is added to lower the out-

put impedance of the circuit.

Photodiode Application

The AD854x family has very high impedance with input bias

current typically around 4 pA. This characteristic allows the

AD854x op amps to be used in photodiode applications and

other applications that require high input impedance. Note that

the AD854x has significant voltage offset, which can be removed

by capacitive coupling or software calibration.

1/4 AD8544

R1

Q ADJUST

200⍀

9

8

Figure 35, illustrates a photodiode or current measurement

application. The feedback resistor is limited to 10 MΩ to avoid

excessive output offset. Also note that a resistor is not needed

on the noninverting input to cancel bias current offset, because

the bias current related output offset is not significant when

compared to the voltage offset contribution. For the best per-

formance follow the standard high impedance layout techniques

including: shield circuit, clean circuit board, put a trace con-

nected to the noninverting input around the inverting input,

and use separate analog and digital power supplies.

U3

V_OUT

10

C1

1␮F

R

2.5V

REF

2.61k⍀

1/4 AD8544

1

4

3

C2

1␮F

U1

1/4 AD8544

2

6

11

7

U2

R

5

2.61k⍀

R

C

2.61k⍀

100pF

1/4 AD8544

R

13

1

f =

14

R

10M⍀

2.61k⍀

2π

LC1

U4

NC

12

2.5V

REF

SPARE

2

L =

R C2

V+

7

OR

2.5V

2

3

REF

6

V

OUT

Figure 33. FNDR 60 Hz Notch Filter with Output Buffer

4

D

AD8541

Comparator Function

A comparator function is a common application for a spare op

amp in a quad package. Figure 34 illustrates 1/4 of the AD8544

as a comparator in a standard overload detection application.

Unlike so many op amps, the AD854x family can double as

comparator because this op amp family has rail-to-rail differen-

tial input range, rail-to-rail output, and a great speed vs. power

ratio. R2 is used to introduce hysteresis. The AD854x when

used as comparators have 5 µs propagation delay @ 5 V and 5 µs

overload recovery time.

2.5V

REF

Figure 35. High Input Impedance Application–Photodiode

Amplifier

R2

1M⍀

R1

1k⍀

V_OUT

V

IN

1/4 AD8544

2.5V

DC

2.5V

REF

Figure 34. The AD854x Comparator Application–Overload

Detector

–10–

REV. B

AD8541/AD8542/AD8544

* AD8542 SPICE Macro-model Typical Values

* VOLTAGE NOISE REFERENCE OF 35nV/rt(Hz)

* 6/98, Ver. 1

*

* TAM / ADSC

VN1 80 0 0

*

RN1 80 0 16.45E-3

HN 81 0 VN1 35

*

RN2 81 0 1

* Refer to “README.DOC” file for License State-

ment. Use of this

*

* INTERNAL VOLTAGE REFERENCE

* model indicates your acceptance of the terms

and provisions in

*

VFIX 90 98 DC 1

* the License Statement.

*

S1

90 91 (50,99) VSY_SWITCH

VSN1 91 92 DC 0

* Node Assignments

RSY 92 98 1E3

*

noninverting input

EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5

GSY 99 50 POLY(1) (99,50) 0 3.7E-6

*

* ADAPTIVE GAIN STAGE

* AT Vsy>+4.2, AVol=45 V/mv

* AT Vsy<+3.8, AVol=450 V/mv

*

|

1

inverting input

|

2

positive supply

|

negative supply

|

output

|

.SUBCKT AD8542

*

99 50 45

G1 98 30 POLY(2) (4,6) (11,12) 0 2.5E-5 2.5E-5

VR1 30 31 DC 0

* INPUT STAGE

*

H1 31 98 POLY(2) VR1 VSN1 0 5.45E6 0 0 49.05E9

CF 45 30 10E-12

M1

M2

4

6

1 8 8 PIX L=0.6E-6 W=16E-6

7 8 8 PIX L=0.6E-6 W=16E-6

D3 30 99 DX

D4 50 30 DX

M3 11 1 10 10 NIX L=0.6E-6 W=16E-6

M4 12 7 10 10 NIX L=0.6E-6 W=16E-6

RC1 4 50 20E3

*

* OUTPUT STAGE

*

RC2 6 50 20E3

RC3 99 11 20E3

RC4 99 12 20E3

M5 45 46 99 99 POX L=0.6E-6 W=375E-6

M6 45 47 50 50 NOX L=0.6E-6 W=500E-6

EG1 99 46 POLY(1) (98,30) 1.05 1

EG2 47 50 POLY(1) (30,98) 1.04 1

*

C1

4

6 1.5E-12

C2 11 12 1.5E-12

I1 99 8 1E-5

I2 10 50 1E-5

V1 99 9 0.2

V2 13 50 0.2

* MODELS

*

.MODEL POX PMOS (LEVEL=2,KP=20E-6,VTO=-

+1,LAMBDA=0.067)

D1

8

9 DX

.MODEL NOX NMOS (LEVEL=2,KP=20E-

+6,VTO=1,LAMBDA=0.067)

.MODEL PIX PMOS (LEVEL=2,KP=20E-6,VTO=-

+0.7,LAMBDA=0.01,KF=1E-31)

.MODEL NIX NMOS (LEVEL=2,KP=20E-

+6,VTO=0.7,LAMBDA=0.01,KF=1E-31)

.MODEL DX D(IS=1E-14)

.MODEL VSY_SWITCH VSWITCH(ROFF=100E3,RON=1,VOFF=-

+4.2,VON=-3.5)

D2 13 10 DX

EOS

1

IOS

*

* CMRR 64dB, ZERO AT 20kHz

*

ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5

7

1

2 POLY(3) (22,98) (73,98) (81,0) 1E-3 1 1

2 2.5E-12

RCM1 21 22 79.6E3

CCM1 21 22 100E-12

RCM2 22 98 50

.ENDS AD8542

*

* PSRR=90dB, ZERO AT 200Hz

*

RPS1 70 0 1E6

RPS2 71 0 1E6

CPS1 99 70 1E-5

CPS2 50 71 1E-5

EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1

RPS3 72 73 1.59E6

CPS3 72 73 500E-12

RPS4 73 98 25

*

REV. B

–11–

AD8541/AD8542/AD8544

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

8-Lead TSSOP

(RU-08)

0.122 (3.10)

0.114 (2.90)

14-Lead TSSOP

(RU-14)

0.201 (5.10)

0.193 (4.90)

8

1

5

4

14

8

7

1

PIN 1

0.0256 (0.65)

BSC

0.006 (0.15)

0.002 (0.05)

0.006 (0.15)

0.002 (0.05)

PIN 1

0.0433

(1.10)

MAX

0.0433

(1.10)

MAX

0.028 (0.70)

0.020 (0.50)

0.028 (0.70)

0.020 (0.50)

8؇

0؇

8؇

0؇

0.0118 (0.30)

0.0075 (0.19)

0.0118 (0.30)

0.0075 (0.19)

0.0256

(0.65)

BSC

SEATING

PLANE

0.0079 (0.20)

0.0035 (0.090)

SEATING

PLANE

0.0079 (0.20)

0.0035 (0.090)

14-Lead SOIC

8-Lead SOIC

(SO-8)

(SO-14)

0.3444 (8.75)

0.3367 (8.55)

0.1968 (5.00)

0.1890 (4.80)

14

8

1

5

4

0.1574 (4.00)

0.1497 (3.80)

0.2440 (6.20)

0.2284 (5.80)

0.1574 (4.00)

0.1497 (3.80)

0.2440 (6.20)

0.2284 (5.80)

1

7

0.0688 (1.75)

0.0532 (1.35)

PIN 1

0.0196 (0.50)

0.0099 (0.25)

x 45؇

PIN 1

0.0688 (1.75)

0.0532 (1.35)

0.0098 (0.25)

0.0040 (0.10)

0.0196 (0.50)

0.0099 (0.25)

x 45؇

0.0098 (0.25)

0.0040 (0.10)

8؇

0؇

0.0500

(1.27)

BSC

0.0192 (0.49)

0.0138 (0.35)

SEATING

PLANE

0.0500 (1.27)

0.0160 (0.41)

0.0099 (0.25)

0.0075 (0.19)

8؇

0؇

0.0500

(1.27)

BSC

0.0192 (0.49)

0.0138 (0.35)

SEATING

PLANE

0.0098 (0.25)

0.0075 (0.19)

0.0500 (1.27)

0.0160 (0.41)

8-Lead MSOP

(RM-8)

5-Lead SOT-23

(RT Suffix)

0.122 (3.10)

0.114 (2.90)

0.1220 (3.100)

0.1063 (2.700)

PIN 1

8

5

4

0.193

(4.90)

BSC

3

2

1

5

0.122 (3.10)

0.114 (2.90)

0.1181 (3.000)

0.0984 (2.500)

0.0709 (1.800)

0.0590 (1.500)

4

1

PIN 1

0.0256 (0.65) BSC

0.037 (0.95)

0.030 (0.75)

0.0374 (0.950) BSC

0.043

(1.10)

MAX

0.0748 (1.900)

REF

0.006 (0.15)

0.002 (0.05)

0.0079 (0.200)

0.0035 (0.090)

6؇

0؇

0.016 (0.40)

0.010 (0.25)

SEATING

PLANE

0.0512 (1.300)

0.0354 (0.900)

0.0571 (1.450)

0.0354 (0.900)

0.028 (0.70)

0.016 (0.40)

0.009 (0.23)

0.005 (0.13)

10؇

0؇

SEATING

PLANE

0.0197 (0.500)

0.0118 (0.300)

0.0590 (0.150)

0.0000 (0.000)

NOTE:

PACKAGE OUTLINE INCLUSIVE AS SOLDER PLATING.

0.0236 (0.600)

0.0039 (0.100)

5-Lead SC70

(KS-5)

0.026 (0.65) BSC

PIN 1

3

2

1

5

0.053 (1.35)

0.045 (1.15)

0.094 (2.40)

0.071 (1.80)

4

0.016 (0.40)

0.004 (0.10)

0.087 (2.20)

0.071 (1.80)

0.039 (1.00)

0.031 (0.80)

0.043 (1.10)

0.031 (0.80)

0.012 (0.30)

0.006 (0.15)

0.012 (0.30)

0.004 (0.10)

0.007 (0.18)

0.004 (0.10)

0.000 (0.00)

SEATING

PLANE

–12–

REV. B


型号：	AD8541AKS
厂家：	ETC
描述：	General-Purpose CMOS Rail-to-Rail Amplifiers(177.60 k) 通用CMOS轨到轨放大器（ 177.60 K）\n 放大器光电二极管
文件：	总12页 (文件大小：178K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD8541AKS [ETC]

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