AD484M1644VTA-8L_技术文档

Ascend Semiconductor Corporation

64Mb SDRAM

ASCEND

Semiconductor

64M SDRAM

Data sheet

Tel: (03)5635888 / Fax: (03)5635188/ http://www.ascendsemi.com.tw

Preliminary

1

Ascend Semiconductor Corporation

64Mb SDRAM

Ordering Information

AD 48 4M 16 4 4 V T A – 7 L I

Ascend

Semiconductor

Operating Range

I : Industrial

-40℃ ~ 85℃

Non : Commercial

0℃ ~ 70℃

EDO

FPM

DDRSDRAM

DDRSGRAM

SGRAM

SDRAM

: 40

: 41

: 42

: 43

: 46

: 48

S

: Special

0℃ ~ 85℃

Density

16M : 16 Mega Bits

8M : 8 Mega Bits

4M : 4 Mega Bits

2M : 2 Mega Bits

1M : 1 Mega Bit

Power

Non : Standard

L : Low power

Min Cycle Time ( Max Freq.)

-55 : 5.5ns ( 183MHz )

Organization

8 : x8

9 : x9

16 : x16

18 : x18

32 : x32

-6 : 6ns

-7 : 7ns

-8 : 8ns

( 167MHz )

( 143MHz )

( 125MHz )

-10 : 10ns ( 100MHz )

-15 : 15ns (66MHz,CL1 applicable)

Refresh

1 : 1K, 8 : 8K

2 : 2K, 6 :16K

4 : 4K

Bank

Revision

2 : 2Bank 6 : 16Bank

A : 1st B : 2nd

C : 3rd D :4th

4 : 4Bank 3 : 32Bank

8 : 8Bank

Interface

V: 3.3V

R: 2.5V

Package

C: CSP B: uBGA

T: TSOP Q: TQFP

P: PQFP ( QFP )

Preliminary

2

Ascend Semiconductor Corporation

64Mb SDRAM

64Mb( 4Banks ) Synchronous DRAM

AD484M1644VTA ( 4Mx16 )

Description

The AD484M1644VTA is Synchronous Dynamic Random Access Memory ( SDRAM )

organized as 1,048,756 words x 4 banks x 16 bits. All inputs and outputs are synchronized

with the positive edge of the clock . The 64Mb SDRAM uses synchronized pipelined

architecture to achieve high speed data transfer rates and is designed to operate in 3.3V

low power memory system. It also provides auto refresh with power saving / down mode.

All inputs and outputs voltage levels are compatible with LVTTL .

Features

• Fully synchronous to positive clock edge

• Single 3.3V +/- 0.3V power supply

• LVTTL compatible with multiplexed address

• Industrial temperature available

• Programmable Burst Length ( BL ) - 1,2,4,8 or full page

• Programmable CAS Latency ( CL ) -1, 2 or 3

• Data Mask ( DQM ) for Read/Write masking

• Programmable wrap sequential - Sequential ( BL = 1/2/4/8/full page )

- Interleave ( BL = 1/2/4/8 )

• Burst read with single-bit write operation

• All inputs are sampled at the positive rising edge of the system clock.

• Auto refresh and self refresh

• 4,096 refresh cycles / 64ms

Ordering Information

Part number

Max

Package

Operation Range

Power

Note

Freg.

AD484M1644VTA-55

183MHz

167MHz

143MHz

66MHz

54pins,

TSOPII

Commercial Range : 0℃ ~ 70℃

Standard

AD484M1644VTA-6

AD484M1644VTA-7

AD484M1644VTA-15

AD484M1644VTA-7L

AD484M1644VTA-8L

AD484M1644VTA-10L

54pins,

TSOPII

Commercial Range : 0℃ ~ 70℃

Standard

54pins,

TSOPII

Standard

54pins,

TSOPII

Standard

CL1

143MHz

125MHz

100MHz

54pins,

TSOPII

Low power

54pins,

TSOPII

54pins,

TSOPII

* Ascend Semiconductor reserves the right to change products or specification without notice.

Preliminary

3

Ascend Semiconductor Corporation

64Mb SDRAM

Ordering Information

Part number

Max

Package

Operation Range

Power

Note

Freg.

AD484M1644VTA-7I

143MHz

125MHz

100MHz

143MHz

125MHz

100MHz

54pins,

TSOPII

Industrial Range : -40℃ ~ 85℃

Standard

AD484M1644VTA-8I

AD484M1644VTA-10I

AD484M1644VTA-7LI

AD484M1644VTA-8LI

AD484M1644VTA-10LI

54pins,

TSOPII

Industrial Range : -40℃ ~ 85℃

Standard

54pins,

TSOPII

Standard

54pins,

TSOPII

Low power

54pins,

TSOPII

54pins,

TSOPII

* Ascend Semiconductor reserves the right to change products or specification without notice.

Pin Assignment ( Top View )

VDD

1

2

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

VSS

DQ0

DQ15

VSSQ

DQ14

DQ13

VDDQ

DQ12

DQ11

VSSQ

DQ10

DQ9

VDDQ

DQ8

VSS

2

VDDQ

3

DQ1

4

DQ2

5

6

VSSQ

6

DQ3

7

DQ4

8

VDDQ

9

DQ5

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

10

DQ6

11

VSSQ

12

DQ7

13

VDD

14

LDQM

15

NC

/WE

UDQM

CLK

CKE

NC

16

/CAS

17

/RAS

18

/CS

19

BA0

A11

20

BA1

21

A9

A8

A10/AP

22

A0

23

A7

A1

A6

24

A2

25

A5

A3

A4

26

VDD

VSS

27

54pin TSOP-II

(400milx875mil)

(0.8mm Pin pitch)

Preliminary

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Ascend Semiconductor Corporation

64Mb SDRAM

Pin Descriptions ( Simplified )

CLK

/CS

Name

System Clock

Chip select

Pin Function

Master Clock Input(Active on the Positive rising edge)

Selects chip when active

Activates the CLK when“H” and deactivates when“L”.

CKE should be enabled at least one cycle prior to new

command. Disable input buffers for power down in standby.

CKE

Clock Enable

Row address (A0 to A11) is determined by A0 to A11 level

at the bank active command cycle CLK rising edge.

CA(CA0 to CA7) is determined by A0 to A7 level at the

read or write command cycle CLK rising edge.

A0 ~ A11

Address

And this column address becomes burst access start

address. A10 defines the pre-charge mode. When A10 = High

at the pre-charge command cycle, all banks are pre-charged.

But when A10 = Low at the pre-charge command cycle,

only the bank that is selected by BA0/BA1 is pre-charged.

BA0, BA1

/RAS

Bank Address

Row address strobe

Column address strobe

Write Enable

Selects which bank is to be active.

Latches Row Addresses on the positive rising edge of the

CLK with /RAS “L” . Enables row access & pre-charge.

Latches Column Addresses on the positive rising edge of the

CLK with /CAS low. Enables column access.

/CAS

Latches Column Addresses on the positive rising edge of the

CLK with /CAS low. Enables column access.

/WE

LDQM/ UDQM

DQ0 ~ 15

Data input/output Mask

Data input/output

DQM controls I/O buffers.

DQ pins have the same function as I/O pins on a conventional

DRAM.

VDD/VSS

Power supply/Ground

VDD and VSS are power supply pins for internal circuits.

VDDQ and VSSQ are power supply pins for the output buffers.

VDDQ/VSSQ

This pin is recommended to be left No Connection on the

device.

NC

No connection

Preliminary

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Ascend Semiconductor Corporation

64Mb SDRAM

Block Diagram

Auto/Self

Refresh Counter

A0

A1

A2

A3

A4

DQM

Memory

Array

A5

Write DQM

Control

A6

A7

Data In

A8

S/A & I/O gating

Col. Decoder

DQi

A9

A10

Data Out

A11

Col. Add. Buffer

Read DQM

Control

BA0

BA1

Mode Register Set

Col. Add. Counter

Burst Counter

Timing Register

CLK

CKE

/CS

/RAS

/CAS

/WE

DQM

/CLK

Preliminary

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Ascend Semiconductor Corporation

64Mb SDRAM

Simplified State Diagram

Self

Refresh

Mode

Register

Set

MRS

CBR

Refresh

REF

IDLE

Power

Down

CKE¯

Active

Power

Down

Row

Active

CKE

Write

Read

CKE¯

Read

CKE¯

WRITE

Suspend

READ

Suspend

WRITE

READ

Write

CKE

CKE¯

WRITEA

Suspend

READA

Suspend

WRITEA

READA

CKE

POWER

ON

Precharge

Manual Input

Automatic Sequence

Preliminary

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Ascend Semiconductor Corporation

64Mb SDRAM

Address Input for Mode Register Set

BA1 BA0 A11 A10 A9

Operation Mode

A8

A7

A6

A5

A4

A3

BT

A2

A1

A0

CAS Latency

Burst Length

Sequential Interleave A2

A1

0

1

0

1

A0

0

1

0

1

0

1

0

1

2

4

8

1

2

4

8

0

1

Reserved Reserved

Full Page Reserved

Burst Type

Sequential

Interleave

A3

0

1

CAS Latency

Reserved

1

A6

0

1

A5

A4

0

1

0

1

0

1

0

1

0

1

0

1

2

3

Reserved

BA1 BA0 A11

A10

0

A9

0

1

A8

0

A7

0

Operation Mode

Normal

Burst read with Single-bit Write

0

Preliminary

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Ascend Semiconductor Corporation

64Mb SDRAM

Burst Type ( A3 )

Burst Length

2

A2 A1 A0

X X 0

X X 1

X 0 0

X 0 1

X 1 0

X 1 1

0 0 0

Sequential Addressing

0 1

Interleave Addressing

0 1

1 0

0 1 2 3

1 2 3 0

2 3 0 1

1 0

0 1 2 3

1 0 3 2

2 3 0 1

4

3 0 1 2

3 2 1 0

0 1 2 3 4 5 6 7

1 2 3 4 5 6 7 0

2 3 4 5 6 7 0 1

3 4 5 6 7 0 1 2

4 5 6 7 0 1 2 3

5 6 7 0 1 2 3 4

6 7 0 1 2 3 4 5

7 0 1 2 3 4 5 6

Cn Cn+1 Cn+2 …...

0 1 2 3 4 5 6 7

1 0 3 2 5 4 7 6

2 3 0 1 6 7 4 5

3 2 1 0 7 6 5 4

4 5 6 7 0 1 2 3

5 4 7 6 1 0 3 2

6 7 4 5 2 3 0 1

7 6 5 4 3 2 1 0

-

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

n n n

8

Full Page *

* Page length is a function of I/O organization and column addressing

x32 (CA0 ~ CA7) : Full page = 256 bits

Preliminary

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Ascend Semiconductor Corporation

64Mb SDRAM

Truth Table

1. Command Truth Table ( AD484M1644VTA )

CKE

BA0,

BA1

X

A11,

A9~A0

Command

Symbol

/CS /RAS /CAS /WE

A10

n-1

H

n

X

Ignore Command

No operation

Burst stop

DESL

NOP

H

L

X

H

L

X

H

L

X

H

L

X

L

X

V

X

V

H

X

BSTH

READ

READA

WRIT

WRITA

ACT

H

X

Read

H

L

V

Read with auto pre-charge

Write

Write with auto pre-charge

Bank activate

Pre-charge select bank

Pre-charge all banks

Mode register set

H

L

V

H

L

H

L

V

H

L

H

L

V

H

V

L

H

L

V

PRE

H

L

V

PALL

MRS

H

L

X

H

L

H

L

Note : H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input

2. DQM Truth Table

CKE

Command

Symbol

/CS

n-1

n

Data write / output enable

Data mask / output disable

Upper byte write enable / output enable

Read

ENB

H

X

H

L

MASK

BSTH

READ

READA

WRIT

WRITA

ACT

Read with auto pre-charge

Write

Write with auto pre-charge

Bank activate

Pre-charge select bank

Pre-charge all banks

Mode register set

PRE

PALL

MRS

Note : H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input

3. CKE Truth Table

CKE

Command

Symbol

/CS /RAS /CAS /WE Addr.

n-1

H

L

n

L

Activating

Any

Clock suspend mode entry

Clock suspend mode

X

L

X

L

X

L

X

H

X

L

Clock suspend Clock suspend mode exit

Idle

L

H

L

CBR refresh command

Self refresh entry

REF

H

L

SELF

L

H

L

H

X

H

X

Self refresh exit

Self refresh

L

H

X

Idle

Power down

Power down entry

Power down exit

H

L

H

Remark H = High level, L = Low level, X = High or Low level (Don't care)

Preliminary

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Ascend Semiconductor Corporation

64Mb SDRAM

4. Operative Command Table

Current

state

/CS /R /C /W

Addr.

Command

Action

Notes

H

L

H

L

H

L

H

L

X

H

L

X

H

L

X

H

L

X

DESL

NOP or BST

READ/READA

WRIT/WRITA

ACT

Nop or power down

2

3

Nop or power down

ILLEGAL

BA/CA/A10

BA/RA

BA, A10

X

L

ILLEGAL

Idle

H

L

H

L

Row activating

Nop

L

PRE/PALL

REF/SELF

MRS

L

H

L

Refresh or self refresh

Mode register accessing

Nop

4

L

Op-Code

X

H

L

X

H

L

X

H

L

DESL

X

NOP or BST

READ/READA

WRIT/WRITA

ACT

Nop

BA/CA/A10

BA/RA

BA, A10

X

Begin read : Determine AP

Begin write : Determine AP

ILLEGAL

5

3

6

4

L

Row active

H

L

H

L

PRE/PALL

REF/SELF

MRS

Precharge

L

H

L

ILLEGAL

L

Op-Code

X

ILLEGAL

X

H

L

X

H

L

X

H

L

DESL

Continue burst to end ® Row active

Burst stop ® Row active

Terminate burst, new read : Determine AP

Terminate burst, start write : Determine AP

ILLEGAL

X

NOP

X

BST

H

L

BA/CA/A10

BA/RA

BA/A10

X

READ/READA

WRIT/WRITA

ACT

7

7, 8

3

Read

L

H

L

H

L

PRE/PALL

REF/SELF

MRS

Terminate burst, pre-charging

ILLEGAL

4

L

H

L

Op-Code

X

ILLEGAL

X

H

L

X

H

L

X

H

L

DESL

Continue burst to end ® Write recovering

Burst stop ® Row active

Terminate burst, start read : Determine AP 7, 8

Terminate burst, new write : Determine AP 7

ILLEGAL

X

NOP

X

BST

H

L

BA/CA/A10

BA/RA

BA/A10

X

READ/READA

WRIT/WRITA

ACT

7,8

7

Write

L

H

L

H

L

3

L

PRE/PALL

REF/SELF

MRS

Terminate burst, pre-charging

ILLEGAL

9

L

H

L

Op-Code

ILLEGAL

Remark H = High level, L = Low level, X = High or Low level (Don't care)

Preliminary

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Ascend Semiconductor Corporation

64Mb SDRAM

Current

state

/CS /R /C /W

Addr.

Command

Action

Notes

H

L

X

H

L

X

H

L

X

H

L

X

DESL

NOP

Continue burst to end ® Precharging

X

BST

ILLEGAL

H

L

BA/CA/A10

BA/RA

BA, A10

X

READ/READA

WRIT/WRITA

ACT

3

Read with AP

L

H

L

H

L

PRE/PALL

REF/SELF

MRS

L

H

L

Op-Code

burst to end ® Write

recovering with auto precharge

H

L

X

H

X

H

X

H

X

DESL

NOP

Continue burst to end ® Write

recovering with auto precharge

L

H

L

H

L

H

L

H

L

H

L

X

BA/CA/A10

BA/RA

BA, A10

X

BST

READ/READA

WRIT/WRITA

ACT

ILLEGAL

Write with AP

3

L

H

L

H

L

PRE/PALL

REF/SELF

MRS

L

H

L

Op-Code

X

H

L

X

H

L

X

H

L

DESL

Nop ® Enter idle after tRP

ILLEGAL

X

NOP

X

BST

H

L

BA/CA/A10

BA/RA

BA, A10

X

READ/READA

WRIT/WRITA

ACT

ILLEGAL

3

Precharging

L

ILLEGAL

H

L

H

L

ILLEGAL

L

PRE/PALL

REF/SELF

MRS

Nop ® Enter idle after tRP

ILLEGAL

L

H

L

Op-Code

X

ILLEGAL

X

H

L

X

H

L

X

H

L

DESL

Nop ® Enter idle after tRCD

ILLEGAL

X

NOP

X

BST

H

L

BA/CA/A10

BA/RA

BA, A10

X

READ/READA

WRIT/WRITA

ACT

ILLEGAL

3

Row activating

L

ILLEGAL

H

L

H

L

ILLEGAL

3,10

3

L

PRE/PALL

REF/SELF

MRS

ILLEGAL

L

H

L

ILLEGAL

L

Op-Code

ILLEGAL

Remark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Precharge

Preliminary

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Ascend Semiconductor Corporation

64Mb SDRAM

Current

state

/CS /R /C /W

Addr.

Command

Action

Notes

H

L

H

L

H

L

H

L

X

H

L

X

H

L

X

H

L

X

DESL

NOP

Nop ® Enter row active after tDPL

Start read, Determine AP

New write, Determine AP

ILLEGAL

X

BST

H

L

BA/CA/A10

READ/READA

WRIT/WRITA

ACT

Write recovering

L

BA/CA/A10

8

3

H

L

H

L

BA/RA

L

BA, A10

PRE/PALL

REF/SELF

MRS

ILLEGAL

L

H

L

X

ILLEGAL

L

Op-Code

ILLEGAL

X

H

L

X

H

L

X

H

L

X

DESL

Nop ® Enter precharge after tDPL

X

NOP

Nop ® Enter precharge after tDPL

X

BST

Nop ® Enter precharge after tDPL

H

L

BA/CA/A10

READ/READA

WRIT/WRITA

ACT

ILLEGAL

3,8

3

Write recovering

with AP

L

BA/CA/A10

H

L

H

L

BA/RA

3

L

BA, A10

PRE/PALL

REF/SELF

MRS

L

H

L

X

L

Op-Code

X

H

L

X

H

L

X

H

L

X

DESL

Nop ® Enter idle after tRC

NOP/ BST

READ/WRIT

ACT/PRE/PALL

REF/SELF/MRS

DESL

Nop ® Enter idle after tRC

ILLEGAL

Nop

Refreshing

H

L

X

H

X

H

L

NOP

Nop

BST

ILLEGAL

Mode Register

Accessing

X

READ/WRIT

ACT/PRE/PALL/

REF/SELF/MRS

L

X

ILLEGAL

Remark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Precharge

Notes 1. All entries assume that CKE was active (High level) during the preceding clock cycle.

2. If all banks are idle, and CKE is inactive (Low level), SDRAM will enter Power down mode.

All input buffers except CKE will be disabled.

3. Illegal to bank in specified states;

® Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank.

4. If all banks are idle, and CKE is inactive (Low level), SDRAM will enter Self refresh mode.

All input buffers except CKE will be disabled.

5. Illegal if tRCD is not satisfied.

6. Illegal if tRAS is not satisfied.

7. Must satisfy burst interrupt condition.

8. Must satisfy bus contention, bus turn around, and/or write recov ery requirements.

9. Must mask preceding data which don't satisfy tDPL.

10. Illegal if tRRD is not satisfied.

Preliminary

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Ascend Semiconductor Corporation

64Mb SDRAM

5. Command Truth Table for CKE

CKE

Current

state

/CS /R /C /W

Addr.

Action

Notes

n-1

n

X

H

L

H

L

X

H

L

X

H

L

X

H

L

X

H

L

X

INVALID, CLK (n – 1) would exit self refresh

Self refresh recovery

ILLEGAL

L

Self refresh

L

X

H

L

ILLEGAL

L

X

H

L

X

H

L

Maintain self refresh

Idle after tRC

H

L

H

L

Idle after tRC

L

ILLEGAL

L

X

H

L

ILLEGAL

Self refresh

recovery

H

L

X

H

L

ILLEGAL

L

ILLEGAL

L

ILLEGAL

L

X

H

L

ILLEGAL

X

H

L

X

H

L

X

H

L

INVALID, CLK(n-1) would exit power down

Power down

Exit power down ® Idle

L

Maintain power down mode

H

L

H

L

Refer to operations in Operative Command Table

Refresh

L

X

L

Op-Code

Refer to operations in Operative Command Table

Self refresh

Both banks

idle

H

L

X

H

L

X

H

L

X

H

L

X

1

2

L

Op-Code

Refer t o operations in Operative Command Table

Power down

X

H

L

X

H

L

Refer to operations in Operative Command Table

Power down

Row active

H

L

Refer to operations in Operative Command Table

Begin clock suspend next cycle

Any state

other than

listed above

X

H

L

Exit clock suspend next cycle

L

Maintain clock suspend

Remark : H = High level, L = Low level, X = High or Low level (Don't care)

Notes 1. Self refresh can be entered only from the both banks idle state.

Power down can be entered only from both banks idle or row active state.

2. Must be legal command as defined in Operative Command Table.

Preliminary

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Ascend Semiconductor Corporation

64Mb SDRAM

Operating Range

Range

Commercial

Industrial

Special

Ambient Temperature

0°C to +70°C

Vcc

3 V ~ 3.6V

-40°C to +85°C

0°C to +85°C

Absolute Maximum Ratings

Symbol

VIN, VOUT

VDD, VDDQ

TSTG

Item

Rating

Units

Input, Output Voltage

Power Supply Voltage

Storage Temperature

Power Dissipation

Short Circuit Current

-0.3 ~ 4.6

-55 ~ 150

1

V

C

PD

W

mA

IOS

50

Note : Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause

permanent damage. The device is not meant to be operated under conditions outside the limits

described in the operational section of this specification. Exposure to Absolute Maximum

Rating conditions for extended periods may affect device reliability.

Recommended DC Operation Conditions ( All Operating Range )

Symbol

VDD

Parameter

Power Supply Voltage

Min.

3.0

Typical

3.3

Max.

3.6

Units

V

VDDQ

VIH

Power Supply Voltage (for I/O Buffer)

Input logic high voltage

3.0

3.3

3.6

2.0

VDD+0.3

0.8

VIL

Input logic low voltage

-0.3

Note : 1. All voltage referred to VSS.

2. VIH (max) = 5.6V for pulse width £ 3ns

3. VIL (min) = -2.0V for pulse width £ 3ns

Capacitance ( Vcc =3.3V, f = 1MHz, Ta = 25 C )

Symbol

Parameter

Min.

Max.

Units

CCLK

Clock capacitance

2.5

4.0

pF

Input capacitance for CLK, CKE, Address, /CS,

/RAS, /CAS, /WE, DQML,DQMU

CI

2.5

4.0

5.0

6.5

pF

CO

Input/Output capacitance

Preliminary

15

Ascend Semiconductor Corporation

64Mb SDRAM

Recommended DC Operating Conditions

( VDD = 3.3V +/- 0.3 V, All Operating Range)

MAX

Parameter

Symbol

Test condition

Units Notes

-5.5 -6

-7

-8 -10 -15

-- -- 75

CL=1

--

Burst length = 1,

Operating current

ICC1

mA

1

tRC ³ tRC (min), IOL = 0 mA,

One bank active

CL=2

CL=3

-- 100 95 --

135 120 110 100 95 --

Standard

Low power

1000

500

uA

CKE £ VIL (max.), tCk = 15 ns

Precharge standby

current in power down

mode

ICC2P

Standard

Low power

1000

500

ICC2PS

CKE £ VIL (max.), tCk = ¥

uA

CKE ³ VIH (min.), tCK = 15 ns,

/CS ³ VIH (min.)Input signals are changed

one time during 30ns

mA

ICC2N

35

Precharge standby

current in non-power

down mode

CKE ³ VIH(min.), tCK = ¥

Input signals are stable

ICC2NS

mA

25

ICC3P

CKE £ VIL(max), tCK = 15ns

CKE £ VIL(max), tCK = ¥

mA

8

Active standby current

in power down mode

ICC3PS

CKE ³ VIH(min), tCK = 15ns,

/ CS ³ VIH(min) Input signals are

changed one time during 30ns

Active standby current ICC3N

in non-power down

mode

(4 bank activated)

ICC3NS

50

40

mA

CKE ³ VIH(min), tCK = ¥

Input signals are stable

CL=1

--

-- 80

Operating current

ICC4

tCCD = 2CLKs , IOL = 0 mA

mA

2

3

CL=2

CL=3

-- 110 100 --

(Burst mode)

150 140 130 120 110 --

160 150 145 140 130 85

Refresh current

ICC5

ICC6

tRC ³ tRC(min.)

CKE £ 0.2V

Standard

Low power

1

4

5

mA

Self Refresh current

uA

500

Note : 1. ICC1 depends on output loading and cycle rates.

Specified values are obtained with the output open.

Input signals are changed only one time during tCK(min)

2. ICC4 depends on output loading and cycle rates.

Specified values are obtained with the output open.

Input signals are changed only one time during tCK(min)

3. Input signals are changed only one time during tCK(min)

4. Standard power version.

5. Low power version.

Preliminary

16

Ascend Semiconductor Corporation

64Mb SDRAM

Recommended DC Operating Conditions ( Continued )

Parameter

Symbol

Test condition

Min. Max. Unit

0 £ VI £ VDDQ, VDDQ=VDD

All other pins not under test=0 V

Input leakage current

IIL

-0.5

+0.5

uA

Output leakage current

High level output voltage

Low level output voltage

IOL

VOH

VOL

0 £ VO £ VDDQ, DOUT is disabled

Io = -4mA

-0.5

2.4

uA

V

0.4

Io = +4mA

V

AC Operating Test Conditions

( VDD = 3.3V +/- 0.3 V, All Operating Range )

Output Reference Level

Output Load

1.4V / 1.4V

See diagram as below

2.4V / 0.4V

2ns

Input Signal Level

Transition Time of Input Signals

Input Reference Level

1.4V

Vtt = 1.4V

50W

Output

Z = 50W

50pF

Preliminary

17

Ascend Semiconductor Corporation

64Mb SDRAM

Operating AC Characteristics

( VDD = 3.3V +/- 0.3 V, All Operating Range )

-55

-6

-7

-8

-10

Symbol

Units Notes

Parameter

Min. Max. Min. Max. Min. Max.

Min. Max. Min. Max.

CL = 3

CL = 2

CL = 3

CL = 2

5.5

_

6

7

8

10

ns

Clock cycle time

tCK

tAC

_

10

4.5

_

5.5

_

6

5.5

6

Access time from CLK

CLK high level width

CLK low level width

tCH

tCL

2.0

2.5

3

2.0

_

2.5

_

2.5

1.5

2.5

1.5

2.5

1.5

ns

2

3

CL = 3

CL = 2

CL = 3

CL = 2

tOH

Data-out hold time

4.5

5

_

5.5

6

tHZ

tLZ

4

Data-out to high impedance time

Data-out to low impedance time

_

6

1

Input hold time

Input setup time

6

5

tIH

tIS

1.5

60

1.5

60

2

tRC

63

45

18

14

64

70

ACTIVE to ACTIVE command period

tRAS 42 100k 42 100k

100k 46 100k 50 100k

ACTIVE to PRECHARGE command period

PRECHARGE to ACTIVE command period

tRP

18

12

18

16

20

18

tRCD 18

tRRD 10

ACTIVE to READ/WRITE delay time

ACTIVE(one) to ACTIVE(another) command

READ/WRITE command to READ/WRITE

command

tCCD

CLK

1

tDPL

tBDL

2

1

3

2

1

3

2

1

3

2

1

3

2

1

3

2

Data-in to PRECHARGE command

Data-in to BURST stop command

CLK

ms

CL = 3

Data-out to high impedance from

PRECHARGE command

CL = 2

tROH

tREF

64

Refresh time(4,096 cycle)

Preliminary

18

Ascend Semiconductor Corporation

64Mb SDRAM

Operating AC Characteristics-- Continues

( VDD = 3.3V +/- 0.3 V, All Operating Range )

-15

Symbol

Units Notes

Parameter

Min. Max.

CL = 1

Clock cycle time

15

ns

tCK

tAC

12

Access time from CLK

CLK high level width

CLK low level width

tCH

tCL

3

ns

CL = 1

tOH

2

Data-out hold time

3

4

ns

tHZ

tLZ

Data-out to high impedance time

Data-out to low impedance time

6

1

ns

Input hold time

Input setup time

6

5

tIH

tIS

2

tRC

90

ACTIVE to ACTIVE command period

tRAS 60 100k

ACTIVE to PRECHARGE command period

PRECHARGE to ACTIVE command period

tRP

22

25

ACTIVE to READ/WRITE delay time

tRCD

tRRD 15

ACTIVE(one) to ACTIVE(another) command

READ/WRITE command to READ/WRITE

command

tCCD

CLK

1

tDPL

tBDL

1

Data-in to PRECHARGE command

Data-in to BURST stop command

CLK

Data-out to high impedance from

CL = 1

tROH

tREF

CLK

ms

1

PRECHARGE command

64

Refresh time(4,096 cycle)

Note :

1. All voltages referenced to Vss.

2. For commercial range parts.

3. For industrial range parts.

4. tHZ defines the time at which the output achieve the open circuit

condition and is not referenced to output voltage levels.

5. These parameters account for the number of clock cycle and

depend on the operating frequency of the clock, as follows :

The number of clock cycles = Specified value of timing/clock period (Count fractions as a whole number)

6.These parameters are for address/command/data/CLK/CKE.

7. Any “ –“ sign on the data means “ No guarantee” .

Preliminary

19

Ascend Semiconductor Corporation

64Mb SDRAM

Package Dimension

Dimension in Milimeter/Inchs

1.20

0.047

MAX

1.00+/- 0.10

0.039+/- 0.004

11.76 +/- 0.20

0.463 +/- 0.008

0.21+/- 0.05

0.008+/- 0.002

0.05

MIN

0.002

#1

#54

#27

#28

0.10

0.004

MAX

10.16

0.400

0.50

0.020

0.45 ~ 0.75

0.018 ~ 0.030

* Ascend reserves the right to change products or specification without notice.

Preliminary

20


型号：	AD484M1644VTA-8L
厂家：	ETC
描述：	Ascend Semiconductor Corporation(64Mb SDRAM) 航升半导体公司（ 64MB SDRAM ）半导体动态存储器
文件：	总20页 (文件大小：86K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD484M1644VTA-8L [ETC]

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