A54SX08-TQ208PP [ETC]
54SX Family FPGAs; 54SX系列FPGA型号: | A54SX08-TQ208PP |
厂家: | ETC |
描述: | 54SX Family FPGAs |
文件: | 总57页 (文件大小:407K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
v 3 . 1
54SX Family FPGAs
L e a d i n g E d g e P e r f o r m a n c e
• 320 MHz Internal Performance
• 3.7 ns Clock-to-Out (Pin-to-Pin)
• 0.1 ns Input Set-Up
F e a t u r e s
• 66 MHz PCI
• CPLD and FPGA Integration
• Single Chip Solution
• 0.25 ns Clock Skew
• 100% Resource Utilization with 100% Pin Locking
• 3.3V Operation with 5.0V Input Tolerance
• Very Low Power Consumption
• Deterministic, User-Controllable Timing
S p e c i f i c a t i o n s
• 12,000 to 48,000 System Gates
• Up to 249 User-Programmable I/O Pins
• Up to 1080 Flip-Flops
• Unique In-System Diagnostic and Debug capability with
Silicon Explorer II
• 0.35µ CMOS
• Boundary Scan Testing in Compliance with IEEE Standard
1149.1 (JTAG)
• Secure Programming Technology Prevents Reverse
Engineering and Design Theft
S X P r o d u c t P r o f i l e
A54SX08
A54SX16
A54SX16P
A54SX32
Capacity
Typical Gates
System Gates
8,000
12,000
16,000
24,000
16,000
24,000
32,000
48,000
Logic Modules
Combinatorial Cells
768
512
1,452
924
1,452
924
2,880
1800
Register Cells (Dedicated Flip-Flops)
Maximum User I/Os
Clocks
256
130
528
175
528
175
1,080
249
3
3
3
3
JTAG
Yes
Yes
Yes
Yes
PCI
—
—
Yes
—
Clock-to-Out
3.7 ns
0.8 ns
Std, –1, –2, –3
C, I, M
3.9 ns
0.5 ns
Std, –1, –2, –3
C, I, M
4.4 ns
0.5 ns
Std, –1, –2, –3
C, I, M
4.6 ns
0.1 ns
Std, –1, –2, –3
C, I, M
Input Set-Up (External)
Speed Grades
Temperature Grades
Packages (by pin count)
PLCC
PQFP
VQFP
TQFP
PBGA
FBGA
84
208
100
—
208
100
176
—
—
208
100
—
208
—
144, 176
—
144, 176
—
144, 176
313, 329
—
144
—
—
J u n e 2 0 0 3
1
© 2003 Actel Corporation
5 4 S X F a m i l y F P G A s
G e n e r a l D e s c r i p t i o n
Actel’s SX family of FPGAs features a sea-of-modules
architecture that delivers device performance and
machines, and datapath logic. The general system of
segmented routing tracks allows any logic module in the
integration levels not currently achieved by any other FPGA array to be connected to any other logic or I/O module.
architecture. SX devices greatly simplify design time, enable
dramatic reductions in design costs and power
consumption, and further decrease time to market for
performance-intensive applications.
Within this system, propagation delay is minimized by
limiting the number of antifuse interconnect elements to
five (90 percent of connections typically use only three
antifuses). The unique local and general routing structure
featured in SX devices gives fast and predictable
performance, allows 100 percent pin-locking with full logic
utilization, enables concurrent PCB development, reduces
design time, and allows designers to achieve performance
goals with minimum effort.
Actel’s SX architecture features two types of logic modules,
the combinatorial cell (C-cell) and the register cell (R-cell),
each optimized for fast and efficient mapping of synthesized
logic functions. The routing and interconnect resources are
in the metal layers above the logic modules, providing
optimal use of silicon. This enables the entire floor of the
device to be spanned with an uninterrupted grid of
fine-grained, synthesis-friendly logic modules (or
“sea-of-modules”), which reduces the distance signals have
to travel between logic modules. To minimize signal
propagation delay, SX devices employ both local and general
routing resources. The high-speed local routing resources
(DirectConnect and FastConnect) enable very fast local
signal propagation that is optimal for fast counters, state
Further complementing SX’s flexible routing structure is a
hard-wired, constantly loaded clock network that has been
tuned to provide fast clock propagation with minimal clock
skew. Additionally, the high performance of the internal
logic has eliminated the need to embed latches or flip-flops
in the I/O cells to achieve fast clock-to-out or fast input
set-up times. SX devices have easy-to-use I/O cells that do
not require HDL instantiation, facilitating design re-use and
reducing design and verification time.
O r d e r i n g I n f o r m a t i o n
A54SX16
P
–
2
PQ
208
Application (Temperature Range)
Blank = Commercial (0 to +70°C)
I = Industrial (–40 to +85°C)
M = Military (–55 to +125°C)
PP = Pre-production
Package Lead Count
Package Type
BG = Ball Grid Array
PL = Plastic Leaded Chip Carrier
PQ = Plastic Quad Flat Pack
TQ = Thin (1.4 mm) Quad Flat Pack
VQ = Very Thin (1.0 mm) Quad Flat Pack
FG = Fine Pitch Ball Grid Array (1.0 mm)
Speed Grade
Blank = Standard Speed
–1 = Approximately 15% Faster than Standard
–2 = Approximately 25% Faster than Standard
–3 = Approximately 35% Faster than Standard
Blank = Not PCI Compliant
P = PCI Compliant
Part Number
A54SX08 = 12,000 System Gates
A54SX16 = 24,000 System Gates
A54SX16P = 24,000 System Gates
A54SX32 = 48,000 System Gates
2
v3 .1
5 4 S X F a m i l y F P G A s
P r o d u c t P l a n
Speed Grade*
–1
Application
I†
Std
–2
–3
C
M•
A54SX08 Device
84-Pin Plastic Leaded Chip Carrier (PLCC)
100-Pin Very Thin Plastic Quad Flat Pack (VQFP)
144-Pin Thin Quad Flat Pack (TQFP)
144-Pin Fine Pitch Ball Grid Array (FBGA)
176-Pin Thin Quad Flat Pack (TQFP)
208-Pin Plastic Quad Flat Pack (PQFP)
A54SX16 Device
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
—
—
—
—
—
—
100-Pin Very Thin Plastic Quad Flat Pack (VQFP)
176-Pin Thin Quad Flat Pack (TQFP)
208-Pin Plastic Quad Flat Pack (PQFP)
A54SX16P Device
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
P
P
P
100-Pin Very Thin Plastic Quad Flat Pack (VQFP)
144-Pin Thin Quad Flat Pack (TQFP)
176-Pin Thin Quad Flat Pack (TQFP)
208-Pin Plastic Quad Flat Pack (PQFP)
A54SX32 Device
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
—
—
—
—
144-Pin Thin Quad Flat Pack (TQFP)
176-Pin Thin Quad Flat Pack (TQFP)
208-Pin Plastic Quad Flat Pack (PQFP)
313-Pin Plastic Ball Grid Array (PBGA)
329-Pin Plastic Ball Grid Array (PBGA)
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
P
P
P
—
—
Contact your Actel sales representative for product availability.
Applications:C = CommercialAvailability:✔
=
=
=
Available*Speed Grade:–1
=
=
=
Approx. 15% faster than Standard
Approx. 25% faster than Standard
Approx. 35% faster than Standard
I
= Industrial
= Military
P
Planned
–2
–3
M
—
Not Planned
† Only Std, –1, –2 Speed Grade
• Only Std, –1 Speed Grade
P l a s t i c D e v i c e R e s o u r c e s
User I/Os (including clock buffers)
PLCC
VQFP
PQFP
TQFP
TQFP
PBGA
PBGA
FBGA
Device
A54SX08
84-Pin
100-Pin
208-Pin
144-Pin
176-Pin
313-Pin
329-Pin
144-Pin
69
—
—
—
81
81
81
—
130
175
175
174
113
—
128
147
147
147
—
—
—
—
111
—
A54SX16
A54SX16P
A54SX32
113
113
—
—
—
249
249
—
Package Definitions (Consult your local Actel sales representative for product availability.)
PLCC = Plastic Leaded Chip Carrier, PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, VQFP = Very Thin Quad Flat Pack,
PBGA = Plastic Ball Grid Array, FBGA = Fine Pitch (1.0 mm) Ball Grid Array
v3 .1
3
5 4 S X F a m i l y F P G A s
S X F a m i l y A r c h i t e c t u r e
The SX family architecture was designed to satisfy antifuse interconnect elements, which are embedded
next-generation performance and integration requirements
for production-volume designs in a broad range of
applications.
between the M2 and M3 layers. The antifuses are normally
open circuit and, when programmed, form a permanent
low-impedance connection.
The extremely small size of these interconnect elements
gives the SX family abundant routing resources and provides
excellent protection against design pirating. Reverse
engineering is virtually impossible because it is extremely
difficult to distinguish between programmed and
unprogrammed antifuses, and there is no configuration
bitstream to intercept.
P r o g r a m m a b l e I n t e r c o n n e c t E l e m e n t
The SX family provides efficient use of silicon by locating the
routing interconnect resources between the Metal 2 (M2)
and Metal 3 (M3) layers (Figure 1). This completely
eliminates the channels of routing and interconnect
resources between logic modules (as implemented on SRAM
FPGAs and previous generations of antifuse FPGAs), and
enables the entire floor of the device to be spanned with an
uninterrupted grid of logic modules.
Additionally, the interconnect (i.e., the antifuses and metal
tracks) have lower capacitance and lower resistance than
any other device of similar capacity, leading to the fastest
signal propagation in the industry.
Interconnection between these logic modules is achieved
using Actel’s patented metal-to-metal programmable
Routing Tracks
Metal 3
Amorphous Silicon/
Dielectric Antifuse
Tungsten Plug Via
Tungsten Plug Via
Metal 2
Metal 1
Tungsten Plug
Contact
Silicon Substrate
Figure 1 • SX Family Interconnect Elements
L o g i c M o d u l e D e s i g n
The R-cell contains a flip-flop featuring asynchronous clear,
asynchronous preset, and clock enable (using the S0 and S1
lines) control signals (Figure 2 on page 5). The R-cell
registers feature programmable clock polarity selectable on
a register-by-register basis. This provides additional
flexibility while allowing mapping of synthesized functions
into the SX FPGA. The clock source for the R-cell can be
chosen from either the hard-wired clock or the routed clock.
The SX family architecture is described as
a
“sea-of-modules” architecture because the entire floor of
the device is covered with a grid of logic modules with
virtually no chip area lost to interconnect elements or
routing. Actel’s SX family provides two types of logic
modules, the register cell (R-cell) and the combinatorial
cell (C-cell).
4
v3 .1
5 4 S X F a m i l y F P G A s
The C-cell implements a range of combinatorial functions
up to 5-inputs (Figure 3). Inclusion of the DB input and its
associated inverter function dramatically increases the
number of combinatorial functions that can be
implemented in a single module from 800 options in
previous architectures to more than 4,000 in the SX
architecture. An example of the improved flexibility
enabled by the inversion capability is the ability to integrate
a 3-input exclusive-OR function into a single C-cell. This
facilitates construction of 9-bit parity-tree functions with 2
ns propagation delays. At the same time, the C-cell
structure is extremely synthesis friendly, simplifying the
overall design and reducing synthesis time.
Routed
Data Input
S1
S0
PSETB
Direct
Connect
Input
D
Q
Y
HCLK
CLKA,
CLKB,
CLRB
Internal Logic
CKS
CKP
Figure 2 • R-Cell
D0
D1
Y
D2
D3
Sa
Sb
DB
A0 B0
A1 B1
Figure 3 • C-Cell
C h i p A r c h i t e c t u r e
Type 2 contains one C-cell and two R-cells.
The SX family’s chip architecture provides a unique
approach to module organization and chip routing that
delivers the best register/logic mix for a wide variety of new
and emerging applications.
To increase design efficiency and device performance, Actel
has further organized these modules into SuperClusters
(Figure 4 on page 6). SuperCluster 1 is a two-wide grouping
of Type 1 clusters. SuperCluster 2 is a two-wide group
containing one Type 1 cluster and one Type 2 cluster. SX
devices feature more SuperCluster 1 modules than
SuperCluster 2 modules because designers typically require
significantly more combinatorial logic than flip-flops.
M o d u l e O r g a n i z a t i o n
Actel has arranged all C-cell and R-cell logic modules into
horizontal banks called Clusters. There are two types of
Clusters: Type 1 contains two C-cells and one R-cell, while
v3 .1
5
5 4 S X F a m i l y F P G A s
R-Cell
C-Cell
D0
D1
Routed
Data Input
S1
S0
PSETB
Y
D2
D3
Direct
Connect
Input
D
Q
Y
Sa
Sb
HCLK
CLKA,
CLKB,
Internal Logic
CLRB
DB
CKS
CKP
A0 B0
A1 B1
Cluster 1
Cluster 2
Cluster 2
Cluster 1
Type 1 SuperCluster
Figure 4 • Cluster Organization
Type 2 SuperCluster
R o u t i n g R e s o u r c e s
Clusters and SuperClusters can be connected through the
use of two innovative local routing resources called
In addition to DirectConnect and FastConnect, the
architecture makes use of two globally oriented routing
FastConnect and DirectConnect, which enable extremely resources known as segmented routing and high-drive
fast and predictable interconnection of modules within
Clusters and SuperClusters (Figure 5 and Figure 6 on
page 7). This routing architecture also dramatically reduces
the number of antifuses required to complete a circuit,
ensuring the highest possible performance.
routing. Actel’s segmented routing structure provides a
variety of track lengths for extremely fast routing between
SuperClusters. The exact combination of track lengths and
antifuses within each path is chosen by the 100 percent
automatic place and route software to minimize signal
propagation delays.
DirectConnect is a horizontal routing resource that provides
connections from a C-cell to its neighboring R-cell in a given
SuperCluster. DirectConnect uses a hard-wired signal path
requiring no programmable interconnection to achieve its
fast signal propagation time of less than 0.1 ns.
Actel’s high-drive routing structure provides three clock
networks. The first clock, called HCLK, is hard wired from
the HCLK buffer to the clock select MUX in each R-cell. This
provides a fast propagation path for the clock signal,
enabling the 3.7 ns clock-to-out (pin-to-pin) performance of
the SX devices. The hard-wired clock is tuned to provide
clock skew as low as 0.25 ns. The remaining two clocks
(CLKA, CLKB) are global clocks that can be sourced from
external pins or from internal logic signals within the SX
device.
FastConnect enables horizontal routing between any two
logic modules within a given SuperCluster and vertical
routing with the SuperCluster immediately below it. Only
one programmable connection is used in a FastConnect
path, delivering maximum pin-to-pin propagation of 0.4 ns.
6
v3 .1
5 4 S X F a m i l y F P G A s
O t h e r A r c h i t e c t u r a l F e a t u r e s
T e c h n o lo g y
Actel’s SX family is implemented on a high-voltage twin-well
CMOS process using 0.35µ design rules. The metal-to-metal
antifuse is made up of a combination of amorphous silicon
and dielectric material with barrier metals and has a
programmed (“on” state) resistance of 25Ω with
capacitance of 1.0 fF for low signal impedance.
Direct Connect
• No antifuses
• 0.1 ns routing delay
Fast Connect
• One antifuse
• 0.4 ns routing delay
Routing Segments
• Typically 2 antifuses
• Max. 5 antifuses
Figure 5 • DirectConnect and FastConnect for Type 1 SuperClusters
Direct Connect
• No antifuses
• 0.1 ns routing delay
Fast Connect
• One antifuse
• 0.4 ns routing delay
Routing Segments
• Typically 2 antifuses
• Max. 5 antifuses
Figure 6 • DirectConnect and FastConnect for Type 2 SuperClusters
v3 .1
7
5 4 S X F a m i l y F P G A s
P e r f o r m a n c e
B o u n d a r y S c a n T e s t i n g ( B S T )
The combination of architectural features described above
enables SX devices to operate with internal clock
frequencies exceeding 300 MHz, enabling very fast
All SX devices are IEEE 1149.1 compliant. SX devices offer
superior diagnostic and testing capabilities by providing
Boundary Scan Testing (BST) and probing capabilities.
execution of even complex logic functions. Thus, the SX These functions are controlled through the special test pins
family is an optimal platform upon which to integrate the
functionality previously contained in multiple CPLDs. In
addition, designs that previously would have required a gate
array to meet performance goals can now be integrated into
an SX device with dramatic improvements in cost and time
to market. Using timing-driven place and route tools,
designers can achieve highly deterministic device
performance. With SX devices, designers do not need to use
complicated performance-enhancing design techniques
such as the use of redundant logic to reduce fanout on
critical nets or the instantiation of macros in HDL code to
achieve high performance.
in conjunction with the program fuse. The functionality of
each pin is described in Table 2.In the dedicated test mode,
TCK, TDI and TDO are dedicated pins and cannot be used as
regular I/Os. In flexible mode, TMS should be set HIGH
through a pull-up resistor of 10kΩ. TMS can be pulled LOW
to initiate the test sequence.
The program fuse determines whether the device is in
dedicated or flexible mode. The default (fuse not blown) is
flexible mode. .
Table 2 • Boundary Scan Pin Functionality
Program Fuse Blown
(Dedicated Test Mode)
Program Fuse Not Blown
(Flexible Mode)
I /O M o d u l e s
TCK, TDI, TDO are
dedicated BST pins
TCK, TDI, TDO are flexible
and may be used as I/Os
Each I/O on an SX device can be configured as an input, an
output, a tristate output, or a bidirectional pin. Even without
the inclusion of dedicated I/O registers, these I/Os, in
combination with array registers, can achieve clock-to-out
(pad-to-pad) timing as fast as 3.7 ns. I/O cells that have
embedded latches and flip-flops require instantiation in
HDL code; this is a design complication not encountered in
SX FPGAs. Fast pin-to-pin timing ensures that the device
will have little trouble interfacing with any other device in
the system, which in turn enables parallel design of system
components and reduces overall design time.
No need for pull-up resistor Use a pull-up resistor of 10k
for TMS Ω on TMS
D e v e l o p m e n t T o o l S u p p o r t
The SX devices are fully supported by Actel’s line of FPGA
development tools, including the Actel DeskTOP series and
Designer Advantage tools. The Actel DeskTOP series is an
integrated design environment for PCs that includes design
entry, simulation, synthesis, and place and route tools.
Designer Advantage, Actel’s suite of FPGA development
point tools for PCs and Workstations, includes the ACTgen
Macro Builder, Designer with DirectTime timing driven
place and route and analysis tools, and device programming
software.
P o w e r R e q u i r e m e n t s
The SX family supports 3.3V operation and is designed to
tolerate 5.0V inputs. (Table 1). Power consumption is
extremely low due to the very short distances signals are
required to travel to complete a circuit. Power requirements
are further reduced because of the small number of
low-resistance antifuses in the path. The antifuse
architecture does not require active circuitry to hold a
charge (as do SRAM or EPROM), making it the lowest-power
architecture on the market.
In addition, the SX devices contain ActionProbe circuitry
that provides built-in access to every node in a design,
enabling 100-percent real-time observation and analysis of a
device's internal logic nodes without design iteration. The
probe circuitry is accessed by Silicon Explorer II, an
easy-to-use integrated verification and logic analysis tool
that can sample data at 100 MHz (asynchronous) or 66 MHz
(synchronous). Silicon Explorer II attaches to a PC’s
standard COM port, turning the PC into a fully functional
18-channel logic analyzer. Silicon Explorer II allows
designers to complete the design verification process at
their desks and reduces verification time from several hours
per cycle to only a few seconds.
Table 1 • Supply Voltages
Maximum Maximum
Input
Output
Drive
VCCA VCCI VCCR Tolerance
A54SX08
A54SX16
A54SX32
3.3V 3.3V 5.0V
3.3V 3.3V 3.3V
5.0V
3.3V
3.3V
5.0V
5.0V
3.3V
3.3V
5.0V
A54SX16-P 3.3V 3.3V 5.0V
3.3V 5.0V 5.0V
Note: A54SX16-P has three different entries because it is capable of
both a 3.3V and a 5V drive.
8
v3 .1
5 4 S X F a m i l y F P G A s
S X P r o b e C i r c u i t C o n t r o l P i n s
recommended that the TRST pin be left floating.
The Silicon Explorer II tool uses the boundary scan ports
(TDI, TCK, TMS and TDO) to select the desired nets for
verification. The selected internal nets are assigned to the
PRA/PRB pins for observation. Figure 7 illustrates the
interconnection between Silicon Explorer II and the FPGA
to perform in-circuit verification. The TRST pin is equipped
with a pull-up resistor. To remove the boundary scan state
machine from the reset state during probing, it is
D e s i g n C o n s i d e r a t i o n s
The TDI, TCK, TDO, PRA, and PRB pins should not be used
as input or bidirectional ports. Because these pins are
active during probing, critical signals input through these
pins are not available while probing. In addition, the
Security Fuse should not be programmed because doing so
disables the Probe Circuitry.
SX FPGA
TDI
TCK
TMS
Silicon Explorer II
Serial Connection
TDO
PRA
PRB
Figure 7 • Probe Setup
v3 .1
9
5 4 S X F a m i l y F P G A s
3 . 3 V /5 V O p e r a t i n g C o n d i t i o n s
1
A b s o l u t e M a x i m u m R a t i n g s
R e c o m m e n d e d O p e r a t i n g C o n d i t i o n s
Symbol
Parameter
Limits
Units
Commer
Parameter
cial
Industrial
Military
Units
2
VCCR
DC Supply Voltage3
DC Supply Voltage
DC Supply Voltage
(A54SX08,A54SX16, –0.3 to +4.0
A54SX32)
–0.3 to +6.0
–0.3 to +4.0
V
V
Temperature
Range1
2
0 to+70 –40 to +85 –55 to +125
°C
VCCA
3.3V Power
Supply
Tolerance
2
%VC
VCCI
V
±10
±5
±10
±10
±10
±10
C
DC Supply Voltage
–0.3 to +6.0
2
5.0V Power
Supply
Tolerance
VCCI
V
%VC
(A54SX16P)
C
VI
Input Voltage
–0.5 to +5.5
–0.5 to +3.6
V
V
VO
Output Voltage
I/O Source Sink
Current3
Note:
1. Ambient temperature (TA) is used for commercial and
industrial; case temperature (TC) is used for military.
IIO
–30 to +5.0
–65 to +150
mA
°C
TSTG
Storage Temperature
Notes:
1. Stresses beyond those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
Exposure to absolute maximum rated conditions for extended
periods may affect device reliability. Device should not be
operated outside the Recommended Operating Conditions.
2.
VCCR in the A54SX16P must be greater than or equal to V
during power-up and power-down sequences and duriCnCgI
normal operation.
3. Device inputs are normally high impedance and draw
extremely low current. However, when input voltage is greater
than V + 0.5V or less than GND – 0.5V, the internal protection
diodesCwCill forward-bias and can draw excessive current.
E l e c t r i c a l S p e c i f i c a t i o n s
Commercial
Industrial
Symbol
Parameter
Min.
Max.
Min.
Max.
Units
(IOH = -20uA) (CMOS)
(IOH = -8mA) (TTL)
(IOH = -6mA) (TTL)
(IOL= 20uA) (CMOS)
(IOL = 12mA) (TTL)
(IOL = 8mA) (TTL)
(VCCI – 0.1)
2.4
VCCI
VCCI
(VCCI – 0.1)
VCCI
VOH
V
2.4
VCCI
0.10
0.50
VOL
V
0.50
0.8
VIL
0.8
V
V
VIH
2.0
2.0
tR, tF
CIO
Input Transition Time tR, tF
CIO I/O Capacitance
50
10
50
10
ns
pF
mA
ICC
Standby Current, ICC
4.0
4.0
ICC(D)
ICC(D) Dynamic
I
VCC Supply Current
See “Evaluating Power in 54SX Devices” on page 18
1 0
v3 .1
5 4 S X F a m i l y F P G A s
P C I C o m p l i a n c e f o r t h e 5 4 S X F a m i l y
The 54SX family supports 3.3V and 5V PCI and is compliant with the PCI Local Bus Specification Rev. 2.1.
A5 4 S X1 6 P DC S p e c ific a t io n s (5 . 0 V P C I O p e r a t io n )
Symbol
Parameter
Condition
Min.
Max.
Units
VCCA
VCCR
VCCI
VIH
Supply Voltage for Array
Supply Voltage required for Internal Biasing
Supply Voltage for IOs
Input High Voltage1
3.0
4.75
4.75
2.0
3.6
5.25
V
V
5.25
V
VCC + 0.5
0.8
V
VIL
Input Low Voltage1
–0.5
V
IIH
Input High Leakage Current
Input Low Leakage Current
Output High Voltage
Output Low Voltage2
Input Pin Capacitance3
VIN = 2.7
70
µA
µA
V
IIL
VIN = 0.5
–70
VOH
VOL
CIN
IOUT = –2 mA
IOUT = 3 mA, 6 mA
2.4
5
0.55
10
12
8
V
pF
pF
pF
CCLK
CIDSEL
Notes:
CLK Pin Capacitance
IDSEL Pin Capacitance4
1. Input leakage currents include hi-Z output leakage for all bi-directional buffers with tri-state outputs.
2. Signals without pull-up resistors must have 3 mA low output current. Signals requiring pull up must have 6 mA; the latter include,
FRAME#, IRDY#, TRDY#, DEVSEL#, STOP#, SERR#, PERR#, LOCK#, and, when used AD[63::32], C/BE[7::4]#, PAR64, REQ64#, and ACK64#.
3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK).
4. Lower capacitance on this input-only pin allows for non-resistive coupling to AD[xx].
v3 .1
1 1
5 4 S X F a m i l y F P G A s
A5 4 S X1 6 P AC S p e c ific a t io n s fo r (P C I O p e r a t io n )
Symbol
Parameter
Condition
Min.
Max.
Units
0 < VOUT ≤ 1.41
1.4 ≤ VOUT < 2.41, 2
–44
mA
mA
–44 + (VOUT – 1.4)/0.024
IOH(AC)
Switching Current High
(Test Point)
Equation A: on
page 13
1, 3
3.1 < VOUT < VCC
VOUT = 3.13
–142
mA
mA
V
OUT ≥ 2.21
95
2.2 > VOUT > 0.551
VOUT/0.023
IOL(AC)
Switching Current High
Equation B: on
page 13
0.71 > VOUT > 01, 3
mA
(Test Point)
VOUT = 0.713
206
mA
mA
ICL
Low Clamp Current
Output Rise Slew Rate
Output Fall Slew Rate
–5 < VIN ≤ –1
–25 + (VIN + 1)/0.015
slewR
slewF
Notes:
0.4V to 2.4V load4
2.4V to 0.4V load4
1
1
5
5
V/ns
V/ns
1. Refer to the V/I curves in Figure 8. Switching current characteristics for REQ# and GNT# are permitted to be one half of that specified here;
i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST# which are system outputs.
“Switching Current High” specification are not relevant to SERR#, INTA#, INTB#, INTC#, and INTD# which are open drain outputs.
2. Note that this segment of the minimum current curve is drawn from the AC drive point directly to the DC drive point rather than toward
the voltage rail (as is done in the pull-down curve). This difference is intended to allow for an optional N-channel pull-up.
3. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (A and B)
are provided with the respective diagrams in Figure 8. The equation defined maxima should be met by design. In order to facilitate
component testing, a maximum current test point is defined for each side of the output driver.
4. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any point
within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter with an
unloaded output per revision 2.0 of the PCI Local Bus Specification. However, adherence to both maximum and minimum parameters is
now required (the maximum is no longer simply a guideline). Since adherence to the maximum slew rate was not required prior to
revision 2.1 of the specification, there may be components in the market for some time that have faster edge rates; therefore, motherboard
designers must bear in mind that rise and fall times faster than this specification could occur, and should ensure that signal integrity
modeling accounts for this. Rise slew rate does not apply to open drain outputs.
pin
1/2 in. max.
output
buffer
VCC
10 pF
1kΩ
1kΩ
1 2
v3 .1
5 4 S X F a m i l y F P G A s
Figure 8 shows the 5.0V PCI V/I curve and the minimum and maximum PCI drive characteristics of the A54SX16P family.
0.50
0.45
0.40
PCI I
Maximum
OL
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
SX PCI I
OL
PCI I
4
Mininum
OL
1
2
3
5
6
–0.05
–0.10
–0.15
–0.20
PCI I
Mininum
OH
SX PCI I
OH
PCI I
Maximum
OH
Voltage Out
Figure 8 • 5.0V PCI Curve for A54SX16P Family
Equation A:
Equation B:
IOH = 11.9 * (VOUT – 5.25) * (VOUT + 2.45)
IOL = 78.5 * V
* (4.4 – V
)
OUT
OUT
for V > VOUT > 3.1V
for 0V < VOUT < 0.71V
CC
v3 .1
1 3
5 4 S X F a m i l y F P G A s
A 5 4 S X 1 6 P D C S p e c i f i c a t i o n s ( 3 . 3 V P C I O p e r a t i o n )
Symbol
Parameter
Condition
Min.
Max.
Units
VCCA
VCCR
VCCI
VIH
Supply Voltage for Array
Supply Voltage required for Internal Biasing
Supply Voltage for IOs
Input High Voltage
3.0
3.0
3.0
3.6
3.6
3.6
V
V
V
0.5VCC VCC + 0.5
V
VIL
Input Low Voltage
–0.5
0.3VCC
V
IIPU
Input Pull-up Voltage1
Input Leakage Current2
Output High Voltage
0.7VCC
V
IIL
0 < VIN < VCC
IOUT = –500 µA
IOUT = 1500 µA
±10
µA
V
VOH
VOL
0.9VCC
Output Low Voltage
0.1VCC
V
CIN
Input Pin Capacitance3
CLK Pin Capacitance
IDSEL Pin Capacitance4
10
12
8
pF
pF
pF
CCLK
CIDSEL
Notes:
5
1. This specification should be guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a floated
network. Applications sensitive to static power utilization should assure that the input buffer is conducting minimum current at this
input voltage.
2. Input leakage currents include hi-Z output leakage for all bi-directional buffers with tri-state outputs.
3. Absolute maximum pin capacitance for a PCI input is 10pF (except for CLK).
4. Lower capacitance on this input-only pin allows for non-resistive coupling to AD[xx].
1 4
v3 .1
5 4 S X F a m i l y F P G A s
A 5 4 S X1 6 P AC S p e c ific a t io n s (3 .3 V P CI Op e ra t io n )
Symbol Parameter
Condition
Min.
Max.
Units
1
0 < VOUT ≤ 0.3VCC
mA
mA
1
0.3VCC ≤ VOUT < 0.9VCC
–12VCC
Switching Current High
Equation C: on
page 16
1, 2
IOH(AC)
0.7VCC < VOUT < VCC
–17.1 + (VCC – VOUT)
2
(Test Point)
V
OUT = 0.7VCC
–32VCC
mA
mA
mA
mA
1
V
CC > VOUT ≥ 0.6VCC
1
Switching Current High 0.6VCC > VOUT > 0.1VCC
16VCC
IOL(AC)
0.18VCC > VOUT > 01, 2
26.7VOUT
on page 16
2
(Test Point)
VOUT = 0.18VCC
–3 < VIN ≤ –1
–3 < VIN ≤ –1
38VCC
ICL
Low Clamp Current
–25 + (VIN + 1)/0.015
mA
mA
ICH
High Clamp Current
25 + (VIN – VOUT – 1)/0.015
slewR
slewF
Notes:
Output Rise Slew Rate3 0.2VCC to 0.6VCC load
Output Fall Slew Rate3
0.6VCC to 0.2VCC load
1
1
4
4
V/ns
V/ns
1. Refer to the V/I curves in Figure 9. Switching current characteristics for REQ# and GNT# are permitted to be one half of that specified here;
i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST# which are system outputs.
“Switching Current High” specification are not relevant to SERR#, INTA#, INTB#, INTC#, and INTD# which are open drain outputs.
2. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (C and D)
are provided with the respective diagrams in Figure 9. The equation defined maxima should be met by design. In order to facilitate
component testing, a maximum current test point is defined for each side of the output driver.
3. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any point
within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter with an
unloaded output per the latest revision of the PCI Local Bus Specification. However, adherence to both maximum and minimum
parameters is required (the maximum is no longer simply a guideline). Rise slew rate does not apply to open drain outputs.
pin
1/2 in. max.
output
buffer
VCC
10 pF
1kΩ
1kΩ
v3 .1
1 5
5 4 S X F a m i l y F P G A s
Figure 9 shows the 3.3V PCI V/I curve and the minimum and maximum PCI drive characteristics of the A54SX16P family.
0.50
0.45
0.40
PCI I
Maximum
OL
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
SX PCI I
OL
PCI I
Minimum
OL
SX PCI I
OH
5
1
2
3
4
6
–0.05
–0.10
–0.15
–0.20
PCI I
Minimum
OH
PCI I
Maximum
OH
Voltage Out
Figure 9 • 3.3V PCI Curve for A54SX16P Family
Equation C:
Equation D:
OL = (256/V ) * V
IOH = (98.0/V ) * (VOUT – V ) * (VOUT + 0.4V )
I
* (V – V
)
CC
CC
CC
CC
OUT
CC
OUT
for V > VOUT > 0.7 V
for 0V < VOUT < 0.18 V
CC
CC
CC
1 6
v3 .1
5 4 S X F a m i l y F P G A s
P o w e r -U p S e q u e n c i n g
VCCA
VCCR
VCCI
Power-Up Sequence
Comments
A54SX08, A54SX16, A54SX32
5.0V First
3.3V Second
No possible damage to device.
Possible damage to device.
3.3V
5.0V
3.3V
3.3V First
5.0V Second
A54SX16P
3.3V
3.3V
3.3V
5.0V
3.3V
3.3V
3.3V Only
No possible damage to device.
No possible damage to device.
5.0V First
3.3V Second
3.3V First
5.0V Second
Possible damage to device.
No possible damage to device.
No possible damage to device.
5.0V First
3.3V Second
3.3V
5.0V
5.0V
3.3V First
5.0V Second
P o w e r -D o w n S e q u e n c i n g
VCCA
VCCR
VCCI
Power-Down Sequence
Comments
A54SX08, A54SX16, A54SX32
5.0V First
3.3V Second
No possible damage to device.
Possible damage to device.
3.3V
5.0V
3.3V
3.3V First
5.0V Second
A54SX16P
3.3V
3.3V
3.3V
5.0V
3.3V
3.3V
3.3V Only
No possible damage to device.
Possible damage to device.
5.0V First
3.3V Second
3.3V First
5.0V Second
No possible damage to device.
No possible damage to device.
No possible damage to device.
5.0V First
3.3V Second
3.3V
5.0V
5.0V
3.3V First
5.0V Second
v3 .1
1 7
5 4 S X F a m i l y F P G A s
E v a l u a t i n g P o w e r i n 5 4 S X D e v i c e s
A critical element of system reliability is the ability of
electronic devices to safely dissipate the heat generated
during operation. The thermal characteristics of a circuit
depend on the device and package used, the operating
temperature, the operating current, and the system's ability
to dissipate heat.
dissipation is defined as follows:
PAC = PModule + PRCLKA Net + PRCLKB Net + PHCLK Net
POutput Buffer + PInput Buffer
PAC = V 2 * [(m * CEQM * fm)Module
+
(3)
+
CCA
(n * CEQI * fn)Input Buffer+ (p * (CEQO + CL) * fp)Output Buffer
(0.5 * (q1 * CEQCR * fq1) + (r1 * fq1))RCLKA
(0.5 * (q2 * CEQCR * fq2)+ (r2 * fq2))RCLKB
(0.5 * (s1 * CEQHV * fs1) + (CEQHF * fs1))HCLK
+
+
+
You should complete a power evaluation early in the design
process to help identify potential heat-related problems in
the system and to prevent the system from exceeding the
device’s maximum allowed junction temperature.
]
(4)
D e f i n i t i o n o f T e r m s U s e d i n F o r m u l a
m
n
= Number of logic modules switching at fm
= Number of input buffers switching at fn
= Number of output buffers switching at fp
The actual power dissipated by most applications is
significantly lower than the power the package can
dissipate. However, a thermal analysis should be performed
for all projects. To perform a power evaluation, follow these
steps:
p
q1
= Number of clock loads on the first routed array
clock
q2
= Number of clock loads on the second routed
array clock
• Estimate the power consumption of the application.
x
= Number of I/Os at logic low
= Number of I/Os at logic high
• Calculate the maximum power allowed for the device and
package.
y
r1
= Fixed capacitance due to first routed array
clock
• Compare the estimated power and maximum power
values.
r2
s1
= Fixed capacitance due to second routed array
clock
E s t i m a t i n g P o w e r C o n s u m p t i o n
= Number of clock loads on the dedicated array
clock
The total power dissipation for the 54SX family is the sum of
the DC power dissipation and the AC power dissipation. Use
Equation 1 to calculate the estimated power consumption of
your application.
CEQM = Equivalent capacitance of logic modules in pF
CEQI = Equivalent capacitance of input buffers in pF
PTotal = PDC + PAC
(1)
CEQO = Equivalent capacitance of output buffers in pF
CEQCR = Equivalent capacitance of routed array clock in
pF
D C P o w e r D i s s i p a t i o n
The power due to standby current is typically a small
component of the overall power. The Standby power is
shown below for commercial, worst case conditions (70°C).
CEQHV = Variable capacitance of dedicated array clock
CEQHF = Fixed capacitance of dedicated array clock
CL
fm
fn
= Output lead capacitance in pF
Table 3 •
= Average logic module switching rate in MHz
= Average input buffer switching rate in MHz
= Average output buffer switching rate in MHz
= Average first routed array clock rate in MHz
= Average second routed array clock rate in MHz
= Average dedicated array clock rate in MHz
ICC
VCC
Power
fp
4mA
3.6V
14.4mW
fq1
fq2
fs1
The DC power dissipation is defined in Equation 2 as
follows:
PDC = (Istandby)*VCCA + (Istandby)*V
+
CCR
A54SX08 A54SX16 A54SX16P A54SX32
(Istandby)*VCCI + x*V *IOL + y*(VCCI – V )*V
(2)
OL
OH
OH
CEQM (pF) 4.0
EQI (pF) 3.4
4.0
4.0
4.0
A C P o w e r D i s s i p a t i o n
C
3.4
3.4
3.4
The power dissipation of the 54SX Family is usually
dominated by the dynamic power dissipation. Dynamic
power dissipation is a function of frequency, equivalent
capacitance and power supply voltage. The AC power
CEQO (pF) 4.7
CEQCR (pF) 1.6
4.7
4.7
4.7
1.6
1.6
1.6
CEQHV
CEQHF
r1 (pF)
r2 (pF)
0.615
0.615
96
0.615
96
0.615
140
171
171
60
87
87
138
138
138
138
1 8
v3 .1
5 4 S X F a m i l y F P G A s
G u i d e l i n e s f o r C a l c u l a t i n g P o w e r
C o n s u m p t i o n
A C P o w e r D i s s i p a t i o n
PAC = PModule + PRCLKA Net + PRCLKB Net + PHCLK Net
POutput Buffer + PInput Buffer
PAC = V 2 * [(m * CEQM * fm)Module
+
The following guidelines are meant to represent worst-case
scenarios so that they can be generally used to predict the
upper limits of power dissipation. These guidelines are as
follow:
(6)
(7)
+
CCA
(n * CEQI * fn)Input Buffer+ (p * (CEQO + CL) * fp)Output
+
Buffer
(0.5 * (q1 * CEQCR * fq1) + (r1 * fq1))RCLKA
(0.5 * (q2 * CEQCR * fq2)+ (r2 * fq2))RCLKB
(0.5 * (s1 * CEQHV * fs1) + (CEQHF * fs1))HCLK
+
+
Logic Modules (m)
Inputs Switching (n)
Outputs Switching (p)
= 20% of modules
= # inputs/4
]
= # output/4
Step #1: Define Terms Used in Formula
First Routed Array Clock Loads (q1) = 20% of register
cells
V
3.3
CCA
Module
Second Routed Array Clock Loads (q2) = 20% of register
cells
Number of logic modules switching at fm
(Used 50%)
m
264
20
Load Capacitance (CL)
= 35 pF
Average logic modules switching rate
fm (MHz) (Guidelines: f/10)
fm
Average Logic Module Switching Rate= f/10
(fm)
Module capacitance CEQM (pF)
Input Buffer
CEQM 4.0
Average Input Switching Rate (fn)
Average Output Switching Rate (fp)
= f/5
= f/10
Number of input buffers switching at fn
Average input switching rate fn (MHz)
(Guidelines: f/5)
n
1
Average First Routed Array Clock Rate= f/2
(fq1)
Average Second Routed Array Clock= f/2
Rate (fq2)
Average Dedicated Array Clock Rate = f
(fs1)
fn
40
Input buffer capacitance CEQI (pF)
Output Buffer
CEQI 3.4
Number of output buffers switching at fp
p
1
Dedicated Clock Array clock loads (s1) = 20% of regular
modules
Average output buffers switching rate
fp(MHz) (Guidelines: f/10)
fp
20
Output buffers buffer Capacitance CEQO (pF) CEQO 4.7
S a m p l e P o w e r C a l c u l a t i o n
Output Load capacitance CL (pF)
RCLKA
CL
35
One of the designs used to characterize the A54SX family
was a 528 bit serial in serial out shift register. The design
utilized 100% of the dedicated flip-flops of an A54SX16P
device. A pattern of 0101… was clocked into the device at
frequencies ranging from 1 MHz to 200 MHz. Shifting in a
series of 0101… caused 50% of the flip-flops to toggle from
low to high at every clock cycle.
Number of Clock loads q1
Capacitance of routed array clock (pF)
Average clock rate (MHz)
Fixed capacitance (pF)
RCLKB
q1
528
CEQCR 1.6
fq1
r1
200
138
Number of Clock loads q2
Capacitance of routed array clock (pF)
Average clock rate (MHz)
Fixed capacitance (pF)
HCLK
q2
0
Follow the steps below to estimate power consumption. The
values provided for the sample calculation below are for the
shift register design above. This method for estimating
power consumption is conservative and the actual power
consumption of your design may be less than the estimated
power consumption.
CEQCR 1.6
fq2
r2
0
138
Number of Clock loads
s1
0
The total power dissipation for the 54SX family is the sum of
the AC power dissipation and the DC power dissipation.
Variable capacitance of dedicated
array clock (pF)
CEQHV 0.615
PTotal = PAC (dynamic power) + PDC (static power)
(5)
Fixed capacitance of dedicated
array clock (pF)
CEQHF 96
Average clock rate (MHz)
fs1
0
v3 .1
1 9
5 4 S X F a m i l y F P G A s
Step #2: Calculate Dynamic Power Consumption
CCA*V
m*fm*CEQM
n*fn*CEQI
p*fp*(CEQO+CL)
0.5*(q1*CEQCR*fq1)+(r1*fq1)
0.5*(q2*CEQCR*fq2)+(r2*fq2)
0.5 *(s1 * CEQHV * fs1)+(CEQHF*fs1)
PAC = 1.461W
P
DC = (Istandby)*V
CCA
V
10.89
0.02112
0.000136
0.000794
0.11208
0
PDC = .55mA*3.3V
PDC = 0.001815W
CCA
Step #4: Calculate Total Power Consumption
PTotal = PAC + PDC
PTotal = 1.461 + 0.001815
PTotal = 1.4628W
0
Step #5: Compare Estimated Power Consumption against
Characterized Power Consumption
Step #3: Calculate DC Power Dissipation
DC Power Dissipation
The estimated total power consumption for this design is
1.46W. The characterized power consumption for this design
at 200 MHz is 1.0164W. Figure 10 shows the characterized
power dissipation numbers for the shift register design
using frequencies ranging from 1 MHz to 200 MHz.
PDC = (Istandby)*VCCA + (Istandby)*VCCR + (Istandby)*V
+
CCI
X*V *IOL + Y*(VCCI – V )*V
OL
OH
OH
(8)
For a rough estimate of DC Power Dissipation, only use
PDC = (Istandby)*VCCA. The rest of the formula provides a
very small number that can be considered negligible.
1200
1000
800
600
400
200
0
0
20
40
60
80
100
120
140
160
180
200
Frequency MHz
Figure 10 • Power Dissipation
2 0
v3 .1
5 4 S X F a m i l y F P G A s
J u n c t i o n T e m p e r a t u r e ( T )
P = Power calculated from Estimating Power Consumption
section
J
The temperature that you select in Designer Series software
is the junction temperature, not ambient temperature. This
is an important distinction because the heat generated from
dynamic power consumption is usually hotter than the
ambient temperature. Use the equation below to calculate
junction temperature.
θ
= Junction to ambient of package. θ numbers are
ja
ja
located in Package Thermal Characteristics section.
P a c k a g e T h e r m a l C h a r a c t e r i s t i c s
The device junction to case thermal characteristic is θjc,
and the junction to ambient air characteristic is θja. The
thermal characteristics for θja are shown with two different
air flow rates.
Junction Temperature = ∆T + T
a
Where:
T = Ambient Temperature
a
The maximum junction temperature is 150°C.
∆T = Temperature gradient between junction (silicon) and
ambient
A sample calculation of the absolute maximum power
dissipation allowed for a TQFP 176-pin package at
commercial temperature and still air is as follows:
∆T = θ * P
ja
Max. junction temp. (°C) – Max. ambient temp. (°C)
150°C – 70°C
Maximum Power Allowed = ------------------------------------------------------------------------------------------------------------------------------ = --------------------------------- = 2.86W
θja (°C/W)
28°C/W
θja
θja
Package Type
Pin Count
θjc
Still Air
300 ft/min
Units
Plastic Leaded Chip Carrier (PLCC)
Thin Quad Flat Pack (TQFP)
84
12
11
11
10
8
32
32
22
24
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
144
176
100
208
208
272
313
329
144
Thin Quad Flat Pack (TQFP)
28
21
Very Thin Quad Flatpack (VQFP)
Plastic Quad Flat Pack (PQFP) without Heat Spreader
Plastic Quad Flat Pack (PQFP) with Heat Spreader
Plastic Ball Grid Array (PBGA)
38
32
30
23
3.8
3
20
17
20
14.5
17
Plastic Ball Grid Array (PBGA)
3
23
Plastic Ball Grid Array (PBGA)
3
18
13.5
26.7
Fine Pitch Ball Grid Array (FBGA)
3.8
38.8
Note:
SX08 does not have a heat spreader.
v3 .1
2 1
5 4 S X F a m i l y F P G A s
5 4 S X T i m i n g M o d e l *
Input Delays
Internal Delays
Predicted
Routing
Delays
Output Delays
Combinatorial
Cell
I/O Module
I/O Module
tINY = 1.5 ns
t
IRD2 = 0.6 ns
tDHL = 1.6 ns
tRD1 = 0.3 ns
tRD4 = 1.0 ns
tRD8 = 1.9 ns
tPD =0.6 ns
I/O Module
tDHL = 1.6 ns
Register
Cell
Register
Cell
D
D
Q
Q
tRD1 = 0.3 ns
tRD1 = 0.3 ns
t
ENZH = 2.3 ns
tSUD = 0.5 ns
HD = 0.0 ns
t
t
RCO = 0.8 ns
tRCO = 0.8 ns
Routed
Clock
tRCKH = 1.5 ns (100% Load)
FMAX = 250 MHz
Hard-Wired
Clock
tHCKH = 1.0 ns
FHMAX = 320 MHz
*Values shown for A54SX08-3, worst-case commercial conditions.
H a r d -W i r e d C l o c k
R o u t e d C l o c k
External Set-Up = tINY + tIRD1 + tSUD – tHCKH
= 1.5 + 0.3 + 0.5 – 1.0 = 1.3 ns
Clock-to-Out (Pin-to-Pin)
External Set-Up = tINY + tIRD1 + tSUD – tRCKH
= 1.5 + 0.3 + 0.5 – 1.5 = 0.8 ns
Clock-to-Out (Pin-to-Pin)
= tHCKH + tRCO + tRD1 + tDHL
= 1.0 + 0.8 + 0.3 + 1.6 = 3.7 ns
= tRCKH + tRCO + tRD1 + tDHL
= 1.52+ 0.8 + 0.3 + 1.6 = 4.2 ns
2 2
v3 .1
5 4 S X F a m i l y F P G A s
O u t p u t B u f f e r D e l a y s
E
D
To AC test loads (shown below)
PAD
TRIBUFF
VCC
VCC
VCC
In
GND
1.5V
50%
VOH
En
Out
GND
10%
50%
En
GND
90%
50%
50%
VCC
50%
VOH
50%
1.5V
VOL
Out
VOL
Out
GND
1.5V
1.5V
tDLH
tDHL
tENZL
tENLZ
tENZH
tENHZ
A C T e s t L o a d s
Load 2
(Used to measure enable delays)
Load 3
(Used to measure disable delays)
Load 1
(Used to measure
propagation delay)
VCC
VCC
GND
GND
To the output
under test
35 pF
R to VCC for tPZL
R to GND for tPZH
R = 1 kΩ
R to VCC for tPLZ
R to GND for tPHZ
R = 1 kΩ
To the output
under test
To the output
under test
35 pF
5 pF
I n p u t B u f f e r D e l a y s
C -C e l l D e l a y s
S
A
B
Y
Y
PAD
INBUF
VCC
GND
S, A or B
50% 50%
VCC
3V
In
0V
1.5V
VCC
1.5V
50%
Out
50%
GND
tPD
tPD
50%
Out
GND
50%
VCC
50%
Out
GND
tPD
50%
tPD
tINY
tINY
v3 .1
2 3
5 4 S X F a m i l y F P G A s
R e g i s t e r C e l l T i m i n g C h a r a c t e r i s t i c s
F l i p -F l o p s
D
Q
PRESET
CLR
CLK
(Positive edge triggered)
tHD
D
tHP
tHPWH
tRPWH
,
tSUD
CLK
tHPWL
,
tRPWL
tRCO
Q
CLR
tCLR
tPRESET
tWASYN
PRESET
L o n g T r a c k s
T i m i n g C h a r a c t e r i s t i c s
Timing characteristics for 54SX devices fall into three
categories: family-dependent, device-dependent, and
design-dependent. The input and output buffer
characteristics are common to all 54SX family members.
Internal routing delays are device dependent. Design
dependency means actual delays are not determined until
after placement and routing of the user’s design is complete.
Delay values may then be determined by using the
DirectTime Analyzer utility or performing simulation with
post-layout delays.
Some nets in the design use long tracks. Long tracks are
special routing resources that span multiple rows, columns,
or modules. Long tracks employ three and sometimes five
antifuse connections. This increases capacitance and
resistance, resulting in longer net delays for macros
connected to long tracks. Typically up to 6% of nets in a fully
utilized device require long tracks. Long tracks contribute
approximately 4 ns to 8.4 ns delay. This additional delay is
represented statistically in higher fanout (FO=24) routing
delays in the data sheet specifications section.
C r i t i c a l N e t s a n d T y p i c a l N e t s
T i m i n g D e r a t i n g
Propagation delays are expressed only for typical nets,
which are used for initial design performance evaluation.
Critical net delays can then be applied to the most
time-critical paths. Critical nets are determined by net
property assignment prior to placement and routing. Up to
6% of the nets in a design may be designated as critical,
while 90% of the nets in a design are typical.
54SX devices are manufactured in a CMOS process.
Therefore, device performance varies according to
temperature, voltage, and process variations. Minimum
timing parameters reflect maximum operating voltage,
minimum operating temperature, and best-case processing.
Maximum timing parameters reflect minimum operating
voltage, maximum operating temperature, and worst-case
processing.
T e m p e r a t u r e a n d V o l t a g e D e r a t i n g F a c t o r s
(N o r m a liz e d t o Wo r s t -C a s e C o m m e r c ia l, T = 7 0 °C , V
= 3 . 0 V)
C C A
J
Junction Temperature (TJ)
25
VCCA
3.0
–55
0.75
0.70
0.66
–40
0.78
0.73
0.69
0
70
85
125
1.16
1.08
1.02
0.87
0.82
0.77
0.89
0.83
0.78
1.00
0.93
0.87
1.04
0.97
0.92
3.3
3.6
2 4
v3 .1
5 4 S X F a m i l y F P G A s
A 5 4 S X 0 8 T i m i n g C h a r a c t e r i s t i c s
(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V
= 4 . 7 5 V, V
V
= 3 . 0 V, T = 7 0 °C )
C C R
C C A, C C I J
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
Parameter Description
C-Cell Propagation Delays1
Min. Max. Min. Max. Min. Max. Min. Max. Units
tPD
Internal Array Module
0.6
0.7
0.8
0.9
ns
Predicted Routing Delays2
FO=1 Routing Delay, Direct
Connect
tDC
0.1
0.1
0.1
0.1
ns
tFC
FO=1 Routing Delay, Fast Connect
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
FO=12 Routing Delay
0.3
0.3
0.6
0.8
1.0
1.9
2.8
0.4
0.4
0.7
0.9
1.2
2.2
3.2
0.4
0.4
0.8
1.0
1.4
2.5
3.7
0.5
0.5
0.9
1.2
1.6
2.9
4.3
ns
ns
ns
ns
ns
ns
ns
tRD1
tRD2
tRD3
tRD4
tRD8
tRD12
R-Cell Timing
tRCO
Sequential Clock-to-Q
0.8
0.5
0.7
1.1
0.6
0.8
1.2
0.7
0.9
1.4
0.8
1.0
ns
ns
ns
ns
ns
ns
tCLR
Asynchronous Clear-to-Q
Asynchronous Preset-to-Q
Flip-Flop Data Input Set-Up
Flip-Flop Data Input Hold
Asynchronous Pulse Width
tPRESET
tSUD
0.5
0.0
1.4
0.5
0.0
1.6
0.7
0.0
1.8
0.8
0.0
2.1
tHD
tWASYN
Input Module Propagation Delays
tINYH
tINYL
Input Data Pad-to-Y HIGH
Input Data Pad-to-Y LOW
1.5
1.5
1.7
1.7
1.9
1.9
2.2
2.2
ns
ns
Input Module Predicted Routing Delays2
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
tIRD12
Notes:
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
FO=12 Routing Delay
0.3
0.6
0.8
1.0
1.9
2.8
0.4
0.7
0.9
1.2
2.2
3.2
0.4
0.8
1.0
1.4
2.5
3.7
0.5
0.9
1.2
1.6
2.9
4.3
ns
ns
ns
ns
ns
ns
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
v3 .1
2 5
5 4 S X F a m i l y F P G A s
A 5 4 S X 0 8 T i m i n g C h a r a c t e r i s t i c s (c o n t in u e d )
(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s )
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Units
Dedicated (Hard-Wired) Array Clock Network
tHCKH
Input LOW to HIGH
(Pad to R-Cell Input)
1.0
1.0
1.1
1.2
1.3
1.4
1.5
1.6
ns
ns
tHCKL
Input HIGH to LOW
(Pad to R-Cell Input)
tHPWH
tHPWL
tHCKSW
tHP
Minimum Pulse Width HIGH
Minimum Pulse Width LOW
Maximum Skew
1.4
1.4
1.6
1.6
1.8
1.8
2.1
2.1
ns
ns
0.1
0.2
0.2
0.2
ns
Minimum Period
2.7
3.1
3.6
4.2
ns
fHMAX
Maximum Frequency
350
320
280
240
MHz
Routed Array Clock Networks
Input LOW to HIGH (Light Load)
(Pad to R-Cell Input)
tRCKH
tRCKL
tRCKH
tRCKL
tRCKH
tRCKL
1.3
1.4
1.4
1.5
1.5
1.5
1.5
1.6
1.7
1.7
1.7
1.8
1.7
1.8
1.9
2.0
1.9
2.0
2.0
2.1
2.2
2.3
2.2
2.3
ns
ns
ns
ns
ns
ns
Input HIGH to LOW (Light Load)
(Pad to R-Cell Input)
Input LOW to HIGH (50% Load)
(Pad to R-Cell Input)
Input HIGH to LOW (50% Load)
(Pad to R-Cell Input)
Input LOW to HIGH (100% Load)
(Pad to R-Cell Input)
Input HIGH to LOW (100% Load)
(Pad to R-Cell Input)
tRPWH
Min. Pulse Width HIGH
2.1
2.1
2.4
2.4
2.7
2.7
3.2
3.2
ns
ns
ns
ns
ns
tRPWL
Min. Pulse Width LOW
tRCKSW
tRCKSW
tRCKSW
Maximum Skew (Light Load)
Maximum Skew (50% Load)
Maximum Skew (100% Load)
0.1
0.3
0.3
0.2
0.3
0.3
0.2
0.4
0.4
0.2
0.4
0.4
TTL Output Module Timing1
tDLH
Data-to-Pad LOW to HIGH
1.6
1.6
2.1
2.3
1.4
1.3
1.9
1.9
2.4
2.7
1.7
1.5
2.1
2.1
2.8
3.1
1.9
1.7
2.5
2.5
3.2
3.6
2.2
2.0
ns
ns
ns
ns
ns
ns
tDHL
Data-to-Pad HIGH to LOW
Enable-to-Pad, Z to L
Enable-to-Pad, Z to H
Enable-to-Pad, L to Z
Enable-to-Pad, H to Z
tENZL
tENZH
tENLZ
tENHZ
Note:
1. Delays based on 35 pF loading, except tENZL and tENZH . For tENZL and tENZH the loading is 5 pF.
2 6
v3 .1
5 4 S X F a m i l y F P G A s
A 5 4 S X 1 6 T i m i n g C h a r a c t e r i s t i c s
(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V
= 4 . 7 5 V, V
V
= 3 . 0 V, T = 7 0 °C )
C C R
C C A, C C I J
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
Parameter Description
C-Cell Propagation Delays1
Min. Max. Min. Max. Min. Max. Min. Max. Units
tPD
Internal Array Module
0.6
0.7
0.8
0.9
ns
Predicted Routing Delays2
FO=1 Routing Delay, Direct
Connect
tDC
0.1
0.1
0.1
0.1
ns
tFC
FO=1 Routing Delay, Fast Connect
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
FO=12 Routing Delay
0.3
0.3
0.6
0.8
1.0
1.9
2.8
0.4
0.4
0.7
0.9
1.2
2.2
3.2
0.4
0.4
0.8
1.0
1.4
2.5
3.7
0.5
0.5
0.9
1.2
1.6
2.9
4.3
ns
ns
ns
ns
ns
ns
ns
tRD1
tRD2
tRD3
tRD4
tRD8
tRD12
R-Cell Timing
tRCO
Sequential Clock-to-Q
0.8
0.5
0.7
1.1
0.6
0.8
1.2
0.7
0.9
1.4
0.8
1.0
ns
ns
ns
ns
ns
ns
tCLR
Asynchronous Clear-to-Q
Asynchronous Preset-to-Q
Flip-Flop Data Input Set-Up
Flip-Flop Data Input Hold
Asynchronous Pulse Width
tPRESET
tSUD
0.5
0.0
1.4
0.5
0.0
1.6
0.7
0.0
1.8
0.8
0.0
2.1
tHD
tWASYN
Input Module Propagation Delays
tINYH
tINYL
Input Data Pad-to-Y HIGH
Input Data Pad-to-Y LOW
1.5
1.5
1.7
1.7
1.9
1.9
2.2
2.2
ns
ns
Predicted Input Routing Delays2
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
tIRD12
Notes:
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
FO=12 Routing Delay
0.3
0.6
0.8
1.0
1.9
2.8
0.4
0.7
0.9
1.2
2.2
3.2
0.4
0.8
1.0
1.4
2.5
3.7
0.5
0.9
1.2
1.6
2.9
4.3
ns
ns
ns
ns
ns
ns
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
v3 .1
2 7
5 4 S X F a m i l y F P G A s
A 5 4 S X 1 6 T i m i n g C h a r a c t e r i s t i c s (c o n t in u e d )
(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s )
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Units
Dedicated (Hard-Wired) Array Clock Network
tHCKH
Input LOW to HIGH
(Pad to R-Cell Input)
1.2
1.2
1.4
1.4
1.5
1.6
1.8
1.9
ns
ns
tHCKL
Input HIGH to LOW
(Pad to R-Cell Input)
tHPWH
tHPWL
tHCKSW
tHP
Minimum Pulse Width HIGH
Minimum Pulse Width LOW
Maximum Skew
1.4
1.4
1.6
1.6
1.8
1.8
2.1
2.1
ns
ns
0.2
0.2
0.3
0.3
ns
Minimum Period
2.7
3.1
3.6
4.2
ns
fHMAX
Maximum Frequency
350
320
280
240
MHz
Routed Array Clock Networks
Input LOW to HIGH (Light Load)
(Pad to R-Cell Input)
tRCKH
tRCKL
tRCKH
tRCKL
tRCKH
tRCKL
1.6
1.8
1.8
2.0
1.8
2.0
1.8
2.0
2.1
2.2
2.1
2.2
2.1
2.3
2.5
2.5
2.4
2.5
2.5
2.7
2.8
3.0
2.8
3.0
ns
ns
ns
ns
ns
ns
Input HIGH to LOW (Light Load)
(Pad to R-Cell Input)
Input LOW to HIGH (50% Load)
(Pad to R-Cell Input)
Input HIGH to LOW (50% Load)
(Pad to R-Cell Input)
Input LOW to HIGH (100% Load)
(Pad to R-Cell Input)
Input HIGH to LOW (100% Load)
(Pad to R-Cell Input)
tRPWH
Min. Pulse Width HIGH
2.1
2.1
2.4
2.4
2.7
2.7
3.2
3.2
ns
ns
ns
ns
ns
tRPWL
Min. Pulse Width LOW
tRCKSW
tRCKSW
tRCKSW
Maximum Skew (Light Load)
Maximum Skew (50% Load)
Maximum Skew (100% Load)
0.5
0.5
0.5
0.5
0.6
0.6
0.5
0.7
0.7
0.7
0.8
0.8
TTL Output ModuleTiming1
tDLH
Data-to-Pad LOW to HIGH
1.6
1.6
2.1
2.3
1.4
1.3
1.9
1.9
2.4
2.7
1.7
1.5
2.1
2.1
2.8
3.1
1.9
1.7
2.5
2.5
3.2
3.6
2.2
2.0
ns
ns
ns
ns
ns
ns
tDHL
Data-to-Pad HIGH to LOW
Enable-to-Pad, Z to L
Enable-to-Pad, Z to H
Enable-to-Pad, L to Z
Enable-to-Pad, H to Z
tENZL
tENZH
tENLZ
tENHZ
Note:
1. Delays based on 35 pF loading, except tENZL and tENZH . For tENZL and tENZH the loading is 5 pF.
2 8
v3 .1
5 4 S X F a m i l y F P G A s
A 5 4 S X 1 6 P T i m i n g C h a r a c t e r i s t i c s
(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V
= 4 . 7 5 V, V
V
= 3 . 0 V, T = 7 0 °C )
C C R
C C A, C C I J
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
Parameter Description
C-Cell Propagation Delays1
Min. Max. Min. Max. Min. Max. Min. Max. Units
tPD
Internal Array Module
0.6
0.7
0.8
0.9
ns
Predicted Routing Delays2
FO=1 Routing Delay, Direct
Connect
tDC
0.1
0.1
0.1
0.1
ns
tFC
FO=1 Routing Delay, Fast Connect
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
FO=12 Routing Delay
0.3
0.3
0.6
0.8
1.0
1.9
2.8
0.4
0.4
0.7
0.9
1.2
2.2
3.2
0.4
0.4
0.8
1.0
1.4
2.5
3.7
0.5
0.5
0.9
1.2
1.6
2.9
4.3
ns
ns
ns
ns
ns
ns
ns
tRD1
tRD2
tRD3
tRD4
tRD8
tRD12
R-Cell Timing
tRCO
Sequential Clock-to-Q
0.9
0.5
0.7
1.1
0.6
0.8
1.3
0.7
0.9
1.4
0.8
1.0
ns
ns
ns
ns
ns
ns
tCLR
Asynchronous Clear-to-Q
Asynchronous Preset-to-Q
Flip-Flop Data Input Set-Up
Flip-Flop Data Input Hold
Asynchronous Pulse Width
tPRESET
tSUD
0.5
0.0
1.4
0.5
0.0
1.6
0.7
0.0
1.8
0.8
0.0
2.1
tHD
tWASYN
Input Module Propagation Delays
tINYH
tINYL
Input Data Pad-to-Y HIGH
Input Data Pad-to-Y LOW
1.5
1.5
1.7
1.7
1.9
1.9
2.2
2.2
ns
ns
Predicted Input Routing Delays2
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
tIRD12
Notes:
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
FO=12 Routing Delay
0.3
0.6
0.8
1.0
1.9
2.8
0.4
0.7
0.9
1.2
2.2
3.2
0.4
0.8
1.0
1.4
2.5
3.7
0.5
0.9
1.2
1.6
2.9
4.3
ns
ns
ns
ns
ns
ns
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
v3 .1
2 9
5 4 S X F a m i l y F P G A s
A 5 4 S X 1 6 P T i m i n g C h a r a c t e r i s t i c s (c o n t in u e d )
(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V
= 4 . 7 5 V, V
V
= 3 . 0 V, T = 7 0 °C )
C C R
C C A, C C I
J
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Units
Dedicated (Hard-Wired) Array Clock Network
tHCKH
Input LOW to HIGH
(Pad to R-Cell Input)
1.2
1.2
1.4
1.4
1.5
1.6
1.8
1.9
ns
ns
tHCKL
Input HIGH to LOW
(Pad to R-Cell Input)
tHPWH
tHPWL
tHCKSW
tHP
Minimum Pulse Width HIGH
Minimum Pulse Width LOW
Maximum Skew
1.4
1.4
1.6
1.6
1.8
1.8
2.1
2.1
ns
ns
0.2
0.2
0.3
0.3
ns
Minimum Period
2.7
3.1
3.6
4.2
ns
fHMAX
Maximum Frequency
350
320
280
240
MHz
Routed Array Clock Networks
Input LOW to HIGH (Light Load)
(Pad to R-Cell Input)
tRCKH
tRCKL
tRCKH
tRCKL
tRCKH
tRCKL
1.6
1.8
1.8
2.0
1.8
2.0
1.8
2.0
2.1
2.2
2.1
2.2
2.1
2.3
2.5
2.5
2.4
2.5
2.5
2.7
2.8
3.0
2.8
3.0
ns
ns
ns
ns
ns
ns
Input HIGH to LOW (Light Load)
(Pad to R-Cell Input)
Input LOW to HIGH (50% Load)
(Pad to R-Cell Input)
Input HIGH to LOW (50% Load)
(Pad to R-Cell Input)
Input LOW to HIGH (100% Load)
(Pad to R-Cell Input)
Input HIGH to LOW (100% Load)
(Pad to R-Cell Input)
tRPWH
Min. Pulse Width HIGH
2.1
2.1
2.4
2.4
2.7
2.7
3.2
3.2
ns
ns
ns
ns
ns
tRPWL
Min. Pulse Width LOW
tRCKSW
tRCKSW
tRCKSW
Maximum Skew (Light Load)
Maximum Skew (50% Load)
Maximum Skew (100% Load)
0.5
0.5
0.5
0.5
0.6
0.6
0.5
0.7
0.7
0.7
0.8
0.8
TTL Output Module Timing
tDLH
Data-to-Pad LOW to HIGH
2.4
2.3
3.0
3.3
2.3
2.8
2.8
2.9
3.4
3.8
2.7
3.2
3.1
3.2
3.9
4.3
3.0
3.7
3.7
3.8
4.6
5.0
3.5
4.3
ns
ns
ns
ns
ns
ns
tDHL
Data-to-Pad HIGH to LOW
Enable-to-Pad, Z to L
Enable-to-Pad, Z to H
Enable-to-Pad, L to Z
Enable-to-Pad, H to Z
tENZL
tENZH
tENLZ
tENHZ
TTL/PCI Output Module Timing
tDLH
Data-to-Pad LOW to HIGH
1.5
1.9
2.3
1.5
2.7
2.9
1.7
2.2
2.6
1.7
3.1
3.3
2.0
2.4
3.0
1.9
3.5
3.7
2.3
2.9
3.5
2.3
4.1
4.4
ns
ns
ns
ns
ns
ns
tDHL
Data-to-Pad HIGH to LOW
Enable-to-Pad, Z to L
Enable-to-Pad, Z to H
Enable-to-Pad, L to Z
Enable-to-Pad, H to Z
tENZL
tENZH
tENLZ
tENHZ
3 0
v3 .1
5 4 S X F a m i l y F P G A s
A 5 4 S X 1 6 P T i m i n g C h a r a c t e r i s t i c s (c o n t in u e d )
(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s V
= 3 . 0 V, V
, V
= 3 . 0 V, T = 7 0 °C )
C C I J
C C R
C C A
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
Parameter Description
PCI Output Module Timing1
Min. Max. Min. Max. Min. Max. Min. Max. Units
tDLH
Data-to-Pad LOW to HIGH
Data-to-Pad HIGH to LOW
Enable-to-Pad, Z to L
Enable-to-Pad, Z to H
Enable-to-Pad, L to Z
Enable-to-Pad, H to Z
1.8
1.7
0.8
1.2
1.0
1.1
2.0
2.0
1.0
1.2
1.1
1.3
2.3
2.2
1.1
1.5
1.3
1.5
2.7
2.6
1.3
1.8
1.5
1.7
ns
ns
ns
ns
ns
ns
tDHL
tENZL
tENZH
tENLZ
tENHZ
TTL Output Module Timing
tDLH
Data-to-Pad LOW to HIGH
2.1
2.0
2.5
3.0
2.3
2.9
2.5
2.3
2.9
3.5
2.7
3.3
2.8
2.6
3.2
3.9
3.1
3.7
3.3
3.1
3.8
4.6
3.6
4.4
ns
ns
ns
ns
ns
ns
tDHL
Data-to-Pad HIGH to LOW
Enable-to-Pad, Z to L
Enable-to-Pad, Z to H
Enable-to-Pad, L to Z
Enable-to-Pad, H to Z
tENZL
tENZH
tENLZ
tENHZ
Note:
1. Delays based on 10 pF loading.
v3 .1
3 1
5 4 S X F a m i l y F P G A s
A 5 4 S X 3 2 T i m i n g C h a r a c t e r i s t i c s
(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V
= 4 . 7 5 V, V
V
= 3 . 0 V, T = 7 0 °C )
C C R
C C A, C C I
J
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
Parameter Description
C-Cell Propagation Delays1
Min. Max. Min. Max. Min. Max. Min. Max. Units
tPD
Internal Array Module
0.6
0.7
0.8
0.9
ns
Predicted Routing Delays2
tDC
FO=1 Routing Delay, Direct Connect
0.1
0.3
0.3
0.7
1.0
1.4
2.7
4.0
0.1
0.4
0.4
0.8
1.2
1.6
3.1
4.7
0.1
0.4
0.4
0.9
1.4
1.8
3.5
5.3
0.1
0.5
0.5
1.0
1.6
2.1
4.1
6.2
ns
ns
ns
ns
ns
ns
ns
ns
tFC
FO=1 Routing Delay, Fast Connect
FO=1 Routing Delay
tRD1
tRD2
FO=2 Routing Delay
tRD3
FO=3 Routing Delay
tRD4
FO=4 Routing Delay
tRD8
FO=8 Routing Delay
tRD12
FO=12 Routing Delay
R-Cell Timing
tRCO
Sequential Clock-to-Q
0.8
0.5
0.7
1.1
0.6
0.8
1.3
0.7
0.9
1.4
0.8
1.0
ns
ns
ns
ns
ns
ns
tCLR
Asynchronous Clear-to-Q
Asynchronous Preset-to-Q
Flip-Flop Data Input Set-Up
Flip-Flop Data Input Hold
Asynchronous Pulse Width
tPRESET
tSUD
0.5
0.0
1.4
0.6
0.0
1.6
0.7
0.0
1.8
0.8
0.0
2.1
tHD
tWASYN
Input Module Propagation Delays
tINYH
tINYL
Input Data Pad-to-Y HIGH
Input Data Pad-to-Y LOW
1.5
1.5
1.7
1.7
1.9
1.9
2.2
2.2
ns
ns
Predicted Input Routing Delays2
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
tIRD12
Notes:
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
FO=12 Routing Delay
0.3
0.7
1.0
1.4
2.7
4.0
0.4
0.8
1.2
1.6
3.1
4.7
0.4
0.9
1.4
1.8
3.5
5.3
0.5
1.0
1.6
2.1
4.1
6.2
ns
ns
ns
ns
ns
ns
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
3 2
v3 .1
5 4 S X F a m i l y F P G A s
A 5 4 S X 3 2 T i m i n g C h a r a c t e r i s t i c s (c o n t in u e d )
(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s )
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Units
Dedicated (Hard-Wired) Array Clock Network
tHCKH
Input LOW to HIGH
(Pad to R-Cell Input)
1.9
1.9
2.1
2.1
2.4
2.4
2.8
2.8
ns
ns
tHCKL
Input HIGH to LOW
(Pad to R-Cell Input)
tHPWH
tHPWL
tHCKSW
tHP
Minimum Pulse Width HIGH
Minimum Pulse Width LOW
Maximum Skew
1.4
1.4
1.6
1.6
1.8
1.8
2.1
2.1
ns
ns
0.3
0.4
0.4
0.5
ns
Minimum Period
2.7
3.1
3.6
4.2
ns
fHMAX
Maximum Frequency
350
320
280
240
MHz
Routed Array Clock Networks
Input LOW to HIGH (Light Load)
(Pad to R-Cell Input)
tRCKH
tRCKL
tRCKH
tRCKL
tRCKH
tRCKL
2.4
2.4
2.7
2.7
2.7
2.8
2.7
2.7
3.0
3.1
3.1
3.2
3.0
3.1
3.5
3.6
3.5
3.6
3.5
3.6
4.1
4.2
4.1
4.3
ns
ns
ns
ns
ns
ns
Input HIGH to LOW (Light Load)
(Pad to R-Cell Input)
Input LOW to HIGH (50% Load)
(Pad to R-Cell Input)
Input HIGH to LOW (50% Load)
(Pad to R-Cell Input)
Input LOW to HIGH (100% Load)
(Pad to R-Cell Input)
Input HIGH to LOW (100% Load)
(Pad to R-Cell Input)
tRPWH
Min. Pulse Width HIGH
2.1
2.1
2.4
2.4
2.7
2.7
3.2
3.2
ns
ns
ns
ns
ns
tRPWL
Min. Pulse Width LOW
tRCKSW
tRCKSW
tRCKSW
Maximum Skew (Light Load)
Maximum Skew (50% Load)
Maximum Skew (100% Load)
0.85
1.23
1.30
0.98
1.4
1.1
1.6
1.7
1.3
1.9
2.0
1.5
TTL Output Module Timing1
tDLH
Data-to-Pad LOW to HIGH
1.6
1.6
2.1
2.3
1.4
1.3
1.9
1.9
2.4
2.7
1.7
1.5
2.1
2.1
2.8
3.1
1.9
1.7
2.5
2.5
3.2
3.6
2.2
2.0
ns
ns
ns
ns
ns
ns
tDHL
Data-to-Pad HIGH to LOW
Enable-to-Pad, Z to L
Enable-to-Pad, Z to H
Enable-to-Pad, L to Z
Enable-to-Pad, H to Z
tENZL
tENZH
tENLZ
tENHZ
Note:
1. Delays based on 35pF loading, except tENZL and tENZH . For tENZL and tENZH the loading is 5pF.
v3 .1
3 3
5 4 S X F a m i l y F P G A s
P i n D e s c r i p t i o n
C LK A/B
C lo c k A a n d B
T C K
Te s t C lo c k
These pins are 3.3V/5.0V PCI/TTL clock inputs for clock
distribution networks. The clock input is buffered prior to
clocking the R-cells. If not used, this pin must be set LOW or
HIGH on the board. It must not be left floating. (For
A54SX72A, these clocks can be configured as bidirectional.)
Test clock input for diagnostic probe and device
programming. In flexible mode, TCK becomes active when
the TMS pin is set LOW (refer to Table 2 on page 8). This pin
functions as an I/O when the boundary scan state machine
reaches the “logic reset” state.
G N D
G r o u n d
T DI
Te s t Da t a In p u t
LOW supply voltage.
Serial input for boundary scan testing and diagnostic probe.
In flexible mode, TDI is active when the TMS pin is set LOW
(refer to Table 2 on page 8). This pin functions as an I/O
when the boundary scan state machine reaches the “logic
reset” state.
H C LK
De d ic a t e d (H a r d -w ir e d )
Ar r a y C lo c k
This pin is the 3.3V/5.0V PCI/TTL clock input for sequential
modules. This input is directly wired to each R-cell and
offers clock speeds independent of the number of R-cells
T DO
Te s t Da t a O u t p u t
being driven. If not used, this pin must be set LOW or HIGH Serial output for boundary scan testing. In flexible mode,
on the board. It must not be left floating.
TDO is active when the TMS pin is set LOW (refer to Table 2
on page 8). This pin functions as an I/O when the boundary
scan state machine reaches the “logic reset” state.
I/O
In p u t /O u t p u t
The I/O pin functions as an input, output, tristate, or
bidirectional buffer. Based on certain configurations, input
and output levels are compatible with standard TTL, LVTTL,
3.3V PCI or 5.0V PCI specifications. Unused I/O pins are
automatically tristated by the Designer Series software.
T MS
Te s t Mo d e S e le c t
The TMS pin controls the use of the IEEE 1149.1 Boundary
Scan pins (TCK, TDI, TDO). In flexible mode when the TMS
pin is set LOW, the TCK, TDI, and TDO pins are boundary
scan pins (refer to Table 2 on page 8). Once the boundary
scan pins are in test mode, they will remain in that mode
until the internal boundary scan state machine reaches the
“logic reset” state. At this point, the boundary scan pins will
be released and will function as regular I/O pins. The “logic
reset” state is reached 5 TCK cycles after the TMS pin is set
HIGH. In dedicated test mode, TMS functions as specified in
the IEEE 1149.1 specifications.
N C
N o C o n n e c t io n
This pin is not connected to circuitry within the device.
P R A, I/O
P r o b e A
The Probe A pin is used to output data from any
user-defined design node within the device. This
independent diagnostic pin can be used in conjunction with
the Probe B pin to allow real-time diagnostic output of any
signal path within the device. The Probe A pin can be used
as a user-defined I/O when verification has been completed.
The pin’s probe capabilities can be permanently disabled to
protect programmed design confidentiality.
V
S u p p ly Vo lt a g e
C C I
Supply voltage for I/Os. See Table 1 on page 8.
V
S u p p ly Vo lt a g e
C C A
Supply voltage for Array. See Table 1 on page 8.
P R B , I/O
P r o b e B
V
S u p p ly Vo lt a g e
The Probe B pin is used to output data from any node within
the device. This diagnostic pin can be used in conjunction
with the Probe A pin to allow real-time diagnostic output of
any signal path within the device. The Probe B pin can be
used as a user-defined I/O when verification has been
completed. The pin’s probe capabilities can be permanently
disabled to protect programmed design confidentiality.
C C R
Supply voltage for input tolerance (required for internal
biasing) See Table 1 on page 8.
3 4
v3 .1
5 4 S X F a m i l y F P G A s
P a c k a g e P i n A s s i g n m e n t s
8 4 -P i n P L C C ( T o p V i e w )
1
84
84-Pin
PLCC
v3 .1
3 5
5 4 S X F a m i l y F P G A s
8 4 -P i n P L C C P a c k a g e
Pin
Number
A54SX08
Function
Pin
Number
A54SX08
Function
1
VCCR
GND
VCCA
PRA, I/O
I/O
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
VCCR
I/O
2
3
HCLK
I/O
4
5
I/O
6
I/O
I/O
7
VCCI
I/O
I/O
8
I/O
9
I/O
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
I/O
TDO, I/O
I/O
TCK, I/O
TDI, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TMS
I/O
I/O
VCCA
VCCI
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
GND
I/O
GND
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PRB, I/O
VCCA
GND
I/O
CLKA
CLKB
3 6
v3 .1
5 4 S X F a m i l y F P G A s
P a c k a g e P i n A s s i g n m e n t s (c o n t in u e d )
2 0 8 -P i n P Q F P ( T o p V i e w )
208
1
208-Pin PQFP
v3 .1
3 7
5 4 S X F a m i l y F P G A s
2 0 8 -P i n P Q F P
A54SX16,
A54SX16P
Function
A54SX16,
A54SX16P
Function
A54SX08
Function
A54SX32
Function
A54SX08
Function
A54SX32
Function
Pin Number
Pin Number
1
2
3
4
5
6
7
8
GND
TDI, I/O
I/O
NC
I/O
NC
I/O
I/O
I/O
GND
TDI, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
TDI, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
54
55
56
57
58
59
60
61
62
63
64
65*
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
V
V
V
CCI
I/O
I/O
CCI
CCI
NC
I/O
I/O
NC
I/O
I/O
NC
I/O
I/O
NC
I/O
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
I/O
TMS
I/O
TMS
I/O
TMS
V
CCI
I/O
I/O
NC*
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
V
V
CCI
CCI
I/O
NC
I/O
I/O
NC
I/O
I/O
NC
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PRB, I/O
GND
PRB, I/O
GND
PRB, I/O
GND
V
V
V
V
V
V
CCA
GND
CCR
CCR
CCR
CCA
CCA
GND
GND
GND
GND
GND
V
V
V
V
V
V
CCR
CCA
CCA
CCA
CCR
CCR
GND
I/O
I/O
NC
I/O
I/O
I/O
NC
I/O
I/O
I/O
NC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
HCLK
I/O
I/O
NC
I/O
I/O
NC
I/O
I/O
HCLK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
HCLK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
V
V
V
I/O
CCI
CCI
CCI
V
V
V
NC
I/O
CCA
CCA
CCA
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
NC
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
NC
V
V
V
CCI
CCI
CCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TDO, I/O
I/O
TDO, I/O
I/O
TDO, I/O
I/O
GND
NC
GND
I/O
GND
I/O
* Please note that Pin 65 in the A54SX32—PQ208 is a no connect (NC).
3 8
v3 .1
5 4 S X F a m i l y F P G A s
2 0 8 -P i n P Q F P ( C o n t i n u e d )
A54SX16,
A54SX16P
Function
A54SX16,
A54SX16P
Function
A54SX08
Function
A54SX32
Function
A54SX08
Function
A54SX32
Function
Pin Number
Pin Number
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
V
V
V
CCI
CCI
CCI
V
V
V
I/O
I/O
I/O
I/O
I/O
I/O
CCA
CCA
CCA
V
V
V
CCI
CCI
CCI
NC
I/O
I/O
NC
I/O
I/O
NC
I/O
I/O
NC
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CLKA
CLKB
CLKA
CLKB
CLKA
CLKB
V
V
V
CCA
CCA
CCA
GND
GND
GND
V
V
V
CCR
CCR
CCR
V
V
V
GND
GND
GND
CCR
CCR
CCR
I/O
I/O
NC
I/O
I/O
NC
I/O
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
V
V
V
CCA
CCA
CCA
GND
PRA, I/O
I/O
GND
PRA, I/O
I/O
GND
PRA, I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
V
V
V
I/O
I/O
I/O
CCA
CCA
CCA
GND
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
NC
I/O
I/O
V
V
V
I/O
I/O
I/O
CCI
CCI
CCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
V
V
V
CCI
CCI
CCI
I/O
I/O
I/O
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
NC
NC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
TCK, I/O
TCK, I/O
TCK, I/O
* Please note that Pin 65 in the A54SX32—PQ208 is a no connect (NC).
v3 .1
3 9
5 4 S X F a m i l y F P G A s
P a c k a g e P i n A s s i g n m e n t s (c o n t in u e d )
1 4 4 -P i n T Q F P ( T o p V i e w )
144
1
144-Pin
TQFP
4 0
v3 .1
5 4 S X F a m i l y F P G A s
1 4 4 -P in T Q F P
A54SX08
Function
A54SX16P
Function
A54SX32
Function
A54SX08
Function
A54SX16P
Function
A54SX32
Function
Pin Number
Pin Number
1
GND
TDI, I/O
I/O
GND
TDI, I/O
I/O
GND
TDI, I/O
I/O
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
I/O
I/O
I/O
I/O
I/O
I/O
2
3
I/O
I/O
I/O
4
I/O
I/O
I/O
VCCI
I/O
VCCI
I/O
VCCI
I/O
5
I/O
I/O
I/O
6
I/O
I/O
I/O
I/O
I/O
I/O
7
I/O
I/O
I/O
I/O
I/O
I/O
8
I/O
I/O
I/O
I/O
I/O
I/O
9
TMS
VCCI
GND
I/O
TMS
VCCI
GND
I/O
TMS
VCCI
GND
I/O
I/O
I/O
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PRB, I/O
I/O
PRB, I/O
I/O
PRB, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
GND
VCCR
I/O
VCCA
GND
VCCR
I/O
VCCA
GND
VCCR
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCR
VCCA
I/O
VCCR
VCCA
I/O
VCCR
VCCA
I/O
HCLK
I/O
HCLK
I/O
HCLK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCCI
VCCA
I/O
GND
VCCI
VCCA
I/O
GND
VCCI
VCCA
I/O
VCCI
I/O
VCCI
I/O
VCCI
I/O
I/O
I/O
I/O
TDO, I/O
I/O
TDO, I/O
I/O
TDO, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
VCCI
VCCA
VCCI
VCCA
VCCI
I/O
I/O
I/O
v3 .1
4 1
5 4 S X F a m i l y F P G A s
1 4 4 -P in T Q F P (C o n t in u e d )
A54SX08
Function
A54SX16P
Function
A54SX32
Function
A54SX08
Function
A54SX16P
Function
A54SX32
Function
Pin Number
Pin Number
81
82
GND
I/O
GND
I/O
GND
I/O
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
I/O
I/O
I/O
I/O
I/O
I/O
83
I/O
I/O
I/O
VCCI
I/O
VCCI
I/O
VCCI
I/O
84
I/O
I/O
I/O
85
I/O
I/O
I/O
I/O
I/O
I/O
86
I/O
I/O
I/O
I/O
I/O
I/O
87
I/O
I/O
I/O
I/O
I/O
I/O
88
I/O
I/O
I/O
I/O
I/O
I/O
89
VCCA
VCCR
I/O
VCCA
VCCR
I/O
VCCA
VCCR
I/O
I/O
I/O
I/O
90
I/O
I/O
I/O
91
I/O
I/O
I/O
92
I/O
I/O
I/O
I/O
I/O
I/O
93
I/O
I/O
I/O
CLKA
CLKB
VCCR
GND
VCCA
I/O
CLKA
CLKB
VCCR
GND
VCCA
I/O
CLKA
CLKB
VCCR
GND
VCCA
I/O
94
I/O
I/O
I/O
95
I/O
I/O
I/O
96
I/O
I/O
I/O
97
I/O
I/O
I/O
98
VCCA
GND
I/O
VCCA
GND
I/O
VCCA
GND
I/O
99
PRA, I/O
I/O
PRA, I/O
I/O
PRA, I/O
I/O
100
101
102
103
104
105
106
107
108
109
110
111
112
113
GND
VCCI
I/O
GND
VCCI
I/O
GND
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
VCCI
I/O
VCCI
I/O
GND
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TCK, I/O
TCK, I/O
TCK, I/O
I/O
I/O
I/O
4 2
v3 .1
5 4 S X F a m i l y F P G A s
P a c k a g e P i n A s s i g n m e n t s (c o n t in u e d )
1 7 6 -P i n T Q F P ( T o p V i e w )
176
1
176-Pin
TQFP
v3 .1
4 3
5 4 S X F a m i l y F P G A s
1 7 6 -P i n T Q F P
A54SX16,
A54SX16P
Function
A54SX16,
A54SX16P
Function
A54SX08
Function
A54SX32
Function
A54SX08
Function
A54SX32
Function
Pin Number
Pin Number
1
GND
TDI, I/O
NC
I/O
GND
TDI, I/O
I/O
GND
TDI, I/O
I/O
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
I/O
I/O
I/O
I/O
I/O
I/O
2
3
I/O
I/O
I/O
4
I/O
I/O
I/O
I/O
I/O
5
I/O
I/O
I/O
I/O
I/O
I/O
6
I/O
I/O
I/O
I/O
I/O
I/O
7
I/O
I/O
I/O
I/O
I/O
I/O
8
I/O
I/O
I/O
VCCI
I/O
VCCI
I/O
VCCI
I/O
9
I/O
I/O
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
TMS
VCCI
NC
I/O
TMS
VCCI
I/O
TMS
VCCI
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PRB, I/O
GND
VCCA
VCCR
I/O
PRB, I/O
GND
VCCA
VCCR
I/O
PRB, I/O
GND
VCCA
VCCR
I/O
GND
VCCA
GND
I/O
GND
VCCA
GND
I/O
GND
VCCA
GND
I/O
I/O
I/O
I/O
HCLK
I/O
HCLK
I/O
HCLK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
VCCA
I/O
VCCI
VCCA
I/O
VCCI
VCCA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
VCCI
I/O
VCCI
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TDO, I/O
I/O
TDO, I/O
I/O
TDO, I/O
I/O
GND
GND
GND
4 4
v3 .1
5 4 S X F a m i l y F P G A s
1 7 6 -P i n T Q F P ( C o n t i n u e d )
A54SX16,
A54SX16P
Function
A54SX16,
A54SX16P
Function
A54SX08
Function
A54SX32
Function
A54SX08
Function
A54SX32
Function
Pin Number
Pin Number
89
90
GND
NC
NC
I/O
GND
I/O
GND
I/O
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
GND
I/O
GND
I/O
GND
I/O
91
I/O
I/O
I/O
I/O
I/O
92
I/O
I/O
I/O
I/O
I/O
93
I/O
I/O
I/O
I/O
I/O
I/O
94
I/O
I/O
I/O
I/O
I/O
I/O
95
I/O
I/O
I/O
I/O
I/O
I/O
96
I/O
I/O
I/O
VCCI
I/O
VCCI
I/O
VCCI
I/O
97
I/O
I/O
I/O
98
VCCA
VCCI
I/O
VCCA
VCCI
I/O
VCCA
VCCI
I/O
I/O
I/O
I/O
99
I/O
I/O
I/O
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCCA
GND
I/O
GND
VCCA
GND
I/O
GND
VCCA
GND
I/O
CLKA
CLKB
VCCR
GND
VCCA
PRA, I/O
I/O
CLKA
CLKB
VCCR
GND
VCCA
PRA, I/O
I/O
CLKA
CLKB
VCCR
GND
VCCA
PRA, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
VCCA
GND
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
GND
VCCI
I/O
VCCA
GND
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
VCCI
I/O
VCCI
I/O
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TCK, I/O
TCK, I/O
TCK, I/O
v3 .1
4 5
5 4 S X F a m i l y F P G A s
P a c k a g e P i n A s s i g n m e n t s (c o n t in u e d )
1 0 0 -P i n V Q F P ( T o p V i e w )
100
1
100-Pin
VQFP
4 6
v3 .1
5 4 S X F a m i l y F P G A s
1 0 0 -V Q F P
A54SX16,
A54SX16P
Function
A54SX16
A54SX16P
Function
A54SX08
Function
A54SX08
Function
Pin Number
Pin Number
1
2
3
4
5
6
7
8
GND
TDI, I/O
I/O
I/O
I/O
GND
TDI, I/O
I/O
I/O
I/O
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
GND
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TMS
VCCI
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PRB, I/O
VCCA
GND
VCCR
I/O
HCLK
I/O
I/O
I/O
I/O
VCCI
I/O
I/O
TMS
VCCI
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PRB, I/O
VCCA
GND
VCCR
I/O
HCLK
I/O
I/O
I/O
I/O
VCCI
I/O
I/O
VCCA
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
I/O
I/O
VCCA
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
I/O
I/O
VCCA
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
I/O
I/O
I/O
I/O
CLKA
CLKB
VCCR
VCCA
GND
PRA, I/O
I/O
CLKA
CLKB
VCCR
VCCA
GND
PRA, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TDO, I/O
I/O
I/O
I/O
TDO, I/O
I/O
TCK, I/O
TCK, I/O
v3 .1
4 7
5 4 S X F a m i l y F P G A s
P a c k a g e P i n A s s i g n m e n t s (c o n t in u e d )
3 1 3 -P in P B G A (T o p Vie w )
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
A
B
C
D
E
F
A
B
C
D
E
F
G
G
H
J
H
J
K
L
K
L
M
N
P
R
M
N
P
R
T
T
U
U
V
V
W
W
Y
Y
AA
AA
AB
AC
AB
AC
AD
AE
AD
AE
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
4 8
v3 .1
5 4 S X F a m i l y F P G A s
3 1 3 -P i n P B G A
A54SX32
Pin Number Function
A54SX32
Pin Number Function
A54SX32
Pin Number Function
A54SX32
Pin Number Function
A1
A3
GND
NC
I/O
I/O
I/O
I/O
VCCR
I/O
I/O
I/O
I/O
NC
GND
I/O
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCR
AC15
AC17
AC19
AC21
AC23
AC25
AD2
AD4
AD6
AD8
AD10
AD12
AD14
AD16
AD18
AD20
AD22
AD24
AE1
AE3
AE5
AE7
AE9
AE11
AE13
AE15
AE17
AE19
AE21
AE23
AE25
B2
I/O
I/O
C5
C7
NC
I/O
I/O
I/O
VCCI
I/O
I/O
VCCI
I/O
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
VCCA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
NC
I/O
I/O
NC
I/O
F20
F22
F24
G1
I/O
I/O
A5
I/O
C9
I/O
A7
I/O
C11
C13
C15
C17
C19
C21
C23
C25
D2
I/O
A9
I/O
G3
TMS
I/O
A11
NC
G5
A13
GND
I/O
G7
I/O
A15
G9
VCCI
I/O
A17
VCCI
I/O
G11
G13
G15
G17
G19
G21
G23
G25
H2
A19
CLKB
I/O
A21
I/O
A23
PRB, I/O
I/O
I/O
A25
D4
I/O
AA1
AA3
AA5
AA7
AA9
AA11
AA13
AA15
AA17
AA19
AA21
AA23
AA25
AB2
AB4
AB6
AB8
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AB24
AC1
AC3
AC5
AC7
AC9
AC11
AC13
I/O
D6
I/O
I/O
D8
I/O
I/O
D10
D12
D14
D16
D18
D20
D22
D24
E1
I/O
NC
I/O
I/O
H4
I/O
NC
H6
I/O
I/O
H8
I/O
I/O
H10
H12
H14
H16
H18
H20
H22
H24
J1
I/O
I/O
PRA, I/O
I/O
I/O
I/O
I/O
VCCA
I/O
E3
NC
I/O
E5
I/O
E7
VCCI
I/O
I/O
E9
I/O
E11
E13
E15
E17
E19
E21
E23
E25
F2
I/O
TDO, I/O
GND
TCK, I/O
I/O
J3
I/O
J5
I/O
J7
NC
I/O
B4
J9
B6
I/O
J11
J13
J15
J17
J19
J21
J23
J25
K2
I/O
B8
I/O
CLKA
I/O
B10
I/O
B12
I/O
I/O
B14
I/O
F4
I/O
B16
I/O
F6
GND
I/O
B18
I/O
F8
B20
I/O
F10
F12
F14
F16
F18
I/O
B22
I/O
I/O
B24
I/O
K4
I/O
C1
TDI, I/O
I/O
K6
I/O
C3
K8
VCCI
v3 .1
4 9
5 4 S X F a m i l y F P G A s
3 1 3 -P i n P B G A ( C o n t i n u e d )
A54SX32
Pin Number Function
A54SX32
Pin Number Function
A54SX32
Pin Number Function
A54SX32
Pin Number Function
K10
K12
K14
K16
K18
K20
K22
K24
L1
I/O
I/O
N3
N5
VCCA
VCCR
I/O
R21
R23
R25
T2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
HCLK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
I/O
I/O
I/O
I/O
I/O
I/O
NC
V18
V20
V22
V24
W1
I/O
I/O
VCCA
VCCI
I/O
I/O
I/O
NC
I/O
I/O
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
NC
I/O
N7
I/O
N9
VCCI
GND
GND
GND
I/O
I/O
N11
N13
N15
N17
N19
N21
N23
N25
P2
T4
VCCA
I/O
T6
W3
T8
W5
I/O
T10
T12
T14
T16
T18
T20
T22
T24
U1
W7
I/O
I/O
W9
L3
I/O
I/O
W11
W13
W15
W17
W19
W21
W23
W25
Y2
L5
I/O
VCCR
VCCA
I/O
L7
I/O
L9
I/O
L11
L13
L15
L17
L19
L21
L23
L25
M2
I/O
P4
I/O
GND
I/O
P6
I/O
P8
I/O
I/O
P10
P12
P14
P16
P18
P20
P22
P24
R1
I/O
U3
I/O
GND
GND
I/O
U5
I/O
U7
Y4
I/O
U9
Y6
I/O
I/O
U15
U17
U19
U21
U23
U25
V2
Y8
I/O
NC
Y10
Y12
Y14
Y16
Y18
Y20
Y22
Y24
M4
I/O
I/O
M6
I/O
I/O
M8
I/O
I/O
M10
M12
M14
M16
M18
M20
M22
M24
N1
I/O
R3
I/O
GND
GND
VCCI
I/O
R5
I/O
R7
I/O
V4
R9
I/O
V6
R11
R13
R15
R17
R19
I/O
V8
I/O
GND
I/O
V10
V12
V14
V16
I/O
I/O
I/O
I/O
I/O
5 0
v3 .1
5 4 S X F a m i l y F P G A s
P a c k a g e P i n A s s i g n m e n t s (c o n t in u e d )
3 2 9 -P in P B G A (T o p Vie w )
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
v3 .1
5 1
5 4 S X F a m i l y F P G A s
3 2 9 -P i n P B G A
A54SX32
A54SX32
Pin Number Function
A54SX32
Pin Number Function
A54SX32
Pin Number Function
Pin Number Function
A1
A2
GND
GND
VCCI
NC
AA23
AB1
VCCI
I/O
AC22
AC23
B1
VCCI
GND
VCCI
GND
I/O
C21
C22
C23
D1
VCCI
GND
NC
I/O
A3
AB2
GND
I/O
A4
AB3
B2
A5
I/O
AB4
I/O
B3
D2
I/O
A6
I/O
AB5
I/O
B4
I/O
D3
I/O
A7
VCCI
NC
AB6
I/O
B5
I/O
D4
TCK, I/O
I/O
A8
AB7
I/O
B6
I/O
D5
A9
I/O
AB8
I/O
B7
I/O
D6
I/O
A10
A11
I/O
AB9
I/O
B8
I/O
D7
I/O
I/O
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AC1
I/O
B9
I/O
D8
I/O
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
I/O
PRB, I/O
I/O
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
C1
I/O
D9
I/O
CLKB
I/O
I/O
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
E1
I/O
HCLK
I/O
PRA, I/O
CLKA
I/O
VCCA
VCCR
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
VCCI
GND
VCCI
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
GND
VCCI
NC
I/O
GND
VCCI
NC
I/O
I/O
GND
I/O
AC2
I/O
AC3
C2
TDI, I/O
GND
I/O
VCCI
I/O
I/O
AC4
C3
E2
I/O
AC5
I/O
C4
E3
I/O
I/O
AC6
I/O
C5
I/O
E4
I/O
I/O
AC7
I/O
C6
I/O
E20
E21
E22
E23
F1
I/O
I/O
AC8
I/O
C7
I/O
I/O
I/O
AC9
VCCI
I/O
C8
I/O
I/O
I/O
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
C9
I/O
I/O
I/O
I/O
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
I/O
I/O
I/O
I/O
I/O
F2
TMS
I/O
I/O
I/O
I/O
F3
I/O
I/O
I/O
F4
I/O
I/O
NC
I/O
I/O
F20
F21
F22
F23
G1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TDO, I/O
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
G2
I/O
NC
I/O
G3
I/O
5 2
v3 .1
5 4 S X F a m i l y F P G A s
3 2 9 -P i n P B G A
A54SX32
Pin Number Function
A54SX32
Pin Number Function
A54SX32
Pin Number Function
A54SX32
Pin Number Function
G4
G20
G21
G22
G23
H1
I/O
I/O
L22
L23
M1
I/O
NC
R20
R21
R22
R23
T1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
I/O
I/O
VCCA
I/O
I/O
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
I/O
I/O
I/O
I/O
VCCA
VCCR
I/O
I/O
M2
I/O
GND
I/O
M3
I/O
M4
VCCA
GND
GND
GND
GND
GND
VCCA
I/O
T2
I/O
H2
I/O
M10
M11
M12
M13
M14
M20
M21
M22
M23
N1
T3
I/O
H3
I/O
T4
I/O
H4
I/O
T20
T21
T22
T23
U1
I/O
H20
H21
H22
H23
J1
VCCA
I/O
I/O
GND
I/O
I/O
I/O
I/O
NC
I/O
U2
I/O
J2
I/O
VCCI
I/O
U3
J3
I/O
U4
J4
I/O
N2
I/O
U20
U21
U22
U23
V1
J20
J21
J22
J23
K1
I/O
N3
I/O
I/O
N4
I/O
I/O
N10
N11
N12
N13
N14
N20
N21
N22
N23
P1
GND
GND
GND
GND
GND
NC
I/O
I/O
V2
K2
I/O
V3
K3
I/O
V4
K4
I/O
V20
V21
V22
V23
W1
W2
W3
W4
W20
W21
W22
W23
Y1
K10
K11
K12
K13
K14
K20
K21
K22
K23
L1
GND
GND
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
P2
I/O
P3
I/O
I/O
P4
I/O
I/O
P10
P11
P12
P13
P14
P20
P21
P22
P23
R1
GND
GND
GND
GND
GND
I/O
I/O
I/O
L2
I/O
L3
I/O
L4
VCCR
GND
GND
GND
GND
GND
VCCR
I/O
Y2
L10
L11
L12
L13
L14
L20
L21
I/O
Y3
I/O
Y4
I/O
Y5
I/O
Y6
R2
I/O
Y7
R3
I/O
Y8
R4
I/O
Y9
v3 .1
5 3
5 4 S X F a m i l y F P G A s
P a c k a g e P i n A s s i g n m e n t s (C o n t in u e d )
1 4 4 -P in F B G A (To p Vie w )
4
1
2
3
5
6
7
8
10 11 12
9
A
B
C
D
E
F
G
H
J
K
L
M
5 4
v3 .1
5 4 S X F a m i l y F P G A s
1 4 4 -P i n F B G A
A54SX08
Function
A54SX08
Function
A54SX08
Function
Pin Number
Pin Number
Pin Number
A1
A2
I/O
I/O
E1
E2
I/O
I/O
J1
J2
I/O
I/O
A3
I/O
E3
I/O
J3
I/O
A4
I/O
E4
I/O
J4
I/O
A5
VCCA
GND
CLKA
I/O
E5
TMS
VCCI
VCCI
VCCI
VCCA
I/O
J5
I/O
A6
E6
J6
PRB, I/O
I/O
A7
E7
J7
A8
E8
J8
I/O
A9
I/O
E9
J9
I/O
A10
A11
A12
B1
I/O
E10
E11
E12
F1
J10
J11
J12
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
K12
L1
I/O
I/O
GND
I/O
I/O
I/O
VCCA
I/O
I/O
I/O
B2
GND
I/O
F2
I/O
I/O
B3
F3
VCCR
I/O
I/O
B4
I/O
F4
I/O
B5
I/O
F5
GND
GND
GND
VCCI
I/O
I/O
B6
I/O
F6
I/O
B7
CLKB
I/O
F7
GND
I/O
B8
F8
B9
I/O
F9
I/O
B10
B11
B12
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
I/O
F10
F11
F12
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
GND
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
GND
I/O
L2
TCK, I/O
I/O
L3
I/O
I/O
L4
I/O
I/O
GND
GND
GND
VCCI
I/O
L5
I/O
PRA, I/O
I/O
L6
I/O
L7
HCLK
I/O
I/O
L8
I/O
L9
I/O
I/O
I/O
L10
L11
L12
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
TDI, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
VCCA
VCCI
VCCI
VCCA
I/O
I/O
I/O
I/O
I/O
VCCA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TDO, I/O
I/O
I/O
VCCR
v3 .1
5 5
5 4 S X F a m i l y F P G A s
L i s t o f C h a n g e s
The following table lists critical changes that were made in the current version of the document.
Previous version
Changes in current version (v3.1)
Page
The storage temperature in the “Absolute Maximum Ratings1” table on page 10 was
updated.
page 10
page 8
v3.0.1
Table 1 on page 8 was updated.
D a t a s h e e t C a t e g o r i e s
In order to provide the latest information to designers, some datasheets are published before data has been fully
characterized. Datasheets are designated as “Product Brief,” “Advanced,” “Production.” The definition of these categories
are as follows:
P r o d u c t B r i e f
The product brief is a modified version of an advanced datasheet containing general product information. This brief
summarizes specific device and family information for unreleased products.
A d v a n c e d
This datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades.
This information can be used as estimates but not for production.
U n m a r k e d ( p r o d u c t i o n )
This datasheet version contains information that is considered to be final.
5 6
v3 .1
Actel and the Actel logo are registered trademarks of Actel Corporation.
All other trademarks are the property of their owners.
http://www.actel.com
Actel Corporation
955 East Arques Avenue
Sunnyvale, California 94086
USA
Actel Europe Ltd.
Actel Japan
Actel Hong Kong
39th Floor
One Pacific Place
88 Queensway
Dunlop House, Riverside Way
Camberley, Surrey GU15 3YL
United Kingdom
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Tel: (408) 739-1010
Fax: (408) 739-1540
Tel: +44 (0)1276 401450
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Tel: +81 03-3445-7671
Fax: +81 03-3445-7668
Admiralty, Hong Kong
Tel: 852-22735712
572137-4/6.03
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A54SX08-TQG176
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