93AA56T-/SN [ETC]
Microwire Serial EEPROM ; Microwire串行EEPROM\n型号: | 93AA56T-/SN |
厂家: | ETC |
描述: | Microwire Serial EEPROM
|
文件: | 总12页 (文件大小:140K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
93AA46/56/66
®
1K/2K/4K 1.8V Microwire Serial EEPROM
FEATURES
PACKAGE TYPES
DIP
• Single supply with programming operation down
to 1.8V
CS
CLK
DI
1
2
3
4
8
7
6
5
VCC
NU
• Low power CMOS technology
- 70 µA typical active READ current at 1.8V
- 2 µA typical standby current at 1.8V
• ORG pin selectable memory configuration
- 128 x 8- or 64 x 16-bit organization (93AA46)
ORG
VSS
DO
- 256 x 8- or 128 x 16-bit organization
(93AA56)
SOIC
- 512 x 8 or 256 x 16 bit organization (93AA66)
1
2
3
4
8
7
6
5
VCC
NU
CS
• Self-timed ERASE and WRITE cycles
(including auto-erase)
CLK
• Automatic ERAL before WRAL
• Power on/off data protection circuitry
• Industry standard 3-wire serial I/O
ORG
VSS
DI
• Device status signal during ERASE/WRITE
cycles
DO
• Sequential READ function
• 1,000,000 E/W cycles guaranteed
• Data retention > 200 years
SOIC
1
2
3
4
8
7
6
5
ORG
Vss
DO
DI
NU
Vcc
CS
• 8-pin PDIP/SOIC
(SOIC in JEDEC and EIAJ standards)
• Temperature ranges supported
- Commercial (C):
- Industrial (I):
0°C to +70°C
CLK
-40°C to +85°C
DESCRIPTION
BLOCK DIAGRAM
The Microchip Technology Inc. 93AA46/56/66 are 1K,
2K and 4K low voltage serial Electrically Erasable
PROMs.The device memory is configured as x8 or x16
bits depending on the ORG pin setup. Advanced
CMOS technology makes these devices ideal for low
power non-volatile memory applications. The 93AA
Series is available in standard 8-pin DIP and surface
mount SOIC packages. The rotated pin-out 93AA46X/
56X/66X are offered in the “SN” package only.
VCC
VSS
ADDRESS
DECODER
MEMORY
ARRAY
ADDRESS
COUNTER
OUTPUT
BUFFER
DATA REGISTER
DO
DI
MODE
DECODE
LOGIC
ORG
CS
CLOCK
GENERATOR
CLK
Microwire is a registered trademark of National Semiconductor Incorporated.
1998 Microchip Technology Inc.
DS20067H-page 1
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93AA46/56/66
TABLE 1-1:
Name
PIN FUNCTION TABLE
Function
1.0
ELECTRICAL CHARACTERISTICS
1.1
Maximum Ratings
CS
CLK
DI
Chip Select
VCC ............................................................................ 7.0V
All inputs and outputs w.r.t. VSS .......... -0.6V to VCC +1.0V
Storage temperature................................-65˚C to +150˚C
Ambient temp. with power applied ...........-65˚C to +125˚C
Soldering temperature of leads (10 seconds)........+300˚C
ESD protection on all pins ......................................... 4 kV
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
DO
VSS
ORG
NU
Memory Configuration
Not Utilized
*Notice: Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
VCC
Power Supply
TABLE 1-2:
DC AND AC ELECTRICAL CHARACTERISTICS
VCC = +1.8V to +5.5V Commercial (C): Tamb = 0˚C to +70˚C
Industrial (I): Tamb = -40°C to +85°C
Parameter
Symbol
Min
Typ
Max
Units
Conditions
High level input voltage
Low level input voltage
Low level output voltage
High level output voltage
VIH1
VIH2
VIL1
2.0
0.7 VCC
-0.3
-0.3
—
—
2.4
VCC-0.2
-10
-10
—
—
—
—
—
—
—
—
—
—
—
VCC+1
VCC+1
0.8
0.2 VCC
0.4
0.2
—
—
10
V
V
V
V
V
V
V
V
VCC ≥ 2.7V
VCC < 2.7V
VCC ≥ 2.7V
VCC < 2.7V
IOL = 2.1 mA; VCC = 4.5V
IOL = 100µA; VCC = 1.8V
IOH = -400 µA; VCC = 4.5V
IOH = -100 µA; VCC = 1.8V
VIN = 0.1V to VCC
VIL2
VOL1
VOL2
VOH1
VOH2
ILI
Input leakage current
Output leakage current
Pin capacitance
(all inputs/outputs)
Operating current
µA
µA
pF
ILO
CIN, COUT
10
7
VOUT = 0.1V to VCC
—
VIN/VOUT = 0V (Note 1 & 2)
Tamb = +25˚C, FCLK = 1 MHz
FCLK=2 MHz; VCC=5.5V (Note 2)
FCLK = 2 MHz; VCC = 5.5V
FCLK = 1 MHz; VCC = 3.0V
FCLK = 1 MHz; VCC = 1.8V
CLK = CS = 0V; VCC = 5.5V
CLK = CS = 0V; VCC = 3.0V
CLK = CS = 0V; VCC = 1.8V
ORG, DI = VSS or VCC
VCC ≥ 4.5V
ICC write
ICC read
—
—
—
—
3
1
500
mA
mA
µA
µA
µA
µA
µA
70
2
Standby current
Clock frequency
ICCS
100
30
FCLK
2
1
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ms
—
VCC < 4.5V
Clock high time
Clock low time
TCKH
TCKL
TCSS
TCSH
TCSL
TDIS
TDIH
TPD
TCZ
TSV
TWC
TEC
TWL
—
250
250
50
Chip select setup time
Chip select hold time
Chip select low time
Data input setup time
Data input hold time
Data output delay time
Data output disable time
Status valid time
Relative to CLK
Relative to CLK
0
250
100
100
Relative to CLK
Relative to CLK
CL = 100 pF
CL = 100 pF (Note 2)
CL = 100 pF
ERASE/WRITE mode
ERAL mode (Vcc = 5V ± 10%)
WRAL mode (Vcc = 5V ± 10%)
25°C, Vcc = 5.0V, Block Mode
(Note 3)
400
100
500
10
15
30
Program cycle time
4
8
16
—
Endurance
1M
1M
Note 1: This parameter is tested at Tamb = 25°C and FCLK = 1 MHz.
2: This parameter is periodically sampled and not 100% tested.
3: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific
application, please consult the Total Endurance Model which can be obtained on our website.
DS20067H-page 2
1998 Microchip Technology Inc.
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93AA46/56/66
TABLE 1-3:
INSTRUCTION SET FOR 93AA46: ORG = 1 (X 16 ORGANIZATION)
Instruction
SB
Opcode
Address
Data In
Data Out
Req. CLK Cycles
READ
EWEN
ERASE
ERAL
1
1
1
1
1
1
1
10
00
11
00
01
00
00
A5 A4 A3 A2 A1 A0
—
—
D15 - D0
High-Z
25
9
1
1 X X X X
A5 A4 A3 A2 A1 A0
—
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
High-Z
9
1
0
X
X
X
X
—
9
WRITE
WRAL
EWDS
A5 A4 A3 A2 A1 A0
D15 - D0
D15 - D0
—
25
25
9
0
0
1
0
X
X
X
X
X
X
X
X
TABLE 1-4:
INSTRUCTION SET FOR 93AA46: ORG = 0 (X 8 ORGANIZATION)
Instruction
SB
Opcode
Address
Data In
Data Out
Req. CLK Cycles
READ
EWEN
ERASE
ERAL
1
1
1
1
1
1
1
10
00
11
00
01
00
00
A6 A5 A4 A3 A2 A1 A0
—
—
D7 - D0
High-Z
18
10
10
10
18
18
10
1
1 X X X X X
A6 A5 A4 A3 A2 A1 A0
—
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
High-Z
1
0
X
X
X
X
X
—
WRITE
WRAL
EWDS
A6 A5 A4 A3 A2 A1 A0
D7 - D0
D7 - D0
—
0
0
1
0
X
X
X
X
X
X
X
X
X
X
TABLE 1-5:
INSTRUCTION SET FOR 93AA56: ORG = 1 (X 16 ORGANIZATION)
Instruction
SB
Opcode
Address
Data In
Data Out
Req. CLK Cycles
READ
EWEN
ERASE
ERAL
1
1
1
1
1
1
1
10
00
11
00
01
00
00
X A6 A5 A4 A3 A2 A1 A0
—
—
D15 - D0
High-Z
27
11
11
11
27
27
11
1
1 X X X X X X
X A6 A5 A4 A3 A2 A1 A0
—
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
High-Z
1
0
X
X
X
X
X
X
—
WRITE
WRAL
EWDS
X A6 A5 A4 A3 A2 A1 A0
D15 - D0
D15 - D0
—
0
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
TABLE 1-6:
INSTRUCTION SET FOR 93AA56: ORG = 0 (X 8 ORGANIZATION)
Instruction
SB
Opcode
Address
Data In
Data Out
Req. CLK Cycles
READ
EWEN
ERASE
ERAL
1
1
1
1
1
1
1
10
00
11
00
01
00
00
X A7 A6 A5 A4 A3 A2 A1 A0
—
—
D7 - D0
High-Z
20
12
12
12
20
20
12
1
1 X X X X X X X
X A7 A6 A5 A4 A3 A2 A1 A0
—
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
High-Z
1
0
X
X
X
X
X
X
X
—
WRITE
WRAL
EWDS
X A7 A6 A5 A4 A3 A2 A1 A0
D7 - D0
D7 - D0
—
0
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
TABLE 1-7:
INSTRUCTION SET FOR 93AA66: ORG = 1 (X 16 ORGANIZATION)
Instruction
SB
Opcode
Address
Data In
Data Out
Req. CLK Cycles
READ
EWEN
ERASE
ERAL
1
1
1
1
1
1
1
10
00
11
00
01
00
00
A7 A6 A5 A4 A3 A2 A1 A0
—
—
D15 - D0
High-Z
27
11
11
11
27
27
11
1
1 X X X X X X
A7 A6 A5 A4 A3 A2 A1 A0
—
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
High-Z
1
0
X
X
X
X
X
X
—
WRITE
WRAL
EWDS
A7 A6 A5 A4 A3 A2 A1 A0
D15 - D0
D15 - D0
—
0
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
TABLE 1-8:
INSTRUCTION SET FOR 93AA66: ORG = 0 (X 8 ORGANIZATION)
Instruction
SB
Opcode
Address
Data In
Data Out
Req. CLK Cycles
READ
EWEN
ERASE
ERAL
1
1
1
1
1
1
1
10
00
11
00
01
00
00
A8 A7 A6 A5 A4 A3 A2 A1 A0
—
—
D7 - D0
High-Z
20
12
12
12
20
20
12
1
1 X X X X X X X
A8 A7 A6 A5 A4 A3 A2 A1 A0
—
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
High-Z
1
0
X
X
X
X
X
X
X
—
WRITE
WRAL
EWDS
A8 A7 A6 A5 A4 A3 A2 A1 A0
D7 - D0
D7 - D0
—
0
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1998 Microchip Technology Inc.
DS20067H-page 3
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93AA46/56/66
2.4
READ
2.0
FUNCTIONAL DESCRIPTION
When the ORG pin is connected to VCC, the (x16) orga-
nization is selected. When it is connected to ground,
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
zero bit precedes the 16 bit (x16 organization) or 8 bit
(x8 organization) output string. The output data bits will
toggle on the rising edge of the CLK and are stable
after the specified time delay (TPD). Sequential read is
possible when CS is held high. The memory data will
automatically cycle to the next register and output
sequentially.
the (x8) organization is selected.
Instructions,
addresses and write data are clocked into the DI pin on
the rising edge of the clock (CLK). The DO pin is nor-
mally held in a high-Z state except when reading data
from the device, or when checking the READY/BUSY
status during a programming operation. The ready/
busy status can be verified during an Erase/Write oper-
ation by polling the DO pin; DO low indicates that pro-
gramming is still in progress, while DO high indicates
the device is ready. The DO will enter the high-Z state
on the falling edge of the CS.
2.5
Erase/Write Enable and Disable
(EWEN,EWDS)
The 93AA46/56/66 power up in the Erase/Write Dis-
able (EWDS) state. All programming modes must be
preceded by an Erase/Write Enable (EWEN) instruc-
tion. Once the EWEN instruction is executed, program-
ming remains enabled until an EWDS instruction is
executed or VCC is removed from the device. To pro-
tect against accidental data disturb, the EWDS instruc-
tion can be used to disable all Erase/Write functions
and should follow all programming operations. Execu-
tion of a READ instruction is independent of both the
EWEN and EWDS instructions.
2.1
START Condition
The START bit is detected by the device if CS and DI
are both HIGH with respect to the positive edge of CLK
for the first time.
Before a START condition is detected, CS, CLK, and
DI may change in any combination (except to that of a
START condition), without resulting in any device oper-
ation (READ, WRITE, ERASE, EWEN, EWDS, ERAL,
and WRAL). As soon as CS is HIGH, the device is no
longer in the standby mode.
2.6
ERASE
An instruction following a START condition will only be
executed if the required amount of opcode, address
and data bits for any particular instruction is clocked in.
The ERASE instruction forces all data bits of the spec-
ified address to the logical “1” state. CS is brought low
following the loading of the last address bit. This falling
edge of the CS pin initiates the self-timed programming
cycle.
After execution of an instruction (i.e., clock in or out of
the last required address or data bit) CLK and DI
become don't care bits until a new start condition is
detected.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL). DO at logical “0” indicates that program-
ming is still in progress. DO at logical “1” indicates that
the register at the specified address has been erased
and the device is ready for another instruction.
2.2
DI/DO
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero”
that precedes the READ operation, if A0 is a logic
HIGH level. Under such a condition the voltage level
seen at Data Out is undefined and will depend upon the
relative impedances of Data Out and the signal source
driving A0. The higher the current sourcing capability
of A0, the higher the voltage at the Data Out pin.
The ERASE cycle takes 4 ms per word typical.
2.7
WRITE
The WRITE instruction is followed by 16 bits (or by 8
bits) of data which are written into the specified
address. After the last data bit is put on the DI pin, CS
must be brought low before the next rising edge of the
CLK clock. This falling edge of CS initiates the self-
timed auto-erase and programming cycle.
2.3
Data Protection
During power-up, all programming modes of operation
are inhibited until VCC has reached a level greater than
1.4V. During power-down, the source data protection
circuitry acts to inhibit all programming modes when
VCC has fallen below 1.4V at nominal conditions.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL) and before the entire write cycle is com-
plete. DO at logical “0” indicates that programming is
still in progress. DO at logical “1” indicates that the reg-
ister at the specified address has been written with the
data specified and the device is ready for another
instruction.
The EWEN and EWDS commands give additional pro-
tection against accidentally programming during nor-
mal operation.
After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
performed before any ERASE or WRITE instruction
can be executed.
The WRITE cycle takes 4 ms per word typical.
DS20067H-page 4
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The ERAL cycle takes (8 ms typical).
2.8
Erase All (ERAL)
2.9
Write All (WRAL)
The ERAL instruction will erase the entire memory
array to the logical “1” state. The ERAL cycle is identi-
cal to the ERASE cycle except for the different opcode.
The ERAL cycle is completely self-timed and com-
mences at the falling edge of the CS. Clocking of the
CLK pin is not necessary after the device has entered
the self clocking mode. The ERAL instruction is guar-
anteed at 5V ± 10%.
The WRAL instruction will write the entire memory
array with the data specified in the command. The
WRAL cycle is completely self-timed and commences
at the falling edge of the CS. Clocking of the CLK pin
is not necessary after the device has entered the self
clocking mode. The WRAL command does include an
automatic ERAL cycle for the device. Therefore, the
WRAL instruction does not require an ERAL instruction
but the chip must be in the EWEN status. The WRAL
instruction is guaranteed at 5V ± 10%.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL) and before the entire write cycle is com-
plete.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL).
The WRAL cycle takes 16 ms typical.
FIGURE 2-1: SYNCHRONOUS DATA TIMING
VIH
CS
TCSS
TCKH
TCKL
VIL
TCSH
VIH
CLK
DI
VIL
TDIH
TDIS
VIH
VIL
TCZ
TPD
TPD
VOH
DO
(READ)
TCZ
VOL
VOH
TSV
DO
(PROGRAM)
STATUS VALID
VOL
FIGURE 2-2: READ TIMING
TCSL
CS
CLK
DI
1
1
0
• A
• • •
A0
n
TRI-
DO
0
Dx
• • •
D0
Dx*
• • •
D0
Dx*
• • •
D0
Tri-State is a registered trademark of National Semiconductor Incorporated.
1998 Microchip Technology Inc.
DS20067H-page 5
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FIGURE 2-3: EWEN TIMING
T
CSL
CS
CLK
DI
• • •
1
0
0
1
1
X
X
FIGURE 2-4: EWDS TIMING
TCSL
CS
CLK
DI
• • •
1
0
0
0
0
X
X
FIGURE 2-5: WRITE TIMING
TCSL
CS
CLK
• • •
• • •
1
0
1
•A
A0
Dx
D0
DI
n
TRI-STATE
BUSY
DO
READY
TWC
DS20067H-page 6
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FIGURE 2-6: WRAL TIMING
TCSL
CS
STANDBY
CLK
1
0
0
0
1
X
• • •
X
Dx
• • •
D0
DI
TRI-STATE
BUSY
READY
TRI-STATE
DO
TWL
Guaranteed at Vcc = +4.5V to +6.0V.
FIGURE 2-7: ERASE TIMING
TCSL
CS
STANDBY
CHECK STATUS
CLK
1
1
1
An An-1 An-2 • • •
A0
DI
TCZ
TSV
BUSY
TRI-STATE
TRI-STATE
READY
DO
TWC
FIGURE 2-8: ERAL TIMING
TCSL
CS
STANDBY
CHECK STATUS
CLK
1
0
0
1
0
DI
TCZ
TSV
TRI-STATE
TRI-STATE
READY
BUSY
DO
TEC
• Guaranteed at VCC = 5.0V ±10%.
1998 Microchip Technology Inc.
DS20067H-page 7
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3.4
Data Out (DO)
3.0
PIN DESCRIPTION
Data Out is used in the READ mode to output data syn-
chronously with the CLK input (TPD after the positive
edge of CLK).
3.1
Chip Select (CS)
A HIGH level selects the device. A LOW level deselects
the device and forces it into standby mode. However, a
programming cycle which is already initiated and/or in
progress will be completed, regardless of the CS input
signal. If CS is brought LOW during a program cycle,
the device will go into standby mode as soon as the
programming cycle is completed.
This pin also provides READY/BUSY status informa-
tion during ERASE and WRITE cycles. READY/BUSY
status information is available on the DO pin if CS is
brought HIGH after being LOW for minimum chip select
LOW time (TCSL) and an ERASE or WRITE operation
has been initiated.
CS must be LOW for 250 ns minimum (TCSL) between
consecutive instructions. If CS is LOW, the internal
control logic is held in a RESET status.
The status signal is not available on DO, if CS is held
LOW or HIGH during the entire WRITE or ERASE
cycle. In all other cases DO is in the HIGH-Z mode. If
status is checked after the WRITE/ERASE cycle, a pull-
up resistor on DO is required to read the READY signal.
3.2
Serial Clock (CLK)
The Serial Clock is used to synchronize the communi-
cation between a master device and the 93AAXX.
Opcode, address, and data bits are clocked in on the
positive edge of CLK. Data bits are also clocked out on
the positive edge of CLK.
3.5
Organization (ORG)
When ORG is connected to VCC, the (x16) memory
organization is selected. When ORG is tied to VSS, the
(x8) memory organization is selected. ORG can only
be floated for clock speeds of 1MHz or less for the (x16)
memory organization. For clock speeds greater than 1
MHz, ORG must be tied to VCC or VSS.
CLK can be stopped anywhere in the transmission
sequence (at HIGH or LOW level) and can be contin-
ued anytime with respect to clock HIGH time (TCKH)
and clock LOW time (TCKL). This gives the controlling
master freedom in preparing opcode, address, and
data.
CLK is a “Don't Care” if CS is LOW (device deselected).
If CS is HIGH, but START condition has not been
detected, any number of clock cycles can be received
by the device without changing its status (i.e., waiting
for START condition).
CLK cycles are not required during the self-timed
WRITE (i.e., auto ERASE/WRITE) cycle.
After detection of a start condition the specified number
of clock cycles (respectively LOW to HIGH transitions
of CLK) must be provided. These clock cycles are
required to clock in all required opcode, address, and
data bits before an instruction is executed (see instruc-
tion set truth table). CLK and DI then become don't care
inputs waiting for a new start condition to be detected.
Note: CS must go LOW between consecutive
instructions.
3.3
Data In (DI)
Data In is used to clock in a START bit, opcode,
address, and data synchronously with the CLK input.
DS20067H-page 8
1998 Microchip Technology Inc.
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93AA46/56/66
NOTES:
1998 Microchip Technology Inc.
DS20067H-page 9
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93AA46/56/66
NOTES:
DS20067H-page 10
1998 Microchip Technology Inc.
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93AA46/56/66
93AA46/56/66 Product Identification System
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.
93AA46/56/66
-
/P
P = Plastic DIP (300 mil Body), 8-lead
SN = Plastic SOIC (150 mil Body), 8-lead
SM = Plastic SOIC (207 mil Body), 8-lead
(93AA46/56/66)
Package:
Temperature
Range:
Blank = 0°C to +70°C
93AA46/56/66
Microwire Serial EEPROM
93AA46/56/66X
Microwire Serial EEPROM in alternate
pinouts (SN package only)
Device
93AA46T/56T/66T
93AA46XT/56XT/66XT
Microwire Serial EEPROM (Tape and Reel)
Microwire Serial EEPROM (Tape and Reel)
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277
3. The Microchip Worldwide Web Site (www.microchip.com)
1998 Microchip Technology Inc.
DS20067H-page 11
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WORLDWIDE SALES AND SERVICE
AMERICAS
AMERICAS (continued)
ASIA/PACIFIC (continued)
Corporate Office
Toronto
Singapore
Microchip Technology Inc.
Microchip Technology Inc.
Microchip Technology Singapore Pte Ltd.
200 Middle Road
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-786-7200 Fax: 480-786-7277
Technical Support: 480-786-7627
Web Address: http://www.microchip.com
5925 Airport Road, Suite 200
Mississauga, Ontario L4V 1W1, Canada
Tel: 905-405-6279 Fax: 905-405-6253
#07-02 Prime Centre
Singapore 188980
Tel: 65-334-8870 Fax: 65-334-8850
Taiwan, R.O.C
Microchip Technology Taiwan
10F-1C 207
Tung Hua North Road
Taipei, Taiwan, ROC
ASIA/PACIFIC
Hong Kong
Microchip Asia Pacific
Unit 2101, Tower 2
Atlanta
Microchip Technology Inc.
500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 852-2-401-1200 Fax: 852-2-401-3431
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
Tel: 770-640-0034 Fax: 770-640-0307
Boston
EUROPE
Microchip Technology Inc.
5 Mount Royal Avenue
Marlborough, MA 01752
Tel: 508-480-9990 Fax: 508-480-8575
Beijing
United Kingdom
Microchip Technology, Beijing
Unit 915, 6 Chaoyangmen Bei Dajie
Dong Erhuan Road, Dongcheng District
New China Hong Kong Manhattan Building
Beijing 100027 PRC
Arizona Microchip Technology Ltd.
505 Eskdale Road
Winnersh Triangle
Wokingham
Berkshire, England RG41 5TU
Tel: 44 118 921 5858 Fax: 44-118 921-5835
Denmark
Microchip Technology Denmark ApS
Regus Business Centre
Lautrup hoj 1-3
Ballerup DK-2750 Denmark
Tel: 45 4420 9895 Fax: 45 4420 9910
Chicago
Microchip Technology Inc.
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 86-10-85282100 Fax: 86-10-85282104
India
Tel: 630-285-0071 Fax: 630-285-0075
Dallas
Microchip Technology Inc.
4570 Westgrove Drive, Suite 160
Addison, TX 75248
Microchip Technology Inc.
India Liaison Office
No. 6, Legacy, Convent Road
Bangalore 560 025, India
Tel: 91-80-229-0061 Fax: 91-80-229-0062
Tel: 972-818-7423 Fax: 972-818-2924
Dayton
Microchip Technology Inc.
Two Prestige Place, Suite 150
Miamisburg, OH 45342
Tel: 937-291-1654 Fax: 937-291-9175
Detroit
Microchip Technology Inc.
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: 248-538-2250 Fax: 248-538-2260
Japan
France
Microchip Technology Intl. Inc.
Benex S-1 6F
Arizona Microchip Technology SARL
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa 222-0033 Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Batiment A - ler Etage
91300 Massy, France
Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Germany
Arizona Microchip Technology GmbH
Gustav-Heinemann-Ring 125
D-81739 München, Germany
Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Korea
Microchip Technology Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea
Tel: 82-2-554-7200 Fax: 82-2-558-5934
Shanghai
Microchip Technology
RM 406 Shanghai Golden Bridge Bldg.
2077 Yan’an Road West, Hong Qiao District
Shanghai, PRC 200335
Italy
Los Angeles
Arizona Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Microchip Technology Inc.
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: 949-263-1888 Fax: 949-263-1338
New York
Microchip Technology Inc.
150 Motor Parkway, Suite 202
Hauppauge, NY 11788
Tel: 631-273-5305 Fax: 631-273-5335
Milan, Italy
Tel: 39-039-65791-1 Fax: 39-039-6899883
Tel: 86-21-6275-5700 Fax: 86 21-6275-5060
11/15/99
San Jose
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950 Fax: 408-436-7955
All rights reserved. © 1999 Microchip Technology Incorporated. Printed in the USA. 11/99
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed
by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products
as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip
logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
1999 Microchip Technology Inc.
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