74VHCT244ASJX [ETC]

Dual 4-Bit Non-Inverting Buffer/Driver ; 双4位非反相缓冲器/驱动器\n
74VHCT244ASJX
型号: 74VHCT244ASJX
厂家: ETC    ETC
描述:

Dual 4-Bit Non-Inverting Buffer/Driver
双4位非反相缓冲器/驱动器\n

驱动器 逻辑集成电路 光电二极管
文件: 总7页 (文件大小:88K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
March 1997  
Revised March 1999  
74VHCT244A  
Octal Buffer/Line Driver with 3-STATE Outputs  
due to mismatched supply and input/output voltages. This  
General Description  
device can be used to interface 5V to 3V systems and two  
supply systems such as battery back up.  
Note 1: Outputs in OFF-State  
The VHCT244A is an advanced high speed CMOS octal  
bus transceiver fabricated with silicon gate CMOS technol-  
ogy. It achieves high speed operation similar to equivalent  
Bipolar Schottky TTL while maintaining the CMOS low  
power dissipation. The VHCT244A is a non-inverting 3-  
STATE buffer having two active-LOW output enables. This  
device is designed to be used as 3-STATE memory  
address drivers, clock drivers, and bus oriented transmitter/  
receivers.  
Features  
High Speed: tPD = 5.9 ns (typ) at VCC = 5V  
Power down protection is provided on inputs and  
outputs  
Low power dissipation: ICC = 4 µA (max) @ TA = 25°C  
Pin and function compatible with 74HCT244  
Protection circuits ensure that 0V to 7V can be applied to  
the input and output (Note 1) pins without regard to the  
supply voltage. These circuits prevent device destruction  
Ordering Code:  
Order Number  
74VHCT244AM  
74VHCT244ASJ  
74VHCT244AMTC  
74VHCT244AN  
Package Number  
M20B  
Package Description  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
M20D  
MTC20  
N20A  
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbol  
Connection Diagram  
Pin Descriptions  
Pin Names  
OE1, OE2  
Description  
3-STATE Output Enable Inputs  
I0–I7  
Inputs  
O0–O7  
3-STATE Outputs  
© 1999 Fairchild Semiconductor Corporation  
DS500003.prf  
www.fairchildsemi.com  
Truth Tables  
Inputs  
Outputs  
(Pins 12, 14, 16, 18)  
OE1  
In  
L
L
L
H
X
L
H
Z
H
Inputs  
Outputs  
(Pins 3, 5, 7, 9)  
OE2  
In  
L
L
L
H
X
L
H
Z
H
H = HIGH Voltage Level  
L = LOW Voltage Level  
I = Immaterial  
Z = High Impedance  
www.fairchildsemi.com  
2
Absolute Maximum Ratings(Note 2)  
Recommended Operating  
Conditions (Note 6)  
Supply Voltage (VCC  
)
0.5V to +7.0V  
0.5V to +7.0V  
DC Input Voltage (VIN  
)
Supply Voltage (VCC  
)
4.5V to +5.5V  
0V to +5.5V  
DC Output Voltage (VOUT  
)
Input Voltage (VIN  
)
(Note 3)  
0.5V to VCC + 0.5V  
0.5V to +7.0V  
20 mA  
Output Voltage (VOUT  
)
(Note 4)  
(Note 3)  
0V to VCC  
0V to +5.5V  
Input Diode Current (IIK  
Output Diode Current (IOK) (Note 5)  
DC Output Current (IOUT  
DC VCC/GND Current (ICC  
)
(Note 4)  
±20 mA  
Operating Temperature (TOPR  
Input Rise and Fall Time (tr, tf)  
CC = 5.0V ± 0.5V  
)
40°C to +85°C  
)
±25 mA  
)
±75 mA  
V
0 ns/V 20 ns/V  
Note 2: Absolute Maximum Ratings are values beyond which the device  
may be damaged or have its useful life impaired. The databook specifica-  
tions should be met, without exception, to ensure that the system design is  
reliable over its power supply, temperature, and output/input loading vari-  
ables. Fairchild does not recommend operation outside databook specifica-  
tions.  
Storage Temperature (TSTG  
Lead Temperature (TL)  
(Soldering, 10 seconds)  
)
65°C to +150°C  
260°C  
Note 3: HIGH or LOW state.  
I
absolute maximum rating must be  
OUT  
observed.  
Note 4: When outputs are in OFF-STATE or when V = OV.  
CC  
Note 5: V  
< GND, V  
> V (Outputs Active).  
OUT CC  
OUT  
Note 6: Unused inputs must be held HIGH or LOW. They may not float.  
DC Electrical Characteristics  
T
= 25°C  
T = −40°C to +85°C  
A
V
(V)  
A
CC  
Symbol  
Parameter  
Units  
Conditions  
Min  
2.0  
2.0  
Typ  
Max  
Min  
Max  
V
V
V
V
HIGH Level  
4.5  
5.5  
4.5  
5.5  
2.0  
2.0  
IH  
V
V
Input Voltage  
LOW Level  
0.8  
0.8  
0.8  
0.8  
IL  
Input Voltage  
HIGH Level  
4.40  
3.94  
4.50  
0.0  
4.40  
3.80  
V
V
V
V
V
V
= V I  
IH OH  
= −50 µA  
= −8 mA  
= 50 µA  
= 8 mA  
OH  
OL  
IN  
4.5  
4.5  
Output Voltage  
LOW Level  
or V  
I
IL OH  
0.1  
0.1  
= V  
I
IN  
IH OL  
Output Voltage  
3-STATE Output  
Off-State Current  
Input Leakage  
Current  
0.36  
0.44  
or V  
I
IL OL  
I
I
I
I
I
V
V
V
= V or V  
IH IL  
OZ  
IN  
5.5  
±0.25  
±0.1  
4.0  
±2.5  
±1.0  
40.0  
1.50  
5.0  
µA  
µA  
µA  
mA  
µA  
= V or GND  
OUT  
CC  
= 5.5V or GND  
IN  
IN  
IN  
IN  
0–5.5  
5.5  
Quiescent Supply  
Current  
V
= V or GND  
CC  
CC  
Maximum I /Input  
V
= 3.4V  
CCT  
OFF  
CC  
5.5  
1.35  
0.5  
Other Input = V or GND  
CC  
Output Leakage Current  
(Power Down State)  
V
= 5.5V  
OUT  
0.0  
3
www.fairchildsemi.com  
Noise Characteristics  
T
= 25°C  
V
(V)  
A
CC  
Symbol  
Parameter  
Units  
Conditions  
Typ  
Limits  
V
Quiet Output Maximum Dynamic V  
OLP  
OL  
5.0  
0.9  
1.1  
1.1  
2.0  
V
V
V
V
C
C
C
C
= 50 pF  
= 50 pF  
= 50 pF  
= 50 pF  
L
L
L
L
(Note 7)  
V
Quiet Output Minimum Dynamic V  
OL  
OLV  
5.0  
5.0  
5.0  
0.9  
(Note 7)  
V
Minimum HIGH Level Dynamic Input Voltage  
Maximum LOW Level Dynamic Input Voltage  
IHD  
(Note 7)  
V
ILD  
0.8  
(Note 7)  
Note 7: Parameter guaranteed by design.  
AC Electrical Characteristics  
T
= 25°C  
T = −40°C to +85°C  
A
V
(V)  
A
CC  
Symbol  
Parameter  
Units  
ns  
Conditions  
Min  
Typ  
5.4  
5.9  
7.7  
8.2  
Max  
7.4  
Min  
Max  
8.5  
t
t
t
t
t
t
t
t
Propagation Delay  
Time  
1.0  
1.0  
1.0  
1.0  
C
C
C
C
C
= 15 pF  
= 50 pF  
= 15 pF  
= 50 pF  
= 50 pF  
PLH  
L
L
L
L
L
5.0 ± 0.5  
5.0 ± 0.5  
5.0 ± 0.5  
5.0 ± 0.5  
8.4  
9.5  
PHL  
3-STATE Output  
Enable Time  
3-STATE Output  
Disable Time  
Output to  
10.4  
11.4  
12.5  
13.5  
R
R
= 1 kΩ  
= 1 kΩ  
PZL  
L
ns  
PZH  
PLZ  
L
8.8  
11.4  
1.0  
10  
1.0  
13.0  
1.0  
10  
ns  
PHZ  
OSLH  
OSHL  
(Note 8)  
ns  
Output Skew  
Input  
C
C
C
V
V
= Open  
= 5.0V  
IN  
CC  
4
9
pF  
Capacitance  
Output  
OUT  
PD  
CC  
pF  
Capacitance  
Power Dissipation  
Capacitance  
(Note 9)  
18  
pF  
Note 8: Parameter guaranteed by design. t  
= |t  
t  
|; t  
= |t  
t  
|
OSLH  
PLH max  
PLH min OSHL  
PHL max  
PHL min  
Note 9: C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average  
PD  
operating current can be obtained by the equation: I (opr.) = C * V * f + I /8 (per F/F). The total C when n pcs. of the Octal D Flip-Flop operates  
CC  
PD  
CC  
IN  
CC  
PD  
can be calculated by the equation: C (total) = 20 + 12n.  
PD  
www.fairchildsemi.com  
4
Physical Dimensions inches (millimeters) unless otherwise noted  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
Package Number M20B  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
Package Number M20D  
5
www.fairchildsemi.com  
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
Package Number MTC20  
www.fairchildsemi.com  
6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Package Number N20A  
LIFE SUPPORT POLICY  
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT  
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD  
SEMICONDUCTOR CORPORATION. As used herein:  
1. Life support devices or systems are devices or systems  
which, (a) are intended for surgical implant into the  
body, or (b) support or sustain life, and (c) whose failure  
to perform when properly used in accordance with  
instructions for use provided in the labeling, can be rea-  
sonably expected to result in a significant injury to the  
user.  
2. A critical component in any component of a life support  
device or system whose failure to perform can be rea-  
sonably expected to cause the failure of the life support  
device or system, or to affect its safety or effectiveness.  
www.fairchildsemi.com  
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.  

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