74LVX373T [ETC]
8-Bit D-Type Latch ; 8位D类锁存器\n
| 型号： | 74LVX373T |
| 厂家： | 
ETC |
| 描述： | 8-Bit D-Type Latch
|
| 文件： | 总10页 (文件大小：78K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVX373
LOW VOLTAGE OCTAL D-TYPE LATCH
(3-STATE NON INV.) WITH 5V TOLERANT INPUTS
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HIGH SPEED:tPD =5.8ns (TYP.) atVCC = 3.3V
5V TOLERANT INPUTS
POWER-DOWN PROTECTIONON INPUTS
INPUT VOLTAGELEVEL:
VIL =0.8V,VIH =2V atVCC =3V
LOW POWER DISSIPATION:
I
M
T
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(Micro Package)
(TSSOPPackage)
CC =4 µA (MAX.) at TA =25 oC
ORDER CODES :
LOWNOISE:
OLP =0.3 V (TYP.)at VCC = 3.3V
74LVX373M
74LVX373T
V
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 4 mA (MIN)
BALANCEDPROPAGATIONDELAYS:
tPLH tPHL
While the LE input is held at a high level, the Q
outputswill follow the data input precisely.
When the LE is taken low, the Q outputs will be
latched precisely at the logic level of D input data.
While the (OE) input is low, the 8 outputs will be
in a normal logic state (high or low logic level)
and while high level the outputs will be in a high
impedance state.
It has better speed performance at 3.3V than 5V
LS-TTL family combined with the true CMOS low
power consuption.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface5V to 3V.
OPERATING VOLTAGERANGE:
VCC (OPR)= 2V to 3.6V
PIN AND FUNCTION COMPATIBLEWITH
74 SERIES373
IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The LVX373 is a low voltage CMOS OCTAL
D-TYPE LATCH with 3 STATE OUTPUT NON
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C2MOS
technology.It is ideal for low power and low noise
3.3V applications.
This 8 bit D-Type latch is controlled by a latch
enable input (LE) and an output enable input
(OE).
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
1/10
May 1999
74LVX373
INPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
SYMBOL NAME AND FUNCTION
1
OE
3 State Output Enable
Input (Active LOW)
2, 5, 6, 9,
12, 15, 17,
18
Q0 to Q7 3 State Outputs
3, 4, 7, 8,
13, 14, 17,
18
D0 to D7 Data Inputs
11
LE
Latch Enable
Input
10
20
GND
VCC
Ground (0V)
Positive Supply Voltage
TRUTH TABLE
INPUTS
OUTPUTS
OE
H
LE
X
D
X
X
L
Q
Z
L
L
NO CHANGE *
L
H
L
L
X:Don’tcare
H
H
H
Z:Highimpedance
* Q outputs arelatched atthe timewhenthe LEinput istaken low.
LOGICS DIAGRAM
2/10
74LVX373
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
VI
Parameter
Value
-0.5 to +7.0
-0.5 to 7.0
-0.5 to VCC + 0.5
- 20
Unit
V
Supply Voltage
DC Input Voltage
V
VO
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
V
IIK
mA
mA
mA
mA
oC
IOK
± 20
IO
25
50
±
±
ICC or IGND DC VCC or Ground Current
Tstg
TL
Storage Temperature
-65 to +150
300
Lead Temperature (10 sec)
oC
AbsoluteMaximum Ratingsarethose values beyond whichdamage tothe device may occur. Functional operation under these condition isnot implied.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VI
Parameter
Supply Voltage (note 1)
Value
2 to 3.6
Unit
V
Input Voltage
0 to 5.5
V
VO
Output Voltage
0 to VCC
-40 to +85
0 to 100
V
oC
Top
Operating Temperature:
dt/dv
Input Rise and Fall Time (VCC = 3V) (note 2)
ns/V
1) Truth Table guaranteed: 1.2V to 3.6V
2)VIN from0.8Vto2V
3/10
74LVX373
DC SPECIFICATIONS
Symbol
Parameter
Test Conditions
Value
TA = 25 oC
Min. Typ. Max. Min. Max.
Unit
VCC
(V)
-40 to 85 oC
VIH
High Level Input Voltage
Low Level Input Voltage
2.0
3.0
3.6
2.0
3.0
3.6
2.0
3.0
3.0
2.0
3.0
3.0
3.6
1.5
2.0
2.4
1.5
2.0
2.4
V
V
V
V
VIL
0.5
0.8
0.8
0.5
0.8
0.8
VI(*)
VIH or
VIL
=
VOH
High Level Output
Voltage
IO=-50 µA
IO=-50 µA
IO=-4 mA
1.9
2.9
2.0
3.0
1.9
2.9
2.58
2.48
VOL
Low Level Output
Voltage
VI(*)
VIH or
VIL
=
I =50
O
A
0.0
0.0
0.1
0.1
0.1
0.1
µ
IO=50 µA
IO=4 mA
0.36
±0.1
±0.25
0.44
±1
II
Input Leakage Current
VI = 5V or GND
µA
µA
IOZ
3 State Output Leakage
Current
VI = VIH or VIL
VO = VCC or GND
±2.5
3.6
3.6
ICC
Quiescent Supply
Current
VI = VCC or GND
2
20
µA
(*) All outputs loaded.
DYNAMIC SWITCHING CHARACTERISTICS
Symbol
Parameter
Test Conditions
Value
TA = 25 oC
Unit
VCC
-40 to 85 oC
(V)
Min. Typ. Max. Min. Max.
VOLP Dynamic Low Voltage
3.3
0.3
0.8
Quiet Output (note 1, 2)
VOLV
-0.8
-0.3
VIHD
VILD
Dynamic High Voltage
Input (note 1, 3)
3.3
3.3
2
CL = 50 pF
V
Dynamic Low Voltage
Input (note 1, 3)
0.8
1)Worstcase package
2)Max number ofoutputs defined as (n). Datainputs aredriven 0Vto3.3V, (n -1)outputs switching andone outputatGND
3)max number ofdatainputs (n)switching.(n-1)switching 0Vto3.3V. Inputsunder testswitching: 3.3Vtothreshold (VILD),0V tothreshold (VIHD).f=1MHz
4/10
74LVX373
AC ELECTRICAL CHARACTERISTICS
(CL = 50 pF, Input tr = tf =3 ns)
Symbol
Parameter
Test Condition
Value
TA = 25 oC
Min. Typ. Max. Min. Max.
Unit
VCC
(V)
CL
(pF)
-40 to 85 oC
tPLH
tPHL
Propagation Delay Time
LE to Q
2.7
2.7
3.3(*)
3.3(*)
2.7
15
50
15
50
15
50
15
50
15
50
15
50
50
50
50
50
50
50
50
50
50
50
7.5
14.5
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
17.5
21.0
12.0
15.5
18.5
22.0
11.5
15.0
18.5
22.0
11.5
15.0
21.0
14.5
7.5
10.0 18.0
ns
ns
ns
6.8
9.3
7.7
10.3
13.8
15.0
tPLH
tPHL
Propagation Delay Time
D to Q
2.7
10.2 18.5
3.3(*)
3.3(*)
2.7
6.0
8.5
7.7
9.7
13.2
15.0
tPZL
tPZH
Output Enable Time
2.7
10.2 18.5
RL = 1 k
RL = 1 k
Ω
Ω
3.3(*)
3.3(*)
2.7
6.0
8.5
9.8
8.2
6.5
5.0
6.0
4.0
1.0
1.0
0.5
0.5
9.7
13.2
18.0
12.8
tPLZ
tPHZ
Output Disable Time
LE pulse Width, HIGH
ns
ns
ns
ns
ns
3.3(*)
tw
ts
th
2.7
3.3(*)
2.7
5.0
Setup Time D to LE
HIGH or LOW
6.0
3.3(*)
4.0
Hold Time D to LE
HIGH or LOW
2.7
3.3(*)
2.7
1.0
1.0
1.5
1.5
tOSLH Output to Output Skew
tOSHL
1.0
1.0
3.3(*)
Time (note 1, 2)
1) Skewis defined astheabsolute value ofthe difference between theactual propagation delay for any twooutputs of thesame device switching inthe
same direction, either HIGHor LOW
2) Parameter guaranteed bydesign
(*) Voltagerangeis3.3V 0.3V
±
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
Test Conditions
Value
TA = 25 oC
Unit
VCC
-40 to 85 oC
(V)
Min. Typ. Max. Min. Max.
CIN
Input Capacitance
5
3.3
3.3
3.3
pF
pF
pF
COUT Output Capacitance
10
10
CPD
Power Dissipation
fIN = 10 MHz
Capacitance (note 1)
1)CPD isdefined as thevalue ofthe IC’sinternal equivalent capacitance whichiscalculated fromthe operating current consumption without load. (Referto
TestCircuit).Average operting current can beobtained bythe followingequation. ICC(opr)= CPD VCC IN + ICC/8(per circuit)
f
•
•
5/10
74LVX373
TEST CIRCUIT
TEST
SWITCH
Open
VCC
tPLH, tPHL
tPZL, tPLZ
tPZH, tPHZ
GND
CL = 15/50 pF or equivalent (includes jig and probe capacitance)
R =R =1K orequivalent
Ω
L
1
RT = ZOUT ofpulse generator (typically50Ω)
WAVEFORM 1: LE TO Qn PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH,
Dn TO LE SETUP AND HOLD TIMES
(f=1MHz; 50% duty cycle)
6/10
74LVX373
WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES
(f=1MHz; 50% duty cycle)
WAVEFORM 3: PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)
7/10
74LVX373
SO-20 MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
TYP.
MAX.
2.65
0.20
2.45
0.49
0.32
MIN.
MAX.
0.104
0.007
0.096
0.019
0.012
A
a1
a2
b
0.10
0.004
0.35
0.23
0.013
0.009
b1
C
0.50
0.020
c1
D
45 (typ.)
12.60
10.00
13.00
10.65
0.496
0.393
0.512
0.419
E
e
1.27
0.050
0.450
e3
F
11.43
7.40
0.50
7.60
1.27
0.75
0.291
0.19
0.299
0.050
0.029
L
M
S
8 (max.)
P013L
8/10
74LVX373
TSSOP20 MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
TYP.
MAX.
1.1
MIN.
MAX.
0.433
0.006
0.374
0.0118
0.0079
0.260
0.256
0.176
A
A1
A2
b
0.05
0.85
0.19
0.09
6.4
0.10
0.9
0.15
0.95
0.30
0.2
0.002
0.335
0.0075
0.0035
0.252
0.246
0.169
0.004
0.354
c
D
6.5
6.4
6.6
0.256
0.252
E
6.25
4.3
6.5
E1
e
4.4
4.48
0.173
0.65 BSC
4o
0.0256 BSC
4o
K
0o
8o
0o
8o
L
0.50
0.60
0.70
0.020
0.024
0.028
A2
A
K
L
b
e
A1
E
c
D
E1
PIN 1 IDENTIFICATION
1
9/10
74LVX373
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subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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10/10
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