74LVX174T [ETC]
Hex D-Type Flip-Flop ; 六路D类触发器\n
| 型号： | 74LVX174T |
| 厂家： | 
ETC |
| 描述： | Hex D-Type Flip-Flop
|
| 文件： | 总10页 (文件大小：74K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVX174
HEX D-TYPE FLIP FLOP WITH CLEAR
WITH 5V TOLERANT INPUTS
■
HIGH SPEED:
MAX =180MHz(TYP.) at VCC =3.3V
5V TOLERANT INPUTS
f
■
■
POWER-DOWN PROTECTIONON INPUTS
INPUT VOLTAGELEVEL:
M
T
VIL =0.8V,VIH =2V atVCC =3V
LOW POWER DISSIPATION:
ICC =4 µA (MAX.) at TA =25 oC
LOWNOISE:
(Micro Package)
(TSSOPPackage)
■
■
■
■
■
■
■
ORDER CODES :
74LVX174M
74LVX174T
VOLP =0.3 V (TYP.)at VCC = 3.3V
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 4 mA (MIN)
BALANCEDPROPAGATIONDELAYS:
tPLH tPHL
Information signals applied to D inputs are
transfered to the Q outputs on the positive going
edge of the clock pulse.
When the CLEAR input is held low, the Q outputs
are held low independentlyof the other inputs .
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface5V to 3V.
OPERATING VOLTAGERANGE:
VCC (OPR)= 2V to 3.6V
PIN AND FUNCTION COMPATIBLEWITH
74 SERIES174
IMPROVED LATCH-UP IMMUNITY
It has better speed performance at 3.3V than 5V
LS-TTL family combined with the true CMOS low
power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
DESCRIPTION
The LVX174 is a low voltage CMOS HEX
D-TYPE FLIP FLOP WITH CLEAR NON
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C2MOS
technology.It is ideal for low power and low noise
3.3V applications.
PIN CONNECTION AND IEC LOGIC SYMBOLS
1/10
April 1999
74LVX174
INPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
SYMBOL NAME AND FUNCTION
1
CLEAR
Asyncronous Master Reset
(Active LOW)
2, 5, 7, 10,
12, 15
Q0 to Q5 Flip-Flop Outputs
3, 4, 6, 11,
13, 14
D0 to D5 Data Inputs
9
CLOCK
Clock Input (LOW-to-HIGH,
Edge- Triggered)
8
GND
VCC
Ground (0V)
16
Positive Supply Voltage
TRUTH TABLE
INPUTS
OUTPUTS
FUNCTION
CLEAR
D
X
L
CLOCK
Q
L
L
H
H
H
X
CLEAR
L
H
X
H
Qn
NO CHANGE
X:Don’t Care
LOGIC DIAGRAM
Thislogic diagram has notbe used to esimate propagation delays
2/10
74LVX174
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
VI
Parameter
Value
-0.5 to +7.0
-0.5 to 7.0
-0.5 to VCC + 0.5
- 20
Unit
V
Supply Voltage
DC Input Voltage
V
VO
DC OutputVoltage
DC Input Diode Current
DC OutputDiode Current
DC OutputCurrent
V
IIK
mA
mA
mA
mA
oC
IOK
± 20
IO
25
50
±
±
ICC or IGND DC VCC or Ground Current
Tstg
TL
Storage Temperature
-65 to +150
300
Lead Temperature (10 sec)
oC
AbsoluteMaximum Ratingsarethose values beyond whichdamage tothe device may occur. Functional operation under these condition isnot implied.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VI
Parameter
Value
2 to 3.6
Unit
V
Supply Voltage (note 1)
Input Voltage
0 to 5.5
V
VO
Output Voltage
0 to VCC
-40 to +85
0 to 100
V
oC
Top
Operating Temperature:
dt/dv
Input Rise and Fall Time (VCC = 3V)(note 2)
ns/V
1) Truth Table guaranteed: 1.2V to 3.6V
2)VIN from0.8Vto2V
3/10
74LVX174
DC SPECIFICATIONS
Symbol
Parameter
Test Conditions
Value
TA = 25 oC
Min. Typ. Max. Min. Max.
Unit
VCC
(V)
-40 to 85 oC
VIH
High LevelInput Voltage
Low Level Input Voltage
High LevelOutputVoltage
Low Level Output Voltage
2.0
3.0
3.6
2.0
3.0
3.6
2.0
3.0
3.0
2.0
3.0
3.0
3.6
3.6
1.5
2.0
2.4
1.5
2.0
2.4
V
V
V
V
VIL
0.5
0.8
0.8
0.5
0.8
0.8
VI(*)
VIH or
VIL
=
VOH
IO=-50 µA
IO=-50 µA
IO=-4 mA
1.9
2.9
2.0
3.0
1.9
2.9
2.58
2.48
VOL
VI(*)
VIH or
VIL
=
I =50
O
A
0.0
0.0
0.1
0.1
0.36
±0.1
4
0.1
0.1
0.44
±1
µ
IO=50 µA
IO=4 mA
II
Input Leakage Current
VI = 5V or GND
VI = VCC or GND
µA
µA
ICC
Quiescent Supply Current
40
(*) All outputs loaded.
DYNAMIC SWITCHING CHARACTERISTICS
Symbol
Parameter
Test Conditions
Value
TA = 25 oC
Unit
VCC
-40 to 85 oC
(V)
Min. Typ. Max. Min. Max.
VOLP Dynamic Low Voltage
3.3
0.3
0.8
Quiet Output (note 1, 2)
VOLV
-0.8
-0.3
VIHD
VILD
Dynamic High Voltage
Input (note 1, 3)
3.3
3.3
2
CL = 50 pF
V
Dynamic Low Voltage
Input (note 1, 3)
0.8
1)Worstcase package
2)Max number ofoutputs defined as (n). Datainputs aredriven 0Vto3.3V, (n -1)outputs switching andone outputatGND
3)max number ofdatainputs (n)switching.(n-1)switching 0Vto3.3V. Inputsunder testswitching: 3.3Vtothreshold (VILD),0V tothreshold (VIHD).f=1MHz
4/10
74LVX174
AC ELECTRICAL CHARACTERISTICS
(Input tr = tf =3 ns)
Symbol
Parameter
Test Condition
Value
TA = 25 oC
Min. Typ. Max. Min. Max.
Unit
VCC
(V)
CL
(pF)
-40 to 85 oC
tPLH
tPHL
Propagation Delay Time
CKto Q
2.7
2.7
3.3(*)
3.3(*)
2.7
15
50
15
50
15
50
15
50
7.6
14.5
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
17.5
21.0
11.0
14.5
18.5
22.0
11.5
15.0
7.5
10.1 18.0
ns
ns
5.9
8.4
7.9
9.3
12.8
15.0
tPLH
tPHL
Propagation Delay Time
CLR to Q
2.7
10.4 18.5
3.3(*)
3.3(*)
2.7
6.2
8.7
6.5
5.0
6.5
5.0
7.5
5.0
9.7
13.2
twL
tw
CLR pulseWidth, HIGH
CKpulse Width
ns
ns
ns
ns
ns
3.3(*)
5.0
2.7
7.5
3.3(*)
2.7
5.0
ts
Setup Time Q to CK HIGH
or LOW
8.5
3.3(*)
6.0
th
Hold TimeQ to CK HIGH
or LOW
2.7
3.3(*)
0.0
0.0
0.0
0.0
tREM
fMAX
Recovery Time CLR to Q
2.7
3.3(*)
2.7
4.5
3.0
130
60
4.5
3.0
Maximum Clock Frequency
15
50
15
50
50
50
65
45
55
40
95
55
2.7
MHz
ns
3.3(*)
3.3(*)
2.7
115
65
180
95
tOSLH Output to OutputSkew
tOSHL
0.5
1.0
1.0
1.5
1.5
3.3(*)
0.5
Time (note 1, 2)
1) Skewis defined astheabsolute value ofthe difference between theactual propagation delay for any twooutputs of thesame device switching inthe
same direction, either HIGHor LOW
2) Parameter guaranteed bydesign
(*) Voltagerangeis3.3V 0.3V
±
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
Test Conditions
Value
TA = 25 oC
Unit
VCC
-40 to 85 oC
(V)
Min. Typ. Max. Min. Max.
CIN
Input Capacitance
5
3.3
3.3
pF
pF
CPD
Power Dissipation
fIN = 10 MHz
23
Capacitance (note 1)
1)CPD isdefined as thevalue ofthe IC’sinternal equivalent capacitance whichiscalculated fromthe operating current consumption without load. (Referto
TestCircuit).Average operting current can beobtained bythe followingequation. ICC(opr)= CPD • VCC • fIN + ICC/n(per circuit)
5/10
74LVX174
TEST CIRCUIT
CL = 50 pF or equivalent (includes jigand probe capacitance)
RT = ZOUT ofpulse generator (typically50
)
Ω
WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)
6/10
74LVX174
WAVEFORM 2: PROPAGATION DELAYS
(f=1MHz; 50% duty cycle)
WAVEFORM 3: RECOVERY TIME (f=1MHz; 50% duty cycle)
7/10
74LVX174
SO-16 MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
TYP.
MAX.
1.75
0.2
MIN.
MAX.
0.068
0.007
0.064
0.018
0.010
A
a1
a2
b
0.1
0.004
1.65
0.46
0.25
0.35
0.19
0.013
0.007
b1
C
0.5
0.019
c1
D
45 (typ.)
9.8
5.8
10
0.385
0.228
0.393
0.244
E
6.2
e
1.27
8.89
0.050
0.350
e3
F
3.8
4.6
0.5
4.0
5.3
0.149
0.181
0.019
0.157
0.208
0.050
0.024
G
L
1.27
0.62
M
S
8 (max.)
P013H
8/10
74LVX174
TSSOP16 MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
TYP.
MAX.
1.1
MIN.
MAX.
0.433
0.006
0.374
0.0118
0.0079
0.201
0.256
0.176
A
A1
A2
b
0.05
0.85
0.19
0.09
4.9
0.10
0.9
0.15
0.95
0.30
0.20
5.1
0.002
0.335
0.0075
0.0035
0.193
0.246
0.169
0.004
0.354
c
D
5
6.4
0.197
0.252
E
6.25
4.3
6.5
E1
e
4.4
4.48
0.173
0.65 BSC
4o
0.0256 BSC
4o
K
0o
8o
0o
8o
L
0.50
0.60
0.70
0.020
0.024
0.028
A2
A
K
L
b
e
A1
c
E
D
E1
PIN 1 IDENTIFICATION
1
9/10
74LVX174
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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10/10
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