74LVTH652MTCX [ETC]
Single 8-bit Bus Transceiver ; 一个8位总线收发器\n
| 型号： | 74LVTH652MTCX |
| 厂家： | 
ETC |
| 描述： | Single 8-bit Bus Transceiver
|
| 文件： | 总8页 (文件大小：82K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 2000
Revised November 2000
74LVTH652
Low Voltage Octal Transceiver/Register
with 3-STATE Outputs
General Description
Features
■ Input and output interface capability to systems at
The LVTH652 consists of bus transceiver circuits with D-
type flip-flops, and control circuitry arranged for multiplexed
transmission of data directly from the input bus or from the
internal registers. Data on the A or B bus will be clocked
into the registers as the appropriate clock pin goes to HIGH
logic level. Output Enable pins (OEAB, OEBA) are pro-
vided to control the transceiver function. (See Functional
Description).
5V VCC
■ Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs
■ Live insertion/extraction permitted
■ Power Up/Down high impedance provides glitch-free
bus loading
■ Outputs source/sink −32 mA/+64 mA
■ Functionally compatible with the 74 series 652
■ Latch-up performance exceeds 500 mA
■ ESD performance:
The LVTH652 data inputs include bushold, eliminating the
need for external pull-up resistors to hold unused inputs.
This octal transceiver/register is designed for low-voltage
(3.3V) VCC applications, but with the capability to provide a
TTL interface to a 5V environment. The LVTH652 is fabri-
cated with an advanced BiCMOS technology to achieve
high speed operation similar to 5V ABT while maintaining
low power dissipation.
Human-body model > 2000V
Machine model > 200V
Charged-device model > 1000V
Ordering Code:
Order Number
74LVTH652WM
74LVTH652MTC
Package Number
M24B
Package Description
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MTC24
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
© 2000 Fairchild Semiconductor Corporation
DS012018
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Pin Descriptions
Connection Diagram
Pin Names
Description
A0–A7
B0–B7
Data Register A Inputs/
3-STATE Outputs
Data Register B Inputs/
3-STATE Outputs
Clock Pulse Inputs
Select Inputs
CPAB, CPBA
SAB, SBA
OEAB, OEBA
Output Enable Inputs
Truth Table
(Note 1)
Inputs
Inputs/Outputs
Operating Mode
OEAB OEBA
CPAB
CPBA
SAB SBA
A0 thru A7
Input
B0 thru B7
Input
L
L
H
H
H
H
X
L
H or L
H or L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
Isolation
Store A and B Data
X
H
L
H or L
Input
Input
Not Specified Store A, Hold B
Output Store A in Both Registers
H or L
Not Specified Input
Hold A, Store B
L
Output
Output
Input
Input
Store B in Both Registers
Real-Time B Data to A Bus
Store B Data to A Bus
Real-Time A Data to B Bus
Stored A Data to B Bus
L
L
X
X
X
H or L
X
L
L
H
X
X
H
H
H
H
X
Input
Output
Output
H or L
X
H
Stored A Data to B Bus and
Stored B Data to A Bus
H
L
H or L
H or L
H
H
Output
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW to HIGH Clock Transition
Note 1: The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled, i.e.,
data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Functional Description
In the transceiver mode, data present at the HIGH imped-
ance port may be stored in either the A or B register or
both.
Data on the A or B data bus, or both can be stored in the
internal D-type flip-flop by LOW-to-HIGH transitions at the
appropriate Clock Inputs (CPAB, CPBA) regardless of the
Select or Output Enable Inputs. When SAB and SBA are in
the real time transfer mode, it is also possible to store data
without using the internal D-type flip-flops by simulta-
neously enabling OEAB and OEBA. In this configuration
each Output reinforces its Input. Thus when all other data
sources to the two sets of bus lines are in a HIGH imped-
ance state, each set of bus lines will remain at its last state.
The select (SAB, SBA) controls can multiplex stored and
real-time.
The examples below demonstrate the four fundamental
bus-management functions that can be performed with the
LVTH652.
Real-Time Transfer
Bus B to Bus A
Real-Time Transfer
Bus A to Bus B
OEAB
L
OEBA
L
CPAB
X
CPBA
X
SAB
X
SBA
L
OEAB
H
OEBA
H
CPAB
X
CPBA
X
SAB
L
SBA
X
Transfer Storage
Data to A or B
Storage
OEAB
H
OEBA
L
CPAB
H or L
CPBA
H or L
SAB
H
SBA
H
OEAB
OEBA
CPAB
X
CPBA
X
SAB
X
SBA
X
X
L
L
H
X
H
X
X
X
X
3
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Absolute Maximum Ratings(Note 2)
Symbol
VCC
Parameter
Supply Voltage
Value
−0.5 to +4.6
−0.5 to +7.0
−0.5 to +7.0
−0.5 to +7.0
−50
Conditions
Units
V
V
VI
DC Input Voltage
VO
DC Output Voltage
Output in 3-STATE
V
Output in HIGH or LOW State (Note 3)
IIK
IOK
IO
DC Input Diode Current
DC Output Diode Current
DC Output Current
VI < GND
mA
mA
−50
V
V
V
O < GND
64
O > VCC Output at HIGH State
O > VCC Output at LOW State
mA
128
ICC
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
±64
mA
mA
°C
IGND
TSTG
±128
−65 to +150
Recommended Operating Conditions
Symbol
VCC
VI
Parameter
Min
2.7
0
Max
Units
V
Supply Voltage
3.6
5.5
−32
64
Input Voltage
V
IOH
HIGH Level Output Current
LOW Level Output Current
mA
mA
°C
IOL
TA
Free-Air Operating Temperature
−40
85
∆t/∆V
Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V
0
10
ns/V
Note 2: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.
Note 3: IO Absolute Maximum Rating must be observed.
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4
DC Electrical Characteristics
VCC
TA =−40°C to +85°C
Symbol
Parameter
Units
Conditions
II = −18 mA
(V)
2.7
Min
Max
VIK
Input Clamp Diode Voltage
−1.2
V
V
VIH
VIL
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
2.7–3.6
2.7–3.6
2.7–3.6
2.7
2.0
V
O ≤ 0.1V or
O ≥ VCC − 0.1V
0.8
V
VOH
V
CC − 0.2
2.4
V
V
IOH = −100 µA
IOH = −8 mA
IOH = −32 mA
IOL = 100 µA
IOL = 24 mA
IOL = 16 mA
IOL = 32 mA
IOL = 64 mA
3.0
2.0
V
VOL
Output LOW Voltage
2.7
0.2
0.5
V
2.7
V
3.0
0.4
V
3.0
0.5
V
3.0
0.55
V
II(HOLD)
II(OD)
II
Bushold Input Minimum Drive
3.0
75
−75
500
−500
µA
µA
µA
µA
µA
µA
µA
µA
µA
VI = 0.8V
VI = 2.0V
Bushold Input Over-Drive
Current to Change State
Input Current
3.0
(Note 4)
(Note 5)
3.6
3.6
10
±1
VI = 5.5V
Control Pins
Data Pins
VI = 0V or VCC
VI = 0V
−5
3.6
0
1
VI = VCC
IOFF
Power OFF Leakage Current
Power Up/Down 3-STATE
Output Current
±100
0V ≤ VI or VO ≤ 5.5V
IPU/PD
VO = 0.5V to 3.0V
0–1.5V
±100
µA
VI = GND or VCC
IOZL
IOZH
IOZH
3-STATE Output Leakage Current
3-STATE Output Leakage Current
3-STATE Output Leakage Current
Power Supply Current
3.6
3.6
3.6
3.6
3.6
3.6
3.6
−5
5
µA
µA
V
O = 0.0V
O = 3.6V
V
+
10
µA
VCC < VO ≤ 5.5V
ICCH
ICCL
ICCZ
0.19
5
mA
mA
mA
mA
Outputs HIGH
Power Supply Current
A or B Port Outputs LOW
Outputs Disabled
Power Supply Current
0.19
0.19
ICCZ+
Power Supply Current
VCC ≤ VO ≤ 5.5V
Outputs Disabled
∆ICC
Increase in Power Supply Current
(Note 6)
3.6
0.2
mA
One Input at VCC − 0.6V
Other Inputs at VCC or GND
Note 4: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 5: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 6: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
Dynamic Switching Characteristics (Note 7)
VCC
T
A = 25°C
Conditions
Symbol
Parameter
Units
C
L = 50 pF, RL = 500Ω
(V)
3.3
3.3
Min
Typ
0.8
Max
VOLP
VOLV
Quiet Output Maximum Dynamic VOL
Quiet Output Minimum Dynamic VOL
V
V
(Note 8)
(Note 8)
−0.8
Note 7: Characterized in SOIC package. Guaranteed parameter, but not tested.
Note 8: Max number of outputs defined as (n). n−1 data inputs are driven 0V to 3V. Output under test held LOW.
5
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AC Electrical Characteristics
TA = −40°C to +85°C
C
L = 50 pF, RL = 500Ω
Symbol
Parameter
Units
V
CC = 3.3V ± 0.3V
VCC = 2.7V
Min
Max
Min
150
1.8
1.8
1.3
1.3
1.5
1.5
1.1
1.1
2.0
2.0
1.3
1.3
1.5
1.5
3.3
1.5
2.2
0.8
Max
fMAX
Maximum Clock Frequency
150
1.8
1.8
1.3
1.3
1.5
1.5
1.1
1.1
2.0
2.0
1.3
1.3
1.5
1.5
3.3
1.2
1.6
0.8
MHz
ns
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
tW
Propagation Delay Data to Output
Clock to A or B
5.6
4.8
4.5
4.6
5.5
5.4
5.2
5.6
5.5
5.5
4.9
5.3
5.6
5.6
6.2
5.6
4.9
5.2
6.4
6.1
6.5
6.6
6.1
5.9
5.7
5.8
6.7
6.3
Propagation Delay Data to Output
Data to A or B
ns
ns
ns
ns
ns
ns
Propagation Delay Data to Output
SBA or SAB to A or B
Output Enable Time
OE to A
Output Disable Time
OE to A
Output Enable Time
OE to B
Output Disable Time
OE to B
Pulse Duration
Clock HIGH or LOW
ns
ns
tS
Setup Time
Data HIGH before CP
Data LOW before CP
Data HIGH or LOW after CP
tH
Hold Time
ns
ns
tOSHL
tOSLH
Output to Output Skew
(Note 9)
1.0
1.0
1.0
1.0
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Capacitance (Note 10)
Symbol
CIN
CI/O
Parameter
Input Capacitance
Input/Output Capacitance
Conditions
CC = 0V, VI = 0V or VCC
CC = 3.0V, VO = 0V or VCC
Typical
Units
pF
V
V
4
8
pF
Note 10: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012.
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6
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M24B
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC24
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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8
相关型号：
74LVTH652MTCX_NL
Registered Bus Transceiver, LVT Series, 1-Func, 8-Bit, True Output, BICMOS, PDSO24, 4.40 MM, MO-153, TSSOP-24
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