74LCX2244SJX [ETC]
Dual 4-Bit Non-Inverting Buffer/Driver ; 双4位非反相缓冲器/驱动器\n
| 型号： | 74LCX2244SJX |
| 厂家： | 
ETC |
| 描述： | Dual 4-Bit Non-Inverting Buffer/Driver
|
| 文件： | 总10页 (文件大小：102K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 1995
Revised March 2001
74LCX2244
Low Voltage Buffer/Line Driver with 5V Tolerant Inputs
and Outputs with 26Ω Series Resistors in the Outputs
General Description
Features
■ 5V tolerant inputs and outputs
The LCX2244 contains eight non-inverting buffers with
3-STATE outputs. The device may be employed as a mem-
ory address driver, clock driver and bus-oriented transmit-
ter/receiver. The LCX2244 is designed for low voltage
(2.5V or 3.3V) VCC applications with capability of interfac-
■ 2.3V–3.6V VCC specifications provided
■ 7.5 ns tPD max (VCC = 3.3V) 10 µA ICC max
■ Power down high impedance inputs and outputs
■ 26Ω-series resistors in the outputs
ing to a 5V signal environment. The 26Ω series resistors
help reduce output overshoot and undershoot.
■ Supports live insertion/withdrawal (Note 1)
■ ±12 mA output drive (VCC = 3.0V)
The LCX2244 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power dissipation.
■ Implements patented noise/EMI reduction circuitry
■ Latch-up performance exceeds 500 mA
■ ESD performance:
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to VCC through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number Package Number
Package Description
74LCX2244WM
74LCX2244SJ
M20B
M20D
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LCX2244MSA
74LCX2244MTC
MSA20
MTC20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
IEEE/IEC
© 2001 Fairchild Semiconductor Corporation
DS012569
www.fairchildsemi.com
Pin Descriptions
Truth Tables
Pin Names
OE1, OE2
Description
3-STATE Output Enable Inputs
I0–I7
Inputs
O0–O7
Outputs
Inputs
Outputs
OE1
(Pins 12, 14, 16, 18)
In
L
L
L
L
H
Z
H
X
H
Inputs
Outputs
OE2
(Pins 3, 5, 7, 9)
In
L
L
H
H
X
L
H
Z
H
H = HIGH Voltage Level
X = Immaterial
L = LOW Voltage Level
Z = High Impedance
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2
Absolute Maximum Ratings(Note 2)
Symbol
VCC
Parameter
Supply Voltage
Value
Conditions
Units
−0.5 to +7.0
−0.5 to +7.0
−0.5 to +7.0
V
V
VI
DC Input Voltage
VO
DC Output Voltage
Output in 3-STATE
V
−0.5 to VCC + 0.5 Output in HIGH or LOW State (Note 3)
IIK
DC Input Diode Current
DC Output Diode Current
−50
−50
VI < GND
mA
mA
IOK
V
V
O < GND
O > VCC
+50
IO
DC Output Source/Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
±50
mA
mA
mA
°C
ICC
±100
IGND
TSTG
±100
−65 to +150
Recommended Operating Conditions (Note 4)
Symbol
Parameter
Min
2.0
1.5
0
Max
3.6
3.6
5.5
VCC
5.5
±12
±8
Units
VCC
Supply Voltage
Operating
V
V
V
Data Retention
VI
Input Voltage
VO
Output Voltage
HIGH or LOW State
3-STATE
0
0
IOH/IOL
Output Current
V
V
V
CC = 3.0V − 3.6V
CC = 2.7V − 3.0V
CC = 2.3V − 2.7V
mA
±4
TA
Free-Air Operating Temperature
−40
85
°C
∆t/∆V
Input Edge Rate, VIN = 0.8V − 2.0V, VCC = 3.0V
0
10
ns/V
Note 2: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recom-
mended Operating Conditions” table will define the conditions for actual device operation.
Note 3: IO Absolute Maximum Rating must be observed.
Note 4: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
VCC
TA = −40°C to +85°C
Symbol
VIH
Parameter
Conditions
Units
(V)
2.3 − 2.7
2.7 − 3.6
2.3 − 2.7
2.7 − 3.6
2.3 − 3.6
2.3
Min
1.7
2.0
Max
HIGH Level Input Voltage
V
V
VIL
LOW Level Input Voltage
HIGH Level Output Voltage
0.7
0.8
VOH
I
I
I
I
I
I
I
I
I
I
I
I
OH = −100 µA
OH = −4 mA
OH = −4 mA
OH = −6 mA
OH = − 8mA
OH = −12 mA
OL = 100 µA
OL = 4 mA
VCC − 0.2
1.8
2.7
2.2
V
V
3.0
2.4
2.7
2.0
3.0
2.0
VOL
LOW Level Output Voltage
2.3 − 3.6
2.3
0.2
0.6
OL = 4 mA
2.7
0.4
OL = 6 mA
3.0
0.55
0.6
OL = 8 mA
2.7
OL = 12 mA
3.0
0.8
II
Input Leakage Current
0 ≤ VI ≤ 5.5V
0 ≤ VO ≤ 5.5V
VI = VIH or VIL
2.3 − 3.6
2.3 − 3.6
±5.0
±5.0
µA
µA
IOZ
3-STATE Output Leakage
3
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DC Electrical Characteristics (Continued)
VCC
TA = −40°C to +85°C
Symbol
IOFF
Parameter
Conditions
VI or VO = 5.5V
Units
µA
(V)
Min
Max
10
Power-Off Leakage Current
Quiescent Supply Current
0
ICC
VI = VCC or GND
2.3 − 3.6
2.3 − 3.6
2.3 − 3.6
10
µA
3.6V ≤ VI, VO ≤ 5.5V (Note 5)
±10
500
∆ICC
Increase in ICC per Input
VIH = VCC − 0.6V
µA
Note 5: Outputs disabled or 3-STATE only.
AC Electrical Characteristics
T
A = −40°C to +85°C, RL = 500Ω
V
CC = 3.3V ± 0.3V
V
CC = 2.7V
L = 50pF
Max
V
CC = 2.5 ± 0.2V
Symbol
Parameter
Units
CL = 50pF
C
CL = 30pF
Min
Max
Min
1.5
1.5
1.5
1.5
1.5
1.5
Min Max
tPHL
tPLH
tPZL
tPZH
tPLZ
Propagation Delay
Data to Output
1.5
1.5
1.5
1.5
1.5
1.5
7.5
7.5
9.0
9.0
7.0
7.0
1.0
1.0
8.5
8.5
1.5
1.5
1.5
1.5
1.5
1.5
9.0
9.0
ns
ns
ns
ns
Output Enable Time
10.0
10.0
8.0
10.5
10.5
8.4
Output Disable Time
tPHZ
tOSHL
tOSLH
8.0
8.4
Output to Output Skew (Note 6)
Note 6: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Dynamic Switching Characteristics
VCC
TA = 25°C
Symbol
VOLP
Parameter
Conditions
Units
(V)
3.3
2.5
3.3
2.5
Typical
0.35
Quiet Output Dynamic Peak VOL
C
C
C
C
L = 50 pF, VIH = 3.3V, VIL = 0V
L = 30 pF, VIH = 2.5V, VIL = 0V
L = 50 pF, VIH = 3.3V, VIL = 0V
L = 30 pF, VIH = 2.5V, VIL = 0V
V
V
0.25
VOLV
Quiet Output Dynamic Valley VOL
−0.35
−0.25
Capacitance
Symbol
Parameter
Conditions
CC = Open, VI = 0V or VCC
Typical
Units
pF
CIN
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
V
V
V
7
8
COUT
CPD
CC = 3.3V, VI = 0V or VCC
pF
CC = 3.3V, VI = 0V or VCC, f = 10 MHz
25
pF
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4
AC LOADING and WAVEFORMS Generic for LCX Family
FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance)
Test
tPLH, tPHL
PZL, tPLZ
Switch
Open
t
6V at VCC = 3.3 ± 0.3V
VCC x 2 at VCC = 2.5 ± 0.2V
tPZH,tPHZ
GND
3-STATE Output High Enable and
Waveform for Inverting and Non-Inverting Functions
Disable Times for Logic
Setup Time, Hold Time and Recovery Time for Logic
Propagation Delay. Pulse Width and trec Waveforms
trise and tfall
3-STATE Output Low Enable and
Disable Times for Logic
FIGURE 2. Waveforms
(Input Characteristics; f =1MHz, tr = tf = 3ns)
VCC
Symbol
3.3V ± 0.3V
1.5V
2.7V
1.5V
2.5V ± 0.2V
VCC/2
Vmi
Vmo
Vx
1.5V
1.5V
VCC/2
V
OL + 0.3V
V
OL + 0.3V
VOL + 0.15V
Vy
V
OH − 0.3V
V
OH − 0.3V
VOH − 0.15V
5
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Schematic Diagram Generic for LCX Family
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6
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
Package Number MSA20
9
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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10
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