74FST6800/D [ETC]
10-Bit Bus Switch with Precharged Outputs ; 10位总线开关与预充电输出\n
| 型号： | 74FST6800/D |
| 厂家： | 
ETC |
| 描述： | 10-Bit Bus Switch with Precharged Outputs
|
| 文件： | 总8页 (文件大小：94K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74FST6800
10-Bit Bus Switch with
Precharged Outputs
The ON Semiconductor 74FST6800 is a 10–bit bus switch with
precharged outputs. The device is CMOS TTL compatible when
operating between 4 and 5.5 Volts. The device exhibits extremely low
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R
ON
and adds nearly zero propagation delay. The device adds no noise
or ground bounce to the system.
• R t 4 W Typical
• Less Than 0.25 ns–Max Delay Through Switch
• Nearly Zero Standby Current
ON
MARKING
DIAGRAMS
24
1
• No Circuit Bounce
24
FST6800
AWLYWW
• Control Inputs are TTL/CMOS Compatible
• Pin–For–Pin Compatible With QS6800, FST6800, CBT6800
• All Popular Packages: SOIC–24, TSSOP–24, QSOP–24
1
SO–24
DW SUFFIX
CASE 751E
OE
V
B
B
B
B
B
B
B
B
B
B
1
2
3
4
5
6
7
8
9
24
23
24
CC
0
A
0
24
FST
6800
ALYW
TRUTH TABLE
A
1
22
21
20
19
18
17
16
15
14
13
1
A
2
2
1
Function
OE
B –B
0
9
A
3
3
TSSOP–24
DT SUFFIX
CASE 948H
Connect
1
L
A –A
0
9
A
4
4
A
5
5
Precharge
H
Bias V
NOTE:
A
6
6
A
7
7
H = HIGH Voltage Level
L = LOW Voltage Level
A
8
10
11
12
8
24
1
A
9
9
24
GND
BIASV
FST6800
AWLYYWW
1
QSOP–24
QS SUFFIX
CASE 492B
Figure 1. 24–Lead
Pinout
A
= Assembly Location
PIN NAMES
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
Pin
Description
OE
Bus Switch Enable
Bus A
A
B
ORDERING INFORMATION
Bus B
Device
Package
Shipping
74FST6800DW
74FST6800DWR2
74FST6800DT
SO–24
SO–24
48 Units/Rail
2500 Units/Reel
96 Units/Rail
TSSOP–24
74FST6800DTR2 TSSOP–24 2500 Units/Reel
74FST6800QS
QSOP–24
QSOP–24
96 Units/Rail
74FST6800QSR
2500 Units/Reel
Semiconductor Components Industries, LLC, 2002
1
Publication Order Number:
May, 2002 – Rev. 4
74FST6800/D
74FST6800
13
23
Bias V
2
11
1
A
A
B
0
0
14
B
9
9
OE
Figure 2. Logic Diagram
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2
74FST6800
MAXIMUM RATINGS
Symbol
Parameter
Value
*0.5 to )7.0
*0.5 to )7.0
*0.5 to )7.0
*50
Unit
V
V
V
V
DC Supply Voltage
CC
I
DC Input Voltage
V
DC Output Voltage
V
O
I
I
I
I
I
DC Input Diode Current
DC Output Diode Current
DC Output Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature Range
V t GND
mA
mA
mA
mA
mA
°C
IK
I
V
t GND
O
*50
OK
O
128
$100
CC
GND
$100
T
T
T
*65 to )150
260
STG
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
Thermal Resistance
°C
L
)150
°C
J
q
SOIC
TSSOP
QSOP
125
170
200
°C/W
JA
MSL
Moisture Sensitivity
Flammability Rating
ESD Withstand Voltage
Level 1
F
R
Oxygen Index: 28 to 34
UL 94 V–0 @ 0.125 in
V
ESD
Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
u2000
u200
N/A
V
I
Latch–Up Performance
Above V and Below GND at 85°C (Note 4)
$500
mA
LATCH–UP
CC
Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those
indicated may adversely affect device reliability. Functional operation under absolute maximum–rated conditions is not implied. Functional
operation should be restricted to the Recommended Operating Conditions.
1. Tested to EIA/JESD22–A114–A.
2. Tested to EIA/JESD22–A115–A.
3. Tested to JESD22–C101–A.
4. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
4.0
0
Max
5.5
Unit
V
V
Supply Voltage
Operating, Data Retention Only
(Note 5)
CC
I
V
V
Input Voltage
5.5
V
Output Voltage
(HIGH or LOW State)
0
5.5
V
O
T
Operating Free–Air Temperature
*40
)85
°C
ns/V
A
Dt/DV
Input Transition Rise or Fall Rate
Switch I/O
Switch Control Input
DC
5
V
= 5.0 V $ 0.5 V
0
CC
5. Unused control inputs may not be left open. All control inputs must be tied to a high or low logic input voltage level.
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3
74FST6800
DC ELECTRICAL CHARACTERISTICS
T = *405C to )855C
A
V
(V)
CC
Min
Typ*
Max
Symbol
Parameter
Conditions
Unit
V
V
IK
V
IH
V
IL
Clamp Diode Resistance
High–Level Input Voltage
Low–Level Input Voltage
Input Leakage Current
I
= *18mA
4.5
*1.2
IN
4.0 to 5.5
4.0 to 5.5
5.5
2.0
V
0.8
$1.0
$1.0
7
V
I
I
0 v V v 5.5 V
mA
mA
W
IN
I
OFF–STATE Leakage Current
Switch On Resistance (Note 6)
0 v A, B v V
5.5
OZ
CC
R
V
V
V
V
V
= 0 V, I = 64 mA
4.5
4
4
ON
IN
IN
IN
IN
IN
IN
= 0 V, I = 30 mA
4.5
7
IN
= 2.4 V, I = 15 mA
4.5
8
15
IN
= 2.4 V, I = 15 mA
4.0
11
20
IN
I
Quiescent Supply Current
= V or GND, I = 0
OUT
5.5
3
mA
CC
CC
DI
CC
Increase In I per Input
One input at 3.4 V, Other inputs at V or GND
5.5
2.5
mA
CC
CC
*Typical values are at V = 5.0 V and T = 25°C.
CC
A
6. Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower
of the voltages on the two (A or B) pins.
AC ELECTRICAL CHARACTERISTICS
T = *405C to )855C
A
C = 50 pF, RU = RD = 500 W
L
V
= 4.5–5.5 V
Max
V
= 4.0 V
CC
CC
Min
Min
Max
Symbol
, t
Parameter
Conditions
Unit
ns
t
t
Prop Delay Bus to Bus (Note 7)
V = OPEN
0.25
0.25
5.6
PHL PLH
I
, t
Output Enable Time, I to Bus A, B
Bias V = GND
1.0
1.0
5.1
ns
PZH PZL
OE
V = OPEN for t
I
PZH
t
, t
Output Disable Time, I to Bus A, B
Bias V = GND
5.5
5.5
ns
PHZ PLZ
OE
V = OPEN for t
I
PHZ
7. This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the
typical On resistance of the switch and the 50 pF load capacitance, when driven by an ideal voltage source (zero output impedance).
CAPACITANCE (Note 8)
Symbol
Parameter
Control Pin Input Capacitance
A/B Port Input/Output Capacitance
Conditions
Typ
3
Max
Unit
pF
C
C
V
V
= 5.0 V
IN
CC
, OE = 5.0 V
5
pF
I/O
CC
8. T = )25°C, f = 1 MHz, Capacitance is characterized but not tested.
A
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4
74FST6800
AC Loading and Waveforms
V
I
500 W
500 W
FROM
OUTPUT
UNDER
TEST
C *
L
NOTES:
1. Input driven by 50 W source terminated in 50 W.
2. CL includes load and stray capacitance.
*C = 50 pF
L
Figure 3. AC Test Circuit
t = 2.5 nS
f
t = 2.5 nS
f
3.0 V
GND
90 %
1.5 V
90 %
1.5 V
SWITCH
INPUT
10 %
10 %
t
t
PLH
PLH
V
OH
OL
1.5 V
1.5 V
OUTPUT
V
Figure 4. Propagation Delays
t = 2.5 nS
f
t = 2.5 nS
f
3.0 V
90 %
1.5 V
90 %
1.5 V
ENABLE
INPUT
10 %
10 %
GND
t
t
PZL
PZL
OUTPUT
1.5 V
V
+ 0.3 V
– 0.3 V
OL
V
OL
t
t
PZH
PHZL
V
OH
OH
V
1.5 V
OUTPUT
Figure 5. Enable/Disable Delays
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5
74FST6800
PACKAGE DIMENSIONS
SO–24
D SUFFIX
CASE 751E–04
ISSUE E
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
24
13
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
–B– 12X P
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
M
B
0.010 (0.25)
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
1
12
24X D
J
MILLIMETERS
INCHES
MIN
M
S
S
0.010 (0.25)
T A
B
DIM MIN
MAX
15.54
7.60
2.65
0.49
0.90
MAX
0.612
0.299
0.104
0.019
0.035
A
B
C
D
F
15.25
7.40
2.35
0.35
0.41
0.601
0.292
0.093
0.014
0.016
F
R X 45
_
G
J
1.27 BSC
0.050 BSC
0.23
0.13
0
0.32
0.29
8
0.009
0.005
0
0.013
0.011
8
C
K
K
M
P
R
–T–
SEATING
PLANE
_
_
_
_
M
10.05
0.25
10.55
0.75
0.395
0.010
0.415
0.029
22X G
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6
74FST6800
PACKAGE DIMENSIONS
TSSOP–24
DT SUFFIX
CASE 948H–01
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
24X KREF
M
S
S
V
0.10 (0.004)
T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
S
0.15 (0.006) T U
24
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
13
2X L/2
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
B
–U–
L
PIN 1
IDENT.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
12
1
7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE -W-.
S
0.15 (0.006) T U
MILLIMETERS
DIM MIN MAX
INCHES
MIN
A
–V–
MAX
0.311
0.177
0.047
0.006
0.030
A
B
7.70
4.30
---
7.90 0.303
4.50 0.169
C
1.20
---
D
0.05
0.50
0.15 0.002
0.75 0.020
F
G
H
0.65 BSC
0.026 BSC
C
0.27
0.09
0.09
0.19
0.19
0.37
0.011
0.015
0.008
0.006
0.012
0.010
J
0.20 0.004
0.16 0.004
0.30 0.007
0.25 0.007
0.10 (0.004)
J1
K
SEATING
PLANE
–T–
G
H
D
K1
L
6.40 BSC
0.252 BSC
0
M
0
8
8
_
_
_
_
N
0.25 (0.010)
K
K1
M
–W–
N
J1
DETAIL E
F
SECTION N–N
DETAIL E
J
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7
74FST6800
PACKAGE DIMENSIONS
QSOP–24
QS SUFFIX
CASE 492B–01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
–A–
Q
R
2. CONTROLLING DIMENSION: INCH.
3. THE BOTTOM PACKAGE SHALL BE BIGGER THAN
THE TOP PACKAGE BY 4 MILS (NOTE: LEAD SIDE
ONLY). BOTTOM PACKAGE DIMENSION SHALL
FOLLOW THE DIMENSION STATED IN THIS
DRAWING.
4. PLASTIC DIMENSIONS DOES NOT INCLUDE MOLD
FLASH OR PROTRUSIONS. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 6 MILS PER
SIDE.
H x 45
_
U
MOLD PIN
MARK
RAD.
0.013 X 0.005
DP. MAX
–B–
RAD.
0.005–0.010
TYP
5. BOTTOM EJECTOR PIN WILL INCLUDE THE
COUNTRY OF ORIGIN (COO) AND MOLD CAVITY I.D.
G
P
L
INCHES
DIM MAX MIN
MILLIMETERS
DETAIL E
M
MAX
8.56
3.81
1.55
0.20
0.41
MIN
8.74
3.99
1.73
0.31
0.89
0.25 (0.010)
T
A
B
C
D
F
0.337
0.150
0.061
0.008
0.016
0.344
0.157
0.068
0.012
0.035
V
G
H
J
0.025 BSC
0.64 BSC
0.008 0.018
0.0098 0.0075
0.20
0.249
0.10
5.84
0
0.46
0.191
0.25
6.20
8
N 8 PL
K
L
0.004
0.230
0
0.010
0.244
8
J
K
M
N
P
Q
R
U
V
_
_
_
_
M
0
0.027
7
0.037
0
0.69
7
0.94
_
_
_
_
0.035 DIA
0.89 DIA
–T–
SEATING
PLANE
0.035
0.035
0
0.045
0.045
8
0.89
0.89
0
1.14
1.14
8
C
24 PL D
F
_
_
_
_
M
S
S
A
0.25 (0.010)
T
B
DETAIL E
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make
changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
Literature Fulfillment:
JAPAN: ON Semiconductor, Japan Customer Focus Center
4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031
Phone: 81–3–5740–2700
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada
Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada
Email: ONlit@hibbertco.com
Email: r14525@onsemi.com
ON Semiconductor Website: http://onsemi.com
For additional information, please contact your local
Sales Representative.
N. American Technical Support: 800–282–9855 Toll Free USA/Canada
74FST6800/D
相关型号：
74FST6800DT
CBT/FST/QS/5C/B SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24, LEAD FREE, TSSOP-24
ROCHESTER
74FST6800DTR2
CBT/FST/QS/5C/B SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24, LEAD FREE, TSSOP-24
ROCHESTER
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