5962R9563801VQYC [ETC]
Radiation-Hardened MicroController; 抗辐射微控制器
| 型号： | 5962R9563801VQYC |
| 厂家： | 
ETC |
| 描述： | Radiation-Hardened MicroController |
| 文件： | 总18页 (文件大小：183K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UStaTnda6rd9PRrodHuc0ts51 Radiation-Hardened MicroController
Data Sheet
February 2000
FEATURES
q Three 16-bit timer/counters
- High speed output
- Compare/capture
- Pulse width modulator
- Watchdog timer capabilities
q Flexible clock operation
- 1Hz to 20MHz with external clock
- 2MHz to 20MHz using internal oscillator with external
crystal
q 256 bytes of on-chip data RAM
q 32 programmable I/O lines
q 7 interrupt sources
q Radiation-hardened process and design; total dose irradia-
tion testing MIL-STD-883 Method 1019
- Total dose: 1.0E6 rads(Si)
- Latchup immune
q Programmable serial channel with:
- Framing error detection
q Packaging options:
- 40-pin 100-mil center DIP (0.600 x 2.00)
- 44-lead 25-mil center Flatpack (0.670 x 0.800)
- Automatic address recognition
q TTL and CMOS compatible logic levels
q 64K external data and program memory space
q MCS-51 fully compatible instruction set
q Standard Microcircuit Drawing 5962-95638 available
- QML Q & V compliant
PORT 0
PORT 2
DRIVERS
DRIVERS
PORT 2
LATCH
PORT 0
LATCH
RAM
PROGRAM
ADDRESS
REGISTER
ACC
TMP2
B
STACK
POINTER
SPECIAL FUNCTION
REGISTERS,
TIMERS,
BUFFER
REGISTER
TMP1
PC
INCREMENTER
ALU
PSW TMP3
PCA,
SERIAL PORT
PROGRAM
COUNTER
PSEN
ALE
EA
DPTR
RST
PORT 1
LATCH
PORT 3
LATCH
OSC.
PORT 1
PORT 3
DRIVERS
DRIVERS
XTAL2
XTAL1
P3.0 - P3.7
P1.0 - P1.7
Figure 1. UT69RH051 MicroController Block Diagram
1.0 INTRODUCTION
Table 1. Port 1 Alternate Functions
The UT69RH051 is a radiation-tolerant 8-bit microcontroller
that is pin equivalent to the MCS-51 industry standard
microcontroller when in a 40-pin DIP. The UT69RH051’s static
design allows operation from 1Hz to 20MHz. This data sheet
describes hardware and software interfaces to the UT69RH051.
Port
Pin
Alternate
Name
Alternate Function
P1.0
T2
External clock input to Timer/
Counter 2
P1.1
T2EX
Timer/Counter 2 Capture/Reload
trigger and direction control
2.0 SIGNAL DESCRIPTION
V
V
: +5V Supply voltage
: Circuit Ground
P1.2
P1.3
ECI
External count input to PCA
DD
SS
CEX0
External I/O for PCA capture/
compare Module 0
Port 0 (P0.0 - P0.7): Port 0 is an 8-bit port. Port 0 pins are used
as the low-order multiplexed address and data bus during
accesses to external program and data memory. Port 0 pins use
internal pullups when emitting 1’s and are TTL compatible.
P1.4
P1.5
P1.6
P1.7
CEX1
CEX2
CEX3
CEX4
External I/O for PCA capture/
compare Module 1
External I/O for PCA capture/
compare Module 2
Port 1 (P1.0 - P1.7): Port 1 is an 8-bit bidirectional I/O port with
internal pullups. The output buffers can drive TTL loads. When
the Port 1 pins have 1’s written to them, they are pulled high by
the internal pullups and can be used as inputs in this state. As
inputs, any pins that are externally pulled low sources current
because of the pullups. In addition, Port 1 pins have the alternate
uses shown in table 1.
External I/O for PCA capture/
compare Module 3
External I/O for PCA capture/
compare Module 4
Port 2 (P2.0 - P2.7): Port 2 is an 8-bit port. Port 2 pins are used
asthehigh-orderaddressbusduringaccessestoexternalProgram
Memory and during accesses to external Data Memory that uses
16-bit addresses (i.e., MOVX@DPTR). Port 2 uses internal
pullups when emitting 1’s in this mode. During operations that
do not require a 16-bit address, Port 2 emits the contents of the
P2 Special Function Registers (SFR). The pins have internal
pullups and drives TTL loads.
Table 2. Port 3 Alternate Functions
Port
Pin
Alternate
Name
Alternate Function
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
RXD
TXD
INT0
INT1
T0
Serial port input
Serial port output
Port 3 (P3.0 - P3.7): Port 3 is an 8-bit bidirectional I/O port with
internal pullups. The output buffers can drive TTL loads. When
the Port 3 pins have 1’s written to them, they are pulled high by
the internal pullups and can be used as inputs in this state. As
inputs, any pins that are externally pulled low sources current
because of the pullups. In addition, Port 3 pins have the alternate
uses shown in table 2.
External interrupt 0
External interrupt 1
External clock input for Timer 0
External clock input for Timer 1
T1
WR
External Data Memory write
strobe
P3.7
RD
External Data Memory read strobe
2
RST: Reset Input. A high on this input for 24 oscillator periods
while the oscillator is running resets the device. All ports and
SFRs reset to their default conditions. Internal data memory is
undefined after reset. Program execution begins within 12
oscillator periods (one machine cycle) after the RST signal is
brought low. RST contains an internal pulldown resistor to allow
implementing power-up reset with only an external capacitor.
2.1 Hardware/Software Interface
2.1.1 Memory
The UT69RH051 has a separate address space for Program and
Data Memory. Internally, the UT69RH051 contains 256 bytes of
Data Memory. It addresses up to 64Kbytes of external Data
Memory and 64Kbytes of external Program Memory.
2.1.1.1 Program Memory
There is no internal program memory in the UT69RH051. All
program memory is accessed as external through ports P0 and
ALE: Address Latch Enable. The ALE output is a pulse for
latching the low byte of the address during accesses to external
memory. Innormaloperation, theALEpulseisoutputeverysixth
oscillator cycle and may be used for external timing or clocking.
However, during each access to external Data Memory (MOVX
instruction), one ALE pulse is skipped.
P2. The EA pin must be tied to V (ground) to enable access to
SS
external locations 0000 through 7FFF . Following reset, the
H
H
UT69RH051 fetches the first instruction at address 0000h.
2.1.1.2 Data Memory
PSEN: Program Store Enable. This active low signal is the read
strobe to the external program memory. PSEN activates every
sixth oscillator cycle except that two PSEN activations are
skipped during external data memory accesses.
The UT69RH051 implements 256 bytes of internal data RAM.
The upper 128 bytes of this RAM occupy a parallel address space
to the SFRs. The CPU determines if the internal access to an
address above 7F is to the upper 128 bytes of RAM or to the
H
EA: External Access Enable. This pin should be strapped to V
(Ground) for the UT69RH051.
SS
SFR space by the addressing mode of the instruction. If direct
addressing is used, the access is to the SFR space. If indirect
addressing is used, the access is to the internal RAM. Stack
operations are indirectly addressed so the upper portion of RAM
can be used as stack space. Figure 3 shows the organization of
the internal Data Memory.
XTAL1: Input to the inverting oscillator amplifier.
XTAL2: Output from the inverting oscillator amplifier.
The first 32 bytes are reserved for four register banks of eight
bytes each. The processor uses one of the four banks as its
working registers depending on the RS1 and RS0 bits in the PSW
SFR. At reset, bank 0 is selected. If four register banks are not
required, use the unused banks as general purpose scratch pad
memory. The next 16 bytes (128 bits) are individually bit
addressable. The remaining bytes are byte addressable and can
be used as general purpose scratch pad memory. For addresses 0
- 7F , use either direct or indirect addressing. For addresses
H
larger than 7F , use only indirect addressing.
H
In addition to the internal Data Memory, the processor can access
64Kbytes of external Data Memory. The MOVX instruction
accesses external Data Memory.
2.1.2 Special Function Registers
Table 3 contains the SFR memory map. Unoccupied addresses
are not implemented on the device. Read accesses to these
addresses will return unknown values and write accesses will
have no effect.
3
(T2)
(T2EX)
(ECI)
(CEX0)
(CEX1)
(CEX2)
(CEX3)
(CEX4)
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDD
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
EA
ALE
PSEN
P2.7
P2.6
P2.5
P2.4
(AD0)
(AD1)
(AD2)
(AD3)
(AD4)
(AD5)
(AD6)
(AD7)
(RXD)
(TXD)
(INT0)
(INT1)
(T0)
(T1)
(WR)
(A15)
(A14)
(A13)
(A12)
(A11)
(A10)
(A9)
(RD)
P3.7
XTAL2
XTAL1
VSS
17
18
19
20
24
23
22
21
P2.3
P2.2
P2.1
P2.0
(A8)
Figure 2a. UT69RH051 40-Pin DIP Connections
VDD
VSS
P1.0
P1.1
NC
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
P3.0
P3.1
P3.2
1
2
3
4
5
6
7
44
43
42
41
40
39
38
37
36
35
34
33
32
31
(T2)
(T2EX)
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
EA
ALE
PSEN
P2.7
P2.6
(AD0)
(AD1)
(AD2)
(AD3)
(AD4)
(AD5)
(AD6)
(AD7)
(ECI)
(CEX0)
(CEX1)
(CEX2)
(CEX3)
(CEX4)
8
9
10
11
12
13
14
(RXD)
(TXD)
(INTO)
(INT1)
(TO)
(T1)
(A15)
(A14)
(A13)
(A12)
(A11)
(A10)
(A9)
P3.3
P3.4
P3.5
P3.6
P3.7
XTAL2
XTAL1
VSS
15
16
17
18
19
20
21
22
30
29
28
27
26
25
24
23
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
NC
(WR)
(RD)
(A8)
VDD
Figure 2b. UT69RH051 44-Pin Flatpack Connections
4
8 BYTES
F8
F0
FF
F7
INDIRECT
ACCESS
ONLY
·
·
·
·
·
·
88
8F
SCRATCH
PAD AREA
80
87
78
70
7F
77
·
·
·
·
·
·
38
3F
DIRECT OR
INDIRECT
ACCESS
30
37
BIT
28
20
18
10
08
00
2F
27
1F
17
0F
07
ADDRESSABLE
SEGMENT
REGISTER
BANKS
Figure 3. Internal Data Memory Organization
2.1.3 Reset
While RST is high,PSEN and the port pins are pulled high; ALE
is pulled low. All SFRs are reset to their reset values as shown
in table 3. The internal Data Memory content is indeterminate.
The reset input is the RST pin. To reset, hold the RST pin high
for a minimum of 24 oscillator periods while the oscillator is
running. The CPU generates an internal reset from the external
signal. The port pins are driven to the reset state as soon as a valid
high is detected on the RST pin.
The processor will begin operation one machine cycle after the
RST line is brought low. A memory access occurs immediately
after the RST line is brought low, but the data is not brought into
the processor. The memory access repeats on the next machine
cycle and actual processing begins at that time.
5
Table 3. SFR Memory Registers
CCAP0H CCAP1H CCAP2H CCAP3H
F8
F0
E8
E0
D8
D0
C8
C0
B8
B0
A8
A0
98
CH
00000000
CCAP4H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
FF
F7
EF
E7
DF
D7
CF
C7
BF
B7
AF
A7
9F
97
B
00000000
CL
00000000
CCAP0L
CCAP1L
CCAP2L
CCAP3L
CCAP4L
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
ACC
00000000
CCON
00X00000
CMOD
OOXXX000
CCAPM0
CCAPM1
CCAPM2
CCAPM3
CCAPM4
X00000000
X00000000
X00000000
X00000000
X00000000
PSW
00000000
T2CON
00000000
T2MOD
XXXXXX00
RCAP2L
00000000
RCAP2H
00000000
TL2
00000000
TH2
00000000
IP
SADEN
00000000
X0000000
P3
11111111
IPH
X00000000
IE
SADDR
00000000
00000000
P2
11111111
SCON
00000000
SBUF
XXXXXXXX
90
P1
11111111
88
TCON
00000000
TMOD
00000000
TL0
00000000
TL1
00000000
TH0
00000000
TH1
00000000
8F
87
80
P0
SP
DPL
DPH
PCON
11111111
00000111
00000000
00000000
00XX00XX
Notes:
1. Values shown are the reset values of the registers.
2. X = undefined.
6
3.0 RADIATION HARDNESS
circuit density and reliability. For transient radiation hardness
and latchup immunity, UTMC builds all radiation-hardened
products on epitaxial wafers using an advanced twin-tub CMOS
process. In addition, UTMC pays special attention to power and
ground distribution during the design phase, minimizing dose-
rate upset caused by rail collapse.
The UT69RH051 incorporates special design and layout features
which allow operation in high-level radiation environments.
UTMC has developed special low-temperature processing
techniques designed to enhance the total-dose radiation hardness
of both the gate oxide and the field oxide while maintaining the
1
RADIATION HARDNESS DESIGN SPECIFICATIONS
Total Dose
1.0E6
14
rad(Si)
2
LET Threshold
MeV-cm /mg
2
Neutron Fluence
1.0E14
1E-4
n/cm
2
Saturated Cross-Section (1Kx8)
Single Event Upset
cm /device
2
1.3E-7
errors/device-day
1
2
LET>128
Single Event Latchup
MeV-cm /mg
Note:
1. Worst case temperature TA = +125°C.
2. Adams 90% worst case environment (geosynchronous).
1
4.0 ABSOLUTE MAXIMUM RATINGS
(Referenced to V
)
SS
SYMBOL
PARAMETER
DC Supply Voltage
LIMITS
UNITS
V
-0.5 to 7.0
V
DD
V
Voltage on Any Pin
-0.5 to V +0.3V
V
°C
I/O
DD
T
Storage Temperature
-65 to +150
STG
P
Maximum Power Dissipation
Maximum Junction Temperature
750
175
10
mW
°C
D
T
J
2
Q
°C/W
mA
JC
Thermal Resistance, Junction-to-Case
DC Input Current
I
±10
I
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2. Test per MIL-STD-883, Method 1012.
7
5.0 DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*
V
= 5.0V ±10%; TA = -55°C < T < +125°C)
C
DD
SYMBOL
PARAMETER
CONDITION
MINIMUM
MAXIMUM
UNIT
V
V
Low-level Input Voltage
0.8
IL
V
High-level Input Voltage
(except XTAL, RST)
2.0
V
IH
V
High-level Input Voltage
(XTAL)
3.85
V
V
IH1
1
V
I
= 100mA
0.3
OL
Low-level Output Voltage
(Ports 1, 2 and 3)
OL
I
I
I
= 1.6mA
= 3.5mA
= 200mA
0.45
1.0
V
V
V
OL
OL
OL
1,2
V
0.3
OL1
Low-level Output Voltage
(Port 0, ALE, PSEN, PROG)
I
I
I
= 3.2mA
= 7.0mA
= -10mA
0.45
1.0
V
V
V
OL
OL
OH
3
V
4.2
OH
High-level Output Voltage
(Ports 1, 2, and 3
ALE and PSEN)
I
I
I
= -30mA
= -60mA
= -200mA
3.8
3.0
4.2
V
V
V
OH
OH
OH
V
High-level Output Voltage
OH1
(Port 0 in External Bus Mode)
I
I
= -3.2mA
= -7.0mA
= 0.0V
3.8
3.0
V
V
OH
OH
I
Logical 0 Input Current
(Ports 1, 2, and 3)
V
V
V
V
V
V
V
V
-50
-65
mA
IL
IL
LI
LI
IN
= 5.5V
CC
I
Logical 0 Input Current
(XTAL 1)
= 0.0V
-65
mA
mA
mA
IN
= 5.5V
CC
IN
I
I
Input Leakage Current
(Port 0)
= 0.0V or V
= 5.5V
±25
±65
CC
CC
CC
Input Leakage Current
(XTAL1)
= 0.0V or V
= 5.5V
±65
IN
CC
4
Pin Capacitance
@ 1MHZ, 25°C
15
pF
C
IO
I
Power Supply Current:
@16MHz
@20 MHz
95
120
mA
DD
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883.
1. Under steady state (non-transient) conditions, IOL must be limited externally as follows:
Maximum IOL per port pin:
Maximum IOL per 8-bit port-
10mA
Port 0: 26mA
Ports 1, 2, & 3: 15mA
Maximum total IOL for all output pins: 71mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.
2. Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE and ports 1 and 3. The noise is due to external bus
capacitance discharging into the port 0 and port 2 pins when these pins make 1 to 0 transitions during bus operations. In applications where capacitance loading
exceeds 100 pF, the noise pulse on the ALE may exceed 0.8V. In these cases, it may be desirable to qualify ALE with a schmitt trigger or use an address latch
with a schmitt trigger strobe input.
3. Capacitive loading ports 0 and 2 cause the VOH on ALE and PSEN to drop below the VDD-0.3 specification when the address lines are stabilizing.
4. Capacitance measured for initial qualification or design changes which may affect the value.
8
VDD
IDD
VDD
VDD
VDD
P0
RST
EA
(NC)
XTAL2
XTAL1
VSS
CLOCK
SIGNAL
GND
tCLCH = tCHCL = 5ns
Figure 4. I Test Condition, Active Mode
DD
All other pins
disconnected
VDD -0.5
0.45V
0.7 VDD
0.2 VDD -0.1
tCHCX
tCLCH
tCHCX
tCHCL
tCLCL
Figure 5. Clock Signal Waveform for I Tests in Active and Idle Modes
DD
t
= t
= 5ns
CLCH
CHCL
9
6.0 AC CHARACTERISTICS READ CYCLE (Post-Radiation)*
(V = 5.0V ±10%; -55°C < T < +125°C)
DD
C
SYMBOL
PARAMETER
MINIMUM
MAXIMUM
UNIT
t
Clock Period
50
ns
CLCL
1/t
Oscillator Frequency
20
MHz
ns
CLCL
LHLL
t
t
ALE Pulse Width
2 t
-40
CLCL
Address Valid to ALE Low
Address Hold after ALE Low
t
-40
ns
AVLL
1
CLCL
CLCL
t
-30
ns
t
LLAX
t
ALE Low to Valid Instruction
ALE Low to PSEN Low
4 t
3 t
-100
-105
ns
ns
ns
ns
ns
LLIV
LLPL
PLPH
CLCL
CLCL
t
t
t
-30
CLCL
PSEN Pulse Width
3 t
-45
CLCL
t
PSEN Low to Valid Instruction In
Input Instruction Hold after PSEN
PLIV
1
0
t
PXIX
1
Input Instruction Float after PSEN
t
-25
ns
CLCL
t
PXIZ
t
Address to Valid Instruction In
PSEN Low to Address Float
5 t
-105
ns
ns
AVIV
CLCL
1
10
t
PLAZ
t
RD Pulse Width
6 t
6 t
-100
-100
ns
ns
ns
ns
RLRH
CLCL
CLCL
t
WR Pulse Width
WLWH
t
RD Low to Valid Data In
Data Hold After RD High
5 t
CLCL
-165
RLDV
1
0
t
RHDX
1
Data Float After RD High
2 t
-60
ns
CLCL
t
RHDZ
t
ALE Low Valid Data In
Address to Valid Data In
ALE Low to RD or WR Low
Address Valid to WR Low
Data Valid Before WR High
Data Hold After WR High
Data Valid to WR High
8 t
9 t
-150
-165
ns
ns
ns
ns
ns
ns
ns
LLDV
CLCL
CLCL
t
AVDV
LLWL
AVWL
t
3 t
-50
3 t
+50
CLCL
CLCL
t
4 t
-130
CLCL
t
t
t
t
-33
-33
QVWX
WHQX
CLCL
CLCL
7 t
-150
CLCL
t
t
QVWH
1
RD Low to Address Float
0
ns
ns
RLAZ
t
RD or WR High to ALE High
t
-40
t
+40
CLCL
WHLH
CLCL
Note:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 at 1.0E6 rads(Si).
1. Guaranteed, but not tested.
10
tLHLL
ALE
tLLPL
tAVLL
tPLPH
tLLIV
tPLIV
PSEN
tPXIZ
tPLAZ
tLLAX
tPXIX
INSTR IN
A0 - A7
A0 - A7
PORT 0
tAVIV
A8 - A15
A8 - A15
PORT 2
Figure 6. External Program Memory Read Timing Waveforms
ALE
tLHLL
tWHLH
tLLDV
PSEN
RD
tRLRH
tLLWL
tRLDV
tLLAX
tAVLL
tRHDZ
tRHDX
tRLAZ
A0 -A7 FROM RI OR DPL
DATA IN
A0 - A7 FROM PCL
INSTR IN
PORT 0
PORT 2
tAVWL
tAVDV
P2.0 - P2.7 OR A8 -A15 FROM DPH
A8 - A15 FROM PCH
Figure 7. External Data Memory Read Cycle Waveforms
ALE
tLHLL
tWHLH
PSEN
WR
tLLWL
tQVWX
tWLWH
tAVLL
tWHQX
tLLAX
tQVWH
INSTR IN
A0 -A7 FROM RI OR DPL
DATA OUT
A0 - A7 FROM PCL
PORT 0
PORT 2
tAVWL
P2.0 - P2.7 OR A8 -A15 FROM DPH
A8 - A15 FROM PCH
Figure 8. External Data Memory Write Cycle Waveforms
11
7.0 SERIAL PORT TIMING CHARACTERISTICS
(V = 5.0V ±10%; -55°C < T < +125°C)
DD
C
SYMBOL
PARAMETER
MINIMUM
12 t -10
MAXIMUM
12 t +10
UNIT
1
Serial Port Clock Period
ns
CLCL
CLCL
t
XLXL
t
Output Data Setup to Clock Rising Edge
Output Data Hold after Clock Rising Edge
Input Data Hold after Clock Rising Edge
10 t
2 t
-133
-70
ns
ns
ns
QVXH
XHQX
CLCL
t
CLCL
1
0
t
XHDX
t
Clock Rising Edge to Input Data Valid
10 t
-133
ns
XHDV
CLCL
Note:
1. Guaranteed, but not tested.
0
1
2
3
4
5
6
7
8
ALE
TXLXL
CLOCK
TXHQX
TQVXH
OUTPUT DATA
0
1
2
3
4
5
6
7
(WRITE TO SBUF)
TXHDX
SET TI
TXHDV
INPUT DATA
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
(CLEAR RI)
SET RI
Figure 9. Serial Port Timing Waveforms
8.0 EXTERNAL CLOCK DRIVE TIMING CHARACTERISTICS
SYMBOL PARAMETER
Oscillator Frequency
MINIMUM
MAXIMUM
UNIT
1/t
20
MHz
CLCL
t
High Time
Low Time
Rise Time
Fall Time
16
16
ns
ns
ns
ns
CHCX
t
t
t
CLCX
CLCH
CHCL
20
20
Note:
1. Guaranteed, but not tested.
VDD - 0.5
0.7 VDD
0.2 VDD - 0.1
0.45 V
tCHCX
tCHCX
tCHCL
tCLCH
tCLCL
Figure 10. External Clock Drive Timing Waveforms
12
9.0 PACKAGING
E
0.595+0.010
S2
0.005 MIN. typ.
S1
0.005 MIN. TYP.
e
0.100
D
2.000 +0.025
b
0.018 +0.002
L
PIN 1 I.D.
(Geometry OPTIONAL)
A
0.200
0.125
0.185 MAX.
TOP VIEW
SIDE VIEW
Notes:
C
1. All package finishes are per MIL-PRF-38535.
2. Letter designations are for cross-reference MIL-STD-1835.
+ 0.002
0.010
- 0.001
0.600
END VIEW
Figure 11. 40-pin Side-Brazed DIP
13
C
Notes:
1. All exposed metalized areas to be plated per MIL-PRF-38535.
2. Dimension letters refer to MIL-STD-1835.
Figure 12. 44-Lead Flatpack
14
APPENDIX A
Difference Between Industry Standard and UT69RH051
The areas in which the UT69RH051 differs from the industry
2.0 POWER SAVING MODES OF OPERATION
2.1 Idle Mode
standard will be covered in this section. In this discussion,
industry standard will be used generically to refer to all speed
grades including the 20MHz.
Idle mode and the corresponding control bit in the PCON SFR
have not been implemented in the UT69RH051. Setting the idle
control bit has no effect.
1.0 RESET
The UT69RH051 requires the RST input to be held high for at
least 24 oscillator periods to guarantee the reset is completed in
the chip. Also, the port pins are reset asynchronously as soon as
the RST pin is pulled high. On the UT69RH051 all portions of
the chip are reset synchronously when the RST pin is high during
a rising edge of the input clock. When coming out of reset, the
industry standard takes 1 to 2 machine cycles to begin driving
ALE and PSEN immediately after the RST is removed, but the
access during the first machine cycle after reset is ignored by the
processor. The second cycle will repeat the access and processing
will begin.
2.2 Power Down Mode
PowerdownmodeandthecorrespondingcontrolbitinthePCON
register have not been implemented in the UT69RH051. Setting
the power down control bit has no effect. Also, the Power Off
Flag in the PCON has not been implemented.
3.0 ON CIRCUIT EMULATION
The On Circuit Emulation mode of operation in the industry
standard has not been implemented in the UT69RH051.
4.0 OPERATING CONDITIONS
The operating voltage range for the industry standard is
5V+20%. The operating temperature range is 0°C to 70°C. On
the UT69RH051, the operating voltage range is 5V+10%. The
operating temperature range is -55°C to +125°C.
15
APPENDIX B
Impact of External Program ROM
The 8051 family of microcontrollers, including the industry
standards, use ports 0 and 2 to access external memory. In
implementations with external program memory, these two ports
are dedicated to the program ROM interface and can not be used
as Input/Output ports. The UT69RH051 uses external program
ROM, so ports 0 and 2 will not be available for I/O.
16
ORDERING INFORMATION
UT69RH051 Microcontroller: SMD
5962
* 95638 *
*
*
*
Lead Finish:
(A)
(C)
=
=
Solder
Gold
(X)
=
Optional
Case Outline:
(Q)
(Y)
=
=
40-pin DIP
44-pin Flatpack
Class Designator:
(Q)
(V)
=
=
Class Q
Class V
Device Type
(01) = 8-bit Microcontroller
Drawing Number: 95638
Total Dose:
(H)
(G)
(F)
(R)
=
=
=
=
1E6 rads(Si)
5E5 rads(Si)
3E5 rads(Si)
1E5 rads(Si)
Federal Stock Class Designator: No options
Notes:
1. Lead finish (A, C, or X) must be specified.
2. If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening.
17
UT69RH051 Microcontroller
UT **** *** - * * * *
Total Dose:
( ) None
=
Lead Finish:
(A)
(C)
(X)
=
=
=
Solder
Gold
Optional
Screening:
(C)
(P)
=
=
Mil Temp
Prototype
Package Type:
(P) 40-pin DIP
=
(W) = 44-pin Flatpack
Device Type:
(UT69RH051) = 8-bit Microcontroller
Notes:
1. Lead finish (A,C, or X) must be specified.
2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Radiation characteristics are neither tested nor guaranteed and may not be specified.
4. Devices have prototype assembly and are tested at 25°C only. Radiation characteristics are neither tested nor guaranteed and may not be specified.
18
相关型号：
5962R9566301VXC
HCT SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDFP14, CERAMIC, DFP-14
RENESAS
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