5962F9211804QYA [ETC]
Controller Miscellaneous - Datasheet Reference ; 控制器杂项 - 数据表参考\n
| 型号： | 5962F9211804QYA |
| 厂家： | 
ETC |
| 描述： | Controller Miscellaneous - Datasheet Reference
|
| 文件： | 总55页 (文件大小：354K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
REVISIONS
LTR
A
DESCRIPTION
Changes in accordance with NOR 5962-R208-93.
Changes in accordance with NOR 5962-R187-94.
Add device type 02. Editorial changes throughout.
Changes in accordance with NOR 5962-R299-97.
DATE (YR-MO-DA)
93-08-06
APPROVED
Monica L. Poelking
Monica L. Poelking
Monica L. Poelking
Monica L. Poelking
Monica L. Poelking
Monica L. Poelking
B
94-06-08
C
96-01-05
D
97-05-29
E
Add device type 03. Editorial changes throughout. - TVN
98-06-29
F
In table IA: Add test conditions for IIN; change the limits for QIDD; remove the test
condition VDD = 4.5 V for all the propagation delay tests; change the limits for ta
and ti in memory read timing section; change the limits of tc in DMA timing
section; and change the limit of ta in JTAG timing section. Include pin connections
for case outlines X and Z in radiation exposure connections. Editorial changes
throughout. - TVN
98-09-18
G
In table I, change IIN limits; add a footnote to QIDD; add tc in power-up master reset
timing section. Correct the JTAG timing waveforms. – TVN
99-05-26
Monica L. Poelking
H
J
Add device type 04. Editorial changes throughout. – TVN
00-07-18
01-03-15
Monica L. Poelking
Thomas M. Hess
Add notes to memory write and memory read waveforms. Add figure B-1 to
appendix A. Editorial changes throughout. – TVN
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PREPARED BY
Thomas M. Hess
PMIC N/A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216
CHECKED BY
Thomas M. Hess
http://www.dscc.dla.mil
STANDARD
MICROCIRCUIT
DRAWING
APPROVED BY
Monica L. Poelking
MICROCIRCUIT, DIGITAL, CMOS, MIL-STD-1553
SERIAL MICROCODED MONOLITHIC MULTI-MODE
INTELLIGENT TERMINAL, MONOLITHIC SILICON
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DRAWING APPROVAL DATE
93-06-07
DEPARTMENTS
REVISION LEVEL
SIZE
CAGE CODE
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
5962-92118
A
67268
J
AMSC N/A
SHEET
1
OF
45
DSCC FORM 2233
APR 97
5962-E271-01
DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.
1. SCOPE
1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and
M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the
Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the
PIN.
1.2 PIN. The PIN is as shown in the following example:
5962
H
92118
01
V
X
X
Federal
stock class
designator
\
RHA
designator
(see 1.2.1)
Device
type
(see 1.2.2)
Device
class
designator
(see 1.2.3)
Case
outline
(see 1.2.4)
Lead
finish
(see 1.2.5)
/
\/
Drawing number
1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and
are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A
specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type
Generic number
Circuit function
01
02
UT69151
UT69151E
MIL-STD-1553 bus controller, remote terminal, monitor interface
MIL-STD-1553 bus controller, remote terminal, monitor interface
radiation hardened
03
04
UT69151E
UT69151E
MIL-STD-1553 bus controller, remote terminal, monitor interface
MIL-STD-1553 bus controller, remote terminal, monitor interface
radiation hardened
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as
follows:
Device class
M
Device requirements documentation
Vendor self-certification to the requirements for MIL-STD-883 compliant,
non-JAN class level B microcircuits in accordance with MIL-PRF-38535,
appendix A
Q or V
Certification and qualification to MIL-PRF-38535
1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter
Descriptive designator
Terminals
Package style
X
Y
Z
CMGA3-P84
See figure 1
See figure 1
84
84
132
Pin grid array
Leaded chip carrier
Leaded chip carrier with unformed
leads, nonconductive tier bar
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535,
appendix A for device class M.
SIZE
STANDARD
5962-92118
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
SHEET
H
2
DSCC FORM 2234
APR 97
1.3 Absolute maximum ratings. 1/
Supply voltage range (VDD).............................................................................. -0.3 V dc to +7.0 V dc
Voltage on any pin .......................................................................................... -0.3 V dc to VCC + 0.3 V dc
Latchup immunity (ILU) .................................................................................... ±150 mA
DC input current (II)......................................................................................... ±10 mA
Maximum power dissipation (PD)..................................................................... 2.5 W
Storage temperature range (TSTG).................................................................... -65°C to +150°C
Lead temperature (soldering, 5 seconds)......................................................... +300°C
Thermal resistance, junction-to-case (QJC)....................................................... 15°C/W
Maximum junction temperature (TJ)................................................................. 175°C
1.4 Recommended operating conditions.
Supply voltage range (VDD).............................................................................. +4.5 V dc to +5.5 V dc
DC input voltage (VIN)...................................................................................... 0 V dc to VDD
Maximum input voltage (VIL) ............................................................................ 0.8 V dc
Maximum input voltage, 24 MHz input (VILC).................................................... 0.3 VDD
Minimum input voltage (VIH) ............................................................................ 2.2 V dc
Minimum input voltage, 24 MHz input (VIHC) .................................................... 0.7 VDD
Operating frequency (fIN) ................................................................................. 24 ±0.01% MHz
Duty cycle (DC)................................................................................................ 50 ±5%
Case operating temperature range (TC) ........................................................... -55°C to +125°C
Radiation features:
Total dose:
Device type 02...................................................................................... ³ 1 x 106 Rads (Si)
Device type 04...................................................................................... = 300k Rads (Si)
Single event phenomenon (SEP) effective
LET, no upsets:
Device type 02............................................................................... = 47 MeV/(mg/cm2)
Device type 04............................................................................... < 14.4 MeV/(mg/cm2)
LET, no latchup:
Device type 02............................................................................... > 136 MeV/(mg/cm2)
Device type 04............................................................................... > 128 MeV/(mg/cm2)
Dose rate upset (20 ns pulse) .................................................................... 2/
Dose rate latchup ...................................................................................... 2/
Dose rate survivability ............................................................................... 2/
Neutron irradiated...................................................................................... 2/
1.5 Digital logic testing for device classes Q and V.
Fault coverage measurement of manufacturing
logic tests (MIL-STD-883, test method 5012) ................................................ 95.12 percent
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a
part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed
in the issue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, cited in
the solicitation.
1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
2/ When characterized as a result of the procuring activities request, the condition will be specified.
SIZE
STANDARD
5962-92118
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
SHEET
H
3
DSCC FORM 2234
APR 97
SPECIFICATION
DEPARTMENT OF DEFENSE
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
STANDARDS
DEPARTMENT OF DEFENSE
MIL-STD-883
-
Test Methods and Procedures for Microelectronics.
MIL-STD-1835 - Interface Standard Electronic Component Case Outlines.
HANDBOOKS
DEPARTMENT OF DEFENSE
MIL-HDBK-103 - List of Standard Microcircuit Drawings (SMD's).
MIL-HDBK-780 - Standard Microcircuit Drawings.
(Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the Standardization
Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein.
Unless otherwise specified, the issues of the documents which are DOD adopted are those listed in the issue of the DODISS
cited in the solicitation. Unless otherwise specified, the issues of documents not listed in the DODISS are the issues of the
documents cited in the solicitation.
INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS (IEEE)
IEEE Standard 1149.1 - IEEE Standard Test Access Port and Boundary Scan Architecture.
(Applications for copies should be addressed to the Institute of Electrical and Electronics Engineers, 445 Hoes Lane,
Piscataway, NJ 08854-4150.)
(Non-Government standards and other publications are normally available from the organizations that prepare or distribute
the documents. These documents may also be available in or through libraries or other informational sevices.)
2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for
device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified
herein.
3.1.1 Microcircuit die. For the requirements for microcircuit die, see appendix A to this document.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as
specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class
M.
SIZE
STANDARD
5962-92118
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
SHEET
H
4
DSCC FORM 2234
APR 97
3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 and figure 1 herein.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2.
3.2.3 Block diagram. The block diagram shall be as specified on figure 3.
3.2.4 Boundary scan instruction codes. The boundary scan instruction codes shall be as specified on figure 4.
3.2.5 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figures 5
through 13.
3.2.6 Radiation exposure connections. The radiation exposure connecttions shall be as specified on figure 14.
3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and postirradiation parameter limits are as specified in table IA and shall apply over the
full case operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The
electrical tests for each subgroup are defined in table IA.
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked as listed in MIL-HDBK-103. For packages where marking of the entire SMD PIN number is not feasible due to space
limitations, the manufacturer has the option of not marking the "5962-" on the device. For RHA product using this option, the
RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535.
Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A.
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required
in MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.
3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate
of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103
(see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for
this drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-
38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or
for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing.
3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2
herein) involving devices acquired to this drawing is required for any change as defined in MIL-PRF-38535, appendix A.
3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain
the option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made
available onshore at the option of the reviewer.
3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in
microcircuit group number 105 (see MIL-PRF-38535, appendix A).
3.11 IEEE 1149.1 compliance. Theses devices shall be compliant with IEEE 1149.1.
SIZE
STANDARD
5962-92118
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
SHEET
H
5
DSCC FORM 2234
APR 97
TABLE IA. Electrical performance characteristics.
Test
Symbol
Test conditions 1/
-55°C £ TC £ +125°C
4.5 V £ VDD £ 5.5 V
Device
type
Group A
subgroups
Limits
Unit
V
Min
Max
0.8
unless otherwise specified
Low level input voltage,
except TCK input
VIL1
VIL2
All
1, 2, 3
1, 2, 3
Low level input voltage,
TCK input only
01, 02
04
0.8
0.7
03
All
All
All
All
High level input voltage
Low level input voltage
High level intput voltage
VIH
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
2.2
VILC
VIHC
VOL
24 MHz input only
0.3VDD
0.7VDD
Low level output
voltage
Outputs loads IOL = 4.0 mA
IOL = 1.0 mA 2/
0.4
0.05
High level output
voltage
VOH
Outputs loads IOH = 4.0 mA
IOH = 1.0 mA 2/
All
1, 2, 3
2.4
VDD-0.05
-10
mA
mA
Input leakage current
IIN
TTL driven
inputs
VIN = VDD
or VSS
All
All
1, 2, 3
1, 2, 3
+10
Inputs with
pull-up
resistors
VIN = VDD
VIN = VSS
-10
+10
01, 02
04
-900
-150
03
All
-167
-10
-27
Three-state output
leakage current, TTL
loaded outputs
IOZ
Single-drive buffer
VO = VDD or VSS
1, 2, 3
1, 2, 3
+10
Short-circuit output
current, output loads
IOS
2/ 3/
Single-drive buffer
VDD = 5.5 V, VO = 0 V
All
-100
+100
mA
pF
Input capacitance
CIN
f = 1 MHz at 0 V
See 4.4.1c
All
All
All
4
4
4
15
15
25
Output capacitance
COUT
CIO
Bidirectional
capacitance
Quiescent current
4/
QIDD
f = 0 MHz 5/
01, 02
03
1, 3
2
35
1
mA
mA
mA
Pre-irradiation
level R
04
04
1, 3
2
35
1
mA
mA
Pre-irradiation
level F
1, 3
2
35
5
mA
mA
Standby operating
current
SIDD
f = 24 MHz
See 4.4.1b
All
All
1, 2, 3
40
Functional tests
7, 8
See footnotes at end of table.
SIZE
STANDARD
5962-92118
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
SHEET
H
6
DSCC FORM 2234
APR 97
TABLE IA. Electrical performance characteristics - Continued.
Test
Symbol
Test conditions 1/
-55°C £ TC £ +125°C
4.5 V £ VDD £ 5.5 V
Device
type
Group A
subgroups
Limits
Unit
ns
Min
Max
unless otherwise specified
Register write timing
Address setup time 6/
Data setup time 6/
Data hold time 6/
ta
tb
tc
td
te
CL = 35 pF minimum
See figures 5 and 12
All
All
All
All
All
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
0
10
8
Address hold time 6/
8
105
CS (L) to CS (H) 6/
Access delay 6/ 7/ 8/
tf
All
All
9, 10, 11
9, 10, 11
85
0
tg
RD/ WR assertion to
CS assertion 2/
th
All
9, 10, 11
0
CS negation to
RD/ WR negation 2/
tI
tj
All
All
9, 10, 11
9, 10, 11
0
5
40
35
CS assertion to output
enable 6/
CS negation to output
three-state 2/
Register read timing
Address setup time 6/
ta
tb
CL = 35 pF minimum
See figures 6 and 12
All
All
9, 10, 11
9, 10, 11
0
5
ns
95
35
CS assertion to output
enable data valid 6/
tc
All
9, 10, 11
CS negation to output
disabled 2/
Address hold time 6/
td
te
All
All
9, 10, 11
9, 10, 11
0
0
40
CS assertion to output
enable data invalid 6/
Access delay 6/ 7/ 8/
CS (L) to CS (H) 2/
tf
All
All
9, 10, 11
9, 10, 11
45
tg
105
Memory write timing
Address propagation
delay
ta
CL = 35 pF minimum
See figures 7 and 12
01, 02
04
9, 10, 11
0
18
ns
03
All
9, 10, 11
9, 10, 11
0
21
35
tb
15
Address valid to RCS ,
RWR assertion 6/
See footnotes at end of table.
SIZE
STANDARD
5962-92118
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
SHEET
H
7
DSCC FORM 2234
APR 97
TABLE IA. Electrical performance characteristics - Continued.
Test
Symbol
Test conditions 1/
-55°C £ TC £ +125°C
4.5 V £ VDD £ 5.5 V
Device
type
Group A
subgroups
Limits
Unit
ns
Min
Max
50
unless otherwise specified
Memory write timing – Continued
tc
td
CL = 35 pF minimum
See figures 7 and 12
All
All
9, 10, 11
9, 10, 11
10
20
DTACK setup time 6/
RCS and RWR hold
time 6/ 9/
Data propagation delay
6/
te
All
9, 10, 11
20
60
30
Address hold time 6/
tg
th
All
All
9, 10, 11
9, 10, 11
10
10
DTACK hold time 6/
RWR and RCS pulse
ti
01, 02
04
9, 10, 11
34
width (DTACK tied to
ground)
03
All
9, 10, 11
9, 10, 11
32
15
tj
125
RWR and RCS • to
•
2/ 9/
DMACK
Data hold time 2/
tk
ta
All
9, 10, 11
9, 10, 11
10
0
40
18
Memory read timing
Address propagation
delay
CL = 35 pF minimum
See figures 8 and 12
01, 02
04
ns
03
All
9, 10, 11
9, 10, 11
0
21
35
tb
15
Address valid to RCS ,
RRD assertion 6/
tc
td
All
All
9, 10, 11
9, 10, 11
10
20
DTACK setup time 6/
50
RCS and RRD hold
time 6/ 9/
Data setup delay 6/
te
01, 02
04
9, 10, 11
12
03
9, 10, 11
9, 10, 11
10
0
Data hold delay
tf
01, 02
04
03
All
All
9, 10, 11
9, 10, 11
9, 10, 11
2
Address hold time 6/
DTACK hold time
tg
th
10
10
30
45
ti
01, 02
04
9, 10, 11
34
RRD and RCS pulse
width (DTACK tied to
ground)
03
9, 10, 11
9, 10, 11
32
15
tj
All
RRD and RCS • to
•
2/
DMACK
See footnotes at end of table.
SIZE
STANDARD
5962-92118
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
SHEET
H
8
DSCC FORM 2234
APR 97
TABLE IA. Electrical performance characteristics - Continued.
Test
Symbol
Test conditions 1/
-55°C £ TC £ +125°C
4.5 V £ VDD £ 5.5 V
Device
type
Group A
subgroups
Limits
Unit
Min
5
Max
unless otherwise specified
DMA timing
ta
tb
CL = 35 pF minimum
See figures 9 and 12
All
01
9, 10, 11
ms
TERACT assertion to
DMAR assertion 2/
Bus controller
9, 10, 11
9, 10, 11
7
DMAR assertion to
02, 03
04
16
DMACK negation 2/
Remote terminal
All
All
9, 10, 11
9, 10, 11
7
7
Remote terminal
with monitor
Monitor
All
9, 10, 11
9, 10, 11
7
tc
01, 02
04
0
30
ns
DMAG assertion to
DMACK assertion 6/
03
All
9, 10, 11
9, 10, 11
5
0
30
35
td
te
DMAG assertion to
DMAR negation 2/
01, 02
04
9, 10, 11
0
5
5
DMACK assertion to
address bus active
03
All
9, 10, 11
9, 10, 11
-5
tf
10
DMACK assertion to
DMAG negation 6/
tg
th
All
9, 10, 11
9, 10, 11
500
DMACK negation to
DMAG assertion 2/
01, 02
04
0
5
DMACK assertion to
RAM control active
(negated)
03
All
-5
5
5
ti
tj
9, 10, 11
9, 10, 11
DMACK negation to
address three-state 2/
All
5
DMACK assertion to
RAM control disabled
2/
Power-up master reset timing
ta
tb
All
All
9, 10, 11
9, 10, 11
500
ns
CL = 35 pF minimum
See figures 10 and 12
MRST pulse width 2/
5
ms
MRST negation to
ROMEN assertion 2/
tc
td
All
All
9, 10, 11
9, 10, 11
10
ms
MRST negation to
READY assertion 2/
500
ns
DMACK negation to
ROMEN negation 2/
See footnotes at end of table.
SIZE
STANDARD
5962-92118
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
SHEET
H
9
DSCC FORM 2234
APR 97
TABLE IA. Electrical performance characteristics - Continued.
Test
Symbol
Test conditions 1/
-55°C £ TC £ +125°C
4.5 V £ VDD £ 5.5 V
Device
type
Group A
subgroups
Limits
Unit
ns
Min
Max
unless otherwise specified
Biphase timing
Biphase output skew
ta
tb
CL = 35 pF minimum
See figures 11 and 12
All
All
9, 10, 11
9, 10, 11
10
Biphase input skew
(low to high) 2/
250
Biphase input skew
(high to low) 2/
tc
td
All
All
250
9, 10, 11
9, 10, 11
Biphase input pulse
width 2/
250
JTAG timing
TCK frequency
TCK period
See figure 13
All
All
All
All
All
All
All
All
All
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
1
MHz
ns
ta
tb
tc
td
te
tf
1000
1/2ta
1/2ta
TCK high time
TCK low time
TCK rise time
5
5
TCK fall time
TDI, TMS setup time
TDI, TMS hold time
TDO valid delay
250
250
250
tg
th
1/ Device type 02 supplied to this drawing will meet all levels M, D, L, R, F, G and H of irradiation. However, this device is
only tested at the 'H' level. Device type 04 supplied to this drawing will meet levels R and F of irradiation and will only be
tested at the levels suplied. Pre and Post irradiation values are identical unless otherwise specified in table IA. When
performing post irradiation electrical measurements for any RHA level, TA = +25°C. Unless otherwise specified, all testing
shall be conducted under worst-case conditions. "GND" may not vary from 0 V dc by more than ±50 mV.
2/ This parameter is guaranteed, but not tested, to the values in table IA herein.
3/ Tested one output at a time for a maximum duration of 1 second.
4/ Device type 02 post irradiation limit is 1 mA for subgroup 1. Device type 04 post irradiation limit is 1 mA irradiation level
R and 5 mA irradiation level F for subgroup 1.
5/ Tested with all inputs tied to VDD
.
6/ For device type 03, this parameter is guaranteed, but not tested, to the values in table IA herein.
7/ Minimum pulse width from latter rising edge of RD/ WR or CS to first falling edge.
8/ Read cycle followed by a read cycle - minimum 45 ns.
Read cycle followed by a write cycle - minimum 45 ns.
Write cycle followed by a read cycle - minimum 85 ns.
Write cycle followed by a write cycle - minimum 85 ns.
9/ Pulse width duration is measured with respect to the device's recognition of DTACK assertion.
SIZE
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
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REVISION LEVEL
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H
10
DSCC FORM 2234
APR 97
TABLE IB. SEP test limits. 1/ 2/
VDD = 4.5 V
Device
type
TA =
Temperature
±10°C
Bias for
latch-up test
VDD = 5.5 V
no latch-up
LET = 4/
Effective LET
no upsets
Maximum device
cross section
LET 3/
[MeV/(mg/cm2)]
02
04
= 47
1.6 x 10-3 cm2
1.5 x 10-4 cm2
+25°C
+25°C
> 136
> 128
< 14.4
1/ For SEP test conditions, see 4.4.4.4.
2/ Technology characterization and model verfication supplemented by in-line data may be used in lieu of
end-of-line testing. Test plan must be approved by TRB and qualifying activity.
3/ LET = 136 for device type 02 and LET = 128 for device type 04.
4/ Test at worst case temperature TA = +125°C.
SIZE
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11
DSCC FORM 2234
APR 97
Case Y
FIGURE 1. Case outline.
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DSCC FORM 2234
APR 97
Case Y
Millimeters
Nom
Inches
Nom
Symbol
Min
Max
3.30
2.74
.46
Min
Max
A
A1
b
0.130
0.108
0.018
0.008
2.03
.36
0.080
0.014
0.006
C
.15
.20
e
1.27
0.50
D/E
HD/HE
L
28.91
45.59
.66
29.52
46.36
1.138
1.795
0.026
0.005
1.162
1.825
S1
N
.13
84
84
FIGURE 1. Case outline - Continued.
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DSCC FORM 2234
APR 97
Case Z
FIGURE 1. Case outline - Continued.
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DSCC FORM 2234
APR 97
Device
type
All
X
Case
outline
Terminal
number
Terminal
symbol
Terminal
number
Terminal
symbol
Terminal
number
Terminal
symbol
Terminal
number
Terminal
symbol
A1
A2
B11
C1
F9
F10
F11
G1
VDD
VSS
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
L1
RRD
A0
ROMEN
D15
TIMERONA
TA
RA
TB
A3
A1
A3
C2
TCLK
24 MHz
VDD
DMACK
D8
A4
C5
A5
A6
C6
G2
D7
TB
A6
A4
C7
A9
G3
D6
TDO
TDI
TMS
D5
READY
RTA3
A7
A7
C10
C11
D1
G9
CS
A8
A10
A12
A13
G10
G11
H1
RTA0
AUTOEN
D13
A9
LOCK
A10
A11
D2
D14
MSEL1
D10
H2
D4
D0
TA
YF_INT
RD/ WR
B1
B2
B3
D11
E1
H10
H11
J1
L2
L3
L4
MSG_INT
D10
MRST
DTACK
RCS
TRST
D3
RA
E2
D11
RWR
A2
TIMERONB
B4
B5
B6
B7
E3
E9
VDD
TCK
J2
J5
J6
J7
D1
RB
VSS
L5
L6
L7
L8
RB
A5
VDD
VSS
A8
E10
E11
DMAG
TERACT
RTA4
DMAR
D9
SSYSF
B8
B9
A11
A14
A15
F1
F2
F3
J10
J11
K1
L9
RTA2
RTA1
A/B STD
MSEL0
D2
D12
VSS
L10
L11
B10
RTPTY
FIGURE 2. Terminal connections.
SIZE
STANDARD
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MICROCIRCUIT DRAWING
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DSCC FORM 2234
APR 97
Device
type
All
Y
Case
outline
Terminal
number
Terminal
symbol
Terminal
number
Terminal
symbol
Terminal
number
Terminal
symbol
Terminal
number
Terminal
symbol
1
2
3
4
5
6
22
23
24
25
26
27
43
44
45
46
47
48
64
65
66
67
68
69
A15
A14
A13
A12
A11
A10
RCS
TIMERONA
LOCK
A/B STD
MSEL1
MSEL0
TCLK
TA
TA
DTACK
D15
RA
RA
D14
D13
MRST
TRST
TDO
TDI
TIMERONB
7
8
D12
D11
D10
D9
28
29
30
31
32
33
34
49
50
51
52
53
54
55
70
71
72
73
74
75
76
A9
A8
TB
TB
9
TMS
VSS
A7
RB
VSS
VDD
RB
10
11
12
13
VDD
VSS
VDD
D8
VDD
VSS
TCK
24 MHz
A6
TERACT
READY
SSYSF
RTA4
DMAR
DMAG
14
15
16
D7
D6
D5
35
36
37
56
57
58
77
78
79
A5
A4
A3
DMACK
MSG_INT
17
18
19
20
21
D4
D3
D2
D1
D0
38
39
40
41
42
RTA3
RTA2
RTA1
RTA0
RTPTY
59
60
61
62
63
80
81
82
83
84
A2
A1
A0
YF_INT
AUTOEN
ROMEN
CS
RWR
RRD
RD/ WR
FIGURE 2. Terminal connections - Continued.
SIZE
STANDARD
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MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
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DSCC FORM 2234
APR 97
Device
type
All
Case
outline
Z
Terminal Terminal Terminal
Terminal
symbol
Terminal Terminal Terminal
Terminal
symbol
Terminal
number
Terminal
symbol
number
symbol
number
number
symbol
number
1
2
VSS
28
NC
NC
D2
55
NC
82
VSS
VDD
109
110
111
A9
A8
NC
29
56
NC
83
RCS
3
4
TCLK
30
31
57
58
84
85
TCK
SSYSF
RTA4
D1
112
NC
DMAR
DTACK
NC
5
6
7
8
32
33
34
35
D0
VSS
VDD
59
60
61
62
RTA3
RTA2
NC
86
87
88
89
113
114
115
116
NC
A7
DMAG
NC
NC
D15
D14
NC
VDD
VSS
NC
NC
TIMERONA
9
D13
D12
D11
36
37
38
63
64
65
RTA1
RTA0
90
91
92
117
118
119
24 MHz
A6
TA
TA
DMACK
10
11
MSG_INT
RTPTY
A5
YF_INT
RA
NC
NC
RA
12
13
14
NC
NC
NC
39
40
41
66
67
68
VDD
VSS
93
94
95
120
121
122
NC
NC
NC
AUTOEN
NC
NC
LOCK
A/B STD
NC
15
16
D10
VSS
42
43
69
70
96
97
123
124
A4
A3
ROMEN
CS
TIMERONB
TB
TB
NC
NC
NC
17
18
19
20
21
VDD
D9
D8
D7
NC
44
45
46
47
48
71
72
73
74
75
NC
NC
98
99
125
126
127
128
129
A2
A1
NC
NC
A0
RD/ WR
VSS
MSEL1
MSEL0
100
101
102
VDD
A15
A14
RB
MRST
NC
22
23
24
25
26
27
NC
NC
D6
D5
D4
D3
49
50
51
52
53
54
VSS
76
77
78
79
80
81
103
104
105
106
107
108
A13
NC
130
131
132
RWR
VDD
RB
NC
RRD
VDD
NC
TRST
TDO
A12
A11
A10
TERACT
TDI
READY
NC
TMS
NC = No connection
FIGURE 2. Terminal connections - Continued.
SIZE
STANDARD
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A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
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DSCC FORM 2234
APR 97
FIGURE 3. Block diagram.
SIZE
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MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
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5962-92118
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REVISION LEVEL
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DSCC FORM 2234
APR 97
Device types 02 and 04
Instruction name
Instruction code
1111
BYPASS
SAMPLE/PRELOAD
EXTEST
0010
0000
INTEST
0001
RUNBIST
0111
IDCODE
0100
GL-TRISTATE
INTERNAL-SCAN
PRIVATE
0011
0101
0110
USER-SELECTABLE
1000 ® 1110
Device type 03
Instruction name
BYPASS
Instruction code
1111
SAMPLE/PRELOAD
EXTEST
0010
0000
FIGURE 4. Boundary scan instruction codes.
SIZE
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DSCC FORM 2234
APR 97
FIGURE 5. Register write.
FIGURE 6. Register read.
SIZE
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DSCC FORM 2234
APR 97
NOTE: The memory read and write timing diagrams are applicable for reads and writes resulting from the
auto-initialization sequence.
FIGURE 7. Memory write.
NOTE: The memory read and write timing diagrams are applicable for reads and writes resulting from the
auto-initialization sequence.
FIGURE 8. Memory read.
SIZE
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MICROCIRCUIT DRAWING
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REVISION LEVEL
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21
DSCC FORM 2234
APR 97
FIGURE 9. DMA timing.
FIGURE 10. Power-up master reset.
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MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
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22
DSCC FORM 2234
APR 97
FIGURE 11. Biphase timing.
NOTES: V switch = (VOLmax + VOLmin)/2
CL = 35 pF
FIGURE 12. AC test circuit.
SIZE
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
5962-92118
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23
DSCC FORM 2234
APR 97
FIGURE 13. JTAG timing waveforms.
Case
Open
Ground
VDD = 5 V ± 0.5 V
outline
X
Y
Z
A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, B1, B2, B3,
B4, B5, B7, B8, B9, B10, B11, C1, C7, D1, D2, D10,
D11, E1, E2, E11, F1, F2, F11, G1, G2, G3, G9, H1,
H2, J1, J2, K1, K2, K3, K5, K6, K7, L1, L2, L4, L7
A11, C2, C6, C11,
E3, E9, F9, G10,
H10, J5, K4, K9,
B6, C5, C10, E10, F3,
F10, G11, H11, J6,
J7, J10, J11, K8, L3,
L5, L10, L11
K10, K11, L6, L8, L9
1, 3, 4, 5, 6, 7, 8, 9, 10, 13, 14, 15, 16, 17, 18, 19, 20,
21, 22, 23, 24, 27, 28, 29, 34, 35, 49, 55, 57, 58, 59,
61, 64, 65, 66, 67, 68, 69, 70, 71, 72, 76, 77, 78, 79,
80, 81, 82, 83, 84
2, 12, 26, 32, 33, 37,
39, 41, 43, 45, 47,
50, 53, 54, 60, 63, 73
11, 25, 30, 31, 36, 38,
40, 42, 44, 46, 48, 51,
52, 56, 62, 74, 75
2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 18, 19, 20,
21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 35, 36,
37, 39, 40, 42, 43, 44, 45, 46, 47, 52, 53, 54, 55, 56,
61, 62, 70, 71, 72, 76, 77, 79, 85, 87, 88, 89, 90, 91,
92, 94, 95, 96, 101, 102, 103, 104, 105, 106, 107, 108,
109, 110, 111, 112, 113, 114, 118, 119, 120, 121, 122,
123, 124, 125, 126, 127, 128, 129, 130, 131
3, 17, 34, 41, 50, 51,
58, 60, 64, 66, 68,
73, 75, 80, 83, 84,
93, 98, 100, 115, 132
1, 16, 33, 38, 48, 49,
57, 59, 63, 65, 67, 69,
74, 78, 81, 82, 86, 97,
99, 116, 117
NOTE: Each pin except B6, C6, E3, F3, F9, F10, J6, and L6 for case outline X (11, 12, 31, 32, 52, 53, 73, and 74 for
case outline Y; and 1, 16, 17, 33, 34, 49, 50, 66, 67, 82, 83, 99, 100, 115, 116, and 132 for case outline Z) will
have a resistor of 2.49 kW ± 5% for irradiation testing.
FIGURE 14. Radiation exposure connections.
SIZE
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5962-92118
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MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
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DSCC FORM 2234
APR 97
4. QUALITY ASSURANCE PROVISIONS
4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with
MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan
shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be
in accordance with MIL-PRF-38535, appendix A.
4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted
on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in
accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection.
4.2.1 Additional criteria for device class M.
a. Burn-in test, method 1015 of MIL-STD-883.
(1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision
level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
test method 1015.
(2) TA = +125°C, minimum.
b. Interim and final electrical test parameters shall be as specified in table IIA herein.
4.2.2 Additional criteria for device classes Q and V.
a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the
device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained
under document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance
with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit
shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified
in test method 1015 of MIL-STD-883.
b. Interim and final electrical test parameters shall be as specified in table IIA herein.
c. Additional screening for device class V beyond the requirements of device class Q shall be as specified in
MIL-PRF-38535, appendix B.
4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in
accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for
groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with
MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein. Quality conformance inspection for
device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed
for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E
inspections (see 4.4.1 through 4.4.4).
4.4.1 Group A inspection.
a. Tests shall be as specified in table IIA herein.
b. For device class M, subgroups 7 and 8 tests shall be sufficient to verify the functionality of the device. For device
classes Q and V, subgroups 7 and 8 shall include verifying the functionality of the device; these tests shall have been
fault graded in accordance with MIL-STD-883, test method 5012 (see 1.5 herein).
c. Subgroup 4 (CIN, COUT, and CI/O measurements) shall be measured only for the initial test and after process or design
changes which may affect input capacitance. A minimum sample of 5 devices with zero failures shall be required.
SIZE
STANDARD
5962-92118
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
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DSCC FORM 2234
APR 97
TABLE IIA. Electrical test requirements.
Subgroups
Test requirements
Subgroups
(in accordance with
MIL-STD-883,
(in accordance with
MIL-PRF-38535, table III)
method 5005, table I)
Device
class M
Device
class Q
Device
class V
Interim electrical
---
1
1
parameters (see 4.2)
Final electrical
parameters (see 4.2)
1, 2, 3, 7, 8, 9,
10, 11 1/
1, 2, 3, 7, 8, 9,
10, 11 1/
1, 2, 3, 7, 8, 9,
10, 11 2/ 3/
Group A test
requirements (see 4.4)
1, 2, 3, 4, 7, 8, 9,
10, 11
1, 2, 3, 4, 7, 8, 9,
10, 11
1, 2, 3, 4, 7, 8, 9,
10, 11
Group C end-point electrical
parameters (see 4.4)
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
Group D end-point electrical
parameters (see 4.4)
Group E end-point electrical
parameters (see 4.4)
1/ PDA applies to subgroup 1.
2/ PDA applies to subgroups 1 and 7.
3/ Delta limits, as specified in table IIB herein, shall be required when specified and the delta values shall be
completed with reference to the zero hour electrical parameters.
TABLE IIB. Burn-in and operating life test, delta parameters (+25°C).
Parameter
Symbol
QIDD
Delta limits
Quiescent current
±10% of measured values or
35 mA whichever is greater
NOTE: If the device is tested at or below 35 mA, no deltas are required.
4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883:
a. Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level
control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify
the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test
method 1005 of MIL-STD-883.
b. TA = +125°C, minimum.
c. Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.
SIZE
STANDARD
5962-92118
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
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DSCC FORM 2234
APR 97
4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test
temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with
MIL-PRF-38535. The test circuit shall be maintained under document revision level control by the device manufacturer's TRB
in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test
circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
test method 1005 of MIL-STD-883.
4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness
assured (see 3.5 herein). RHA levels for device classes M, Q and V shall be as specified in MIL-PRF-38535. End-point
electrical parameters shall be as specified in table IIA herein.
4.4.4.1 Total dose irradiation testing. Total dose irradiation testing shall be performed in accordance with MIL-STD-883
method 1019 and as specified herein.
4.4.4.1.1 Accelerated aging test. Accelerated aging tests shall be performed on all devices requiring a RHA level greater
than 5k rads(Si). The post-anneal end-point electrical parameter limits shall be as specified in table IA herein and shall be the
pre-irradiation end-point electrical parameter limit at 25°C ±5°C. Testing shall be performed at initial qualification and after
any design or process changes which may affect the RHA response of the device.
4.4.4.2 Dose rate induced latchup testing. Dose rate induced latchup testing shall be performed in accordance with test
method 1020 of MIL-STD-883 and as specified herein (See 1.4). Tests shall be performed on devices, SEC, or approved test
structures at technology qualification and after any design or process changes which may effect the RHA capability of the
process.
4.4.4.3 Dose rate upset testing. Dose rate upset testing shall be performed in accordance with test method 1021 of
MIL-STD-883 and herein (see 1.4).
a. Transient dose rate upset testing shall be performed at initial qualification and after any design or process changes
which may effect the RHA performance of the devices. Test 10 devices with 0 defects unless otherwise specified.
b. Transient dose rate upset testing for class Q and V devices shall be performed as specified by a TRB approved
radiation hardness assurance plan and MIL-PRF-38535.
4.4.4.4 Single event phenomena (SEP). SEP testing shall be required on class V devices (see 1.4). SEP testing shall be
performed on the Standard Evaluation Circuit (SEC) or alternate SEP test vehicle as approved by the qualifying activity at
initial qualification and after any design or process changes which may affect the upset or latchup characteristics. The
recommended test conditions for SEP are as follows:
a. The ion beam angle of incidence shall be between normal to the die surface and 60° to the normal, inclusive (i.e. 0° £
angle £ 60°). No shadowing of the ion beam due to fixturing or package related effects is allowed.
b. The fluence shall be ³ 100 errors or ³ 106 ions/cm2.
c. The flux shall be between 102 and 105 ions/cm2/s. The cross-section shall be verified to be flux independent by
measuring the cross-section at two flux rates which differ by at least an order of magnitude.
d. The particle range shall be ³ 20 microns in silicon.
e. The test temperature shall be +25°C and the maximum rated operating temperature ±10°C.
f. Bias conditions shall be defined by the manufacturer for latchup measurements.
g. Test four devices with zero failures.
SIZE
STANDARD
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MICROCIRCUIT DRAWING
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5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device
classes Q and V or MIL-PRF-38535, appendix A for device class M.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a
contractor-prepared specification or drawing.
6.1.2 Substitutability. Device class Q devices will replace device class M devices.
6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus when a system
application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of
users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering
microelectronic devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544.
6.4 Comments. Comments on this drawing should be directed to DSCC-VA , Columbus, Ohio 43216-5000, or telephone
(614) 692-0674.
6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535, MIL-HDBK-1331, and table III herein.
6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in
QML-38535. The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and
have agreed to this drawing.
6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103.
The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been
submitted to and accepted by DSCC-VA.
6.7 Additional information. A copy of the following additional data shall be maintained and available from the device
manufacturer:
a. RHA upset levels.
b. Test conditions (SEP).
c. Number of upsets (SEP).
d. Number of transients (SEP).
e. Occurrence of latchup (SEP).
SIZE
STANDARD
5962-92118
A
MICROCIRCUIT DRAWING
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TABLE III. Pin descriptions.
Description
Name
Type 1/
Active 2/
Data bus
D0
TTB
TTB
TTB
TTB
TTB
TTB
TTB
TTB
TTB
TTB
TTB
TTB
TTB
TTB
TTB
TTB
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Bit 0 (LSB) of the bidirectional Data bus.
Bit 1 of the bidirectional Data bus.
Bit 2 of the bidirectional Data bus.
Bit 3 of the bidirectional Data bus.
Bit 4 of the bidirectional Data bus.
Bit 5 of the bidirectional Data bus.
Bit 6 of the bidirectional Data bus.
Bit 7 of the bidirectional Data bus.
Bit 8 of the bidirectional Data bus.
Bit 9 of the bidirectional Data bus.
Bit 10 of the bidirectional Data bus.
Bit 11 of the bidirectional Data bus.
Bit 12 of the bidirectional Data bus.
Bit 13 of the bidirectional Data bus.
Bit 14 of the bidirectional Data bus.
Bit 15 (MSB) of the bidirectional Data bus.
Address bus
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
A0
TTB
TTB
TTB
TTB
TTB
TTB
TTB
TTB
TTB
TTB
TTB
TTB
TTB
TTB
TTB
TTB
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Bit 0 (LSB) of the bidirectional Address bus.
Bit 1 of the bidirectional Address bus.
Bit 2 of the bidirectional Address bus.
Bit 3 of the bidirectional Address bus.
Bit 4 of the bidirectional Address bus.
Bit 5 of the bidirectional Address bus.
Bit 6 of the bidirectional Address bus.
Bit 7 of the bidirectional Address bus.
Bit 8 of the bidirectional Address bus.
Bit 9 of the bidirectional Address bus.
Bit 10 of the bidirectional Address bus.
Bit 11 of the bidirectional Address bus.
Bit 12 of the bidirectional Address bus.
Bit 13 of the bidirectional Address bus.
Bit 14 of the bidirectional Address bus.
Bit 15 (MSB) of the bidirectional Address bus.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
See footnotes at end of table.
SIZE
STANDARD
5962-92118
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
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TABLE III. Pin descriptions - Continued.
Description
Name
RTA0
Type 1/
TUI
Active 2/
--
Remote terminal address inputs
Remote Terminal Address bit 0. This is bit 0 of the RT address. This is the least
significant bit for the RT address.
RTA1
RTA2
RTA3
RTA4
RTPTY
TUI
TUI
TUI
TUI
TUI
--
--
--
--
--
Remote Terminal Address bit 1. This is bit 1 of the RT address.
Remote Terminal Address bit 2. This is bit 2 of the RT address.
Remote Terminal Address bit 3. This is bit 3 of the RT address.
Remote Terminal Address bit 4. This is the most significant bit of the RT address.
Remote Terminal Parity. This is an odd parity input for the RT address.
JTAG testability pins
TDO
TCK
TMS
TDI
TTO
TUI
TUI
TUI
TUI
--
--
--
--
--
TDO. This output performs the operation of Test Data Output as defined in the IEEE
Standard 1149.1. This cell provides the output signal for the Test Access Port (TAP).
This noninverfting output buffer is optimized for driving TTL loads.
TCK. This input performs the operation of Test Clock input as defined in the IEEE
Standard 1149.1. This noninverting input buffer is optimized for driving TTL input
levels.
TMS. This input performs the operation of Test Mode Select as defined in the IEEE
Standard 1149.1. This cell provides the input signal for the Test Access Port (TAP).
This noninverting input buffer is optimized for driving TTL input levels.
TDI. This input performs the operation of Test Data In as defined in the IEEE Standard
1149.1. This cell provides the input signal for the Test Access Port (TAP). This
noninverting input buffer is optimized for driving TTL input levels.
TRST
TRST . This input provides the reset to the TAP controller as defined in the IEEE
Standard 1149.1. This non-inverting input buffer is optimized for driving TTL input
levels. When not exercising JTAG, tie TRST to a logical 0.
Biphase inputs
RA
TI
TI
TI
TI
--
--
--
--
Receive Channel A (true). This is the Manchester-encoded true signal input for channel
A. (Quiescent low).
Receive Channel A (complement). This is the Manchester-encoded complement signal
input for channel A. (Quiescent low).
RA
RB
Receive Channel B (true). This is the Manchester-encoded true signal input for channel
B. (Quiescent low).
Receive Channel B (complement). This is the Manchester-encoded complement signal
input for channel B. (Quiescent low).
RB
TA
Biphase outputs
TO
TO
TO
TO
--
--
--
--
Transmit Channel A (true). This is the Manchester-encoded true signal output for
channel A. The signal is idle low. (Quiescent low).
Transmit Channel A (complement). This is the Manchester-encoded complement
signal output for channel A. The signal is idle low. (Quiescent low).
TA
TB
Transmit Channel B (true). This is the Manchester-encoded true signal output for
channel B. The signal is idle low. (Quiescent low).
Transmit Channel B (complement). This is the Manchester-encoded complement
signal output for channel B. The signal is idle low. (Quiescent low).
TB
See footnotes at end of table.
SIZE
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
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REVISION LEVEL
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TABLE III. Pin descriptions - Continued.
Description
Name
Type 1/
TTO 3/
Active 2/
AL
DMA signals
DMA Request. This signal is asserted when access to RAM is required. It goes
inactive upon receipt of the DMAG signal.
DMAR
TI
AL
AL
DMA Grant. Once this input is received, the device is allowed to access RAM.
DMAG
TTO 3/
DMA Acknowledge. This signal is asserted by the device to indicate the receipt of
DMAG . The signal remains active until all RAM bus activity is completed.
DMACK
TI
TI
AL
--
Data Transfer Acknowledge. This pin indicates that a data transfer is to occur and
that the device may complete the memory cycle.
DTACK
RD/ WR
Control signals
Read/Write. This indicates the direction of data flow with respect to the host. A
logic high signal means the host is trying to read data from the device, and a logic
low signal means the host is trying to write data to the device.
TI
AL
AL
AL
AL
Chip Select. This pin selects the device when accessing the internal registers.
RAM Read. This signal is generated by the device to read data from RAM.
RAM Write. This signal is generated by the device to write data to RAM.
CS
TTO
TTO
TTO
RRD
RWR
RCS
RAM Chip Select. This signal is used in conjunction with the RRD /RWR signals to
access RAM.
TUI
AL
AL
Auto Enable. This pin, when active, enables automatic initialization applications.
AUTOEN
ROMEN
TTO 3/
ROM Enable. This pin, when active, enables the ROM for automatic initialization
applications.
TUI
CI
AL
--
Subsystem Fail. Upon receipt, this signal propagates directly to the RT 1553
Status word.
SSYSF
24 MHz
24 MHz Clock. This 24 MHz input clock requires a 50% ±10% duty cycle with an
accuracy of ±0.01%.
TUI
TI
AL
--
Master Reset. This input pin resets the internal encoders, decoders, all register,
and associated logic.
MRST
MSEL1
Mode Select 1. This pin is the most significant bit for the mode select. For proper
mode selection, see below:
MSEL1
MSEL0
Mode of Operation
Bus Controller = SBC
Remote Terminal = SRT
Monitor Terminal = SMT
SMT/SRT
0
0
1
1
0
1
0
1
MSEL0
TI
--
Mode Select 0. This pin is the least significant bit for the mode select. (See
MSEL1 for proper logic states.)
See footnotes at end of table.
SIZE
STANDARD
5962-92118
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
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TABLE III. Pin descriptions - Continued.
Description
Name
Type 1/
TI
Active 2/
--
Control signals - Continued.
TCLK
Timer Clock. This internal timer is a 16-bit counter with a 64 ms resolution when
using the 24 MHz input clock. For different applications, the user may input a
clock (0-60 MHz) to establish the timer resolution. (Duty Cycle = 50% ±10%).
TUI
TUI
--
Military Standard A or B. This pin defines whether the device will be used a
MIL-STD-1553A or 1553B mode of operation.
A/B STD
LOCK
AL
Lock. This pin, when set active, prevents software changes to both the RT
address, A/B STD, and mode select.
Status signals
TO
TO
AL
AL
Terminal Active. This output pin indicates that the terminal is actively processing a
1553 command.
TERACT
Timer On A. This is a 800 ms fail-safe transmitter enable timer for channel A. This
ouput is reset on receipt of a new command or after 760 ms.
TIMERONA
TO
AL
Timer On B. This is a 800 ms fail-safe transmitter enable timer for channel B. This
ouput is reset on receipt of a new command or after 760 ms.
TIMERONB
MSG_INT
YF_INT
TTO 3/
TTO 3/
TO
AL
AL
AL
Message Interrupt. This pin is active for three clock cycles (i. e., 125 ns pulse)
upon the occurrence of interrupt events which are enabled.
YOU Failed Interrupt. This pin is active for three clock cycles (i. e., 125 ns pulse)
upon the occurrence of interrupt events which are enabled.
Ready. This signal indicates the device has completeed initialization or BIT, and
regular execution may begin.
READY
Power/Ground
+5 Volt Power (± 10%)
Digital ground.
VDD
VSS
--
--
--
--
1/ TO = TTL output
TTB = Three-state TTL bidirectional
CI = CMOS input
TUI = TTL input (internally pulled high)
TI = TTL input
TTO = Three-state TTL output
2/ AH = Active high
AL = Active low
3/ High impedance and active low.
SIZE
STANDARD
5962-92118
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
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Appendix A
APPENDIX A FORMS A PART OF SMD 5962-92118
10. SCOPE
10.1 Scope. This appendix establishes minimum requirements for microcircuit die to be supplied under the Qualified
Manufacturers List (QML) Program. QML microcircuit die meeting the requirements of MIL-PRF-38535 and the manufacturers
approved QML plan for use in monolithic microcircuits, multichip modules (MCMs), hybrids, electronic modules, or devices
using chip and wire designs in accordance with MIL-PRF-38534 are specified herein. Two product assurance classes
consisting of military high reliability (device class Q) and space application (device Class V) are reflected in the Part or
Identification Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the
PIN.
10.2 PIN. The PIN is as shown in the following example:
5962
H
92118
01
V
9
X
Federal
stock class
designator
\
RHA
designator
(see 10.2.1)
Device
type
(see 10.2.2)
Device
class
designator
(see 10.2.3)
Die
code
(see 10.2.4)
Die
detail
(see 10.2.5)
/
\/
Drawing number
10.2.1 RHA designator. Device classes Q and V RHA identified die shall meet the MIL-PRF-38535 specified RHA levels. A
dash (-) indicates a non-RHA die.
10.2.2 Device type(s). The device type(s) shall identify the circuit function as follows:
Device type 1/
Generic number
Circuit function
01
02
UT69151
UT69151E
MIL-STD-1553 bus controller, remote terminal, monitor interface
MIL-STD-1553 bus controller, remote terminal, monitor interface
radiation hardened
03
04
UT69151E
UT69151E
MIL-STD-1553 bus controller, remote terminal, monitor interface
MIL-STD-1553 bus controller, remote terminal, monitor interface
radiation hardened
10.2.3 Device class designator.
Device class
Device requirements documentation
Certification and qualification to the die requirements of MIL-PRF-38535
Q or V
10.2.4 Die code. The die code designator shall be a number 9 for all devices supplied as die only with no case outline.
10.2.5. Die Details. The die details designation shall be a unique letter which designates the die’s physical dimensions,
bonding pad location(s) and related electrical function(s), interface materials, and other assembly related information, for
each product and variant supplied to this appendix.
1/ Device types 01and 03 are not available as QML die only.
SIZE
STANDARD
5962-92118
A
MICROCIRCUIT DRAWING
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Appendix A
APPENDIX A FORMS A PART OF SMD 5962-92118
10.2.5.1 Die physical dimensions.
Die type
Figure number
02
04
A-1
B-1
10.2.5.2 Die bonding pad locations and electrical functions.
Die type
Figure number
02
04
A-1
B-1
10.2.5.3 Interface materials.
Die type
Figure number
02
04
A-1
B-1
10.2.5.4 Assembly related information.
Die type
Figure number
02
04
A-1
B-1
10.3. Absolute maximum ratings.
See paragraph 1.3 within the body of this drawing for details.
10.4 Recommended operating conditions.
See paragraph 1.4 within the body of this drawing for details.
20. APPLICABLE DOCUMENTS.
20.1 Government specifications, standards, bulletin, and handbooks. Unless otherwise specified, the following
specifications, standards, bulletin, and handbook of the issue listed in that issue of the Department of Defense Index of
Specifications and Standards specified in the solicitation, form a part of this drawing to the extent specified herein.
SPECIFICATION
MILITARY
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
STANDARDS
MILITARY
MIL-STD-883 - Test Methods and Procedures for Microelectronics.
SIZE
STANDARD
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A
MICROCIRCUIT DRAWING
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Appendix A
APPENDIX A FORMS A PART OF SMD 5962-92118
HANDBOOK
MILITARY
MIL-HDBK-103 - List of Standard Microcircuit Drawings (SMD’s).
(Copies of the specification, standards, bulletin, and handbook required by manufacturers in connection with specific
acquisition functions should be obtained from the contracting activity or as directed by the contracting activity).
20.2. Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the
text of this drawing shall take precedence.
30. REQUIREMENTS
30.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer’s Quality Management (QM) plan. The
modification in the QM plan shall not effect the form, fit or function as described herein.
30.2 Design, construction and physical dimensions. The design, construction and physical dimensions shall be as
specified in MIL-PRF-38535 and the manufacturer’s QM plan, for device classes Q and V and herein.
30.2.1 Die physical dimensions. The die physical dimensions shall be as specified in 10.2.5.1 and on figures A-1 and B-1.
30.2.2 Die bonding pad locations and electrical functions. The die bonding pad locations and electrical functions shall be
as specified in 10.2.5.2 and on figures A-1 and B-1.
30.2.3 Interface materials. The interface materials for the die shall be as specified in 10.2.5.3 and on figures A-1 and B-1.
30.2.4 Assembly related information. The assembly related information shall be as specified in 10.2.5.4 and figures A-1
and B-1.
30.3 Electrical performance characteristics and post-irradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and post-irradiation parameter limits are as specified in table IA of the body of this
document.
30.4 Electrical test requirements. The test requirements shall include functional and parametric testing sufficient to make
the packaged die capable of meeting the electrical performance requirements in table IA.
30.5 Marking. As a minimum, each unique lot of die, loaded in single or multiple stack of carriers, for shipment to a
customer, shall be identified with the wafer lot number, the certification mark, the manufacturer’s identification and the PIN
listed in 10.2 herein. The certification mark shall be a “QML” or “Q” as required by MIL-PRF-38535.
30.6 Certification of compliance. For device classes Q and V, a certificate of compliance shall be required from a
QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 60.4 herein). The certificate of
compliance submitted to DSCC-VA prior to listing as an approved source of supply for this appendix shall affirm that the
manufacturer’s product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and the requirements herein.
30.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535
shall be provided with each lot of microcircuit die delivered to this drawing.
SIZE
STANDARD
5962-92118
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
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Appendix A
APPENDIX A FORMS A PART OF SMD 5962-92118
40. QUALITY ASSURANCE PROVISIONS
40.1 Sampling and inspection. For device classes Q and V, die sampling and inspection procedures shall be in accordance
with MIL-PRF-38535 or as modified in the device manufacturer’s Quality Management (QM) plan. The modifications in the QM
plan shall not effect the form, fit or function as described herein.
40.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and as defined in the
manufacturer’s QM plan. As a minimum it shall consist of:
a) Wafer lot acceptance for Class V product using the criteria defined within MIL-STD-883 test method 5007.
b) 100% wafer probe (see paragraph 30.4).
c) 100% internal visual inspection to the applicable class Q or V criteria defined within MIL-STD-883 test method 2010
or the alternate procedures allowed within MIL-STD-883 test method 5004.
40.3 Conformance inspection
40.3.1 Group E inspection. Group E inspection is required only for parts intended to be identified as radiation assured (see
30.5 herein). RHA levels for device classes Q and V shall be as specified in MIL-PRF-38535. End point electrical testing of
packaged die shall be as specified in table IIA herein.
50. Die carrier
50.1 Die carrier requirements. The requirements for the die carrier shall be accordance with the manufacturer’s QM plan or
as specified in the purchase order by the acquiring activity. The die carrier shall provide adequate physical, mechanical and
electrostatic protection.
60. NOTES
60.1 Intended use. Microcircuit die conforming to this drawing are intended for use in microcircuits built in accordance with
MIL-PRF-38535 or MIL-PRF-38534 for government microcircuit applications (original equipment), design applications and
logistics purposes.
60.2 Comments. Comments on this appendix should be directed to DSCC-VA, Columbus, Ohio, 43216-5000 or telephone
(614) 692-0674.
60.3 Abbreviations, symbols and definitions. The abbreviations, symbols, and definitions used herein are defined within
MIL-PRF-38535 and MIL-STD-1331.
60.4 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535.
The vendors listed within QML-38535 have submitted a certificate of compliance (see 30.6 herein) to DSCC-VA and have
agreed to this drawing.
SIZE
STANDARD
5962-92118
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
SHEET
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Appendix A
APPENDIX A FORMS A PART OF SMD 5962-92118
Die bonding pad locations and electrical functions.
Device type 02
Device type 04
Die physical dimensions
495 mils x 495 mils
17.5 ±1 mils
Die size
495 mils x 495 mils
Die thickness
24.6 ±0.8 mils
Interface materials
Si Al Cu 9 kA –12.5 kA
None: Backgrind
Top metallization
TiW-AlCu-TiW 6.2 kA -7.6 kA
None: Backgrind
Backside metallization
Glassivation
PSG
Nitride
Type
Oxide/Nitride
9 kA -11 kA
Thickness
9 kA / ±11 kA
EPI on single crystal silicon
Tied to VDD
Substrate
EPI on single crystal silicon
Tied to GND
Substrate potential
Special assembly
instructions
None
None
SIZE
STANDARD
5962-92118
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
SHEET
H
37
DSCC FORM 2234
APR 97
Appendix A
APPENDIX A FORMS A PART OF SMD 5962-92118
Die bonding pad locations and electrical functions
PAD
XCENTER
YCENTER
PAD NAME
1
2
3
0.2173
0.2110
0.2047
0.2406
0.2406
0.2406
VDD
VSS
No connect
4
5
6
7
0.1984
0.1921
0.1858
0.1795
0.2406
0.2406
0.2406
0.2406
RCS
No connect
TCLK
No connect
8
9
0.1732
0.1669
0.1606
0.1543
0.1480
0.1417
0.1354
0.1291
0.1228
0.1165
0.1102
0.1039
0.0976
0.0913
0.0850
0.0787
0.0724
0.0661
0.0598
0.0535
0.0472
0.0410
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
DTACK
No connect
No connect
D15
No connect
D14
No connect
D13
No connect
VDDQ
VSSQ
VDD
VSS
No connect
D12
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
No coonect
D11
No connect
No connect
No connect
No connect
No connect
30
31
32
33
34
35
36
37
38
39
40
0.0347
0.0284
0.0221
0.0158
0.0095
0.0031
-0.0032
-0.0095
-0.0158
-0.0221
-0.0284
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
D10
No connect
D9
No connect
VSSQ
VSS
VDD
VDDQ
No connect
D8
No connect
NOTE: The die center is the coordinate origin (0,0).
FIGURE A-1
SIZE
STANDARD
5962-92118
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
SHEET
H
38
DSCC FORM 2234
APR 97
Appendix A
APPENDIX A FORMS A PART OF SMD 5962-92118
Die bonding pad locations and electrical functions
PAD
XCENTER
YCENTER
PAD NAME
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
-0.0346
-0.0409
-0.0472
-0.0535
-0.0598
-0.0661
-0.0724
-0.0787
-0.0850
-0.0913
-0.0976
-0.1039
-0.1102
-0.1165
-0.1228
-0.1291
-0.1354
-0.1417
-0.1480
-0.1543
-0.1606
-0.1669
-0.1732
-0.1795
-0.1858
-0.1921
-0.1984
-0.2047
-0.2110
-0.2173
-0.2349
-0.2349
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2173
0.2110
D7
No connect
No connect
No connect
No connect
No connect
D6
No connect
D5
No connect
VSS
VDD
VSSQ
VDDQ
No connect
D4
No connect
D3
No connect
No connect
No connect
No connect
No connect
D2
No connect
D1
No connect
D0
VSS
VDD
VSSQ
VDDQ
73
74
-0.2349
-0.2349
0.2047
0.1984
TIMERONA
No connect
75
76
77
78
-0.2349
-0.2349
-0.2349
-0.2349
0.1921
0.1858
0.1795
0.1732
TA
No connect
TA
No connect
79
80
-0.2349
-0.2349
0.1669
0.1606
RA
No connect
NOTE: The die center is the coordinate origin (0,0).
FIGURE A-1
SIZE
STANDARD
5962-92118
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
SHEET
H
39
DSCC FORM 2234
APR 97
Appendix A
APPENDIX A FORMS A PART OF SMD 5962-92118
Die bonding pad locations and electrical functions
PAD
XCENTER
YCENTER
PAD NAME
81
82
83
84
-0.2349
-0.2349
-0.2349
-0.2349
0.1543
0.1480
0.1417
0.1354
No connect
No connect
RA
No connect
85
86
87
88
89
90
91
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
0.1291
0.1228
0.1165
0.1102
0.1039
0.0976
0.0913
TIMERONB
No connect
VSS
VDD
VSSQ
VDDQ
No connect
92
93
94
95
96
97
98
99
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
0.0850
0.0787
0.0724
0.0661
0.0598
0.0535
0.0472
0.0409
TB
No connect
TB
No connect
No connect
No connect
No connect
No connect
100
101
102
103
104
105
106
107
108
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
0.0347
0.0284
0.0221
0.0158
0.0095
0.0032
-0.0032
-0.0095
-0.0158
RB
No connect
RB
No connect
VSSQ
VSS
VDD
VDDQ
No connect
109
110
-0.2349
-0.2349
-0.0221
-0.0284
TERACT
No connect
111
112
113
114
115
116
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.0374
-0.0409
-0.0472
-0.0535
-0.0598
-0.0661
READY
No connect
No connect
No connect
No connect
No connect
117
118
119
120
-0.2349
-0.2349
-0.2349
-0.2349
-0.0724
-0.0787
-0.0850
-0.0913
SSYSF
No connect
RTA4
No connect
NOTE: The die center is the coordinate origin (0,0).
FIGURE A-1
SIZE
STANDARD
5962-92118
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
SHEET
H
40
DSCC FORM 2234
APR 97
Appendix A
APPENDIX A FORMS A PART OF SMD 5962-92118
Die bonding pad locations and electrical functions
PAD
XCENTER
YCENTER
PAD NAME
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2173
-0.2110
-0.0976
-0.1039
-0.1102
-0.1165
-0.1228
-0.1291
-0.1354
-0.1417
-0.1480
-0.1543
-0.1606
-0.1669
-0.1732
-0.1795
-0.1858
-0.1921
-0.1984
-0.2047
-0.2110
-0.2173
-0.2406
-0.2406
VDDQ
VSSQ
VDD
VSS
No connect
RTA3
No connect
RTA2
No connect
No connect
No connect
No connect
No connect
RTA1
No connect
RTA0
No connect
RTPTY
VDDQ
VSSQ
VDD
VSS
143
144
-0.2047
-0.1984
-0.2406
-0.2406
LOCK
No connect
145
146
147
148
149
150
151
152
153
154
-0.1921
-0.1858
-0.1795
-0.1732
-0.1669
-0.1606
-0.1543
-0.1480
-0.1417
-0.1354
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
A/B STD
No connect
No connect
No connect
No connect
No connect
MSEL1
No connect
MSEL0
No connect
155
156
157
158
159
160
-0.1291
-0.1228
-0.1165
-0.1102
-0.1039
-0.0976
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
MRST
No connect
VDDQ
VSSQ
VDD
VSS
NOTE: The die center is the coordinate origin (0,0).
FIGURE A-1
SIZE
STANDARD
5962-92118
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
SHEET
H
41
DSCC FORM 2234
APR 97
Appendix A
APPENDIX A FORMS A PART OF SMD 5962-92118
Die bonding pad locations and electrical functions
PAD
XCENTER
YCENTER
PAD NAME
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
-0.0913
-0.0850
-0.0787
-0.0724
-0.0661
-0.0598
-0.0535
-0.0472
-0.0409
-0.0347
-0.0284
-0.0221
-0.0158
-0.0095
-0.0032
0.0032
0.0095
0.0158
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
No connect
No connect
No connect
No connect
No connect
No connect
No connect
No connect
TRS
TDO
TDI
TMS
TCK
VDDQ
VDD
VSS
VSSQ
No connect
179
180
0.0221
0.0284
-0.2406
-0.2406
DMAR
No connect
181
182
183
184
185
186
0.0347
0.0409
0.0472
0.0535
0.0598
0.0661
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
DMAG
No connect
No connect
No connect
No connect
No connect
187
188
0.0724
0.0787
-0.2406
-0.2406
DMACK
No connect
189
0.0850
-0.2406
MSG_INT
190
191
192
193
194
195
0.0913
0.0976
0.1039
0.1102
0.1165
0.1228
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
No connect
VSS
VDD
VSSQ
VDDQ
No connect
196
197
0.1291
0.1354
-0.2406
-0.2406
YF_INT
No connect
198
199
200
0.1417
0.1480
0.1543
-0.2406
-0.2406
-0.2406
AUTOEN
No connect
No connect
NOTE: The die center is the coordinate origin (0,0).
FIGURE A-1
SIZE
STANDARD
5962-92118
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
SHEET
H
42
DSCC FORM 2234
APR 97
Appendix A
APPENDIX A FORMS A PART OF SMD 5962-92118
Die bonding pad locations and electrical functions
PAD
XCENTER
YCENTER
PAD NAME
201
202
203
0.1606
0.1669
0.1732
-0.2406
-0.2406
-0.2406
No connect
No connect
No connect
204
205
0.1795
0.1858
-0.2406
-0.2406
ROMEN
No connect
206
207
0.1921
0.1984
-0.2406
-0.2406
CS
No connect
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
0.2047
0.2110
0.2173
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
-0.2406
-0.2406
-0.2406
-0.2173
-0.2110
-0.2047
-0.1984
-0.1921
-0.1858
-0.1795
-0.1732
-0.1669
-0.1606
-0.1543
-0.1480
-0.1417
-0.1354
-0.1291
-0.1228
-0.1165
-0.1102
-0.1039
-0.0976
-0.0913
-0.0850
-0.0787
-0.0724
-0.0661
-0.0598
-0.0535
-0.0472
-0.0409
-0.0347
RD/ WR
VSS
VDD
VSSQ
VDDQ
A15
No connect
A14
No connect
A13
No connect
No connect
No connect
A12
No connect
A11
No connect
A10
No connect
VSS
VDD
VSSQ
VDDQ
No connect
A9
No connect
A8
No connect
No connect
No connect
No connect
No connect
A7
NOTE: The die center is the coordinate origin (0,0).
FIGURE A-1
SIZE
STANDARD
5962-92118
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
SHEET
H
43
DSCC FORM 2234
APR 97
Appendix A
APPENDIX A FORMS A PART OF SMD 5962-92118
Die bonding pad locations and electrical functions
PAD
XCENTER
YCENTER
PAD NAME
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
-0.0284
-0.0221
-0.0158
-0.0095
-0.0032
0.0032
0.0095
0.0158
0.0221
0.0284
0.0347
0.0409
0.0472
0.0535
0.0598
0.0661
0.0724
0.0787
0.0850
0.0913
0.0976
0.1039
0.1102
0.1165
0.1228
0.1291
0.1354
0.1417
0.1480
0.1543
0.1606
0.1669
0.1732
0.1795
0.1858
No connect
MHz24
No connect
VDDQ
VDD
VSS
VSSQ
No connect
A6
No connect
A5
No connect
No connect
No connect
No connect
No connect
A4
No connect
A3
No connect
VDDQ
VSSQ
VDD
VSS
No connect
A2
No connect
A1
No connect
No connect
No connect
No connect
No connect
A0
No connect
276
277
0.2349
0.2349
0.1921
0.1984
RWR
No connect
278
279
280
0.2349
0.2349
0.2349
0.2047
0.2110
0.2173
RRD
VDDQ
VSSQ
NOTE: The die center is the coordinate origin (0,0).
FIGURE A-1
SIZE
STANDARD
5962-92118
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
SHEET
H
44
DSCC FORM 2234
APR 97
Appendix A
APPENDIX A FORMS A PART OF SMD 5962-92118
NOTES:
1. Die bondpad numbers are for reference only.
2. Dimensions are in inches and are basic.
3. Die thickness is 0.0175 ±0.001.
4. Die backside is as lapped.
5. The die center is the coordinate origin (0,0).
6. Backside bias is VDD for device type 02.
FIGURE A-1
SIZE
STANDARD
5962-92118
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
J
SHEET
45
DSCC FORM 2234
APR 97
Appendix A
APPENDIX A FORMS A PART OF SMD 5962-92118
Die bonding pad locations and electrical functions
PAD
XCENTER
YCENTER
PAD NAME
1
2
3
0.2173
0.2110
0.2047
0.2406
0.2406
0.2406
VDD
VSS
No connect
4
5
6
7
0.1984
0.1921
0.1858
0.1795
0.2406
0.2406
0.2406
0.2406
RCS
No connect
TCLK
No connect
8
9
0.1732
0.1669
0.1606
0.1543
0.1480
0.1417
0.1354
0.1291
0.1228
0.1165
0.1102
0.1039
0.0976
0.0913
0.0850
0.0787
0.0724
0.0661
0.0598
0.0535
0.0472
0.0410
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
DTACK
No connect
No connect
D15
No connect
D14
No connect
D13
No connect
VDDQ
VSSQ
VDD
VSS
No connect
D12
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
No coonect
D11
No connect
No connect
No connect
No connect
No connect
30
31
32
33
34
35
36
37
38
39
40
0.0347
0.0284
0.0221
0.0158
0.0095
0.0031
-0.0032
-0.0095
-0.0158
-0.0221
-0.0284
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
D10
No connect
D9
No connect
VSSQ
VSS
VDD
VDDQ
No connect
D8
No connect
NOTE: The die center is the coordinate origin (0,0).
FIGURE B-1
SIZE
STANDARD
5962-92118
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
J
SHEET
46
DSCC FORM 2234
APR 97
Appendix A
APPENDIX A FORMS A PART OF SMD 5962-92118
Die bonding pad locations and electrical functions
PAD
XCENTER
YCENTER
PAD NAME
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
-0.0346
-0.0409
-0.0472
-0.0535
-0.0598
-0.0661
-0.0724
-0.0787
-0.0850
-0.0913
-0.0976
-0.1039
-0.1102
-0.1165
-0.1228
-0.1291
-0.1354
-0.1417
-0.1480
-0.1543
-0.1606
-0.1669
-0.1732
-0.1795
-0.1858
-0.1921
-0.1984
-0.2047
-0.2110
-0.2173
-0.2349
-0.2349
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2173
0.2110
D7
No connect
No connect
No connect
No connect
No connect
D6
No connect
D5
No connect
VSS
VDD
VSSQ
VDDQ
No connect
D4
No connect
D3
No connect
No connect
No connect
No connect
No connect
D2
No connect
D1
No connect
D0
VSS
VDD
VSSQ
VDDQ
73
74
-0.2349
-0.2349
0.2047
0.1984
TIMERONA
No connect
75
76
77
78
-0.2349
-0.2349
-0.2349
-0.2349
0.1921
0.1858
0.1795
0.1732
TA
No connect
TA
No connect
79
80
-0.2349
-0.2349
0.1669
0.1606
RA
No connect
NOTE: The die center is the coordinate origin (0,0).
FIGURE B-1
SIZE
STANDARD
5962-92118
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
J
SHEET
47
DSCC FORM 2234
APR 97
Appendix A
APPENDIX A FORMS A PART OF SMD 5962-92118
Die bonding pad locations and electrical functions
PAD
XCENTER
YCENTER
PAD NAME
81
82
83
84
-0.2349
-0.2349
-0.2349
-0.2349
0.1543
0.1480
0.1417
0.1354
No connect
No connect
RA
No connect
85
86
87
88
89
90
91
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
0.1291
0.1228
0.1165
0.1102
0.1039
0.0976
0.0913
TIMERONB
No connect
VSS
VDD
VSSQ
VDDQ
No connect
92
93
94
95
96
97
98
99
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
0.0850
0.0787
0.0724
0.0661
0.0598
0.0535
0.0472
0.0409
TB
No connect
TB
No connect
No connect
No connect
No connect
No connect
100
101
102
103
104
105
106
107
108
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
0.0347
0.0284
0.0221
0.0158
0.0095
0.0032
-0.0032
-0.0095
-0.0158
RB
No connect
RB
No connect
VSSQ
VSS
VDD
VDDQ
No connect
109
110
-0.2349
-0.2349
-0.0221
-0.0284
TERACT
No connect
111
112
113
114
115
116
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.0374
-0.0409
-0.0472
-0.0535
-0.0598
-0.0661
READY
No connect
No connect
No connect
No connect
No connect
117
118
119
120
-0.2349
-0.2349
-0.2349
-0.2349
-0.0724
-0.0787
-0.0850
-0.0913
SSYSF
No connect
RTA4
No connect
NOTE: The die center is the coordinate origin (0,0).
FIGURE B-1
SIZE
STANDARD
5962-92118
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
J
SHEET
48
DSCC FORM 2234
APR 97
Appendix A
APPENDIX A FORMS A PART OF SMD 5962-92118
Die bonding pad locations and electrical functions
PAD
XCENTER
YCENTER
PAD NAME
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2173
-0.2110
-0.0976
-0.1039
-0.1102
-0.1165
-0.1228
-0.1291
-0.1354
-0.1417
-0.1480
-0.1543
-0.1606
-0.1669
-0.1732
-0.1795
-0.1858
-0.1921
-0.1984
-0.2047
-0.2110
-0.2173
-0.2406
-0.2406
VDDQ
VSSQ
VDD
VSS
No connect
RTA3
No connect
RTA2
No connect
No connect
No connect
No connect
No connect
RTA1
No connect
RTA0
No connect
RTPTY
VDDQ
VSSQ
VDD
VSS
143
144
-0.2047
-0.1984
-0.2406
-0.2406
LOCK
No connect
145
146
147
148
149
150
151
152
153
154
-0.1921
-0.1858
-0.1795
-0.1732
-0.1669
-0.1606
-0.1543
-0.1480
-0.1417
-0.1354
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
A/B STD
No connect
No connect
No connect
No connect
No connect
MSEL1
No connect
MSEL0
No connect
155
156
157
158
159
160
-0.1291
-0.1228
-0.1165
-0.1102
-0.1039
-0.0976
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
MRST
No connect
VDDQ
VSSQ
VDD
VSS
NOTE: The die center is the coordinate origin (0,0).
FIGURE B-1
SIZE
STANDARD
5962-92118
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
J
SHEET
49
DSCC FORM 2234
APR 97
Appendix A
APPENDIX A FORMS A PART OF SMD 5962-92118
Die bonding pad locations and electrical functions
PAD
XCENTER
YCENTER
PAD NAME
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
-0.0913
-0.0850
-0.0787
-0.0724
-0.0661
-0.0598
-0.0535
-0.0472
-0.0409
-0.0347
-0.0284
-0.0221
-0.0158
-0.0095
-0.0032
0.0032
0.0095
0.0158
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
No connect
No connect
No connect
No connect
No connect
No connect
No connect
No connect
TRS
TDO
TDI
TMS
TCK
VDDQ
VDD
VSS
VSSQ
No connect
179
180
0.0221
0.0284
-0.2406
-0.2406
DMAR
No connect
181
182
183
184
185
186
0.0347
0.0409
0.0472
0.0535
0.0598
0.0661
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
DMAG
No connect
No connect
No connect
No connect
No connect
187
188
0.0724
0.0787
-0.2406
-0.2406
DMACK
No connect
189
0.0850
-0.2406
MSG_INT
190
191
192
193
194
195
0.0913
0.0976
0.1039
0.1102
0.1165
0.1228
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
No connect
VSS
VDD
VSSQ
VDDQ
No connect
196
197
0.1291
0.1354
-0.2406
-0.2406
YF_INT
No connect
198
199
200
0.1417
0.1480
0.1543
-0.2406
-0.2406
-0.2406
AUTOEN
No connect
No connect
NOTE: The die center is the coordinate origin (0,0).
FIGURE B-1
SIZE
STANDARD
5962-92118
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
J
SHEET
50
DSCC FORM 2234
APR 97
Appendix A
APPENDIX A FORMS A PART OF SMD 5962-92118
Die bonding pad locations and electrical functions
PAD
XCENTER
YCENTER
PAD NAME
201
202
203
0.1606
0.1669
0.1732
-0.2406
-0.2406
-0.2406
No connect
No connect
No connect
204
205
0.1795
0.1858
-0.2406
-0.2406
ROMEN
No connect
206
207
0.1921
0.1984
-0.2406
-0.2406
CS
No connect
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
0.2047
0.2110
0.2173
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
-0.2406
-0.2406
-0.2406
-0.2173
-0.2110
-0.2047
-0.1984
-0.1921
-0.1858
-0.1795
-0.1732
-0.1669
-0.1606
-0.1543
-0.1480
-0.1417
-0.1354
-0.1291
-0.1228
-0.1165
-0.1102
-0.1039
-0.0976
-0.0913
-0.0850
-0.0787
-0.0724
-0.0661
-0.0598
-0.0535
-0.0472
-0.0409
-0.0347
RD/ WR
VSS
VDD
VSSQ
VDDQ
A15
No connect
A14
No connect
A13
No connect
No connect
No connect
A12
No connect
A11
No connect
A10
No connect
VSS
VDD
VSSQ
VDDQ
No connect
A9
No connect
A8
No connect
No connect
No connect
No connect
No connect
A7
NOTE: The die center is the coordinate origin (0,0).
FIGURE B-1
SIZE
STANDARD
5962-92118
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
J
SHEET
51
DSCC FORM 2234
APR 97
Appendix A
APPENDIX A FORMS A PART OF SMD 5962-92118
Die bonding pad locations and electrical functions
PAD
XCENTER
YCENTER
PAD NAME
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
-0.0284
-0.0221
-0.0158
-0.0095
-0.0032
0.0032
0.0095
0.0158
0.0221
0.0284
0.0347
0.0409
0.0472
0.0535
0.0598
0.0661
0.0724
0.0787
0.0850
0.0913
0.0976
0.1039
0.1102
0.1165
0.1228
0.1291
0.1354
0.1417
0.1480
0.1543
0.1606
0.1669
0.1732
0.1795
0.1858
No connect
MHz24
No connect
VDDQ
VDD
VSS
VSSQ
No connect
A6
No connect
A5
No connect
No connect
No connect
No connect
No connect
A4
No connect
A3
No connect
VDDQ
VSSQ
VDD
VSS
No connect
A2
No connect
A1
No connect
No connect
No connect
No connect
No connect
A0
No connect
276
277
0.2349
0.2349
0.1921
0.1984
RWR
No connect
278
279
280
0.2349
0.2349
0.2349
0.2047
0.2110
0.2173
RRD
VDDQ
VSSQ
NOTE: The die center is the coordinate origin (0,0).
FIGURE B-1
SIZE
STANDARD
5962-92118
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
J
SHEET
52
DSCC FORM 2234
APR 97
Appendix A
APPENDIX A FORMS A PART OF SMD 5962-92118
NOTES:
1. Die bondpad numbers are for reference only.
2. Dimensions are in inches and are basic.
3. Die thickness is 0.0175 ±0.001.
4. Die backside is as lapped.
5. The die center is the coordinate origin (0,0).
6. Backside bias is GND for device type 04.
FIGURE B-1
SIZE
STANDARD
5962-92118
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
J
SHEET
53
DSCC FORM 2234
APR 97
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 01-03-15
Approved sources of supply for SMD 5962-92118 are listed below for immediate acquisition information only and
shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be
revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a
certificate of compliance has been submitted to and accepted by DSCC-VA. This bulletin is superseded by the next
dated revision of MIL-HDBK-103 and QML-38535.
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962-9211801MXA
5962-9211801MXC
3/
3/
5962-9211801MYA
5962-9211801MYC
5962H9211802QXA
5962H9211802QXC
5962H9211802QYA
5962H9211802QYC
5962H9211802QZA
5962H9211802QZC
5962H9211802VXA
5962H9211802VXC
5962H9211802VYA
5962H9211802VYC
5962H9211802VZA
5962H9211802VZC
5962H9211802Q9A
5962H9211802V9A
5962-9211803QXA
5962-9211803QXC
5962-9211803QYA
5962-9211803QYC
3/
3/
3/
3/
3/
3/
3/
3/
3/
3/
3/
3/
3/
3/
3/
3/
65342
65342
65342
65342
UT69151EGCA
UT69151EGCC
UT69151EWCA
UT69151EWCC
See footnotes at end of table.
STANDARD MICROCIRCUIT DRAWING BULLETIN - Continued.
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962-9211803QZA
5962-9211803QZC
5962R9211804QYA
5962R9211804QYC
5962R9211804VYA
5962R9211804VYC
5962R9211804Q9B
5962R9211804V9B
5962F9211804QYA
5962F9211804QYC
5962F9211804VYA
5962F9211804VYC
5962F9211804Q9B
5962F9211804V9B
65342
65342
65342
65342
65342
65342
65342
65342
65342
65342
65342
65342
65342
65342
UT69151EFCA
UT69151EFCC
UT69151EWCAR
UT69151EWCCR
UT69151EWCAR
UT69151EWCCR
UT69151EQ-DIER
UT69151EV-DIER
UT69151EWCAF
UT69151EWCCF
UT69151EWCAF
UT69151EWCCF
UT69151EQ-DIEF
UT69151EV-DIEF
1/ The lead finish shown for each PIN representing
a hermetic package is the most readily available
from the manufacturer listed for that part. If the
desired lead finish is not listed, contact the vendor
to determine its availability.
2/ Caution. Do not use this number for item
acquisition. Items acquired to this number may not
satisfy the performance requirements of this drawing.
3/ No longer available from an approved source of supply.
Vendor CAGE
number
Vendor name
and address
65342
UTMC Microelectronics System Inc.
4350 Centennial Boulevard
Colorado Springs, Colorado 80907-3486
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.
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