5962-9305606MYA [ETC]
8K X 8 nvSRAM QuantumTrap CMOS Nonvolatile Static RAM; 8K ×8的nvSRAM QuantumTrap CMOS非易失性静态RAM
| 型号： | 5962-9305606MYA |
| 厂家： | 
ETC |
| 描述： | 8K X 8 nvSRAM QuantumTrap CMOS Nonvolatile Static RAM |
| 文件： | 总12页 (文件大小：335K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STK10C68
ABSOLUTE MAXIMUM RATINGSa
Note a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at condi-
tions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
Voltage on Input Relative to Ground. . . . . . . . . . . . . .–0.5V to 7.0V
Voltage on Input Relative to VSS . . . . . . . . . . –0.6V to (VCC + 0.5V)
Voltage on DQ0-7. . . . . . . . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V)
Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration). . . . . . . . 15mA
DC CHARACTERISTICS
(VCC = 5.0V ± 10%)
INDUSTRIAL/
MILITARY
COMMERCIAL
SYMBOL
PARAMETER
UNITS
NOTES
MIN
MAX
MIN
MAX
b
I
Average V
Current
85
75
90
75
65
55
mA
mA
mA
mA
t
t
t
t
= 25ns
= 35ns
= 45ns
= 55ns
CC
CC
AVAV
AVAV
AVAV
AVAV
1
65
N/A
c
I
I
Average V
Average V
Current during STORE
3
3
mA
All Inputs Don’t Care, V = max
CC
CC
CC
CC
CC
2
3
b
Current at t
= 200ns
W ≥ (V
– 0.2V)
AVAV
CC
All Others Cycling, CMOS Levels
10
10
mA
5V, 25°C, Typical
d
d
I
Average V
Current
27
23
28
24
21
20
mA
mA
mA
mA
t
t
t
t
= 25ns, E ≥ V
= 35ns, E ≥ V
= 45ns, E ≥ V
= 55ns, E ≥ V
SB
CC
(Standby, Cycling TTL Input Levels)
AVAV
AVAV
AVAV
AVAV
IH
IH
IH
IH
1
20
N/A
I
I
I
V
Standby Current
E ≥ (V
– 0.2V)
IN
SB
CC
CC
All Others V ≤ 0.2V or ≥ (V
2
750
±1
1500
±1
µA
µA
µA
(Standby, Stable CMOS Input Levels)
– 0.2V)
CC
Input Leakage Current
V
V
= max
CC
ILK
= V to V
SS
IN
CC
Off-State Output Leakage Current
V
V
= max
CC
= V to V , E or G ≥ V
SS CC
OLK
±5
±5
IN
IH
V
V
V
V
Input Logic “1” Voltage
Input Logic “0” Voltage
2.2
V
+ .5
2.2
V
+ .5
V
V
All Inputs
All Inputs
IH
CC
0.8
CC
0.8
V
– .5
V
– .5
IL
SS
SS
2.4
I
I
=– 4mA
Note a: Output Logic “1” Voltage
Output Logic “0” Voltage
Operating Temperature
2.4
V
OH
OL
OUT
OUT
0.4
70
0.4
85/125
V
= 8mA
T
0
–40/-55
°C
A
Note b: ICC and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
Note c: ICC1 is the average current required for the duration of the STORE cycle (tSTORE ).
Note d: E ≥2VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V
Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .See Figure 1
5.0V
480 Ohms
OUTPUT
CAPACITANCEe
(TA = 25°C, f = 1.0MHz)
30 pF
INCLUDING
SCOPE AND
FIXTURE
255 Ohms
SYMBOL
PARAMETER
MAX
UNITS
CONDITIONS
∆V = 0 to 3V
∆V = 0 to 3V
C
Input Capacitance
8
7
pF
IN
C
Output Capacitance
pF
OUT
Note e: These parameters are guaranteed but not tested.
Figure 1: AC Output Loading
September 2003
2
Document Control # ML0006 rev 0.1
STK10C68
SRAM READ CYCLES #1 & #2
(VCC = 5.0V ± 10%)
SYMBOLS
STK10C68-25 STK10C68-35 STK10C68-45 STK10C68-55
PARAMETER
UNITS
NO.
#1, #2
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
1
2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Chip Enable Access Time
Read Cycle Time
25
35
45
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ELQV
ACS
f
25
35
45
55
AVAV
RC
AA
g
3
Address Access Time
25
10
35
15
45
20
55
25
AVQV
4
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
GLQV
OE
OH
LZ
g
5
5
5
5
5
5
5
5
5
AXQX
6
ELQX
h
7
10
10
25
10
10
35
12
12
45
12
12
55
EHQZ
HZ
8
0
0
0
0
0
0
0
0
GLQX
OLZ
OHZ
PA
h
9
GHQZ
e
10
11
ELICCH
EHICCL
d, e
PS
Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles. NE must be high during entire cycle.
Note g: I/O state assumes E, G < VIL, W > VIH , and NE ≥ VIH; device is continuously selected.
Note h: Measured + 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlledf, g
2
t
AVAV
ADDRESS
3
t
AVQV
5
t
AXQX
DQ (DATA OUT)
DATA VALID
SRAM READ CYCLE #2: E Controlledf
2
t
AVAV
ADDRESS
E
1
11
EHICCL
t
ELQV
t
6
t
ELQX
7
t
EHQZ
G
9
t
4
GHQZ
t
GLQV
8
t
GLQX
DATA VALID
DQ (DATA OUT)
10
ELICCH
t
ACTIVE
STANDBY
I
CC
September 2003
3
Document Control # ML0006 rev 0.1
STK10C68
SRAM WRITE CYCLES #1 & #2
(VCC = 5.0V ± 10%)
SYMBOLS
STK10C68-25
STK10C68-35
STK10C68-45
STK10C68-55
NO.
PARAMETER
UNITS
#1
#2
Alt.
MIN
25
20
20
10
0
MAX
MIN
35
25
25
12
0
MAX
MIN
45
30
30
15
0
MAX
MIN
55
45
45
30
0
MAX
12
13
14
15
16
17
18
19
20
21
t
t
t
WC
Write Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
AVAV
t
t
t
Write Pulse Width
WLWH
WLEH
WP
CW
DW
t
t
t
t
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
ELWH
DVWH
WHDX
ELEH
DVEH
EHDX
t
t
t
t
t
DH
t
t
t
20
0
25
0
30
0
45
0
AVWH
AVEH
AW
t
t
t
AVWL
AVEL
EHAX
AS
t
t
t
0
0
0
0
WHAX
WR
h, i
t
t
10
13
14
15
WLQZ
WZ
t
t
5
5
5
5
WHQX
OW
Note i: If W is low when E goes low, the outputs remain in the high-impedance state.
Note j: E or W must be ≥ VIH during address transitions. NE ≥ VIH
.
SRAM WRITE CYCLE #1: W Controlledj
12
AVAV
t
ADDRESS
19
WHAX
14
ELWH
t
t
E
17
AVWH
t
18
AVWL
t
13
WLWH
W
t
16
15
DVWH
t
t
WHDX
DATA IN
DATA VALID
20
WLQZ
t
21
WHQX
t
HIGH IMPEDANCE
DATA OUT
PREVIOUS DATA
SRAM WRITE CYCLE #2: E Controlledj
12
AVAV
t
ADDRESS
18
19
14
ELEH
t
t
EHAX
t
AVEL
E
17
AVEH
t
13
WLEH
t
W
16
EHDX
15
DVEH
t
t
DATA IN
DATA VALID
HIGH IMPEDANCE
DATA OUT
September 2003
4
Document Control # ML0006 rev 0.1
STK10C68
STORE INHIBIT/POWER-UP RECALL
(VCC = 5.0V + 10%)
SYMBOLS
STK10C68
NO.
PARAMETER
UNITS NOTES
Standard
MIN
MAX
550
10
22
23
24
25
t
t
Power-up RECALL Duration
STORE Cycle Duration
µs
ms
V
k
RESTORE
STORE
V
V
Low Voltage Trigger Level
Low Voltage Reset Level
4.0
4.5
SWITCH
RESET
3.6
V
Note k: tRESTORE starts from the time VCC rises above VSWITCH
.
STORE INHIBIT/POWER-UP RECALL
VCC
5V
24
VSWITCH
25
VRESET
STORE INHIBIT
POWER-UP RECALL
22
t
RESTORE
DQ (DATA OUT)
POWER-UP
RECALL
BROWN OUT
STORE INHIBIT
BROWN OUT
STORE INHIBIT
BROWN OUT
STORE INHIBIT
NO RECALL
NO RECALL
RECALL WHEN
(V DID NOT GO
(V DID NOT GO
V
RETURNS
CC
CC
CC
BELOW V
)
BELOW V
)
ABOVE V
SWITCH
RESET
RESET
September 2003
5
Document Control # ML0006 rev 0.1
STK10C68
MODE SELECTION
E
H
L
L
L
L
W
X
H
L
G
X
L
NE
X
MODE
POWER
Standby
Active
Not Selected
H
H
L
Read SRAM
X
L
Write SRAM
Active
l
H
L
Nonvolatile RECALL
Nonvolatile STORE
Active
H
L
I
CC
2
L
L
L
H
L
H
L
X
No Operation
Active
Note l: An automatic RECALL takes place at power up, starting when VCC exceeds 4.25V and taking tRESTORE
.
STORE CYCLES #1 & #2
(VCC = 5.0V ± 10%)
SYMBOLS
NO.
PARAMETER
MIN
MAX
UNITS
#1
#2
Alt.
m
n
26
27
28
29
30
31
32
t
t
t
t
t
t
STORE Cycle Time
10
ms
ns
ns
ns
ns
ns
ns
WLQX
WLNH
ELQX
ELNH
STORE
WC
STORE Initiation Cycle Time
Output Disable Set-up to NE Fall
Output Disable Set-up to E Fall
NE Set-up
20
0
tGHNL
t
t
0
GHEL
NLEL
t
t
0
NLWL
ELWL
Chip Enable Set-up
0
t
Write Enable Set-up
0
WLEL
Note m: Measured with W and NE both returned high, and G returned low. STORE cycles are inhibited below 4.0V.
Note n: Once tWC has been satisfied by NE, G, W and E, the STORE cycle is completed automatically. Any of NE, G, W or E may be used to terminate
the STORE initiation cycle.
Note o: If E is low for any period of time in which W is high while G and NE are low, then a RECALL cycle may be initiated.
STORE CYCLE #1: W Controlledo
NE
28
30
27
G
t
t
t
GHNL
NLWL
WLNH
W
31
t
ELWL
E
26
t
WLQX
HIGH IMPEDANCE
DQ (DATA OUT)
STORE CYCLE #2: E Controlledo
30
t
NLEL
NE
29
t
GHEL
G
32
t
WLEL
W
E
27
t
ELNH
26
t
ELQX
HIGH IMPEDANCE
DQ (DATA OUT)
September 2003
6
Document Control # ML0006 rev 0.1
STK10C68
RECALL CYCLES #1, #2 & #3
(VCC = 5.0V ± 10%)
SYMBOLS
NO.
PARAMETER
MIN
MAX
UNITS
#1
#2
#3
p
33
34
35
36
37
38
39
40
t
t
t
t
t
t
t
t
t
t
t
RECALL Cycle Time
20
µs
ns
ns
ns
ns
ns
ns
µs
NLQX
ELQXR
ELNHR
NLEL
GLQXR
GLNH
NLGL
q
RECALL Initiation Cycle Time
NE Set-up
20
0
NLNH
tGLNL
Output Enable Set-up
Write Enable Set-up
0
GLEL
t
t
t
t
t
t
0
WHNL
ELNL
NLQZ
WHEL
GLEL
WHGL
ELGL
Chip Enable Set-up
0
NE Fall to Outputs Inactive
Power-up RECALL Duration
20
550
RESTORE
Note p: Measured with W and NE both high, and G and E low.
Note q: Once tNLNH has been satisfied by NE, G, W and E, the RECALL cycle is completed automatically. Any of NE, G or E may be used to terminate
the RECALL initiation cycle.
Note r: If W is low at any point in which both E and NE are low and G is high, then a STORE cycle will be initiated instead of a RECALL.
RECALL CYCLE #1: NE Controlledo
34
t
NLNH
NE
36
t
GLNL
G
W
E
37
t
WHNL
38
33
t
t
39
ELNL
NLQX
t
NLQZ
HIGH IMPEDANCE
DQ (DATA OUT)
RECALL CYCLE #2: E Controlledo
35
t
NLEL
NE
36
t
GLEL
G
W
E
37
34
t
t
WHEL
ELNHR
33
t
ELQXR
HIGH IMPEDANCE
DQ (DATA OUT)
,
r
RECALL CYCLE #3: G Controlledo
35
t
NLGL
NE
34
t
GLNH
G
37
t
WHGL
W
E
38
t
ELGL
33
t
GLQXR
HIGH IMPEDANCE
DQ (DATA OUT)
September 2003
7
Document Control # ML0006 rev 0.1
STK10C68
DEVICE OPERATION
The STK10C68 has two modes of operation: SRAM
mode and nonvolatile mode, determined by the
state of the NE pin. When in SRAM mode, the mem-
ory operates as a standard fast static RAM. While in
nonvolatile mode, data is transferred in parallel from
SRAM to Nonvolatile Elements or from Nonvolatile
Elements to SRAM.
NONVOLATILE STORE
A STORE cycle is performed when NE, E and W and
low and G is high. While any sequence that
achieves this state will initiate a STORE, only W initi-
ation (STORE cycle #1) and E initiation (STORE cycle
#2) are practical without risking an unintentional
SRAM WRITE that would disturb SRAM data. During a
STORE cycle, previous nonvolatile data is erased
and the SRAM contents are then programmed into
nonvolatile elements. Once a STORE cycle is initi-
ated, further input and output are disabled and the
DQ0-7 pins are tri-stated until the cycle is complete.
NOISE CONSIDERATIONS
Note that the STK10C68 is a high-speed memory
and so must have a high-frequency bypass capaci-
tor of approximately 0.1µF connected between VCC
and VSS, using leads and traces that are as short as
possible. As with all high-speed CMOS ICs, normal
careful routing of power, ground and signals will help
prevent noise problems.
If E and G are low and W and NE are high at the end
of the cycle, a READ will be performed and the out-
puts will go active, signaling the end of the STORE.
NONVOLATILE RECALL
SRAM READ
A RECALL cycle is performed when E, G and NE are
low and W is high. Like the STORE cycle, RECALL is
initiated when the last of the four clock signals goes
to the RECALL state. Once initiated, the RECALL
cycle will take tNLQX to complete, during which all
inputs are ignored. When the RECALL completes,
any READ or WRITE state on the input pins will take
effect.
The STK10C68 performs a READ cycle whenever E
and G are low and NE and W are high. The address
specified on pins A0-12 determines which of the 8,192
data bytes will be accessed. When the READ is initi-
ated by an address transition, the outputs will be
valid after a delay of tAVQV (READ cycle #1). If the
READ is initiated by E or G, the outputs will be valid
at tELQV or at tGLQV, whichever is later (READ cycle #2).
The data outputs will repeatedly respond to address
changes within the tAVQV access time without the need
for transitions on any control input pins, and will
remain valid until another address change or until E
or G is brought high or W or NE is brought low.
Internally, RECALL is a two-step procedure. First, the
SRAM data is cleared, and second, the nonvolatile
information is transferred into the SRAM cells. The
RECALL operation in no way alters the data in the
nonvolatile cells. The nonvolatile data can be
recalled an unlimited number of times.
SRAM WRITE
As with the STORE cycle, a transition must occur on
any one control pin to cause a RECALL, preventing
inadvertent multi-triggering. On power up, once VCC
exceeds the VCC sense voltage of 4.25V, a RECALL
cycle is automatically initiated. Due to this automatic
RECALL, SRAM operation cannot commence until
tRESTORE after VCC exceeds approximately 4.25V.
A WRITE cycle is performed whenever E and W are
low and NE is high. The address inputs must be sta-
ble prior to entering the WRITE cycle and must
remain stable until either E or W goes high at the
end of the cycle. The data on pins DQ0-7 will be writ-
ten into the memory if it is valid tDVWH before the end
of a W controlled WRITE or tDVEH before the end of an
E controlled WRITE.
POWER-UP RECALL
It is recommended that G be kept high during the
entire WRITE cycle to avoid data bus contention on
the common I/O lines. If G is left low, internal circuitry
will turn off the output buffers tWLQZ after W goes low.
During power up, or after any low-power condition
(VCC < 3.0V), an internal RECALL request will be
latched. When VCC once again exceeds the sense
voltage of 4.25V, a RECALL cycle will automatically
be initiated and will take tRESTORE to complete.
September 2003
8
Document Control # ML0006 rev 0.1
STK10C68
If the STK10C68 is in a WRITE state at the end of
power-up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10K Ohm resistor
should be connected either between W and system
VCC or between E and system VCC.
LOW AVERAGE ACTIVE POWER
The STK10C68 draws significantly less current
when it is cycled at times longer than 55ns. Figure 2
shows the relationship between ICC and READ cycle
time. Worst-case current consumption is shown for
both CMOS and TTL input levels (commercial tem-
perature range, VCC = 5.5V, 100% duty cycle on chip
enable). Figure 3 shows the same relationship for
WRITE cycles. If the chip enable duty cycle is less
than 100%, only standby current is drawn when the
chip is disabled. The overall average current drawn
by the STK10C68 depends on the following items:
1) CMOS vs. TTL input levels; 2) the duty cycle of
chip enable; 3) the overall cycle rate for accesses;
4) the ratio of READs to WRITEs; 5) the operating
temperature; 6) the VCC level; and 7) I/O loading.
HARDWARE PROTECT
The STK10C68 offers two levels of protection to
suppress inadvertent STORE cycles. If the control
signals (E, G, W and NE) remain in the STORE con-
dition at the end of a STORE cycle, a second STORE
cycle will not be started. The STORE (or RECALL)
will be initiated only after a transition on any one of
these signals to the required state. In addition to
multi-trigger protection, STOREs are inhibited when
VCC is below 4.0V, protecting against inadvertent
STOREs.
100
80
100
80
60
60
TTL
CMOS
40
40
TTL
20
20
CMOS
0
0
50
100
150
200
50
100
150
200
Cycle Time (ns)
Cycle Time (ns)
Figure 2: ICC (max) Reads
Figure 3: ICC (max) Writes
September 2003
9
Document Control # ML0006 rev 0.1
STK10C68
ORDERING INFORMATION
- 5 P F 45 I
STK10C68
Temperature Range
Blank = Commercial (0 to 70°C)
I = Industrial (–40 to 85°C)
M = Military (–55 to 125°C)
Access Time
25 = 25ns
35 = 35ns
45 = 45ns
55 = 55ns (Military only)
Lead Finish (Plastic only)
Blank = 85%Sn/15%Pb
F = 100% Sn (Matte Tin)
Package
P = Plastic 28-pin 300 mil DIP
S = Plastic 28-pin 350 mil SOIC
C = Ceramic 28-pin 300 mil DIP (gold lead finish)
K = Ceramic 28-pin 300 mil DIP (solder dip finish)
L = Ceramic 28 pin LCC
Retention / Endurance
6
Blank = Comm/Ind (100 years/10 cycles)
5
5 = Military (10 years/10 cycles)
5962-93056 04 MX X
Lead Finish
A = Solder DIP lead finish
C = Gold lead DIP finish
X = Lead finish “A” or “C” is acceptable
Package
MX = Ceramic 28 pin 300-mil DIP
MY = Ceramic 28 pin LCC
Access Time
04 = 55ns
05 = 45ns
06 = 35ns
September 2003
10
Document Control # ML0006 rev 0.1
STK10C68
Document Revision History
Revision
0.0
Date
December 2002
September 2003
Summary
Combined commercial, industrial and military data sheets. Removed 20 nsec device.
Added lead-free lead finish
0.1
September 2003
11
Document Control # ML0006 rev 0.1
STK10C68
September 2003
12
Document Control # ML0006 rev 0.1
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