5962-9089913QUA
更新时间:2024-09-18 01:55:59
品牌:ETC
描述:MICROCIRCUIT, MEMORY, DIGITAA, CMOS, 128K X 8 BIT FLASH EEPROM, MONOLITHIC SILICON
5962-9089913QUA 概述
MICROCIRCUIT, MEMORY, DIGITAA, CMOS, 128K X 8 BIT FLASH EEPROM, MONOLITHIC SILICON 微型电路,内存, DIGITAA , CMOS , 128K ×8位闪存EEPROM ,单片硅
5962-9089913QUA 数据手册
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PDF下载1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix
A for device class M.
1.3 Absolute maximum ratings. 1/
Endurance:
Device types 01-04, 09 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10,000 cycles/byte, minimum
Device types 05-08 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1,000 cycles/byte, minimum
Device types 10-13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100,000 cycles/byte, minimum
Supply voltage range (V ) 2/ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0 V dc to +7.0 V dc
CC
Storage temperature range (T ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 C to +150 C
stg
Maximum power dissipation (P ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 W
D
Lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . +300 C
Junction temperature (T ) 3/ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150 C
J
Thermal resistance, junction-to-case (
Thermal resistance, junction-to-case (
Thermal resistance, junction-to-case (
) (case outline X, Y) . . . . . . See MIL-STD-1835
) (case outlines T, Z) . . . . . . 13 C/W
) (case outline U) . . . . . . . . . 27 C/W
JC
JC
JC
Voltage on any pin with respect to ground 2/ . . . . . . . . . . . . . . . . . . . . . -2.0 V dc to +7.0 V dc
Voltage on pin A with respect to ground 4/ . . . . . . . . . . . . . . . . . . . . . -2.0 V dc to +13.5 V dc
9
V
V
supply voltage with respect to ground 4/ . . . . . . . . . . . . . . . . . . . . -2.0 V dc to +14.0 V dc
supply voltage with respect to ground 2/ . . . . . . . . . . . . . . . . . . . . -2.0 V dc to +7.0 V dc
PP
CC
Output short circuit current 5/ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA
Data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 years minimum
1.4 Recommended operating conditions. 6/
Supply voltage range (V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5 V dc to +5.5 V dc
CC
Operating temperature range (T
Low level input voltage range (V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V dc to +0.8 V dc
High level input voltage range (V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.0 V dc to V
High level input voltage range, CMOS (V ) . . . . . . . . . . . . . . . . . . . . . . V
) . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to +125 C
case
IL
IH
+0.5 V dc
CC
-0.5 V dc to V
+0.5 V dc
IH
CC
CC
Chip clear (V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4 V dc to 12.6 V dc
P
1.5 Digital logic testing for device classes Q and V.
Fault coverage measurement of manufacturing
logic tests (MIL-STD-883, test method 5012) . . . . . . . . . . . . . . . . . . . . 100 percent
1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
2/ Minimum dc voltage on input or V pins is -0.5 V. During voltage transitions, inputs may overshoot V
to -2.0 V for
O
SS
periods of up to 20 ns. Maximum dc voltage on output and V pins is V
+0.5 V. During voltage transitions outputs
O
CC
may overshoot to V
+2.0 V for periods up to 20 ns.
CC
3/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in
accordance with method 5004 of MIL-STD-883.
4/ Minimum dc input voltage on A or V
may overshoot to +14.0 V for periods less than 20 ns.
9
PP
5/ No more than one output shorted at a time. Duration of short circuit should not be greater than 1 second.
6/ All voltages are referenced to V (ground).
SS
SIZE
STANDARD
5962-90899
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
C
SHEET
3
DSCC FORM 2234
APR 97
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a
part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in
the issue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, cited in the
solicitation.
SPECIFICATION
DEPARTMENT OF DEFENSE
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
STANDARDS
DEPARTMENT OF DEFENSE
MIL-STD-883
MIL-STD-973
-
-
Test Method Standard Microcircuits.
Configuration Management.
MIL-STD-1835 - Interface Standard for Microcircuit Case Outlines.
HANDBOOKS
DEPARTMENT OF DEFENSE
MIL-HDBK-103 - List of Standard Microcircuit Drawings (SMD's).
MIL-HDBK-780 - Standard Microcircuit Drawings.
(Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the Standardization
Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094).
2.2 Non-Government publications. The following documents form a part of this document to the extent specified herein.
Unless otherwise specified, the issues of the documents which are DoD adopted are those listed in the issue of the DODISS
cited in the solicitation. Unless otherwise specified, the issues of documents not listed in the DODISS are the issues of the
documents cited in the solicitation.
AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM)
ASTM Standard F1192-95
-
Standard Guide for the Measurement of Single Event Phenomena from
Heavy Ion Irradiation of Semiconductor Devices.
(Applications for copies of ASTM publications should be addressed to the American Society for Testing and Materials,
1916 Race Street, Philadelphia, PA 19103).
ELECTRONICS INDUSTRIES ASSOCIATION (EIA)
JEDEC Standard EIA/JESD78
-
IC Latch-Up Test.
(Applications for copies should be addressed to the Electronics Industries Alliance, 2500 Wilson Blvd., Arlington, VA 22201.)
(Non-Government standards and other publications are normally available from the organizations that prepare or distribute
the documents. These documents also may be available in or through libraries or other informational services).
2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the
text of this drawing shall take precedence. Nothing in this document, however, supersedes applicable laws and regulations
unless a specific exemption has been obtained.
SIZE
STANDARD
5962-90899
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
REVISION LEVEL
C
SHEET
COLUMBUS, OHIO 43216-5000
4
DSCC FORM 2234
APR 97
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-
38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The modification in
the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M
shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as
specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class
M.
3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2.
3.2.3 Truth tables. The truth tables shall be as specified on figure 3.
3.2.3.1 Unprogrammed devices. The truth table for unprogrammed devices for contracts involving no altered item
drawing shall be as specified on figure 3 herein. When required, in screening (see 4.2 herein), or quality conformance
inspection groups A, B, C, or D (see 4.4 herein), the devices shall be programmed by the manufacturer prior to test in a
checkerboard or similar pattern (a minimum of 50 percent of the total number of bits programmed).
3.2.3.2 Programmed devices. The requirements for supplying programmed devices are not part of this document.
3.2.3.3 Command definitions. The command definitions table shall be as specified on figure 3.
3.2.4 Switching test circuits and waveforms. The switching test circuits and waveforms shall be as specified on figure 4.
3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the
full case operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The
electrical tests for each subgroup are defined in table I.
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked as listed in MIL-HDBK-103. For packages where marking of the entire SMD PIN number is not feasible due to space
limitations, the manufacturer has the option of not marking the "5962-" on the device. For RHA product using this option, the
RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535.
Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A.
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required
in MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.
3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of
compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see
6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this
drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535
and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or
for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing.
3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 -
herein) involving devices acquired to this drawing is required for any change as defined in MIL-STD-973.
SIZE
STANDARD
5962-90899
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
REVISION LEVEL
C
SHEET
COLUMBUS, OHIO 43216-5000
5
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics.
Test
Symbol
Conditions
+125 C 1/
5.5 V
unless otherwise specified
Group A
Subgroups
Device
type
Limits
Units
-55 C
4.5 V
T
C
V
CC
Min
Max
DC CHARACTERISTICS
Input leakage
current
I
V
= V
CC CC
max,
max or V
1, 2, 3
1, 2, 3
All
All
±1.0
±10
µA
µA
LI
V
= V
CC
IN
SS
Output leakage
current
I
V
V
= V
= V
max,
max or V
LO
CC
OUT
CC
CC
SS
V
standby
I
I
I
V
= V
CC
max, CE = V
1, 2, 3
1, 2, 3
1, 2, 3
All
All
All
1.0
100
30
mA
µA
CC
current (TTL)
CCS1
CCS2
CC1
CC
IH
V
standby
CE = V
±0.2 V,
max
CC
current (CMOS)
CC
= V
V
CC
CC
V
active read
V
I
= V
CC
max, CE = V
mA
CC
current
CC
OUT
IL
= 0 mA, f = 6.0 MHz,
OE = V
IH
V
programming
I
I
I
CE = V , programming in
IL
1, 2, 3
1, 2, 3
1, 2, 3
All
All
All
30 2/
30 2/
±10
mA
mA
µA
CC
current
CC2
CC3
PPS
progress
V
erase
CE = V , erasure in progress
IL
CC
current
V
standby
V
= V
PP
current
PP
PPL
V
read current
I
V
V
= V
= V
1, 2, 3
All
All
200
±10
µA
PP
PP1
PP
PPH
PP
PPL
V
programming
I
V
= V
, programming in
1, 2, 3
30 2/
mA
PP
PP2
PP
PPH
current
progress
See footnotes at end of table.
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-90899
A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
C
SHEET
6
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions
+125 C 1/
5.5 V
unless otherwise specified
Group A
Subgroups
Device
type
Limits
Units
-55 C
4.5 V
T
C
V
CC
Min
Max
DC CHARACTERISTICS - Continued
V
erase current
I
V
PP
= V
PPH
erasure in progress 1, 2, 3
All
All
30 2/
0.8
mA
V
PP
PP3
Low level input
voltage
V
V
V
V
V
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
-0.5 2/
2.0
IL
High level input
voltage (TTL)
All
All
All
All
V
+ 0.5
V
V
V
V
IH1
IH2
OL
OH1
CC
2/
High level input
voltage (CMOS)
0.7 V
CC
V
+ 0.5
CC
2/
Low level output
voltage
I
OL
= 2.1 mA, V
CC
= V
CC
min
0.45
High level output
voltage (TTL)
I
= -2.5 mA, V
= V
min
2.4
OH
CC
CC
High level output
voltage (CMOS)
V
V
I
I
= -2.5 mA, V
= -100 µA, V
= V
= V
min
min
0.85 V
CC
V
V
OH2
OH
CC
CC
1, 2, 3
All
V
- 0.4
OH3
OH
CC
CC
CC
2/
A9 auto select
voltage
V
I
A9 = V
ID
1, 2, 3
1, 2, 3
All
All
All
All
All
11.5
13.0
V
ID
A9 auto select
current
A9 = V max, V
ID
= V
max
500 2/
µA
V
ID
CC
CC
V
during read
V
NOTE: erase/program are
inhibited when V
1, 2, 3
0
V
+ 2.0
PP
only operations
PPL
PPH
CC
2/
= V
PP
PPL
V
during read/write
V
1, 2, 3
11.4
12.6
V
PP
operations
Functional tests
See 4.4.1d
7, 8A, 8B
See footnotes at end of table.
SIZE
STANDARD
5962-90899
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
C
SHEET
7
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions
Group A
Device
type
Limits
Units
-55 C
4.5 V
T
+125 C 1/ Subgroups
5.5 V
C
V
CC
Min
Max
unless otherwise specified
CAPACITANCE 2/
Input capacitance
C
V
= 0 V, T = 25 C,
4
All
10
pF
IN1
IN
A
f = 1.0 Mhz, see 4.4.1c
Output capacitance
C
V
= 0 V, T = 25 C,
4
4
All
All
12
12
pF
pF
OUT
OUT
A
f = 1.0 Mhz, see 4.4.1c
V
input capacitance
C
V
= 0 V, T = 25 C,
PP
IN2
IN
A
f = 1.0 Mhz, see 4.4.1c
AC CHARACTERISTICS - READ ONLY OPERATIONS (See figure 5 as applicable.)
Read cycle time
t
2/
9, 10, 11
01,05,10
02,06,11
03,07,12
04,08,13
09
250
200
150
120
90
ns
AVAV
Chip enable access
time
t
t
9, 10, 11
9, 10, 11
01,05,10
02,06,11
03,07,12
04,08,13
09
250
200
150
120
90
ns
ns
ELQV
Address access
time
01,05,10
02,06,11
03,07,12
04,08,13
09
250
200
150
120
90
AVQV
See footnotes at end of table.
SIZE
STANDARD
5962-90899
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
C
SHEET
8
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions
+125 C 1/
5.5 V
unless otherwise specified
Group A
Subgroups
Device
type
Limits
Units
-55 C
4.5 V
T
C
V
CC
Min
Max
AC CHARACTERISTICS - READ ONLY OPERATIONS - Continued. (See figure 5 as applicable.)
Output enable
access time
t
9, 10, 11
01,05
02,06
03,07,10,
11,12
04,08,13
09
65
60
ns
GLQV
55
50
40
Chip enable to
output in low Z
t
t
t
t
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
All
0 2/
ns
ns
ns
ns
ELQX
EHQZ
GLQX
GHQZ
Chip disable to
output in high Z
2/
2/
All
All
55
Output enable to
output in low Z
0 2/
Output disable to
output in high Z
01,05
02,06
60
45
03,07,10,
11,12
04,08,09,
13
35
30
Output hold from
address, CE, or
OE change
t
t
3/
9, 10, 11
9, 10, 11
All
0 2/
6.0
ns
µs
AXQX
Write recovery
time before read
All
WHGL
ERASE AND PROGRAMMING PERFORMANCE
Chip erase
Excludes 00H programming
9, 10, 11
All
All
60
24
s
s
Chip program
Excludes system overhead 4/ 9, 10, 11
1/ Case temperatures are instant on.
2/ Parameters shall be tested as part of device initial characterization and after design and process change. Parameter
shall be guaranteed to the limits specified in table I for all lots not specifically tested.
3/ Whichever occurs first.
4/ Minimum byte programming time excluding system overhead is 16 µs (10 µs programming +6.0 µs write recovery), while
maximum is 400 µs/byte (16 µs x 25 loops allowed by algorithm). Maximum chip programming time is specified lower
than the worst case allowed by the programming algorithm since most bytes program significantly faster than the worst
case byte.
SIZE
STANDARD
5962-90899
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
REVISION LEVEL
C
SHEET
COLUMBUS, OHIO 43216-5000
9
DSCC FORM 2234
APR 97
3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain
the option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made
available onshore at the option of the reviewer.
3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in
microcircuit group number 41 (see MIL-PRF-38535, appendix A).
3.11 Processing of EEPROMs. All testing requirements and quality assurance provisions herein shall be satisfied by the
manufacturer prior to delivery.
3.11.1 Conditions of the supplied devices. Devices will be supplied in an unprogrammed or clear state. No provision will
be made for supplying programmed devices.
3.11.2 Erasure of EEPROMs. When specified, devices shall be erased in accordance with procedures and
characteristics specified in 4.5.1.
3.11.3 Programming of EEPROMs. When specified, devices shall be programmed in accordance with procedures and
characteristics specified in 4.5.2.
3.11.4 Verification of state of EEPROMs. When specified, devices shall be verified as either written to the specified
pattern or cleared. As a minimum, verification shall consist of performing a read of the entire array to verify that all bits are in
the proper state. Any bit that does not verify to be in the proper state shall constitute a device failure and the device shall be
removed from the lot or sample.
3.12 Endurance. A reprogrammability test shall be completed as part of the vendor's reliability monitors. This
reprogrammability test shall be done for initial characterization and after any design or process changes which may affect the
reprogrammability of the device. The methods and procedures may be vendor specific, but shall guarantee the number of
program/erase endurance cycles listed in section 1.3 herein over the full military temperature range. The vendor's procedure
shall be kept under document control and shall be made available upon request of the acquiring or preparing activity, along
with test data.
3.13 Data retention. A data retention stress test shall be completed as part of the vendor's reliability monitors. This test
shall be done for initial characterization and after any design or process change which may affect data retention. The
methods and procedures may be vendor specific, but shall guarantee the number of years listed in section 1.3 herein over
the full military temperature range. The vendor's procedure shall be kept under document control and shall be made
available upon request of the acquiring or preparing activity, along with test data.
SIZE
STANDARD
5962-90899
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
REVISION LEVEL
C
SHEET
COLUMBUS, OHIO 43216-5000
10
DSCC FORM 2234
APR 97
Case T
NOTE: Metric equivalents are given in parenthesis.
Symbol
Inches
Millimeters
Notes
Min
.057
.122
.010
.055
.014
.000
.540
Max
.080
.159
.014
.065
.018
.004
.565
Min
Max
2.03
4.04
0.36
1.65
0.46
0.10
14.35
A
1.45
3.10
0.25
1.38
0.36
0.00
13.72
A
1
Solid lid
Solid lid
A
2
A
3
B
CP
D
D
.400
.500
10.16
12.70
Reference
1
D
2
E
.440
.464
11.17
11.79
E
.300
.400
7.62
Reference
Typical
1
E
2
10.16
e
R
N
.043
.057
1.09
0.68
1.45
0.84
0.027
0.033
32
FIGURE 1. Case outlines.
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-90899
A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
C
SHEET
11
DSCC FORM 2234
APR 97
Case U
Inches mm Inches mm
.001
.002
.005
.006
.008
.017
.020
.034
0.03
0.05
0.13
0.15
0.20
0.43
0.51
0.86
.040
.045
.050
.132
.295
.280
1.02
1.15
1.27
3.35
7.49
7.11
.410 10.41
.820 20.83
NOTES:
1. Terminal one shall be identified by a mechanical index on the lead or body, or a mark on the top surface within the
region shown.
2. Terminal identification numbers need not appear on the package.
3. Weight: 1.5 g maximum.
4. Dimensions are in inches.
5. Metric equivalents are given for general information only.
FIGURE 1. Case outlines - Continued.
SIZE
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DSCC FORM 2234
APR 97
Case Z
Family: Ceramic leadless chip carrier
Millimeters
Inches
Symbol
A
Notes
Min
.057
.122
.010
.055
.014
.000
Max
.080
.159
.014
.065
.018
.004
.670
Min
1.45
3.10
0.25
1.40
0.36
0.00
Max
2.03
4.04
0.36
1.65
0.46
0.10
17.01
A
Solid lid
Solid lid
1
A
2
A
3
B
CP
D
D
.400
.300
10.16
7.62
Reference
1
D
2
E
.540
.560
.570
13.71
14.22
14.49
E
Reference
Typical
1
E
2
e
.440
.043
.460
.057
11.18
1.09
11.68
1.45
N
32
FIGURE 1. Case outlines - Continued.
SIZE
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MICROCIRCUIT DRAWING
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A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
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13
DSCC FORM 2234
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Device types
All
All
Case outlines
Terminal number
Terminal symbol
1
2
V
PP
A
16
3
A
15
4
A
12
5
A
7
6
A
6
7
A
5
8
A
4
9
A
3
10
11
12
13
14
15
16
17
18
19
20
21
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
V
SS
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
22
23
CE
A
10
24
25
26
27
28
29
30
31
32
OE
A
11
A
9
A
8
A
13
A
14
NC
WE
V
CC
FIGURE 2. Terminal connections.
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DSCC FORM 2234
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Bus operations
Pins
Operation
V
A
A
CE OE WE DQ - DQ
PP
1/
0
9
0
7
Read only
Read
V
A
A
V
V
V
V
V
V
V
V
Data out
3-state
PPL
PPL
PPL
PPL
0
9
IL
IL
IH
IL
IL
IH
Output disable
Standby
V
V
V
X 2/ X 2/
IH
IH
X 2/ X 2/
X 2/ X 2/ 3-state
Auto-select manufacturer
code 3/
V
V
4/
4/
V
V
5/
IL
ID
IL
IH
Auto-select device code 3/
V
V
V
V
V
V
A
V
A
V
V
V
V
V
V
V
V
V
V
V
6/
PPL
PPH
PPH
PPH
PPH
IH
ID
IL
IL
IL
IH
IL
IL
IL
IH
IH
IH
IH
Read/write Read
Output disable
Data out 7/
3-state
0
9
X 2/ X 2/
X 2/ X 2/
Standby 8/
Write
X 2/ X 2/ 3-state
A
A
V
V
Data in 9/
0
9
IH
IL
1/ Refer to dc characteristics. When V
= V
memory contents can be read but not written or erased.
PP
PPL
2/ X can be V or V
.
IL IH
3/ Manufacture and device code may also be accessed via a command register write sequence.
4/ is the auto select high voltage. Refer to dc characteristics.
5/ The output for DQ - DQ shall be as follows:
V
ID
0
7
DQ - DQ
0
7
DATA = 89H
DATA = 01H
6/ The output for DQ - DQ shall be as follows:
0
7
DQ - DQ
0
7
DATA = B4H (device types 01-09, 11-13)
DATA = A7H (device types 01-09)
DATA = A2H (device types 10-13)
7/ Read operations with V
= V
may access array data or the auto select codes.
at high voltage, the standby current equals I +I (standby).
PP
PPH
8/ With V
PP
CC PP
9/ Refer to command definitions for valid Data-In during a write operation.
FIGURE 3. Truth tables.
SIZE
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Command definitions, device types 01-09
Command
BUS
cycles
First BUS cycle
Second BUS cycle
Operation Address
Data
3/
Operation Address
Data
3/
required
1/
2/
1/
2/
RA
IA
X
Read memory
1
2
2
2
2
2
2
Write
Write
Write
Write
Write
Write
Write
X
00H/FFH
90H/80H
20H
Read
Read
Write
Read
Write
Read
Write
RD
ID
Read auto select codes 4/
Setup erase/erase
Erase verify
X
X
20H
EVD
PD
EA
X
A0H
X
Setup program/program
Program verify
40H
PA
X
X
C0H
PVD
FFH
Reset 5/
X
FFH
X
1/ Refer to BUS operations for definitions.
2/ RA = Address of the memory location to be read.
IA = Identifier address: 00H/01H for manufacturer code, 01H/A7H for device code.
EA = Address of memory location to be read during erase verify.
PA = Address of memory location to be programmed.
Address are latched on the falling edge of the write-enable pulse.
3/ RD = Data read from location RA during read operation.
ID = Data read from location IA during device identification.
EVD = Data read from location EA during erase verify.
PD = Data to be programmed at location PA. Data is latched on the rising edge of write-enable.
PVD = Data read from location PA during program verify. PA is latched on the program command.
4/ Following the read Auto Select code ID command, two read operations access manufacturer and device codes.
5/ The second bus cycle must be followed by the desired command register write.
Command definitions, device types 10-13
Command
BUS
cycles
First BUS cycle
Second BUS cycle
Operation Address
Data
3/
Operation Address
Data
3/
required
1/
2/
X
X
X
X
1/
2/
Read memory
1
3
2
2
Write
Write
Write
Write
00H/FFH
80H/90H
30H
Read
Read
Write
Write
RA
RD
Read auto select codes 4/
00H/01H 01H/A2H
Embedded erase setup/erase
X
30H
PD
Embedded program
setup/program
10H/50H
PA
Reset 5/
2
Write
X
FFH
Write
X
FFH
1/ Refer to BUS operations for definitions.
2/ RA = Address of the memory location to be read.
PA = Address of memory location to be programmed.
Address are latched on the falling edge of the WE pulse.
3/ RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE.
4/ Following the read Auto Select code ID command, two read operations access manufacturer and device codes.
5/ The second bus cycle must be followed by the desired command register write.
FIGURE 3. Truth tables - Continued.
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AC testing: Inputs are driven at 2.4 V for a
logic "1" and 0.45 V for a logic "0". Input pulse
rise and fall times are 10 ns.
FIGURE 4. Switching test circuits and waveforms.
SIZE
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AC waveforms for read operations
FIGURE 4. Switching test circuits and waveforms - Continued.
SIZE
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4. QUALITY ASSURANCE PROVISIONS
4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with
MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan
shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be
in accordance with MIL-PRF-38535, appendix A.
4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted
on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in
accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection.
4.2.1 Additional criteria for device class M.
a. Delete the sequence specified as initial (preburn-in) electrical parameters through interim (postburn-in) electrical
parameters of method 5004 and substitute lines 1 through 6 of table IIA herein.
b. Prior to burn-in, the devices shall be programmed (see 4.5.2 herein) with a checkerboard pattern or equivalent
(manufacturers at their option may employ an equivalent pattern provided it is a topologically true alternating bit
pattern). The pattern shall be read before and after burn-in. Devices having bits not in the proper state after burn-in
shall constitute a device failure and shall be included in the PDA calculation and shall be removed from the lot.
c. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made
available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases,
and power dissipation, as applicable, in accordance with the intent specified in test method 1015.
(1) Dynamic burn-in (method 1015 of MIL-STD-883, test condition D; for circuit, see 4.2.1c herein).
d. Interim and final electrical parameters shall be as specified in table IIA herein.
e. After the completion of all screening, the device shall be erased and verified prior to delivery.
4.2.2 Additional criteria for device classes Q and V.
a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the
device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under
document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with MIL-
PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test
method 1015 of MIL-STD-883.
b. Interim and final electrical test parameters shall be as specified in table IIA herein.
c. Additional screening for device class V beyond the requirements of device class Q shall be as specified in appendix B
of MIL-PRF-38535 and as detailed in table IIB herein.
4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in
accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for
groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with MIL-PRF-
38535 including groups A, B, C, D, and E inspections and as specified herein except where option 2 of MIL-PRF-38535 permits
alternate in-line control testing. Quality conformance inspection for device class M shall be in accordance with MIL-PRF-38535,
appendix A and as specified herein. Inspections to be performed for device class M shall be those specified in method 5005 of
MIL-STD-883 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
SIZE
STANDARD
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MICROCIRCUIT DRAWING
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TABLE IIA. Electrical test requirements. 1/ 2/ 3/ 4/ 5/ 6/ 7/
Line
no.
Test
requirements
Subgroups
(per method
5005, table I)
Subgroups
(per MIL-PRF-38535,
table III)
Device
class
M
Device
class
Q
Device
class
V
1
2
Interim electrical
parameters
(see 4.2)
1,7,9
or
2,8A,10
1,7,9
or
2,8A,10
Static burn-in I
method 1015
Not
required
Not
required
Not
required
3
4
Same as line 1
1*,7*
Dynamic burn-in
(method 1015)
Required
Required
Required
5
6
Same as line 1
1*,7*
Final electrical
parameters
1*,2,3,7*,
8A,8B,9,10,
11
1*,2,3,7*,
8A,8B,9,10,
11
1*,2,3,7*,
8A,8B,9,10,
11
7
8
Group A test
requirements
1,2,3,4**,7,8A, 1,2,3,4**,7,
1,2,3,4**,7,
8A,8B,9,10,
11
8B,9,10,
11
8A,8B,9,10,
11
Group C end-point
electrical
parameters
2,8A,10
2,8A,10
1,7,9
1,2,3,7
8A,8B
1,2,3,7,
8A,8B,9,10,
11
9
Group D end-point
electrical
parameters
2,3,7
8A,8B
2,3,7
8A,8B
10
Group E end-point
electrical
1,7,9
1,7,9
parameters
1/ Blank spaces indicate test are not applicable.
2/ Any or all subgroups may be combined when using high-speed testers.
3/ Subgroups 7 and 8 functional tests shall verify the truth table.
4/ * Indicates PDA applies to subgroups 1 and 7.
5/ ** See 4.4.1c.
6/
Indicates delta limit (see table IIB) shall be required where specified, and the delta values
shall be computed with reference to the previous interim electrical parameters (see line 1).
7/ See 4.4.1e.
4.4.1 Group A inspection.
a. Tests shall be as specified in table IIA herein.
b. Subgroups 5 and 6 in table I, method 5005 of MIL-STD-883 shall be omitted.
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c. Subgroup 4 (C and C
IN OUT
measurements) shall be measured only for initial qualification and after any process or
design changes which may affect input or output capacitance. Capacitance shall be measured between the
designated terminal and GND at a frequency of 1 MHz. Sample size is 15 devices with no failures and all input and
output terminals tested.
d. For device class M, subgroups 7 and 8 tests shall be sufficient to verify the truth table. For device classes Q and V,
subgroups 7 and 8 shall include verifying the functionality of the device; these tests shall have been fault graded in
accordance with MIL-STD-883, test method 5012 (see 1.5 herein).
e. O/V (latch-up) tests shall be measured only for initial qualification and after any design or process changes which may
affect the performance of the device. For device class M, procedures and circuits shall be maintained under document
revision level control by the manufacturer and shall be made available to the preparing activity or acquiring activity
upon request. For device classes Q and V, the procedures and circuits shall be under the control of the device
manufacturer's TRB in accordance with MIL-PRF-38535 and shall be made available to the preparing activity or
acquiring activity upon request. Testing shall be on all pins, on five devices with zero failures. Latch-up test shall be
considered destructive. Information contained in JEDEC Standard EIA/JESD78 may be used for reference.
f. All devices selected for testing shall be programmed with a checkerboard pattern or equivalent. After completion of all
testing, the devices shall be erased and verified, (except devices submitted for groups B, C, and D testing).
4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.2.1 Additional criteria for device class M.
a. Steady-state life test conditions, method 1005 of MIL-STD-883:
(1) The device selected for testing shall be programmed with a checkerboard pattern. After completion of all testing,
the devices shall be erased and verified (except devices submitted for group D testing).
(2) Test condition D or E. The test circuit shall be maintained by the manufacturer under document revision level
control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify
the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test
method 1005.
(3)
T = +125 C, minimum.
A
(4) Test duration: 1,000 hours, except as specified in method 1005 of MIL-STD-883.
b. All devices requiring end-point electrical testing shall be programmed with a checkerboard or equivalent alternating bit
pattern.
c. After the completion of all testing, the devices shall be cleared and verified prior to delivery.
4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature,
or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The
test circuit shall be maintained under document revision level control by the device manufacturer's TRB, in accordance with
MIL-PRF-38535, and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify
the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005 of
MIL-STD-883.
4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein.
The devices selected for testing shall be programmed with a checkerboard pattern. After completion of all testing, the devices
shall be erased and verified.
SIZE
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TABLE IIB. Delta limits at 25 C.
Test 1/
Device types
All
I
±10 percent of specified value
in table I.
CCS2
standby
I
±10 percent of specified value
in table I.
LI
I
±10 percent of specified value
in table I.
LO
1/ The above parameter shall be recorded before and after
the required burn-in and life tests to determine delta.
4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness
assured (see 3.5 herein). RHA levels for device classes M, Q, and V shall be as specified in MIL-PRF-38535.
a. End-point electrical parameters shall be as specified in table IIA herein.
b. For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as
specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to
radiation hardness assured tests as specified in MIL-PRF-38535, appendix A for the RHA level being tested. All
device classes must meet the postirradiation end-point electrical parameter limits as defined in table IA at T = +25 C
A
±5 C, after exposure, to the subgroups specified in table IIA herein.
c. When specified in the purchase order or contract, a copy of the RHA delta limits shall be supplied.
4.5 Methods of inspection. Methods of inspection shall be as specified in the appropriate figures and tables as follows.
4.5.1 Erasing procedures. The erasing procedures shall be as specified by the device manufacturer and shall be available
upon request.
4.5.2 Programming procedure. The programming procedures shall be as specified by the device manufacturer and shall be
made available upon request.
4.6 Delta measurements for device class V. Delta measurements, as specified in table IIA, shall be made and recorded
before and after the required burn-in screens and steady-state life tests to determine delta compliance. The electrical
parameters to be measured, with associated delta limits are listed in table IIB. The device manufacturer may, at his option,
either perform delta measurements or within 24 hours after burn-in perform final electrical parameter tests, subgroups 1, 7, and
9.
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device
classes Q and V or MIL-PRF-38535, appendix A for device class M.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a
contractor-prepared specification or drawing.
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6.1.2 Substitutability. Device class Q devices will replace device class M devices.
6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished in accordance with MIL-STD-973 using DD Form 1692,
Engineering Change Proposal.
6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus when a system
application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users
and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering
microelectronic devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0525.
6.4 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43216-5000, or telephone
(614) 692-0674.
6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in MIL-
PRF-38535, MIL-STD-1331, and as follows:
C
, C
. . . . . . . . . . . . . . Input and bidirectional output, terminal-to-GND capacitance.
IN OUT
GND . . . . . . . . . . . . . . . . . . . . Ground zero voltage potential.
I
I
I
T
T
. . . . . . . . . . . . . . . . . . . . . Supply current.
CC
IL
IH
C
A
. . . . . . . . . . . . . . . . . . . . . . Input current low.
. . . . . . . . . . . . . . . . . . . . . Input current high.
. . . . . . . . . . . . . . . . . . . . . Case temperature.
. . . . . . . . . . . . . . . . . . . . . Ambient temperature.
. . . . . . . . . . . . . . . . . . . . Positive supply voltage.
V
V
CC
. . . . . . . . . . . . . . . . . . . . . Output enable and Write enable voltage during chip erase.
H
O/V . . . . . . . . . . . . . . . . . . . . . Latchup over-voltage.
6.5.1 Timing limits. The table of timing values shows either a minimum or a maximum limit for each parameter. Input
requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the
system must supply at least that much time (even though most devices do not require it). On the other hand, responses from
the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never
provides data later than that time.
6.5.2 Timing parameter abbreviations. All timing abbreviations use lower case characters with upper case subscripts. The
initial character is always "t" and is followed by four descriptors. These characters specify two signal points arranged in a "from-
to" sequence that define a timing interval. The two descriptors for each signal specify the signal name and the signal transition.
Thus the format is:
t
X
X
X
X
Signal name from which interval is defined
Transition direction for first signal
Signal name to which interval is defined
Transition direction for second signal
a. Signal definitions:
b. Transition definitions:
A = Address
H = Transition to high
D = Data in
L = Transition to low
Q = Data out
V = Transition to valid
W = Write enable
E = Chip enable
G = Output enable
X = Transition to invalid or don't care
Z = Transition to off (high impedance)
SIZE
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6.5.3 Waveforms.
WAVEFORM
SYMBOL
INPUT
MUST BE
OUTPUT
WILL BE
VALID
VALID
CHANGE FROM
H TO L
WIIL CHANGE
FROM
H TO L
CHANGE FROM
L TO H
WILL CHANGE
FROM
L TO H
DON'T CARE
ANY CHANGE
PERMITTED
CHANGING
STATE
UNKNOWN
HIGH
IMPEDANCE
6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535.
The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and have agreed to
this drawing.
6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103.
The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been
submitted to and accepted by DSCC-VA.
SIZE
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STANDARD MICROCIRCUIT DRAWING SOURCE APPROVAL BULLETIN
DATE: 99-11-16
Approved sources of supply for SMD 5962-90899 are listed below for immediate acquisition only and shall be added to
MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised to include the addition
or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been
submitted to and accepted by DSCC-VA. This bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-
38535.
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962-9089901QXA
5962-9089901MXX
0EU86
SMJ28F010B-25JDDM
AM28F010-250/BXA
MD28F010-25/B
3/
3/
5962-9089901QYA
5962-9089901MYX
0EU86
3/
SMJ28F010B-25FEM
AM28F010-250/BUA
MR28F010-25/B
3/
5962-9089901MTX
5962-9089901MZX
5962-9089901QUA
5962-9089901MUX
3/
3/
0EU86
3/
MT28F010-25/B
MZ28F010-25/B
SMJ28F010B-25HKM
MF28F010-25/B
5962-9089902QXA
5962-9089902MXX
0EU86
SMJ28F010B-20JDDM
AM28F010-200/BXA
MD28F010-20/B
3/
3/
5962-9089902QYA
5962-9089902MYX
0EU86
3/
SMJ28F010B-20FEM
AM28F010-200/BUA
MR28F010-20/B
3/
5962-9089902MTX
5962-9089902MZX
5962-9089902QUA
5962-9089902MUX
3/
3/
0EU86
3/
MT28F010-20/B
MZ28F010-20/B
SMJ28F010B-20HKM
MF28F010-20/B
5962-9089903QXA
5962-9089903MXX
0EU86
SMJ28F010B-15JDDM
AM28F010-150/BXA
MD28F010-15/B
3/
3/
5962-9089903QYA
5962-9089903MYX
0EU86
3/
SMJ28F010B-15FEM
AM28F010-150/BUA
MR28F010-15/B
3/
5962-9089903MTX
5962-9089903MZX
5962-9089903QUA
5962-9089903MUX
3/
3/
0EU86
3/
MT28F010-15/B
MZ28F010-15/B
SMJ28F010B-15HKM
MF28F010-15/B
5962-9089904QXA
5962-9089904MXX
0EU86
SMJ28F010B-12JDDM
AM28F010-120/BXA
MD28F010-12/B
3/
3/
5962-9089904QYA
5962-9089904MYX
0EU86
3/
SMJ28F010B-12FEM
AM28F010-120/BUA
MR28F010-12/B
3/
5962-9089904MTX
5962-9089904MZX
5962-9089904QUA
5962-9089904MUX
3/
3/
0EU86
3/
MT28F010-12/B
MZ28F010-12/B
SMJ28F010B-12HKM
MF28F010-12/B
See footnotes at end of table.
1 of 3
STANDARD MICROCIRCUIT DRAWING SOURCE APPROVAL BULLETIN- continued.
Standard
microcircuit drawing
PIN 1/
5962-9089905QXA
5962-9089905MXX
Vendor
CAGE
number
0EU86
3/
3/
0EU86
3/
3/
3/
3/
0EU86
3/
Vendor
similar
PIN 2/
SMJ28F010B-25JDDM
AM28F010-250C3/BXA
MD28F010-25/B
SMJ28F010B-25FEM
AM28F010-250C3/BUA
MR28F010-25/B
MT28F010-25/B
MZ28F010-25/B
SMJ28F010B-25HKM
MF28F010-25/B
5962-9089905QYA
5962-9089905MYX
5962-9089905MTX
5962-9089905MZX
5962-9089905QUA
5962-9089905MUX
5962-9089906QXA
5962-9089906MXX
0EU86
3/
3/
SMJ28F010B-20JDDM
AM28F010-200C3/BXA
MD28F010-20/B
5962-9089906QYA
5962-9089906MYX
0EU86
3/
3/
SMJ28F010B-20FEM
AM28F010-200C3/BUA
MR28F010-20/B
5962-9089906MTX
5962-9089906MZX
5962-9089906QUA
5962-9089906MUX
3/
3/
0EU86
3/
MT28F010-20/B
MZ28F010-20/B
SMJ28F010B-20HKM
MF28F010-20/B
5962-9089907QXA
5962-9089907MXX
0EU86
3/
3/
SMJ28F010B-15JDDM
AM28F010-150C3/BXA
MD28F010-15/B
5962-9089907QYA
5962-9089907MYX
0EU86
3/
3/
SMJ28F010B-15FEM
AM28F010-150C3/BUA
MR28F010-15/B
5962-9089907MTX
5962-9089907MZX
5962-9089907QUA
5962-9089907MUX
3/
3/
0EU86
3/
MT28F010-15/B
MZ28F010-15/B
SMJ28F010B-15HKM
MF28F010-15/B
5962-9089908QXA
5962-9089908MXX
0EU86
3/
3/
SMJ28F010B-12JDDM
AM28F010-120C3/BXA
MD28F010-12/B
5962-9089908QYA
5962-9089908MYX
0EU86
3/
3/
SMJ28F010B-12FEM
AM28F010-120C3/BUA
MR28F010-12/B
5962-9089908MTX
5962-9089908MZX
5962-9089908QUA
5962-9089908MUX
3/
3/
0EU86
3/
MT28F010-12/B
MZ28F010-12/B
SMJ28F010B-12HKM
MF28F010-12/B
5962-9089909MXX
5962-9089909MYX
5962-9089909MTX
5962-9089909MZX
5962-9089909MUX
3/
3/
3/
3/
3/
MD28F010-90/B
MR28F010-90/B
MT28F010-90/B
MZ28F010-90/B
MF28F010-90/B
5962-9089910QXA
5962-9089910MXX
5962-9089910QYA
5962-9089910MYX
5962-9089910QUA
0EU86
3/
0EU86
3/
SMJ28F010B-25JDDM
AM28F010A-250/BXA
SMJ28F010B-25FEM
AM28F010A-250/BUA
SMJ28F010B-25HKM
0EU86
See footnotes at end of table.
2 of 3
STANDARD MICROCIRCUIT DRAWING SOURCE APPROVAL BULLETIN- continued.
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962-9089911QXA
5962-9089911QYA
5962-9089911MXX
5962-9089911MYX
5962-9089911QUA
0EU86
0EU86
3/
3/
0EU86
SMJ28F010B-20JDDM
SMJ28F010B-20FEM
AM28F010A-200/BXA
AM28F010A-200/BUA
SMJ28F010B-20HKM
5962-9089912QXA
5962-9089912QYA
5962-9089912MXX
5962-9089912MYX
5962-9089912QUA
0EU86
0EU86
3/
3/
0EU86
SMJ28F010B-15JDDM
SMJ28F010B-15FEM
AM28F010A-150/BXA
AM28F010A-150/BUA
SMJ28F010B-15HKM
5962-9089913QXA
5962-9089913QYA
5962-9089913MXX
5962-9089913MYX
5962-9089913QUA
0EU86
0EU86
3/
3/
0EU86
SMJ28F010B-12JDDM
SMJ28F010B-12FEM
AM28F010A-120/BXA
AM28F010A-120/BUA
SMJ28F010B-12HKM
1/ The lead finish shown for each PIN representing a hermetic package is the
most readily available from the manufacturer listed for the part. If the desired
lead finish is not listed, contact the Vendor to determine its availability.
2/ Caution. Do not use this number for item acquisition. Items acquired to this
number may not satisfy the performance requirements of this drawing.
3/ No longer available from an approved source.
Vendor CAGE
number
Vendor name
and address
Manufacturer
code
Device
code
0EU86
Austin Semiconductor Inc.
8701 Cross Park Drive
Austin, TX 78754-4566
97
B4H
The information contained herein is disseminated for convenience only and
the Government assumes no liability whatsoever for any inaccuracies in this
information bulletin.
3 of 3
5962-9089913QUA 相关器件
型号 | 制造商 | 描述 | 价格 | 文档 |
5962-9089913QXA | ETC | MICROCIRCUIT, MEMORY, DIGITAA, CMOS, 128K X 8 BIT FLASH EEPROM, MONOLITHIC SILICON | 获取价格 | |
5962-9089913QYA | ETC | MICROCIRCUIT, MEMORY, DIGITAA, CMOS, 128K X 8 BIT FLASH EEPROM, MONOLITHIC SILICON | 获取价格 | |
5962-9090101M3X | ETC | Single 8-bit Bus Transceiver | 获取价格 | |
5962-9090101MKA | IDT | Registered Bus Transceiver, FCT Series, 1-Func, 8-Bit, True Output, CMOS, CDFP24, CERPACK-24 | 获取价格 | |
5962-9090101MKX | ETC | Single 8-bit Bus Transceiver | 获取价格 | |
5962-9090101MLX | ETC | Single 8-bit Bus Transceiver | 获取价格 | |
5962-9090102M3A | IDT | LCC-28, Tube | 获取价格 | |
5962-9090102M3X | ETC | Single 8-bit Bus Transceiver | 获取价格 | |
5962-9090102MKX | ETC | Single 8-bit Bus Transceiver | 获取价格 | |
5962-9090102MLA | IDT | CDIP-24, Tube | 获取价格 |
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