5962-8957701Q9A [ETC]
Controller Miscellaneous - Datasheet Reference ; 控制器杂项 - 数据表参考\n
| 型号： | 5962-8957701Q9A |
| 厂家： | 
ETC |
| 描述： | Controller Miscellaneous - Datasheet Reference
|
| 文件： | 总50页 (文件大小：260K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
REVISIONS
LTR
A
DESCRIPTION
Changes in accordance with NOR 5962-R043-92
Changes in accordance with NOR 5962-R070-93
Change to class level V. Update boilerplate. - LTG
Changes in accordance with NOR 5962-R001-98
DATE (YR-MO-DA)
91-11-25
APPROVED
M. L. Poelking
93-01-22
M. L. Poelking
T. M. Hess
B
97-07-11
C
97-10-17
M. L. Poelking
D
E
Made Rad Hard changes in Table I. Added appendix A. - LTG
Update boilerplate to MIL-PRF-38535 requirements. – LTG
Added tests VOL2 and VOH2 to table I sheet 6. – LTG
99-09-08
01-04-25
01-12-21
02-07-23
M. L. Poelking
Thomas M. Hess
Thomas M. Hess
Thomas M. Hess
F
G
H
Correct the unit of measure from microseconds to nanoseconds for the
DMAG(L) to STDINTL(L) test on sheet 10 in Table I. - CFS
REV
G
35
C
G
36
C
G
37
C
G
G
39
C
G
40
C
G
41
E
G
42
E
G
43
C
G
44
C
G
45
E
G
46
C
G
G
48
E
SHEET
REV
38
C
47
F
E
29
E
F
C
31
E
G
32
C
G
33
C
G
34
C
SHEET
15
16
17
18
REV
19
20
21
H
22
C
23
E
24
F
25
F
26
G
27
E
28
E
30
H
REV STATUS
OF SHEETS
SHEET
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PMIC N/A
PREPARED BY
Christopher A. Rauch
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216
STANDARD
MICROCIRCUIT
DRAWING
CHECKED BY
Tim H. Noh
http://www.dscc.dla.mil
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
APPROVED BY
William K. Heckman
MICROCIRCUIT, DIGITAL, CMOS, BUS
CONTROLLER, REMOTE TERMINAL AND
MONITOR, MONOLITIHIC SILICON
DRAWING APPROVAL DATE
90-02-08
AMSC N/A
REVISION LEVEL
H
SIZE
CAGE CODE
5962-89577
A
67268
SHEET
1
OF
48
DSCC FORM 2233
APR 97
5962-E504-02
DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.
1. SCOPE
1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and
M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the
Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the
PIN.
1.2 PIN. The PIN is as shown in the following examples.
For device classes M and Q:
5962
-
89577
01
X
X
Federal
stock class
designator
\
RHA
designator
(see 1.2.1)
Device
type
(see 1.2.2)
Case
outline
(see 1.2.4)
Lead
finish
(see 1.2.5)
/
\/
Drawing number
For device class V:
5962
H
89577
01
V
X
X
Federal
RHA
designator
(see 1.2.1)
Device
type
(see 1.2.2)
Device
class
designator
(see 1.2.3)
Case
outline
(see 1.2.4)
Lead
finish
(see 1.2.5)
stock class
designator
\
/
\/
Drawing number
1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and
are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A
specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type
01
Generic number
UT1553BCRTM
Circuit function
Bus controller, remote terminal and monitor
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as listed
below. Since the device class designator has been added after the original issuance of this drawing, device classes M and Q
designators will not be included in the PIN and will not be marked on the device.
Device class
M
Device requirements documentation
Vendor self-certification to the requirements for MIL-STD-883 compliant,
non-JAN class level B microcircuits in accordance with MIL-PRF-38535,
appendix A
Q or V
Certification and qualification to MIL-PRF-38535
SIZE
STANDARD
5962-89577
MICROCIRCUIT DRAWING
A
REVISION LEVEL
C
SHEET
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
2
DSCC FORM 2234
APR 97
1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter
Descriptive designator
Terminals
Package style
Pin grid array
Leaded chip carrier w/unformed leads
Square chip carrier
X
Y
Z
CMGA15-P84
CQCC2-J84
CQCC1-N84
84
84
84
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or
MIL-PRF-38535, appendix A for device class M.
1.3 Absolute maximum ratings. 1/
Supply voltage range ...........................................................
DC input/dc output voltage range (VI/O).................................
DC input current (II) .............................................................
Storage temperature range ..................................................
Lead tempreature (soldering 10 seconds) ............................
Maximum power dissipation, (PD) 2/ ...................................
Maximum junction temperature (TJ) ...................................
Thermal resistance, junction-to-case (θJC) ...........................
Latchup immunity (ILU) ........................................................
Duty cycle..............................................................................
0.3 V to +7.0 V
-0.3 V to (VDD +0.3 V)
±10 mA
-65°C to +150°C
+300°C
300 mW
+175°C
See MIL-STD-1835
±150 mA
50 ±10 percent
1.4 Recommended operating conditions.
Supply voltage (VDD) ...........................................................
Case operating temperature range (TC) ..............................
Operating frequency (Fo) ......................................................
Radiation features:
4.5 V to 5.5 V
-55°C to +125°C
12 MHz ± .01 percent
Total dose..........................................................................
≥ 1 x 106 Rads (Si)
Single event phenomenon (SEP) effective linear energy threshold,
no upsets or latchup (see 4.4.4.4).....................................
Dose rate upset (20 ns pulse) ...........................................
Dose rate latchup...............................................................
Dose rate survivability........................................................
Neutron irradiated..............................................................
≥ 27 MEV- cm2 /mg
3/
3/
3/
> 1 x 1014
1.5 Digital logic testing for device classes Q and V.
Fault coverage measurement of manufacturing
logic tests (MIL-STD-883, test method 5012)........................
86.5 percent
1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
2/ Must withstand the added PD due to short circuit test (e.g., IOS).
3/ When characterized as a result of the procuring activities request, the condition will be specified.
SIZE
STANDARD
5962-89577
MICROCIRCUIT DRAWING
A
REVISION LEVEL
E
SHEET
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
3
DSCC FORM 2234
APR 97
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a
part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in
the issue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, cited in the
solicitation.
SPECIFICATION
DEPARTMENT OF DEFENSE
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
STANDARDS
DEPARTMENT OF DEFENSE
MIL-STD-883
-
Test Method Standard Microcircuits.
MIL-STD-1835 - Interface Standard Electronic Component Case Outlines.
HANDBOOKS
DEPARTMENT OF DEFENSE
MIL-HDBK-103 - List of Standard Microcircuit Drawings.
MIL-HDBK-780 - Standard Microcircuit Drawings.
(Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the Standardization
Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for
device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified
herein.
3.1.1 Microcircuit die. For the requirements for microcircuit die, see appendix A to this document.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified
in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.
3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.
3.2.3 Functional block diagram. The functional block diagram shall be as specified on figure 2.
3.2.4 Switching test circuit and waveforms. The switching test circuit and waveforms shall be as specified on figure 3.
3.2.5 Radiation exposure circuit. The radiation exposure circuit shall be as specified on figure 4.
SIZE
STANDARD
5962-89577
MICROCIRCUIT DRAWING
A
REVISION LEVEL
F
SHEET
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
4
DSCC FORM 2234
APR 97
3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and postirradiation parameter limits are as specified in table IA and shall apply over the
full case operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical
tests for each subgroup are defined in table IA.
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked as listed in MIL-HDBK-103. For packages where marking of the entire SMD PIN number is not feasible due to space
limitations, the manufacturer has the option of not marking the "5962-" on the device. For RHA product using this option, the
RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535.
Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A.
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in
MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.
3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of
compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see
6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this
drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535
and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in
MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered
to this drawing.
3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2
herein) involving devices acquired to this drawing is required for any change as defined in MIL-PRF-38535, appendix A.
3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain
the option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made
available onshore at the option of the reviewer.
3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in
microcircuit group number 105 (see MIL-PRF-38535, appendix A).
SIZE
STANDARD
5962-89577
MICROCIRCUIT DRAWING
A
REVISION LEVEL
F
SHEET
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
5
DSCC FORM 2234
APR 97
TABLE IA. Electrical performance characteristics.
Test
Symbol
Conditions
Group A
subgroups
Device
type
Limits
Unit
4.5 V ≤ VDD ≤ 5.5 V 1/
-55°C ≤ TC ≤+125°C
unless otherwise specified
Min
Max
0.8
Low level input voltage
TTL inputs
VIL
VIH
IIN
1, 2, 3
1, 2, 3
1, 2, 3
All
All
All
V
V
High level input voltage
TTL inputs 2/
2.0
-1
Input leakage current
TTL inputs
VIN = VDD or VSS
1
µA
M, D, P,L, R, F, G, H
1
All
-10
-1
10
With pull-up resistors
With pull-up resistors
V
IN = VDD
1, 2, 3
All
1
M, D, P,L, R, F, G, H
IN = VSS
1
All
All
-10
10
V
1, 2, 3
-550
-80
M, D, P,L, R, F, G, H
1
All
All
-900
-150
0.4
Low level output voltage
TTL outputs
VOL
IOL = 3.2 mA
1, 2, 3
V
V
Low level output voltage
CMOS outputs
VOL2
1, 2, 3
All
VSS
IOL = 50 µA
+0.1
High level output voltage
TTL outputs
VOH
1, 2, 3
1, 2, 3
All
All
2.4
V
V
IOH = -400 µA
IOH = -50 µA
High level output voltage
CMOS outputs
VOH2
VDD
-0.1
-10
Three-state output leakage
Current TTL outputs
IOZ
IOS
VOUT = VDD or VSS
1, 2, 3
1, 2, 3
1, 2, 3
All
All
All
10
µA
Short-circuit output current
3/ 4/
VDD = 5.5 V, VOUT = VDD
110
mA
mA
VDD = 5.5 V, VOUT = 0 V
-110
Quiescent current 5/ 14/
QIDD
1, 3
All
All
35
µA
2
1
mA
mA
Average operating current
3/ 6/
Input capacitance
IDD
f = 12 MHz, CL = 50 pF
See 4.4.1c
1, 2, 3
50
CIN
4
4
4
All
All
All
10
15
20
pF
pF
pF
Output capacitance
COUT
CIO
Bidirect I/O capacitance
See footnotes at end of table.
SIZE
STANDARD
5962-89577
MICROCIRCUIT DRAWING
A
REVISION LEVEL
G
SHEET
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
6
DSCC FORM 2234
APR 97
TABLE IA. Electrical performance characteristics. - Continued
Test
Symbol
Conditions
4.5 V ≤ VDD ≤ 5.5 V
Group A
subgroups
Device
type
Limits
Unit
-55°C ≤ TC ≤+125°C 1/
unless otherwise specified
Min
Max
Functional tests
See 4.4.1d
7, 8
TSHL1
See figure 3
9, 10, 11
All
0
10
ns
DMACK (L) to DMAR
high impedance
BURST DMA timing
-5
0
5
M,D,P,L,R,F,G,H
See figure 3
TPZL2
TPHL2
TPzL1
9, 10, 11
9, 10, 11
9, 10, 11
All
All
All
45
ns
ns
ns
DMAG (L) to DMACK (L)
7/
BURST DMA timing
2x
4x
DMAG (L) to TSCTL (L)
15/
MCLK
MCLK
0
40
40
TSCTL (L) to ADDRESS
valid 3/
-2
M,D,P,L,R,F,G,H
See figure 3
tHLH2
9, 10, 11
All
THMC1
-10
THMC1
+10
ns
RWR /RRD (H)
toDMACK (H)
BURST DMA timing
tPHL3
9, 10, 11
9, 10, 11
All
All
MCLK
-20
MCLK
+20
ns
ns
TSCTL (L) toRWR /RRD
(L)
tPW2
MCLK
6xMCLK
DMAG (L) to DMAG (H)
15/
tOOZL1
tPHL4
9, 10, 11
9, 10, 11
All
All
-10
0
10
ns
DMAR (L) to BURST(H)
MCLK = 12 MHz
1.9 (0.8)
µs
DMAR (L) to DMAG (L)
8/ 15/
MCLK = 6 MHz
See figure 3
0
3.5 (1.9)
BURST DMA timing
ADDRESS valid to
tSHL1
9, 10, 11
All
THMC2
-10
THMC2
+5
ns
See figure 3
RRD (L)
(Address setup)
DMA read timing
THMC2
-10
THMC2
+10
M,D,P,L,R,F,G,H
See figure 3
TPW1
tHLZ2
9, 10, 11
9, 10, 11
All
All
MCLK
-10
MCLK
+5
ns
ns
RRD (L) to RRD (H)
DMA read timing
THMC1
-10
THMC1
+10
RRD (H) to ADDRESS
high impedance
(ADDRESS hold)
See footnotes at end of table.
SIZE
STANDARD
5962-89577
MICROCIRCUIT DRAWING
A
REVISION LEVEL
E
SHEET
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
7
DSCC FORM 2234
APR 97
TABLE IA. Electrical performance characteristics. - Continued
Test
Symbol
Conditions
4.5 V ≤ VDD ≤ 5.5 V
Group A
subgroups
Device
type
Limits
Unit
-55°C ≤ TC ≤+125°C 1/
unless otherwise specified
Min
Max
tHLZ1
See figure 3
9, 10, 11
9, 10, 11
All
All
5
ns
ns
RRD (H) to DATA high
impedance (DATA hold)
DMA read timing
tSLH1
40
DATA valid to RRD (H)
(DATA setup)
MCLK(H) to MCLKD2(H)
tPLH1
tPLH2
9, 10, 11
9, 10, 11
All
All
0
0
40
ns
ns
MCLK(H) to
40
TSCTL / MEMCSO (L)
TIOHL1
tSHL1
9, 10, 11
9, 10, 11
All
All
0
60
ns
MCLK(H) to RRD (L)
See figure 3
THMC2 THMC2 ns
-10 +5
THMC2 THMC2
ADDRESS valid to RWR (L)
(ADDRESS setup)
DMA write timing
M,D,P,L,R,F,G,H
-10
0
+10
30
tOOZL1
See figure 3
9, 10, 11
All
ns
RWR (L) to DATA valid 13/
DMA write timing
M,D,P,L,R,F,G,H
-5
30
tHLZ1
tHLZ2
tPW1
9, 10, 11
9, 10, 11
9, 10, 11
All
All
All
THMC1 THMC1 ns
-10 +10
RWR (H) to DATA high
impedance DATA hold)
See figure 3
DMA write timing
THMC1 THMC1 ns
RWR (H) to ADDRESS high
impedance
-10
+10
(ADDRESS hold)
MCLK
-10
0
MCLK
+5
ns
RWR (L) to RWR (H)
MCLK(H) to MCLKD2(H)
tPLH1
tPLH2
9, 10, 11
9, 10, 11
All
All
40
ns
ns
MCLK(H) to
0
40
60
TSCTL / MEMCSO (L)
tIOHL1
9, 10, 11
All
0
ns
MCLK(H) to RWR (L)
See footnotes at end of table.
SIZE
STANDARD
5962-89577
MICROCIRCUIT DRAWING
A
REVISION LEVEL
E
SHEET
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
8
DSCC FORM 2234
APR 97
TABLE IA. Electrical performance characteristics. - Continued
Test
Symbol
Conditions
4.5 V ≤ VDD ≤ 5.5 V
Group A
subgroups
Device
type
Limits
Unit
-55°C ≤ TC ≤+125°C 1/
unless otherwise specified
Min
Max
ADDRESS valid to DATA
Valid 9/
See figure 3
9, 10, 11
9, 10, 11
All
All
80
ns
TOOZH2
Register read timing
tHLH2
5
50
ns
RD + CS (H) to DATA high
impedance (DATA
hold)
tOOZH1
9, 10, 11
9, 10, 11
All
All
60
ns
ns
RD + CS (L) to DATA valid
(DATA access) 9/
tHLH1
5
RD + CS (H) to ADDRESS
high impedance
(ADDRESS hold)
tPW1
tPW2
tSHL1
tSHL2
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
All
All
All
All
60
80
60
5
ns
ns
ns
ns
RD + CS (L) to
RD + CS (H)
RD + CS (H) to
RD + CS (L)
15/
ADDRESS valid to
See figure 3
Register write timing
WR + CS (L)
(ADDRESS setup)
DATA valid to
WR + CS (L)
(DATA setup)
tPW1
9, 10, 11
9, 10, 11
All
All
60
10
ns
ns
WR + CS (L) to
WR + CS (H)
tHLH1
WR + CS (H) to DATA
high
impedance (DATA
hold)
tHLH2
9, 10, 11
9, 10, 11
All
All
10
80
ns
ns
WR + CS (H) to
ADDRESS
high impedance
(ADDRESS hold)
tPW2
WR + CS (H) to
WR + CS (L) 15/
See footnotes at end of table.
SIZE
STANDARD
5962-89577
MICROCIRCUIT DRAWING
A
REVISION LEVEL
E
SHEET
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
9
DSCC FORM 2234
APR 97
TABLE IA. Electrical performance characteristics. - Continued
Test
Symbol
Conditions
4.5 V ≤ VDD ≤ 5.5 V
-55°C ≤ TC ≤+125°C 1/
unless otherwise specified
Group A
subgroups
Devic
e
type
Limits
Unit
ns
Min
Max
30
tPHL1
tPHL2
tPHL3
See figure 3
9, 10, 11
All
0
RD (L) to RRD (L)
WR (L) to RWR (L)
Dual port interface timing
9, 10, 11
9, 10, 11
All
All
0
0
30
30
ns
ns
MEMCSI (L) to
MEMCSO (L)
tOOLH1
See figure 3
9, 10, 11
9, 10, 11
All
All
9
0
µs
µs
MEMWIN(H) to DMA
activity 10/
Memory window (RT) mode
tPW1
10/
MEMWIN(L) to
MEMWIN(H) 10/
Data word to DMA
Activity 15/
tPZL1
tPHL1
9, 10, 11
9, 10, 11
All
All
0
0
4
µs
30
ns
DMAG (L) to DMAGO (L)
12/
See figure 3
Arbitration when DMAG is
asserted before arbitration
tSHL1
9, 10, 11
All
0
10
ns
DMACK (L) to DMAR
high impedance
M,D,P,L,R,F,G,H
-5
0
5
MCLK(H) to MCLKD2(H)
tPLH2
9, 10, 11
9, 10, 11
All
All
40
ns
tOOLH2
9
µs
MEMWIN(H) to
DMAR (L) 10/
See figure 3
Interrupt log list entry
operation timing
tOOLH1
9, 10, 11
9, 10, 11
9, 10, 11
All
All
All
1
µs
ns
ns
TSCTL (H) to
STDINTP / STDINTL (L)
tPW1
320
340
STDINTP (L) to
STDINTP (H)
tOOHL1
3xMCLK
-10
5xMCLK
DMACK (L) to RWR (L)
tOOHL2
9, 10, 11
All
8xMCLK
10x
ns
DMAG (L) to
STDINTL (L)
MCLK
+40
See footnotes on next page.
SIZE
STANDARD
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REVISION LEVEL
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TABLE IA. Electrical performance characteristics. - Continued
1/ Devices supplied to this drawing are characterized at all levels M, D, P, L, R, F, G, and H of irradiation. However, this
device is only tested at the 'H' level. Pre and Post irradiation values are identical unless otherwise specified in Table IA. When
performing post irradiation electrical measurements for any RHA level, TA = +25°C.
2/ Radiation hardened technology shall have a VIH pre-irradiation limit of 2.2 V.
3/ Guaranteed to the limit specified in table IA. Tested only at initial qualification, and after any design or process changes
which may affect this characteristic.
4/ Not more than one output may be shorted at a time for a maximum duration of one second.
5/ All inputs with internal pull-ups should be left floating. All other inputs should be tied high or low.
6/ Includes current through input pull-up. Instantaneous surge currents on the order of 1 ampere can occur during output
switching. Voltage supply should be adequately sized and decoupled to handle a large current surge.
7/ DMAG must be asserted at least 45 ns prior to the rising edge of MCLKD2 in order to be recognized for the next MCLKD2
cycle. If DMAG is not asserted at least 45 ns prior to the rising edge of MCLKD2, DMAG is not recognized until the
following MCLKD2 cycle.
8/ Number in parentheses indicates the longest DMAR (L) to DMAG(L) allowed during worst-case bus switching conditions in
order to meet MIL-STD-1553B RT response time. The number not in parentheses applies to all other circumstances.
9/ User must adhere to both TOOZH1 and TOOZH2 timing constraints to ensure valid data.
10/ MEMWIN is an internal test pin only and should be considered a floating pin and not for use.
11/ The pulse width = (11 µs - tDMA - tPZL1) where tDMA is the time to complete DMA activity.
12/ When
is asserted before DMAR , the DMAG signal passes through device 01 as
DMAGO .
DMAG
13/ Timing is not valid for RT timer field of message status word. The timer value may update during a DMA memory write.
14/ Guaranteed to pre-and post-irradiation limits.
15/ Guaranteed by functional test.
TABLE IB. SEP test limits . 1/ 2/ 3/
Device
type
TA =
Temperature
±10°C 4/
Memory
pattern
V
CC = 4.5 V
Bias for latch-
up test VCC
=5.5 V no
latch-up
TA = +25°C
LET 4/
Effective
LET no
upsets
Maximum
device
TA = +125°C
cross section
cm2 /bit
(LET = 128)
≤ 8.5 x 10-7
≤ 80
All
5/
+25°C
≥ 27
NOTE: Devices that contain cross coupled resistance must be tested at the maximum rated TA
1/ For SEP test conditions, see 4.4.4.4 herein.
2/ Technology characterization and model verification supplemented by in-line data may be used in lieu of end-of-line
testing. Test plan must be approved by TRB and qualifying activity.
3/ Values will be added when they become available. Rad hard devices have not yet been tested for SEP.
4/ Worst case temperature TA = +125°C.
5/ For memories only.
SIZE
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Device
type
01
Case
X
Y, Z
Description
outlines
Terminal
symbol
VSS
Terminal
Numbers
F3
F1
G1
G2
G3
H1
H2
J1
1
2
Ground
D7
D6
D5
D4
D3
D2
D1
D0
Bit 7 of the data bus, TTB
Bit 6 of the data bus, TTB
Bit 5 of the data bus, TTB
Bit 4 of the data bus, TTB
Bit 3 of the data bus, TTB
Bit 2 of the data bus, TTB
Bit 1 of the data bus, TTB
Bit 0, LSB of the data bus, TTB
Master Reset, Active low, TTL input
3
4
5
6
7
8
K1
J2
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
MRST
BCRTSEL
LOCK
TAZ
L1
K2
K3
L2
L3
K4
L4
K6
K5
L5
J5
BC/RT Select, TUI
Lock, Active high, TUI
Transmit (Channel) A Z, TO
Transmit (Channel) A O, TO
Receive (Channel) A Z, TI
Receive (Channel) A O, TI
Transmit (Channel) B Z, TO
Transmit (Channel) B O, TO
Receive (Channel) B Z, TI
Receive (Channel) B O, TI
Clock, TI
TAO
RAZ
RAO
TBZ
TBO
RBZ
RBO
CLK
J6
VSS
Ground
L6
VDD
+5.0 V
FIGURE 1. Terminal connections.
SIZE
STANDARD
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REVISION LEVEL
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Device
Type
01
Case
X
Y, Z
Description
Outlines
Terminal
Symbol
Terminal
Numbers
L7
K7
24
25
External Override, Active low, TUI
(RT) Timer On, Active low, TO
EXTOVR
TIMERON
Channel A/B , TO
J7
L8
K8
L9
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
CHA/
B
(RT) Command Strobe, Active low, TO
Remote Terminal Address Bit 0, LSB, TUI
Remote Terminal Address Bit 1, TUI
Remote Terminal Address Bit 2, TUI
Remote Terminal Address Bit 3, TUI
Remote Terminal Address Bit 4, TUI
Remote Terminal Address, Parity, TUI
Bit 0 (LSB) of the address bus, TTB
Bit 1 of the address bus, TTB
Bit 2 of the address bus, TTB
Bit 3 of the address bus, TTB
Bit 4 of the address bus, TTB
Bit 5 of the address bus, TTB
Bit 6 of the address bus, TTB
Bit 7 of the address bus, TTB
Ground
COMSTR
RTAO
RTA1
RTA2
RTA3
RTA4
RTPTY
A0
L10
K9
L11
K10
J10
K11
J11
H10
H11
G9
A1
A2
A3
A4
A5
G10
G11
F10
F9
A6
A7
VSS
+5.0 V
VDD
Bit 8 of the address bus, TTO
E9
A8
FIGURE 1. Terminal connections. - Continued
SIZE
STANDARD
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REVISION LEVEL
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Device
Type
01
Case
X
Y, Z
Description
outlines
Terminal
Symbol
A9
Terminal
Number
E11
E10
F11
D11
D10
C11
B11
C10
A11
B10
B9
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
Bit 9 of the address bus, TTO
Bit 10 of the address bus, TTO
Bit 11 of the address bus, TTO
Bit 12 of the address bus, TTO
Bit 13 of the address bus, TTO
Bit 14 of the address bus, TTO
Bit 15 of the address bus, TTO
RAM Write, Active low, TO
A10
A11
A12
A13
A14
A15
RWR
RAM Read (Active low)
RRD
Memory Chip Select Out, Active low, TO
Three-State Control, Active low, TO
MEMCSO
TSCTL
DMAR
DMAG
DMACK
MEMCSI
WR
A10
A9
DMA Request, Active low, inactive state is high impedance,
TTO
DMA Grant, Active low, TI
B8
DMA Acknowledge, Active low, inactive state is high
impedance, TTO
Memory Chip Select In, Active low, TI
A8
C7
Write, Active low, TI
Read, Active low, TI
Chip Select, Active low, TI
Ground
B7
RD
A7
CS
B6
VSS
C6
+5.0 V
VDD
C5
Memory Clock, TI
Address Enable, Active high, TI
MCLK
AEN
A5
FIGURE 1. Terminal connections. - Continued
SIZE
STANDARD
5962-89577
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Device
Type
01
Case
X
Y, Z
Outlines
Terminal
symbol
Terminal
Numbers
Description
B5
A6
A4
B4
A3
A2
B3
A1
B2
C2
B1
C1
D2
D1
F2
E2
E1
E3
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
DMA grant out, low, TO
DMAGO
STDINTL
STDINTP
Standard interrupt level, active low, inactive state is high
impedance, TTO
Standard interrupt pulse, active low, TO
High-priority interrupt active low, inactive state is high impedance,
TTO
Memory clock divided by two, TO
HPINT
MCLKD2
SSYSF
Subsystem fail, active high, TI
Memory access window, active low, TO
BURST, DMA cycle, multiple word DMA access, active high, TO
BCRT fail, active high, TO
MEMWIN
BURST
BCRTF
D15
Bit 15 MSB of the data bus, TTB
Bit 14 of the data bus, TTB
Bit 13 of the data bus, TTB
Bit 12 of the data bus, TTB
Bit 11 of the data bus, TTB
Bit 10 of the data bus, TTB
Bit 9 of the data bus, TTB
D14
D13
D12
D11
D10
D9
Bit 8 of the data bus, TTB
D8
+5.0 V
VDD
NOTES: Address and data busses are in the high-impedance state when idle.
TI = TTL input
TO = TTL output
TTB = bidirectional
TTO = three state TTL output
TUI = TTL input (pull-up)
MEMWIN is an internal test pin only and should be considered a floating pin
and not for use.
FIGURE 1. Terminal connections. - Continued
SIZE
STANDARD
5962-89577
MICROCIRCUIT DRAWING
A
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C
SHEET
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FIGURE 2. Functional block diagram.
SIZE
STANDARD
5962-89577
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A
REVISION LEVEL
C
SHEET
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FIGURE 3. Switching test circuit and waveforms.
SIZE
STANDARD
5962-89577
MICROCIRCUIT DRAWING
A
REVISION LEVEL
C
SHEET
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FIGURE 3. Switching test circuit and waveforms. - Continued
SIZE
STANDARD
5962-89577
MICROCIRCUIT DRAWING
A
REVISION LEVEL
C
SHEET
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FIGURE 3. Switching test circuit and waveforms. - Continued
SIZE
STANDARD
5962-89577
MICROCIRCUIT DRAWING
A
REVISION LEVEL
C
SHEET
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FIGURE 3. Switching test circuit and waveforms. - Continued
SIZE
STANDARD
5962-89577
MICROCIRCUIT DRAWING
A
REVISION LEVEL
C
SHEET
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FIGURE 3. Switching test circuit and waveforms. - Continued
SIZE
STANDARD
5962-89577
MICROCIRCUIT DRAWING
A
REVISION LEVEL
E
SHEET
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COLUMBUS, OHIO 43216-5000
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FIGURE 3. Switching test circuit and waveforms. - Continued
SIZE
STANDARD
5962-89577
MICROCIRCUIT DRAWING
A
REVISION LEVEL
E
SHEET
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FIGURE 3. Switching test circuit and waveforms. - Continued
SIZE
STANDARD
5962-89577
MICROCIRCUIT DRAWING
A
REVISION LEVEL
C
SHEET
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COLUMBUS, OHIO 43216-5000
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FIGURE 3. Switching test circuit and waveforms. - Continued
SIZE
STANDARD
5962-89577
MICROCIRCUIT DRAWING
A
REVISION LEVEL
C
SHEET
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
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FIGURE 3. Switching test circuit and waveforms. - Continued
SIZE
STANDARD
5962-89577
MICROCIRCUIT DRAWING
A
REVISION LEVEL
E
SHEET
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Open
Ground
VDD = 5 V ±0.5 V
13 (K3), 14 (L2), 17 (L4), 18 (K6),
25 (K7), 26 (J7), 27 (L8), 38 (H11),
39 (G9), 40 (G10), 41 (G11), 44 (E9),
45 (E11), 46 (E10), 47 (F11), 48 (D11),
49 (D10), 50 (C11), 51 (B11), 52 (C10),
53 (A11), 54 (B10), 55 (B9), 56 (A10),
58 (B8), 67 (B5), 68 (A6), 69 (A4),
70 (B4), 71 (A3), 73 (B3), 74 ( A1),
75 (B2), 76 (C2), 77 (B1), 78 (C1),
79 (D2), 80 (D1), 81 (F2), 82 (E2),
83 (E1)
10 (J2), 11 (L1), 12 (K2), 23 (L6),
24 (L7), 28 (K8), 43 (F9), 57 (A9),
59 (A8), 61 (B7), 64 (C6), 84 (E3)
1 (F3), 2 (F1), 3 (G1), 4 (G2)
5 (G3), 6 (H1), 7 (H2), 8 (J1),
9 (K1), 15 (L3), 16 (K4), 19 (K5), 20
(L5), 21 (J5), 22 (J6), 29 (L9), 30
(L10), 31 (K9), 32 (L11),
33 (K10), 34 (J10), 35 (K11),
36 (J11), 37 (H10), 42 (F10),
60 (C7), 62 (A7), 63 (B6), 65 (C5),
66 (A5), 72 (A2)
Pin grid array pin identification is in parenthesis. Flat pack pin numbers is not in parenthesis.
FIGURE 4. Radiation exposure circuit.
SIZE
STANDARD
5962-89577
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4. QUALITY ASSURANCE PROVISIONS
4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with
MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan
shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be
in accordance with MIL-PRF-38535, appendix A.
4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted
on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in
accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection.
4.2.1 Additional criteria for device class M.
a. Burn-in test, method 1015 of MIL-STD-883.
(1) Test condition A or D. The test circuit shall be maintained by the manufacturer under document revision level
control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
test method 1015.
(2) TA = +125°C, minimum.
b. Interim and final electrical test parameters shall be as specified in table IIA herein.
4.2.2 Additional criteria for device classes Q and V.
a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the
device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under
document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with MIL-
PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test
method 1015 of MIL-STD-883.
b. Interim and final electrical test parameters shall be as specified in table IIA herein.
c. Additional screening for device class V beyond the requirements of device class Q shall be as specified in MIL-PRF-
38535, appendix B.
4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in
accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for
groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with MIL-
PRF-38535 including groups A, B, C, D, and E inspections and as specified herein. Quality conformance inspection for device
class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed for
device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections
(see 4.4.1 through 4.4.4).
SIZE
STANDARD
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4.4.1 Group A inspection.
a. Tests shall be as specified in table IIA herein.
b. Subgroups 5 and 6 in table I, method 5005 of table IV method 5010 of MIL-STD-883 shall be omitted.
c.
Subgroup 4 (CIN, COUT and CIO) shall be measured only for the initial test and after process or design changes
which may affect input/output capacitance. A minimum sample size of 10 devices with zero rejects shall be required.
d. For device class M, subgroups 7 and 8 tests shall be sufficient to verify the functionality of the device. For device
classes Q and V, subgroups 7 and 8 shall include verifying the functionality of the device; these tests shall have been
fault graded in accordance with MIL-STD-883, test method 5012 (see 1.5 herein).
TABLE IIA. Electrical test requirements.
Test requirements
Subgroups
(in accordance with
MIL-STD-883,
Subgroups
(in accordance with
MIL-PRF-38535, table III)
method 5005, table I)
Device
class M
Device
class Q
Device
class V
- - - -
- - - -
- - - -
Interim electrical
parameters (see 4.2)
Final electrical
parameters (see 4.2)
1/ 1, 2, 3, 7, 8, 9,
10, 11
1/ 1, 2, 3, 7, 8,
9, 10, 11
2/ 3/ 1, 2, 3, 7,
8, 9, 10, 11
Group A test
requirements (see 4.4)
1, 2, 3, 4, 7, 8, 9,
10, 11
1, 2, 3, 4, 7, 8,
9, 10, 11
1, 2, 3, 4, 7,
8, 9, 10, 11
Group C end-point electrical
parameters (see 4.4)
1, 2, 7, 8A
1, 2, 7, 8A
1, 2, 7, 8A
3/
Group D end-point electrical
parameters (see 4.4)
1, 2, 7 ,8A
1, 7, 9
1, 2, 7, 8A
1, 7, 9
1, 2, 7, 8A
Group E end-point electrical
parameters (see 4.4)
1, 7, 9
1/ PDA applies to subgroup 1.
2/ PDA applies to subgroups 1 and 7.
3/ Delta limits as specified in Table IIB herein shall be required when specified and the Delta values
shall be completed with reference to the zero hour electrical parameter.
Table IIB. Delta limits
Parameter
QIDD
Condition
TA = 25°C
Limits
±10% of measured value or
35 µA whichever is greater
NOTE: If device is tested at or below 35 µA no deltas are required. Deltas are performed at room temperature.
SIZE
STANDARD
5962-89577
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4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883:
a. Test condition A or D. The test circuit shall be maintained by the manufacturer under document revision level control
and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs,
outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005 of
MIL-STD-883.
b.TA = +125°C, minimum.
c. Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.
4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature,
or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The
test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with MIL-
PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005 of
MIL-STD-883.
4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness
assured (see 3.5 herein). RHA levels for device classes M, Q, and V shall be as specified in MIL-PRF-38535. End-point
electrical parameters shall be as specified in table IIA herein.
4.4.4.1 Total dose irradiation testing. Total dose irradiation testing shall be performed in accordance with MIL-STD-883
method 1019 and as specified herein.
4.4.4.1.1 Accelarated aging test. Accelaerated aging tests shall be performed on all devices requiring a RHA level greater
than 5k rads (Si). The post-anneal end-point electrical parameter limits shall be as specified in table IA herein and shall be the
pre-irradiation end-point electrical parameter limit at 25°C ±5°C. Testing shall be performed at initial qualification and after
any design or process changes which may affect the RHA response of the device.
4.4.4.2 Dose rate induced latchup testing. Dose rate induced latchup testing shall be performed in accoradance with test
method 1020 of MIL-STD-883 and as specified herein (see 1.4). Tests shall be performed on devices, SEC, or approved test
structures at technology qualification and after any design or process changes which may effect the RHA capability of the
process.
4.4.4.3 Dose rate upset testing. Dose rate upset testing shall be performed in accoradance with test method 1021 of
MIL-STD-883 and herein (see 1.4).
a. Transient dose rate upset testing shall be performed at initial qualification and after any design or process changes
which may effect the RHA performance of the devices. Test 10 devices with 0 defects unless otherwise specified.
b. Transient dose rate upset testing for class Q and V devices shall be performed as specified by a TRB approved
radiation hardness assurance plan and MIL-PRF-38535.
SIZE
STANDARD
5962-89577
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4.4.4.4 Single event phenomena (SEP). SEP testing shall be required on class V devices (See 1.4). SEP testing shall be
performed on the Standard Evaluation Circuit (SEC) or alternate SEP test vehice as approved by the qualifying activity at
initial qualification and after any design or process changes which may affect the upse or latchup characteristics. The
recommended test conditions for SEP are as follows:
a. The ion beam angle of incidence shall be between normal to the die surface and 60° to the normal, inclusive (i.e. 0° ≤
angle ≤ 60°). No shadowing of the ion beam due to fixturing or package related effects is allowed.
b. The fluence shall be ≥ 100 errors or ≥ 106 ions/cm2.
c. The flux shall be between 102 and 105 ions/cm2/s. The cross-section shall be verified to be flux independent by
measuring the cross-section at two flux rates which differ by at least an order of magnitude.
d. The particle range shall be ≥ 20 microns in silicon.
e. The upset test temperature shall be +25°C and the maximum rated operating temperature ±10°C.
f. Bias conditions shall be defined by the manufacturer for latchup measurements.
g. Test four devices with zero failures.
h. For SEP test limits, see Table IB herein.
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device
classes Q and V or MIL-PRF-38535, appendix A for device class M.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a
contractor-prepared specification or drawing.
6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus when a system
application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users
and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering
microelectronic devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544.
6.4 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43216-5000, or telephone
(614) 692-0547.
6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in MIL-
PRF-38535 and MIL-HDBK-1331.
SIZE
STANDARD
5962-89577
MICROCIRCUIT DRAWING
A
REVISION LEVEL
F
SHEET
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COLUMBUS, OHIO 43216-5000
30
DSCC FORM 2234
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6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535.
The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and have agreed to
this drawing.
6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103.
The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been
submitted to and accepted by DSCC-VA.
6.7 Additional information. A copy of the following additional data shall be maintained and available from the device
manufacturer:
a. RHA upset levels.
b. Test conditions (SEP).
c. Number of upsets (SEP).
d. Number of transients (SEP).
e. Occurrence of latchup (SEP).
SIZE
STANDARD
5962-89577
MICROCIRCUIT DRAWING
A
REVISION LEVEL
C
SHEET
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
31
DSCC FORM 2234
APR 97
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-89577
A.1 SCOPE
A.1.1 Scope. This appendix establishes minimum requirements for microcircuit die to be supplied under the Qualified
Manufacturers List (QML) Program. QML microcircuit die meeting the requirements of MIL-PRF-38535 and the manufacturers
approved QM plan for use in monolithic microcircuits, multichip modules (MCMs), hybrids, electronic modules, or devices
using chip and wire designs in accordance with MIL-PRF-38534 are specified herein. Two product assurance classes
consisting of military high reliability (device class Q) and space application (device Class V) are reflected in the Part or
Identification Number (PIN). When available a choice of Radiation Hardiness Assurance (RHA) levels are reflected in the PIN.
A.1.2 PIN. The PIN shall be as shown in the following example:
5962
-
89577
01
Q
9
X
Federal
Stock class
designator
RHA
designator
(see A.2.1)
Device
type
(see A.2.2)
Device
class
designator
(see A.2.3)
Die
code
Die
Details
(see A.2.4)
Drawing Number
A.1.2.1 RHA designator. Device classes Q and V RHA identified die shall meet the MIL-PRF-38535 specified RHA levels.
A dash (-) indicates a non-RHA die.
A.1.2.2 Device type(s). The device type(s) shall identify the circuit function as follows:
Device type
01
Generic number
UT1553BCRTM
Circuit function
Bus controller, remote terminal and monitor
A.1.2.3 Device class designator.
Device class
Q or V
Device requirements documentation
Certification and qualification to the die requirements of MIL-PRF-38535.
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-89577
A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
G
SHEET
32
DSCC FORM 2234
APR 97
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-89577
A.1.2.4 Die Details. The die details designation shall be a unique letter which designates the die’s physical dimensions,
bonding pad location(s) and related electrical function(s), interface materials, and other assembly related information, for each
product and variant supplied to this appendix.
A.1.2.4.1 Die Physical dimensions.
Die Types
01
Die detail designator
Figure number
A
B
A-1
B-1
A.1.2.4.2 Die Bonding pad locations and Electrical functions.
Die Types
Die detail designator
Figure number
01
A
B
A-1
B-1
A.1.2.4.3 Interface Materials.
Die Types
01
Die detail designator
Figure number
A
B
A-1
B-1
A.1.2.4.4 Assembly related information.
Die Types
01
Die detail designator
Figure number
Substrate potential
A
B
A-1
B-1
Tied to VDD
Tied to VSS
A.1.3 Absolute maximum ratings. See paragraph 1.3 within the body of this drawing for details.
A.1.4 Recommended operating conditions. See paragraph 1.4 within the body of this drawing for details.
A.2 APPLICABLE DOCUMENTS
A.2.1 Government specifications, standards, bulletin, and handbooks. Unless otherwise specified, the following
specifications, standards, bulletin, and handbook of the issue listed in that issue of the Department of Defense Index of
Specifications and Standards specified in the solicitation, form a part of this drawing to the extent specified herein.
SPECIFICATION
DEPARTMENT OF DEFENSE
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
STANDARDS
DEPARTMENT OF DEFENSE
MIL-STD-883 - Test Method Standard Microcircuits.
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-89577
A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
G
SHEET
33
DSCC FORM 2234
APR 97
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-89577
HANDBOOK
DEPARTMENT OF DEFENSE
MIL-HDBK-103 - List of Standard Microcircuit Drawings.
(Copies of the specification, standards, bulletin, and handbook required by manufacturers in connection with specific
acquisition functions should be obtained from the contracting activity or as directed by the contracting activity).
A.2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the
text of this drawing shall take precedence.
A.3 REQUIREMENTS
A.3.1 Item Requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer’s Quality Management (QM) plan. The
modification in the QM plan shall not effect the form, fit or function as described herein.
A.3.2 Design, construction and physical dimensions. The design, construction and physical dimensions shall be as
specified in MIL-PRF-38535 and the manufacturer’s QM plan, for device classes Q and V and herein.
A.3.2.1 Die Physical dimensions. The die physical dimensions shall be as specified in A.1.2.4.1 and on figures A-1 and
B-1.
A.3.2.2 Die bonding pad locations and electrical functions. The die bonding pad locations and electrical functions shall be
as specified in A.1.2.4.2 and on figures A-1and B-1.
A.3.2.3 Interface materials. The interface materials for the die shall be as specified in A.1.2.4.3 and on figures A-1 and B-1.
A.3.2.4 Assembly related information. The assembly related information shall be as specified in A.1.2.4.4 and figures A-1
and B-1.
A.3.2.5 Radiation exposure circuit. The radiation exposure circuit shall be as defined within paragraph 3.2.5 of the body of
this document.
A.3.3 Electrical performance characteristics and post- irradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and post-irradiation parameter limits are as specified in table IA of the body of this
document.
A.3.4 Electrical test requirements. The wafer probe test requirements shall include functional and parametric testing
sufficient to make the packaged die capable of meeting the electrical performance requirements in table IA.
A.3.5 Marking. As a minimum, each unique lot of die, loaded in single or multiple stack of carriers, for shipment to a
customer, shall be identified with the wafer lot number, the certification mark, the manufacturer’s identification and the PIN
listed in 10.2 herein. The certification mark shall be a “QML” or “Q” as required by MIL-PRF-38535.
A.3.6 Certification of compliance. For device classes Q and V, a certificate of compliance shall be required from a
QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 60.4 herein). The certificate of
compliance submitted to DSCC-VA prior to listing as an approved source of supply for this appendix shall affirm that the
manufacturer’s product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and the requirements herein.
A.3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535
shall be provided with each lot of microcircuit die delivered to this drawing.
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-89577
A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
G
SHEET
34
DSCC FORM 2234
APR 97
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-89577
A.4 QUALITY ASSURANCE PROVISIONS
A.4.1 Sampling and inspection. For device classes Q and V, die sampling and inspection procedures shall be in
accordance with MIL-PRF-38535 or as modified in the device manufacturer’s Quality Management (QM) plan. The
modifications in the QM plan shall not effect the form, fit or function as described herein.
A.4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and as defined in the
manufacturer’s QM plan. As a minimum it shall consist of:
a) Wafer Lot acceptance for Class V product using the criteria defined within MIL-STD-883 TM 5007.
b) 100% wafer probe (see paragraph 30.4).
c) 100% internal visual inspection to the applicable class Q or V criteria defined within MIL-STD-883 TM2010
or the alternate procedures allowed within MIL-STD-883 TM5004.
A.4.3 Conformance inspection.
A.4.3.1 Group E inspection. Group E inspection is required only for parts intended to be identified as radiation assured
(see A.3.5 herein). RHA levels for device classes Q and V shall be as specified in MIL-PRF-38535. End point electrical
testing of packaged die shall be as specified in table IIA herein. Group E tests and conditions are as specified within
paragraphs 4.4.4.1, 4.4.4.1.1, 4.4.4.2, 4.4.4.3, and 4.4.4.4.
A.5 DIE CARRIER
A.5.1 Die carrier requirements. The requirements for the die carrier shall be in accordance with the manufacturer’s QM
plan or as specified in the purchase order by the acquiring activity. The die carrier shall provide adequate physical,
mechanical and electrostatic protection.
A.6 NOTES
A.6.1 Intended use. Microcircuit die conforming to this drawing are intended for use in microcircuits built in accordance with
MIL-PRF-38535 or MIL-PRF-38534 for government microcircuit applications (original equipment), design applications and
logistics purposes.
A.6.2 Comments. Comments on this appendix should be directed to DSCC-VA, Columbus, Ohio, 43216-5000 or telephone
(614)-692-0547.
A.6.3 Abbreviations, symbols and definitions. The abbreviations, symbols, and definitions used herein are defined with
MIL-PRF-38535 and MIL-HDBK-1331.
A.6.4 Sources of Supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-
38535. The vendors listed within QML-38535 have submitted a certificate of compliance (see 30.6 herein) to DSCC-VA and
have agreed to this drawing.
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-89577
A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
G
SHEET
35
DSCC FORM 2234
APR 97
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-89577
DIE BONDING PAD LOCATIONS AND ELECTRICAL FUNCTIONS
o DIE PHYSICAL DIMENSIONS
Die Size:
Die Thickness:
394 mils. x 394 mils.
17.5 +/- 1 mils.
o INTERFACE MATERIALS
Top Metallization:
Si Al Cu 9 kÅ-12.5kÅ
Backside Metallization
None: Backgrind
Glassivation
Type:
PSG
Thickness
10 KÅ +/- 2.kÅ
Substrate:
EPI on single crystal silicon
o ASSEMBLY RELATED INFORMATION
Substrate Potential:
Tied to VDD
None
Special assembly
instructions:
FIGURE A-1
DIE BONDING PAD LOCATIONS AND ELECTRICAL FUNCTIONS
o DIE PHYSICAL DIMENSIONS
Die Size:
Die Thickness:
394 mils. x 394 mils.
17.5 +/- 1 mils.
o INTERFACE MATERIALS
Top Metallization:
Si Al Cu 9 kÅ-12.5kÅ
None: Backgrind
Backside Metallization
Glassivation
Type:
PSG
Thickness
10 KÅ +/- 2.kÅ
Substrate:
EPI on single crystal silicon
o ASSEMBLY RELATED INFORMATION
Substrate Potential:
Tied to VSS
None
Special assembly
instructions:
FIGURE B-1
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-89577
A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
G
SHEET
36
DSCC FORM 2234
APR 97
Appendix A
APPENDIX A FORMS A PART OF SMD 5962-89577
Die bonding pad locations and electrical functions
PAD
1
2
3
4
5
6
7
8
XCENTER
-0.0035
-0.0099
-0.0163
-0.0226
-0.0290
-0.0354
-0.0418
-0.0482
-0.0545
-0.0609
-0.0673
-0.0737
-0.0800
-0.0864
-0.0928
-0.0992
-0.1056
-0.1119
-0.1183
-0.1247
-0.1311
-0.1374
-0.1438
-0.1502
-0.1566
-0.1630
-0.1743
-0.1904
-0.1904
-0.1904
-0.1904
-0.1904
-0.1904
-0.1904
-0.1904
-0.1904
-0.1904
-0.1904
-0.1904
-0.1904
-0.1904
-0.1904
-0.1904
-0.1904
-0.1904
-0.1904
-0.1904
-0.1904
-0.1904
-0.1904
YCENTER
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1676
0.1564
0.1500
0.1436
0.1372
0.1308
0.1245
0.1181
0.1117
0.1053
0.0990
0.0926
0.0862
0.0798
0.0734
0.0671
0.0607
0.0543
0.0479
0.0416
0.0352
0.0288
0.0224
PAD NAME
VSS
No connect
D7
No connect
No connect
D6
No connect
D5
No connect
D4
No connect
No connect
No connect
D3
No connect
D2
No connect
D1
No connect
No connect
No connect
D0
No connect
MRST
No connect
BCRTSEL
No connect
No connect
LOCK
No connect
TAZ
No connect
TA0
No connect
No connect
No connect
RAZ
No connect
RA0
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
No connect
TBZ
No connect
TB0
No connect
RBZ
No connect
No connect
RB0
No connect
MHX12
NOTE: The die center is the coordinate origin (0,0).
Figure A-1
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-89577
A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
SHEET
G
37
DSCC FORM 2234
APR 97
Appendix A
APPENDIX A FORMS A PART OF SMD 5962-89577
Die bonding pad locations and electrical functions
PAD
51
52
53
54
55
56
57
58
59
60
61
62
XCENTER
-0.1904
-0.1904
-0.1904
-0.1904
-0.1904
-0.1904
-0.1904
-0.1904
-0.1904
-0.1904
-0.1904
-0.1904
YCENTER
0.0160
0.0097
PAD NAME
No connect
No connect
VSS
0.0033
-0.0031
-0.0095
-0.0158
-0.0222
-0.0286
-0.0350
-0.0414
-0.0477
-0.0541
VDD
No connect
No connect
No connect
EXTOVR
No connect
No connect
TIMERON
No connect
63
64
65
66
-0.1904
-0.1904
-0.1904
-0.1904
-0.0605
-0.0669
-0.0732
-0.0796
CHA/B
No connect
No connect
No connect
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
-0.1904
-0.1904
-0.1904
-0.1904
-0.1904
-0.1904
-0.1904
-0.1904
-0.1904
-0.1904
-0.1904
-0.1904
-0.1905
-0.1904
-0.1743
-0.1629
-0.1566
-0.1502
-0.1438
-0.1374
-0.1311
-0.1247
-0.1183
-0.1119
-0.1056
-0.0992
-0.0928
-0.0864
-0.0800
-0.0860
-0.0924
-0.0988
-0.1051
-0.1115
-0.1179
-0.1243
-0.1307
-0.1370
-0.1434
-0.1498
-0.1562
-0.1625
-0.1743
-0.1905
-0.1905
-0.1905
-0.1905
-0.1905
-0.1905
-0.1905
-0.1905
-0.1905
-0.1905
-0.1905
-0.1905
-0.1905
-0.1905
-0.1905
COMSTR
No connect
RTA0
No connect
RTA1
No connect
RTA2
No connect
No connect
No connect
RTA3
No connect
RTA4
No connect
No connect
RTPTY
No connect
A0
No connect
No connect
No connect
A1
No connect
A2
No connect
A3
No connect
A4
No connect
NOTE: The die center is the coordinate origin (0,0).
Figure A-1
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-89577
A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
SHEET
G
38
DSCC FORM 2234
APR 97
Appendix A
APPENDIX A FORMS A PART OF SMD 5962-89577
Die bonding pad locations and electrical functions
PAD
96
97
98
99
XCENTER
-0.0737
-0.0673
-0.0609
-0.0545
-0.0482
-0.0418
-0.0354
-0.0290
-0.0226
-0.0163
-0.0099
-0.0035
0.0029
0.0093
0.0156
0.0220
0.0284
0.0348
0.0411
0.0475
0.0539
0.0603
0.0667
0.0730
0.0794
0.0858
0.0922
0.0985
0.1049
0.1113
0.1177
0.1241
0.1305
0.1369
YCENTER
-0.1905
-0.1905
-0.1905
-0.1905
-0.1905
-0.1905
-0.1905
-0.1905
-0.1905
-0.1905
-0.1905
-0.1905
-0.1905
-0.1905
-0.1905
-0.1905
-0.1905
-0.1905
-0.1905
-0.1905
-0.1905
-0.1905
-0.1905
-0.1905
-0.1905
-0.1905
-0.1905
-0.1905
-0.1905
-0.1905
-0.1905
-0.1905
-0.1905
-0.1904
PAD NAME
No connect
No connect
A5
No connect
A6
No connect
A7
No connect
BCRTMSEL
No connect
VSS
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
VDD
No connect
No connect
A8
No connect
A9
No connect
A10
No connect
A11
No connect
No connect
No connect
A12
No connect
A13
No connect
A14
No connect
No connect
No connect
A15
No connect
130
131
0.1433
0.1497
-0.1904
-0.1904
RWR
No connect
132
133
134
135
136
137
138
139
140
141
142
0.1560
0.1676
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
-0.1905
-0.1905
-0.1743
-0.1624
-0.1562
-0.1498
-0.1434
-0.1370
-0.1307
-0.1243
-0.1179
RRD
No connect
No connect
MEMSCO
No connect
TSCTL
No connect
No connect
No connect
DMAR
No connect
NOTE: The die center is the coordinate origin (0,0).
Figure A-1
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-89577
A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
SHEET
G
39
DSCC FORM 2234
APR 97
Appendix A
APPENDIX A FORMS A PART OF SMD 5962-89577
Die bonding pad locations and electrical functions
PAD
143
144
145
146
147
148
149
150
XCENTER
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
YCENTER
-0.1115
-0.1051
-0.0988
-0.0924
-0.0860
-0.0796
-0.0732
-0,0669
PAD NAME
DMAG
No connect
No connect
No connect
DMACK
No connect
MEMCSI
No connect
151
152
153
0.1840
0.1840
0.1840
-0.0605
-0.0541
-0.0477
WR
No connect
No connect
154
155
0.1840
0.1840
-0.0414
-0.0350
RD
No connect
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1676
-0.0286
-0.0222
-0.0158
-0.0095
-0.0031
0.0033
0.0097
0.0160
0.0224
0.0288
0.0352
0.0416
0.0479
0.0543
0.0607
0.0671
0.0734
0.0798
0.0862
0.0926
0.0990
0.1053
0.1117
0.1181
0.1245
0.1308
0.1372
0.1436
0.1500
0.1564
0.1676
0.1840
CS
No connect
No connect
VSS
VDD
No connect
No connect
No connect
MCLK
No connect
AEN
No connect
No connect
DMAGO
No connect
STDINTL
No connect
STDINTP
No connect
HPINT
No connect
No connect
No connect
MCLKD2
No connect
SSYSF
No connect
TEST
No connect
BURST
No connect
No connect
NOTE: The die center is the coordinate origin (0,0).
Figure A-1
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-89577
A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
SHEET
G
40
DSCC FORM 2234
APR 97
Appendix A
APPENDIX A FORMS A PART OF SMD 5962-89577
Die bonding pad locations and electrical functions
PAD
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
XCENTER
0.1559
0.1496
0.1432
0.1368
0.1304
0.1241
0.1177
0.1113
0.1049
0.0985
0.0922
0.0858
0.0794
0.0730
0.0667
0.0603
0.0539
0.0475
0.0411
0.0348
0.0284
0.0220
0.0156
0.0093
0.0029
YCENTER
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
0.1840
PAD NAME
BCRTF
No connect
D15
No connect
D14
No connect
No connect
No connect
D13
No connect
D12
No connect
D11
No connect
No connect
No connect
D10
No connect
D9
No connect
No connect
D8
No connect
No connect
VDD
NOTE: The die center is the coordinate origin (0,0).
Figure A-1
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-89577
A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
SHEET
G
41
DSCC FORM 2234
APR 97
Appendix A
APPENDIX A FORMS A PART OF SMD 5962-89577
Die bonding pad locations and electrical functions
PAD
1
2
3
4
5
6
7
8
XCENTER
165
YCENTER
185.9
185.9
185.9
185.9
185.9
185.9
185.9
185.9
185.9
185.9
185.9
185.9
185.9
185.9
185.9
185.9
185.9
185.9
185.9
185.9
185.9
185.9
185.9
185.9
185.9
185.9
185.9
185.9
185.9
185.9
185.9
185.9
185.9
185.9
185.9
185.9
185.9
185.9
185.9
185.9
185.9
185.9
185.9
185.9
185.9
185.9
185.9
185.9
185.9
185.9
PAD NAME
VSS
VDQ
No Connect
BF
158.7
152.4
146.1
139.8
133.5
127.2
120.9
114.6
108.3
102
95.7
89.4
83.1
76.8
70.5
64.2
57.9
51.6
45.3
39
32.7
26.4
20.1
13.8
7.5
1.2
No Connect
D15
D14
No Connect
No Connect
No Connect
D13
No Connect
D12
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
D11
VSQ
No Connect
No Connect
No Connect
D10
No Connect
D9
No Connect
D8
No Connect
VDQ
VSS
VDD
VSQ
-5.1
-11.4
-17.7
-24
No Connect
No Connect
No Connect
D7
No Connect
D6
No Connect
D5
No Connect
No Connect
VSQ
-30.3
-36.6
-42.9
-49.2
-55.5
-61.8
-68.1
-74.4
-80.7
-87
-93.3
-99.6
105.9
112.2
118.5
124.8
131.1
137.4
143.7
D4
No Connect
D3
No Connect
D2
No Connect
No Connect
D0
MRST
BCRTSEL
No Connect
NOTE: The die center is the coordinate origin (0,0).
Figure B-1
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-89577
A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
SHEET
G
42
DSCC FORM 2234
APR 97
Appendix A
APPENDIX A FORMS A PART OF SMD 5962-89577
Die bonding pad locations and electrical functions
PAD
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
XCENTER
150
YCENTER
185.9
185.9
185.9
185.9
170.2
163.9
157.4
151.1
144.8
138.5
132.2
125.9
119.6
113.3
107.1
100.8
94.5
88.2
81.9
75.6
69.3
63
56.7
50.4
44.1
37.8
31.5
25.2
18.9
12.6
6.3
0
-6.3
-12.6
-18.9
-25.2
-31.5
-37.8
-44.1
-50.4
-56.7
-63
-69.3
-75.6
-81.9
-88.2
-94.5
-100.8
-107.1
-113.4
PAD NAME
No Connect
No Connect
VSQ
156.3
162.6
168.9
184.6
184.6
184.6
184.6
184.6
184.6
184.6
184.6
184.6
184.6
184.6
184.6
184.6
184.6
184.6
184.6
184.6
184.6
184.6
184.6
184.6
184.6
184.6
184.6
184.6
184.6
184.6
184.6
184.6
184.6
184.6
184.6
184.6
184.6
184.6
184.6
184.6
184.6
184.6
184.6
184.6
184.6
184.6
184.6
184.6
184.6
VSS
VDD
VDQ
No Connect
No Connect
LOCK
No Connect
TAZ
TAO
No Connect
RAZ
No Connect
No Connect
RAO
No Connect
VSQ
TBZ
TBO
No Connect
No Connect
RBZ
RBO
No Connect
MHz12
No Connect
VDQ
VDD
VSS
VSQ
No Connect
No Connect
No Connect
No Connect
EXTOVR
No Connect
TIMERON
No Connect
CHAB
No Connect
VSQ
CMDST
VDD
No Connect
RTA0
RTA1
No Connect
No Connect
NOTE: The die center is the coordinate origin (0,0).
Figure B-1
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-89577
A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
SHEET
G
43
DSCC FORM 2234
APR 97
Appendix A
APPENDIX A FORMS A PART OF SMD 5962-89577
Die bonding pad locations and electrical functions
PAD
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
XCENTER
184.6
184.6
184.6
184.6
184.6
184.6
184.6
184.6
184.6
168.9
162.6
156.3
150
143.7
137.4
131.1
124.8
118.5
112.2
105.9
-99.6
-93.3
-87
-80.7
-74.4
-68.1
-61.8
-55.5
-49.2
-42.9
-36.6
-30.3
-24
-17.7
-11.4
-5.1
1.2
7.5
13.8
20.1
26.4
32.7
39
45.3
51.6
57.9
64.2
70.5
76.8
83.1
YCENTER
-119.7
-126
-132.3
-138.6
-144.9
-151.2
-157.5
-164
-170.3
-186
-186
-186
-186
-186
-186
-186
-186
-186
-186
-186
-186
-186
-186
-186
-186
-186
-186
-186
-186
-186
-186
-186
-186
-186
-186
-186
-186
-186
-186
-186
-186
-186
-186
-186
-186
-186
-186
-186
-186
-186
PAD NAME
RTA2
RTA3
RTA4
No Connect
No Connect
No Connect
No Connect
VSQ
VDD
VSS
VDQ
No Connect
RTPTY
No Connect
A0
No Connect
A1
No Connect
No Connect
No Connect
A2
No Connect
No Connect
VSQ
A4
No Connect
No Connect
A5
No Connect
No Connect
A6
A7
No Connect
VDQ
VSS
VDD
VSQ
No Connect
No Connect
No Connect
A8
No Connect
A9
No Connect
A10
No Connect
No Connect
VSQ
A11
No Connect
NOTE: The die center is the coordinate origin (0,0).
Figure B-1
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-89577
A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
SHEET
G
44
DSCC FORM 2234
APR 97
Appendix A
APPENDIX A FORMS A PART OF SMD 5962-89577
Die bonding pad locations and electrical functions
PAD
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
XCENTER
89.4
YCENTER
-186
PAD NAME
A12
No Connect
A13
A14
No Connect
A15
No Connect
RWR
No Connect
RRD
No Connect
VSQ
95.7
102
-186
-186
-186
-186
-186
-186
-186
-186
-186
-186
-186
-186
-170.3
-163.8
-157.5
-151.2
-144.9
-138.6
-132.3
-126
-119.7
-113.4
-107.1
-100.8
-94.5
-88.2
-81.9
-75.6
-69.3
-63
-56.7
-50.4
-44.1
-37.8
-31.5
-25.2
-18.9
-12.6
-6.3
108.3
114.6
120.9
127.2
133.5
139.8
146.1
152.4
158.7
165
VSS
VDD
VDQ
180.7
180.7
180.7
180.7
180.7
180.7
180.7
180.7
180.7
180.7
180.7
180.7
180.7
180.7
180.7
180.7
180.7
180.7
180.7
180.7
180.7
180.7
180.7
180.7
180.7
180.7
180.7
180.7
180.7
180.7
180.7
180.7
180.7
180.7
180.7
180.7
180.7
No Connect
MEMCSO
No Connect
TSCTL
No Connect
DMAR
No Connect
No Connect
DMAG
No Connect
DMAAK
MEMCSI
VSQ
No Connect
No Connect
No Connect
WR
No Connect
RD
No Connect
CS
No Connect
VDQ
VSS
VDD
VSQ
0
6.3
12.6
18.9
25.2
31.5
37.8
44.1
No Connect
No Connect
No Connect
MCLK
No Connect
AEN
No Connect
DMAGO
No Connect
50.4
56.7
NOTE: The die center is the coordinate origin (0,0).
Figure B-1
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-89577
A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
SHEET
G
45
DSCC FORM 2234
APR 97
Appendix A
APPENDIX A FORMS A PART OF SMD 5962-89577
Die bonding pad locations and electrical functions
PAD
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
XCENTER
180.7
180.7
180.7
180.7
180.7
180.7
180.7
180.7
180.7
180.7
180.7
180.7
180.7
180.7
180.7
180.7
180.7
180.7
YCENTER
63
PAD NAME
No Connect
VSQ
69.3
75.6
81.9
88.2
STDINT
STDPUL
No Connect
HPINT
MCKD2
No Connect
SSYSF
No Connect
TEST
No Connect
BURST
No Connect
No Connect
No Connect
VSQ
94.5
100.8
107.1
113.4
119.7
126
132.3
138.6
144.9
151.2
157.6
163.9
170.2
VDD
NOTE: The die center is the coordinate origin (0,0).
Figure B-1
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-89577
A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
SHEET
G
46
DSCC FORM 2234
APR 97
Appendix A
APPENDIX A FORMS A PART OF SMD 5962-89577
Figure A-1
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-89577
A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
G
SHEET
47
DSCC FORM 2234
APR 97
Appendix A
APPENDIX A FORMS A PART OF SMD 5962-89577
Figure B-1
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-89577
A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
G
SHEET
48
DSCC FORM 2234
APR 97
STANDARD MICROCIRCUIT DRAWING SOURCE APPROVAL BULLETIN
DATE: 02-07-23
Approved sources of supply for SMD 5962-89577 are listed below for immediate acquisition information only and
shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be
revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a
certificate of compliance has been submitted to and accepted by DSCC-VA. This bulletin is superseded by the next
dated revision of MIL-HDBK-103 and QML-38535.
Standard
Microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962-8957701XA
5962-8957701XC
5962-8957701YA
5962-8957701YC
5962-8957701ZA
5962-8957701ZC
5962H8957701XA
5962H8957701XC
5962H8957701YA
5962H8957701YC
5962H8957701ZA
5962H8957701ZC
5962H8957701VXA
5962H8957701VXC
5962H8957701VYA
5962H8957701VYC
5962H8957701VZA
5962H8957701VZC
65342
65342
65342
65342
65342
65342
65342
65342
65342
65342
65342
65342
65342
65342
65342
65342
65342
65342
UT1553BCRTMGA
UT1553BCRTMGC
UT1553BCRTMWA
UT1553BCRTMWC
UT1553BCRTMAA
UT1553BCRTMAC
UT1553BCRTMGAH
UT1553BCRTMGCH
UT1553BCRTMWAH
UT1553BCRTMWCH
UT1553BCRTMAAH
UT1553BCRTMACH
UT1553BCRTMVGAH
UT1553BCRTMVGCH
UT1553BCRTMVWAH
UT1553BCRTMVWCH
UT1553BCRTMVAAH
UT1553BCRTMVACH
1 of 2
STANDARD MICROCIRCUIT DRAWING SOURCE APPROVAL BULLETIN – Continued
Standard
Microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
Similar
PIN 2/
5962-8957701Q9A
5962-8957701V9A
5962H8957701Q9A
5962H8957701V9A
5962H8957701Q9B
5962H8957701V9B
65342
65342
3/
UT1553BCRTM-Q DIE
UT1553BCRTM-V DIE
3/
65342
65342
UT1553BCRTM-Q DIE
UT1553BCRTM-V DIE
1/ The lead finish shown for each PIN representing
a hermetic package is the most readily available
from the manufacturer listed for that part. If the
desired lead finish is not listed contact the
Vendor to determine its availability.
2/ Caution. Do not use this number for item
acquisition. Items acquired to this number may not
satisfy the performance requirements of this drawing.
3/ Not available from an approved source of supply.
Vendor CAGE
number
Vendor name
and address
65342
UTMC Aeroflex Microelectronics Systems Inc.
4350 Centennial Boulevard
Colorado Springs, Colorado 80907-3486
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.
2 of 2
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