5962-8957103KYC [ETC]
Hermetically Sealed. Very High Speed. Logic Gate Optocouplers ; 密封。非常高的速度。逻辑门光电耦合器\n
| 型号： | 5962-8957103KYC |
| 厂家： | 
ETC |
| 描述： | Hermetically Sealed. Very High Speed. Logic Gate Optocouplers
|
| 文件： | 总12页 (文件大小：269K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Hermetically Sealed,
Very High Speed,
Logic Gate Optocouplers
HCPL-643X
5962-89571
HCPL-540X*
5962-89570
HCPL-543X
Technical Data
*See matrix for available extensions.
Features
• Computer-Peripheral
Interfaces
• Switching Power Supplies
• Isolated Bus Driver
(Networking Applications)-
(5400/1/K Only)
• Pulse Transformer
Replacement
Each channel contains an AlGaAs
light emitting diode which is
optically coupled to an integrated
high gain photon detector. This
combination results in very high
• Dual Marked with Device
Part Number and DSCC
Standard Microcircuit
Drawing
• Manufactured and Tested on
a MIL-PRF-38534 Certified
Line
• QML-38534, Class H and K
• Three Hermetically Sealed
Package Configurations
Truth Tables
(Positive Logic)
Multichannel Devices
• Ground Loop Elimination
• Harsh Industrial
Environments
• High Speed Disk Drive I/O
• Digital Isolation for A/D,
D/A Conversion
Input
On (H)
Off (L)
Output
L
H
• Performance Guaranteed
over -55°C to +125°C
• High Speed: 40 M bit/s
• High Common Mode
Rejection 500 V/µs
Guaranteed
• 1500 Vdc Withstand Test
Voltage
• Active (Totem Pole) Outputs
• Three Stage Output Available
• High Radiation Immunity
• HCPL-2400/30 Function
Compatibility
Single Channel DIP
Input
On (H)
Off (L)
On (H)
Off (L)
Enable Output
Description
L
L
H
H
L
H
Z
These units are single and dual
channel, hermetically sealed
optocouplers. The products are
capable of operation and storage
over the full military temperature
range and can be purchased as
either standard product or with
full MIL-PRF-38534 Class Level
H or K testing or from the
appropriate DSCC Drawing. All
devices are manufactured and
tested on a MIL-PRF-38534
certified line and are included in
the DSCC Qualified Manufac-
turers List, QML-38534 for
Hybrid Microcircuits.
Z
Functional Diagram
Multiple Channel Devices
Available
• Reliability Data
• Compatible with TTL, STTL,
LSTTL, and HCMOS Logic
Families
V
CC
Applications
• Military and Space
• High Reliability Systems
• Transportation, Medical, and
Life Critical Systems
V
E
V
O
GND
• Isolation of High Speed
Logic Systems
The connection of a 0.1 µF bypass capacitor between V and GND is recommended.
CC
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to
prevent damage and/or degradation which may be induced by ESD.
2
data rate capability. The detector
has a threshold with hysteresis,
which typically provides 0.25 mA
of differential mode noise
immunity and minimizes the
potential for output signal
chatter. The detector in the single
channel units has a three state
output stage which eliminates the
need for a pull-up resistor and
allows for direct drive of a data
bus.
distortion. Figures 13 through 16
show recommended circuits for
reducing pulse width distortion
and optimizing the signal rate of
the product. Package styles for
these parts are 8 pin DIP through
hole (case outlines P), and
leadless ceramic chip carrier
(case outline 2). Devices may be
purchased with a variety of lead
bend and plating options. See
Selection Guide Table for details.
Standard Microcircuit Drawing
(SMD) parts are available for
each package and lead style.
listed in this data sheet, absolute
maximum ratings, recommended
operating conditions, electrical
specifications, and performance
characteristics shown in the
figures are similar for all parts.
Occasional exceptions exist due
to package variations and limita-
tions and are as noted. Addition-
ally, the same package assembly
processes and materials are used
in all devices. These similarities
give justification for the use of
data obtained from one part to
represent other part’s perform-
ance for die related reliability and
certain limited radiation test
results.
All units are compatible with TTL,
STTL, LSTTL, and HCMOS logic
families. The 35 ns pulse width
distortion specification guaran-
tees a 10 MBd signaling rate at
+125°C with 35% pulse width
Because the same electrical die
(emitters and detectors) are used
for each channel of each device
Selection Guide–Package Styles and Lead Configuration Options
Package
Lead Style
Channels
8 Pin DIP
Through Hole
1
8 Pin DIP
Through Hole
2
20 Pad LCCC
Surface Mount
2
Common Channel
Wiring
None
VCC, GND
None
Agilent Part # & Options
Commercial
MIL-PRF-38534, Class H
MIL-PRF-38534, Class K
Standard Lead Finish
Solder Dipped
Butt Cut/Gold Plate
Gull Wing/Soldered
Class H SMD Part #
Prescript for all below
Either Gold or Solder
Gold Plate
HCPL-5400
HCPL-5401
HCPL-540K
Gold Plate
Option #200
Option #100
Option #300
HCPL-5430
HCPL-5431
HCPL-543K
Gold Plate
Option #200
Option #100
Option #300
HCPL-6430
HCPL-6431
HCPL-643K
Solder Pads
5962-
5962-
5962-
89571022X
8957001PX
8957001PC
8957001PA
8957001YC
8957001YA
8957001XA
8957101PX
8957101PC
8957101PA
8957101YC
8957101YA
8957101XA
Solder Dipped
89571022A
Butt Cut/Gold Plate
Butt Cut/Soldered
Gull Wing/Soldered
Class K SMD Part #
Prescript for all below
Either Gold of Solder
Gold Plate
5962-
5962-
5962-
8957104K2X
8957002KPX
8957002KPC
8957002KPA
8957002KYC
8957002KYA
8957002KXA
8957103KPX
8957103KPC
8957103KPA
8957103KYC
8957103KYA
8957103KXA
Solder Dipped
8957104K2A
Butt Cut/Gold Plate
Butt Cut/Soldered
Gull Wing/Soldered
3
Functional Diagrams
8 Pin DIP
Through Hole
1 Channel
8 Pin DIP
Through Hole
2 Channels
20 Pad LCCC
Surface Mount
2 Channels
15
V
CC2
V
8
7
6
5
V
8
7
6
5
1
2
3
4
1
2
3
4
CC
CC
19
20
13
12
V
V
O2
GND
V
O1
V
E
2
V
O2
V
CC1
2
3
10
V
O1
O
GND
GND
GND
1
7
8
Note: All DIP devices have common VCC and ground. LCCC (leadless ceramic chip carrier) package has isolated channels with
separate VCC and ground connections.
Outline Drawings
20 Terminal LCCC Surface Mount, 2 Channels
8.70 (0.342)
9.10 (0.358)
4.95 (0.195)
5.21 (0.205)
1.78 (0.070)
1.02 (0.040) (3 PLCS)
2.03 (0.080)
1.14 (0.045)
1.40 (0.055)
8.70 (0.342)
9.10 (0.358)
4.95 (0.195)
5.21 (0.205)
TERMINAL 1 IDENTIFIER
2.16 (0.085)
METALLIZED
CASTILLATIONS (20 PLCS)
1.78 (0.070)
2.03 (0.080)
0.64
(0.025)
(20 PLCS)
0.51 (0.020)
1.52 (0.060)
2.03 (0.080)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
SOLDER THICKNESS 0.127 (0.005) MAX.
8 Pin DIP Through Hole, 1 and 2 Channel
9.40 (0.370)
9.91 (0.390)
8.13 (0.320)
MAX.
0.76 (0.030)
1.27 (0.050)
7.16 (0.282)
7.57 (0.298)
4.32 (0.170)
MAX.
0.51 (0.020)
3.81 (0.150)
MIN.
0.20 (0.008)
0.33 (0.013)
MIN.
7.36 (0.290)
7.87 (0.310)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
4
Leaded Device Marking
Leadless Device Marking
Agilent DESIGNATOR
A QYYWWZ
XXXXXX
XXXXXXX
XXX XXX
COMPLIANCE INDICATOR,*
DATE CODE, SUFFIX (IF NEEDED)
Agilent DESIGNATOR
Agilent P/N
PIN ONE/
ESD IDENT
COUNTRY OF MFR.
A QYYWWZ
XXXXXX
• XXXX
XXXXXX
COMPLIANCE INDICATOR,*
DATE CODE, SUFFIX (IF NEEDED)
DSCC SMD*
DSCC SMD*
Agilent CAGE CODE*
Agilent P/N
DSCC SMD*
DSCC SMD*
PIN ONE/
COUNTRY OF MFR.
Agilent CAGE CODE*
•
50434
XXX 50434
ESD IDENT
* QUALIFIED PARTS ONLY
* QUALIFIED PARTS ONLY
Hermetic Optocoupler Options
Option
Description
100
Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. This
option is available on commercial and hi-rel product in 8 pin DIP (see drawings below for
details).
4.32 (0.170)
MAX.
0.51 (0.020)
1.14 (0.045)
MIN.
0.20 (0.008)
0.33 (0.013)
1.40 (0.055)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
7.36 (0.290)
7.87 (0.310)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
200
300
Lead finish is solder dipped rather than gold plated. This option is available on commercial
and hi-rel product in 8 pin DIP. DSCC Drawing part numbers contain provisions for lead
finish. All leadless chip carrier devices are delivered with solder dipped terminals as a
standard feature.
Surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. This
option is available on commercial and hi-rel product in 8 pin DIP (see drawings below for
details). This option has solder dipped leads.
4.57 (0.180)
MAX.
4.57 (0.180)
MAX.
0.20 (0.008)
0.33 (0.013)
0.51 (0.020)
MIN.
5° MAX.
1.40 (0.055)
1.65 (0.065)
9.65 (0.380)
9.91 (0.390)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
5
Absolute Maximum Ratings
(No derating required up to +125°C)
Storage Temperature Range, TS .................................. -65°C to +150°C
Operating Temperature, TA ......................................... -55°C to +125°C
Case Temperature, TC ................................................................+170°C
Junction Temperature, TJ ..........................................................+175°C
Lead Solder Temperature .............................................. 260°C for 10 s
Average Forward Current, IF AVG (each channel)........................ 10 mA
Peak Input Current, IF PK (each channel) ............................... 20 mA[1]
Reverse Input Voltage, VR (each channel) ....................................... 3 V
Supply Voltage, VCC ............................................. 0.0 V min., 7.0 V max.
Average Output Current, IO............................ -25 mA min., 25 mA max.
(each channel)
Output Voltage, VO (each channel) .....................-0.5 V min., 10 V max.
Output Power Dissipation, PO (each channel) ........................... 130 mW
Package Power Dissipation, PD (each channel)......................... 200 mW
Single Channel Product Only
Three State Enable Voltage, VE ...........................-0.5 V min., 10 V max.
8 Pin Ceramic DIP Single Channel Schematic
ANODE
VE
VO
C
Note enable pin 7. An external 0.01 µF to 0.1 µF bypass capacitor must be connected
between VCC and ground for each package type.
ESD Classification
(MIL-STD-883, Method 3015)
HCPL-5400/01/0K ............................................................ (∆∆), Class 2
HCPL-5430/31/3K and HCPL-6430/31/3K....................... (Dot), Class 3
Recommended Operating Conditions
Parameter
Symbol Min.
Max.
10
5.25
0.7
5
Units
mA
V
V
Input Current (High)
Supply Voltage, Output
Input Voltage (Low)
Fan Out (Each Channel)
IF(ON)
VCC
VF(OFF)
N
6
4.75
–
–
TTL Loads
Single Channel Product Only
High Level Enable Voltage
Low Level Enable Voltage
VEH
VEL
2.0
0
VCC
0.8
V
V
6
Electrical Characteristics
T = -55°C to +125°C, 4.75 V ≤ VCC ≤ 5.25 V, 6 mA ≤ IF(ON) ≤ 10 mA, 0 V ≤ VF(OFF) ≤ 0.7 V,
uAnless otherwise specified.
Limits
Group A[10]
Parameter
Sym.
Test Conditions
IOL = 8.0 mA (5 TTL Loads)
IOH = -4.0 mA
Subgroups Min. Typ.* Max. Units Fig. Notes
Low Level Output Voltage
High Level Output Voltage
Output Leakage Current
Logic High Single
V
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
0.3
0.5
V
V
1
2
9
9
9
OL
V
2.4
OH
IOHH VO = 5.25 V, VF = 0.7 V
ICCH VCC = 5.25 V, VE = 0 V
(Single Channel Only)
100
26
µA
mA
17
Supply
Channel
Current
Dual Channel
34
19
52
26
13
Logic Low Single
ICCL
1, 2, 3
mA
Supply
Channel
Current
Dual Channel
38
52
13
9
Input Forward Voltage
VF IF = 10 mA
1, 2, 3
1, 2, 3
1.0 1.35 1.85
V
V
4
Input Reverse Break-
down Voltage
VR
IR = 10 µA
3.0
4.8
9
Input-Output Insulation
Leakage Current
II-O VI-O = 1500 Vdc, RH = 45%,
t = 5 s
1
1.0
60
60
35
µA
ns
2, 3
4, 9
4, 9
4, 9
Propagation Delay Time
Logic Low Output
Propagation Delay Time
Logic High Output
tPHL
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
33
30
3
5,
6, 7
5,
6, 7
tPLH
ns
Pulse Width
Distortion
Logic High Common
PWD
ns
5,
6, 7
11
11
|CMH| VCM = 50 VP-P, IF = 0 mA
|CML| VCM = 50 VP-P, IF = 6 mA
500 3000
500 3000
V/µs
V/µs
5, 9,
11
Mode Transient Immunity
Logic Low Common
Mode Transient Immunity
5, 9,
11
Single Channel Product Only
Limits
Group A[10]
Parameter
Sym.
Test Conditions
Subgroups Min. Typ.* Max. Units Fig. Notes
Logic High Enable
Voltage
VEH
1, 2, 3
2.0
V
Logic Low Enable
Voltage
VEL
1, 2, 3
0.8
V
Logic High Enable
Current
IEH VE = 2.4 V
VE = 5.25 V
IEL VE = 0.4 V
1, 2, 3
1, 2, 3
1, 2, 3
20
µA
100
Logic Low Enable
Current
-0.28 -0.4 mA
High Impedance State
Supply Current
High Impedance State
Output Current
ICCZ VCC = 5.25 V,
VE = 5.25 V
IOZL VO = 0.4 V, VE = 2 V
IOZH VO = 2.4 V, VE = 2 V
VO = 5.25 V, VE = 2 V
1, 2, 3
1, 2, 3
22
28
mA
-20
20
100
µA
*All typical values are at VCC = 5 V, T = 25°C, IF = 8 mA except where noted.
A
7
Typical Characteristics
All typical values are at TA = 25°C, VCC = 5 V, IF = 8 mA, unless otherwise specified.
Parameter
Input Current Hysteresis
Input Diode Temperature
Coefficient
Resistance (Input-Output)
Capacitance (Input-Output)
Symbol
IHYS
∆VF
Typ.
0.25
-1.11 mV/°C
Units
mA
Test Conditions
VCC = 5 V
IF = 10 mA
Fig. Notes
3
4
∆TA
RI-O
CI-O
IOSL
1012
0.6
65
Ω
VI-O = 500 V
2
2
6, 9
pF
mA
f = 1 MHz, VI-O = 0 V
VO = VCC = 5.25 V,
IF = 10 mA
Logic Low Short Circuit
Output Current
Logic High Short Circuit
Output Current
IOSH
-50
mA
VCC = 5.25 V, IF = 0 mA,
VO = GND
6, 9
Output Rise Time (10-90%)
Output Fall Time (90-10%)
Propagation Delay Skew
tr
tf
tPSK
PSNI
15
10
30
0.5
ns
ns
ns
5
5
10
12
7
Power Supply Noise Immunity
VP-P
48 Hz ≤ fac ≤ 50 MHz
Single Channel Product Only
Parameter
Symbol Typ. Units
Test Conditions
Fig. Notes
Input Capacitance
CIN
15
pF f = 1 MHz, VF = 0 V,
Pins 2 and 3
Output Enable Time to Logic High
Output Enable Time to Logic Low
Output Disable Time from Logic High
Output Disable Time from Logic Low
tPZH
tPZL
tPHZ
tPLZ
15
30
20
15
ns
ns
ns
ns
8, 9
8, 9
8, 9
8, 9
Dual and Quad Channel Product Only
Input Capacitance
Input-Input Leakage Current
Input-Input Resistance
CIN
II-I
RI-I
CI-I
15
0.5
pF f = 1 MHz, VO = 0 V
nA RH = 45%, V = 500 Vdc
8
8
8
I-I
1012
Ω
VI-I = 500 V
Input-Input Capacitance
1.3
pF f = 1 MHz, VF = 0 V
8
Notes:
1. Not to exceed 5% duty factor, not to exceed 50 µsec pulse width.
2. All devices are considered two-terminal devices: measured between all input leads or terminals shorted together and all output leads
or terminals shorted together.
3. This is a momentary withstand test, not an operating condition.
4. tPHL propagation delay is measured from the 50% point on the rising edge of the input current pulse to the 1.5 V point on the falling
edge of the output pulse. The tPLH propagation delay is measured from the 50% point on the falling edge of the input current pulse to
the 1.5 V point on the rising edge of the output pulse. Pulse Width Distortion, PWD = |tPHL - tPLH|.
5. CML is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic low state
(VO(MAX) < 0.8 V). CMH is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the
logic high state (VO(MIN) > 2.0 V).
6. Duration of output short circuit time not to exceed 10 ms.
7. Power Supply Noise Immunity is the peak to peak amplitude of the ac ripple voltage on the VCC line that the device will withstand and
still remain in the desired logic state. For desired logic high state, VOH(MIN) > 2.0 V, and for desired logic low state, VOL(MAX) < 0.8 V.
8. Measured between adjacent input pairs shorted together for each multichannel device.
9. Each channel.
10. Standard parts receive 100% testing at 25°C (Subgroups 1 and 9). SMD, Class H and Class K parts receive 100% testing at 25, 125,
and –55°C (Subgroups 1 and 9, 2 and 10, 3 and 11, respectively).
11. Parameters are tested as part of device initial characterization and after design and process changes. Parameters are guaranteed to
limits specified for all lots not specifically tested.
12. Propagation delay skew is defined as the difference between the minimum and maximum propagation delays for any given group of
optocouplers with the same part number that are all switching at the same time under the same operating conditions.
13. The HCPL-6430, HCPL-6431, and HCPL-643K dual channel parts function as two independent single channel units. Use the single
channel parameter limits.
Figure 1. Typical Logic Low Output
Voltage vs. Logic Low Output Current.
Figure 2. Typical Logic High Output
Voltage vs. Logic High Output Current.
Figure 3. Typical Output Voltage vs.
Input Forward Current.
Figure 4. Typical Diode Input Forward
Current Characteristic.
9
PULSE GEN.
t = t 5 ns
=
f
r
f = 500 kHz
25 % DUTY
CYCLE
V
CC
V
5.0 V
O
OUTPUT
MONITORING
NODE
D.U.T.
I
1.3 KΩ
F
V
CC
0.1 µF
INPUT
MONITORING
NODE
30 pF
C2
100 Ω
GND
2.5 KΩ
C1
15 pF
THE PROBE AND JIG CAPACITANCES
ARE REPRESENTED BY C AND C
.
2
1
ALL DIODES ARE 1N4150 OR EQUIVALENT.
Figure 5. Test Circuit for tPLH, tPHL, tr, and tf.
Figure 6. Typical Propagation Delay
vs. Ambient Temperature.
Figure 7. Typical Propagation Delay
vs. Input Forward Current.
PULSE
GENERATOR
Z
= 50 Ω
O
t
= t
=
5 ns
V
CC
r
f
5.0 V
D.U.T.
S1
V
1
2
3
4
8
7
6
5
CC
0.1 µF
O
I
F
V
1.3 KΩ
D
1
C1
30 pF
D
D
D
2
3
4
GND
INPUT V
MONITORING
NODE
E
2.5 KΩ
S2
Figure 8. Test Circuit for tPHZ, tPZH, tPLZ, and tPZL. (Single Channel Product Only).
10
t
PSK
←
→
Figure 9. Typical Enable Propagation
Delay vs. Ambient Temperature.
(Single Channel Product Only).
Figure 10. Propagation Delay Skew,
PSK
t
, Waveform.
I
F
V
= 5.0 V
CC
D.U.T.
B
V
CC
0.1 µF*
A
OUTPUT V
MONITORING
NODE
O
+
V
–
FF
GND
† C
15 pF
L
V
CM
V
= 5.25 V
CC
+
–
D.U.T.*
PULSE GEN.
I
I
F
CC
V
CC
I
O
0.01 µF
+
–
V
IN
2.1 V
100 Ω TYP.
100 Ω
GND
V
= 3.0 V
DC
CONDITIONS: I = 10 mA
F
I
= 25 mA
O
T
= +125 °C
A
* FOR SINGLE CHANNEL UNITS,
GROUND ENABLE PIN.
Figure 11. Test Diagram for Common Mode
Transient Immunity and Typical Waveforms.
Figure 12. Operating Circuit for Burn-In and Steady State
Life Tests.
11
MIL-PRF-38534 Class H,
Class K, and DSCC SMD
Test Program
Agilent Technologies’ Hi-Rel
Optocouplers are in compliance
with MIL-PRF-38534 Classes H
and K. Class H and Class K
devices are also in compliance
with DSCC drawings 5962-
89570, and 5962-89571.
Data Rate and Pulse-
Width Distortion
Definitions
Propagation delay is a figure of
merit which describes the finite
amount of time required for a
system to translate information
from input to output when
When tPLH and tPHL differ in
value, pulse width distortion
results. Pulse width distortion is
defined as |tPHL - tPLH| and
determines the maximum data
rate capability of a distortion-
limited system. Maximum pulse
width distortion on the order of
25-35% is typically used when
specifying the maximum data rate
capabilities of systems. The exact
figure depends on the particular
application (RS-232, PCM, T-1,
etc.).
shifting logic levels. Propagation
delay from low to high (tPLH
)
specifies the amount of time
required for a system’s output to
change from a Logic 0 to a Logic
1, when given a stimulus at the
input. Propagation delay from
high to low (tPHL) specifies the
amount of time required for a
system’s output to change from a
Logic 1 to a Logic 0, when given
a stimulus at the input (see
Figure 5).
Testing consists of 100% screen-
ing and quality conformance
inspection to MIL-PRF-38534.
These high performance opto-
couplers offer the advantages of
specified propagation delay (tPLH
tPHL), and pulse width distortion
(|tPLH -t PHL|) over temperature
,
and power supply voltage ranges.
Applications
V
= +5 V
CC1
30 pF
HCPL-5400
226 Ω
274 Ω
V
= 5 V
CC2
V
CC
0.1 µF
DATA
IN
DATA
OUT
TTL
A
LSTTL
STTL
Y
HCMOS
GND 1
GND
TOTEM
POLE
GND 2
Y = A
1
OUTPUT GATE
(e.g. 54AS1000)
2
Figure 13. Recommended HCPL-5400 Interface Circuit.
V
= +5 V
CC1
HCPL-5400
V
= 5 V
CC2
464 Ω
V
CC
DATA
IN
0.1 µF
TTL
STTL
A
DATA
OUT
LSTTL
STTL
Y
GND 1
GND
OPEN
COLLECTOR
OUTPUT
GND 2
Y = A
1
GATE
(e.g. 54S05)
2
Figure 14. Alternative HCPL-5400 Interface Circuit.
30 pF
226 Ω
V
= 5 V
CC1
HCPL-5430
V
V
= +5 V
CC
CC2
DATA
IN A
TTL
274 Ω
274 Ω
0.1 µF
LSTTL
STTL
DATA
OUT Y
HCMOS
TOTEM POLE
OUTPUT GATE
(e.g. 54AS1000)
TTL
LSTTL
STTL
DATA
OUT Y
HCMOS
DATA
IN A
GND
Y = A
GND 2
GND 1
226 Ω
30 pF
2
1
Figure 15. Recommended HCPL-5430 and HCPL-6430 Interface Circuit.
464 Ω
V
= +5 V
CC1
HCPL-5430
DATA
IN A
V
V
= +5 V
CC
CC2
TTL
0.1 µF
LSTTL
HCMOS
STTL
DATA
OUT Y
STTL OPEN COLLECTOR
OUTPUT GATE
464 Ω
TTL
LSTTL
HCMOS
STTL
DATA
OUT Y
(e.g. 54AS05)
DATA
IN A
GND
Y = A
GND 2
GND 1
2
1
Figure 16. Alternative HCPL-5430 and HCPL-6430 Interface Circuit.
www.semiconductor.agilent.com
Data subject to change.
Copyright © 2000 Agilent Technologies
April 1, 2000
Obsoletes 5968-0405E
5968-9403E
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