54ACT258 [ETC]
;
| 型号： | 54ACT258 |
| 厂家： | 
ETC |
| 描述： |
|
| 文件： | 总8页 (文件大小：147K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 1998
54AC258 • 54ACT258
Quad 2-Input Multiplexer with TRI-STATE® Outputs
n Multiplexer expansion by tying outputs together
n Inverting TRI-STATE outputs
n Outputs source/sink 24 mA
n ’ACT258 has TTL-compatible inputs
n Standard Military Drawing (SMD)
— ’ACT258: 5962-88704
General Description
The ’AC/’ACT258 is
a quad 2-input multiplexer with
TRI-STATE outputs. Four bits of data from two sources can
be selected using a common data select input. The four out-
puts present the selected data in the complement (inverted)
form. The outputs may be switched to a high impedance
state with a HIGH on the common Output Enable (OE) input,
allowing the outputs to interface directly with bus-oriented
systems.
— ’AC258: 5962-91604
Features
n ICC and IOZ reduced by 50%
Logic Symbols
IEEE/IEC
DS100287-1
DS100287-2
Pin Names
Description
Common Data Select Input
TRI-STATE Output Enable Input
Data Inputs from Source 0
S
OE
I
I
0a–I0d
1a–I1d
Data Inputs from Source 1
Za–Zd
TRI-STATE Inverting Data Outputs
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
FACT® is a registered trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100287
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Connection Diagrams
Functional Description
The ’AC/’ACT258 is
a quad 2-input multiplexer with
Pin Assignment
for DIP and Flatpak
TRI-STATE outputs. It selects four bits of data from two
sources under control of a common Select input (S). When
the Select input is LOW, the I0x inputs are selected and when
Select is HIGH, the I1x inputs are selected. The data on the
selected inputs appears at the outputs in inverted form. The
’AC/’ACT258 is the logic implementation of
a 4-pole,
2-position switch where the position of the switch is deter-
mined by the logic levels supplied to the Select input. The
logic equations for the outputs are shown below:
=
Za OE • (I1a • S + I0a • S)
=
Zb OE • (I1b • S + I0b • S)
=
Zc OE • (I1c • S + I0c • S)
=
Zd OE • (I1d • S + I0d • S)
DS100287-3
When the Output Enable input (OE) is HIGH, the outputs are
forced to a high impedance state. If the outputs of the
TRI-STATE devices are tied together, all but one device must
be in the high impedance state to avoid high currents that
would exceed the maximum ratings. Designers should en-
sure that Output Enable signals to TRI-STATE devices
whose outputs are tied together are designed so there is no
overlap.
Pin Assignment
for LCC
Truth Table
Output
Select
Data
Outputs
Enable
Input
Inputs
OE
H
L
S
X
H
H
L
I0
X
X
X
L
I1
X
L
Z
Z
H
L
DS100287-4
L
H
X
X
L
H
L
L
L
H
=
=
=
=
H
L
X
Z
HIGH Voltage Level
LOW Voltage Level
Immaterial
High Impedance
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2
Logic Diagram
DS100287-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Recommended Operating
Conditions
Supply Voltage (VCC
)
’AC
2.0V to 6.0V
4.5V to 5.5V
0V to VCC
Supply Voltage (VCC
)
−0.5V to +7.0V
’ACT
DC Input Diode Current (IIK
)
Input Voltage (VI)
=
VI −0.5V
−20 mA
+20 mA
Output Voltage (VO
)
0V to VCC
=
VI VCC + 0.5V
Operating Temperature (TA)
54AC/ACT
DC Input Voltage (VI)
−0.5V to VCC + 0.5V
−55˚C to +125˚C
125 mV/ns
DC Output Diode Current (IOK
)
Minimum Input Edge Rate (∆V/∆t)
’AC Devices
=
VO −0.5V
−20 mA
+20 mA
=
VO VCC + 0.5V
% to 70% of V
VIN from 30
CC
DC Output Voltage (VO
DC Output Source
)
−0.5V to VCC + 0.5V
@
VCC 3.3V 4.5V, 5.5V
Minimum Input Edge Rate (∆V/∆t)
’ACT Devices
±
±
or Sink Current (IO
)
50 mA
DC VCC or Ground Current
per Output Pin (ICC or IGND
VIN from 0.8V to 2.0V
)
50 mA
@
VCC 4.5V, 5.5V
125 mV/ns
Storage Temperature (TSTG
Junction Temperature (TJ)
CDIP
)
−65˚C to +150˚C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACT® circuits outside databook specifications.
175˚C
DC Characteristics for ’AC Family Devices
54AC
=
Symbol
Parameter
VCC
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
TA −55˚C to +125˚C
Units
Conditions
Guaranteed Limits
=
VIH
Minimum High Level
Input Voltage
2.1
3.15
3.85
0.9
VOUT 0.1V
V
V
V
or VCC − 0.1V
=
VIL
Maximum Low Level
Input Voltage
VOUT 0.1V
1.35
1.65
2.9
or VCC − 0.1V
=
VOH
Minimum High Level
Output Voltage
IOUT −50 µA
4.4
5.4
(Note 2)
=
VIN VIL or VIH
3.0
4.5
5.5
3.0
4.5
5.5
2.4
3.7
4.7
0.1
0.1
0.1
IOH = −12 mA
IOH = −24 mA
IOH = −24 mA
V
V
=
VOL
Maximum Low Level
Output Voltage
IOUT 50 µA
(Note 2)
=
VIN VIL or VIH
3.0
4.5
5.5
5.5
0.50
0.50
0.50
IOL = 12 mA
IOL = 24 mA
IOL = 24 mA
V
=
±
IIN
Maximum Input
Leakage Current
Maximum TRI-STATE
Current
1.0
µA
VI VCC, GND
=
IOZ
VI (OE) VIL, VIH
=
±
5.5
5.0
µA
VI VCC, GND
=
VO VCC, GND
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4
DC Characteristics for ’AC Family Devices (Continued)
54AC
=
Symbol
Parameter
VCC
(V)
5.5
5.5
5.5
TA −55˚C to +125˚C
Units
Conditions
Guaranteed Limits
=
VOLD 1.65V Max
IOLD
IOHD
ICC
Minimum Dynamic
Output Current (Note 3)
Maximum Quiescent
Supply Current
50
mA
mA
µA
=
VOHD 3.85V Min
−50
80.0
=
VIN VCC
or GND
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
@
@
Note 4:
I
and I
CC
3.0V are guaranteed to be less than or equal to the respective limit 5.5V V .
IN
CC
@
@
I
for 54AC 25˚C is identical to 74AC 25˚C.
CC
DC Characteristics for ’ACT Family Devices
54ACT
=
Symbol
Parameter
VCC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
TA −55˚C to +125˚C
Units
Conditions
Guaranteed Limits
=
VIH
Minimum High Level
Input Voltage
2.0
2.0
0.8
0.8
4.4
5.4
V
V
V
VOUT 0.1V
or VCC − 0.1V
=
VIL
Maximum Low Level
Input Voltage
VOUT 0.1V
or VCC − 0.1V
=
VOH
Minimum High Level
Output Voltage
IOUT −50 µA
(Note 5)
=
VIN VIL or VIH
4.5
5.5
4.5
5.5
3.70
4.70
0.1
V
V
IOH = −24 mA
IOH = −24 mA
=
VOL
Maximum Low Level
Output Voltage
IOUT 50 µA
0.1
(Note 5)
=
VIN VIL or VIH
4.5
5.5
5.5
0.50
0.50
V
IOL = 24 mA
IOL = 24 mA
=
±
IIN
Maximum Input Leakage
Current
1.0
µA
µA
VI VCC, GND
=
±
IOZ
Maximum TRI-STATE
Current
5.5
5.0
VI VIL, VIH
=
VO VCC, GND
=
VI VCC − 2.1V
ICCT
IOLD
IOHD
ICC
Maximum ICC/Input
Minimum Dynamic
Output Current (Note 6)
Maximum Quiescent
Supply Current
5.5
5.5
5.5
5.5
1.6
mA
mA
mA
µA
=
VOLD 1.65V Max
50
=
VOHD 3.85V Min
−50
80.0
=
VIN VCC
or GND
Note 5: All outputs loaded; thresholds on input associated with output under test.
Note 6: Maximum test duration 2.0 ms, one output loaded at a time.
@ @
I for 54ACT 25˚C is identical to 74ACT 25˚C.
CC
Note 7:
5
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AC Electrical Characteristics
54AC
=
VCC
(V)
TA −55˚C
Fig.
No.
Symbol
Parameter
to +125˚C
Units
=
(Note 8)
CL 50 pF
Min
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max
12.0
9.5
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Propagation Delay
In to Zn
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
ns
ns
ns
ns
ns
ns
ns
ns
Propagation Delay
In to Zn
10.5
7.5
Propagation Delay
S to Zn
15.0
11.5
14.0
10.5
11.5
9.0
Propagation Delay
S to Zn
Output Enable Time
Output Enable Time
Output Disable Time
Output Disable Time
10.5
8.5
11.5
9.5
10.5
8.5
±
Note 8: Voltage Range 3.3 is 3.3V 0.3V
±
Voltage Range 5.0 is 5.0V 0.5V
AC Electrical Characteristics
54ACT
=
VCC
(V)
TA −55˚C
Fig.
No.
Symbol
Parameter
to +125˚C
Units
=
CL 50 pF
(Note 9)
Min
Max
tPLH
tPHL
tPLH
tPHL
Propagation Delay
In to Zn
5.0
5.0
5.0
5.0
1.0
10.5
ns
ns
ns
ns
Propagation Delay
In to Zn
1.0
1.0
1.0
9.0
Propagation Delay
S to Zn
13.0
12.0
Propagation Delay
S to Zn
tPZH
tPZL
tPHZ
tPLZ
Output Enable Time
Output Enable Time
Output Disable Time
Output Disable Time
5.0
5.0
5.0
5.0
1.0
1.0
1.0
1.0
10.5
10.0
10.5
10.0
ns
ns
ns
ns
±
Note 9: Voltage Range 5.0 is 5.0V 0.5V
Capacitance
Symbol
Parameter
Input Capacitance
Power Dissipation
Capacitance
Typ
4.5
Units
Conditions
=
VCC OPEN
CIN
pF
pF
=
VCC 5.0V
CPD
55.0
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6
Physical Dimensions inches (millimeters) unless otherwise noted
20 Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
16-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J16A
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Ceramic Flatpak (F)
NS Package Number W16A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE-
VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI-
CONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or sys-
tems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and whose fail-
ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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