2SK3432-ZJ [ETC]
TRANSISTOR | MOSFET | N-CHANNEL | 40V V(BR)DSS | 83A I(D) | TO-263AB ; 晶体管| MOSFET | N沟道| 40V V( BR ) DSS | 83A I( D) | TO- 263AB\n型号: | 2SK3432-ZJ |
厂家: | ETC |
描述: | TRANSISTOR | MOSFET | N-CHANNEL | 40V V(BR)DSS | 83A I(D) | TO-263AB
|
文件: | 总8页 (文件大小:80K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DATA SHEET
MOS FIELD EFFECT TRANSISTOR
2SK3432
SWITCHING
N-CHANNEL POWER MOS FET
DESCRIPTION
ORDERING INFORMATION
The 2SK3432 is N-channel MOS Field Effect Transistor
designed for high current switching applications.
PART NUMBER
2SK3432
PACKAGE
TO-220AB
TO-262
2SK3432-S
2SK3432-ZJ
2SK3432-Z
FEATURES
TO-263
• Super low on-state resistance:
RDS(on)1 = 4.0 mΩ MAX. (VGS = 10 V, ID = 42 A)
RDS(on)2 = 6.9 mΩ MAX. (VGS = 4 V, ID = 42 A)
• Low Ciss: Ciss = 9500 pF TYP.
• Built-in gate protection diode
TO-220SMDNote
Note TO-220SMD package is produced only
in Japan.
(TO-220AB)
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Drain to Source Voltage (VGS = 0 V)
Gate to Source Voltage (VDS = 0 V)
Drain Current (DC) (TC = 25°C)
Drain Current (pulse) Note1
VDSS
VGSS
ID(DC)
ID(pulse)
PT
40
±20
V
V
±83
A
±332
100
A
Total Power Dissipation (TC = 25°C)
Total Power Dissipation (TA = 25°C)
Channel Temperature
W
PT
1.5
W
(TO-262)
°C
Tch
150
Storage Temperature
Tstg
−55 to +150
69
°C
A
Single Avalanche Current Note2
Single Avalanche Energy Note2
IAS
EAS
476
mJ
Notes 1. PW ≤ 10 µs, Duty cycle ≤ 1%
2. Starting Tch = 25°C, VDD = 20 V, RG = 25 Ω, VGS = 20 → 0 V
(TO-263, TO-220SMD)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No.
Date Published July 2002 NS CP(K)
Printed in Japan
D14601EJ4V0DS00 (4th edition)
The mark ★ shows major revised points.
1999, 2001
©
2SK3432
ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate Leakage Current
SYMBOL
IDSS
TEST CONDITIONS
VDS = 40 V, VGS = 0 V
MIN. TYP. MAX. UNIT
10
±10
2.5
µ A
µ A
V
IGSS
VGS = ±20 V, VDS = 0 V
VDS = 10 V, ID = 1 mA
VDS = 10 V, ID = 42 A
VGS = 10 V, ID = 42 A
VGS = 4 V, ID = 42 A
VDS = 10 V
Gate Cut-off Voltage
VGS(off)
| yfs |
RDS(on)1
RDS(on)2
Ciss
1.5
40
2.0
80
Forward Transfer Admittance
Drain to Source On-state Resistance
S
3.2
4.0
6.9
mΩ
mΩ
pF
pF
pF
ns
4.8
Input Capacitance
9500
2200
920
140
1800
470
410
150
29
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Coss
Crss
VGS = 0 V
f = 1 MHz
td(on)
tr
td(off)
tf
VDD = 20 V, ID = 42 A
VGS = 10 V
ns
Turn-off Delay Time
Fall Time
RG = 10 Ω
ns
ns
Total Gate Charge
QG
VDD = 32 V
nC
nC
nC
V
Gate to Source Charge
Gate to Drain Charge
Body Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
QGS
QGD
VF(S-D)
trr
VGS = 10 V
ID = 83 A
45
IF = 83 A, VGS = 0 V
IF = 83 A, VGS = 0 V
di/dt = 100 A/µ s
1.0
69
ns
Qrr
130
nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
D.U.T.
L
RG
= 25 Ω
V
GS
R
L
90%
90%
PG.
GS = 20 → 0 V
V
GS
V
GS
10%
V
DD
50 Ω
Wave Form
0
RG
V
PG.
V
DD
90%
I
D
BVDSS
I
D
I
AS
V
0
GS
10%
10%
I
D
0
V
DS
Wave Form
I
D
t
r
t
d(on)
t
d(off)
t
f
VDD
τ
t
on
toff
τ = 1µs
Starting Tch
Duty Cycle ≤ 1%
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
I
G
= 2 mA
RL
PG.
V
DD
50 Ω
2
Data Sheet D14601EJ4V0DS
2SK3432
TYPICAL CHARACTERISTICS (TA = 25°C)
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
TOTAL POWER DISSIPATION vs.
CASE TEMPERATURE
140
120
100
80
60
40
20
0
100
80
60
40
20
0
0
20
40 60
80 100 120 140 160
20 40
60
80 100 120 140 160
0
T
ch - Channel Temperature - ˚C
T
C
- Case Temperature - ˚C
FORWARD BIAS SAFE OPERATING AREA
1000
100
10
PW = 10
ID(pulse)
100
µ
s
Limited
= 10 V)
µ
s
GS
1 ms
RDS(on)
(at V
ID(DC)
10 ms
P
DC
er Dissipation
o
w
Limited
1
TC = 25˚C
Single Pulse
0.1
0.1
1
10
100
VDS - Drain to Source Voltage - V
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
1000
100
Rth(ch-A) = 83.3˚C/W
10
1
Rth(ch-C) = 1.25˚C/W
0.1
0.01
Single Pulse
µ
10
1 m
10 m
100 m
1
10
100
1000
100
µ
PW - Pulse Width - s
3
Data Sheet D14601EJ4V0DS
2SK3432
DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
FORWARD TRANSFER CHARACTERISTICS
Pulsed
350
300
250
200
150
100
50
1000
100
VGS =10 V
T
A
= –40˚C
25˚C
10
1
75˚C
150˚C
4 V
Pulsed
1.0
V
DS = 10 V
5
0
0.1
0.2
0.4
0.6
0.8
1.2
6
1
2
3
4
V
DS - Drain to Source Voltage - V
V
GS - Gate to Source Voltage - V
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
FORWARD TRANSFER ADMITTANCE vs.
DRAIN CURRENT
10
100
10
V
DS = 10 V
Pulsed
Pulsed
T
A
= 150˚C
75˚C
5
0
1
25˚C
–40˚C
I = 42 A
D
0.1
0.01
5
10
15
20
0
0.01
0.1
1
10
100
VGS - Gate to Source Voltage - V
ID - Drain Current - A
DRAIN TO SOURCE ON-STATE
RESISTANCE vs. DRAIN CURRENT
GATE CUT-OFF VOLTAGE vs.
CHANNEL TEMPERATURE
3.0
2.5
Pulsed
V
DS = 10 V
15
10
I = 1 mA
D
2.0
1.5
1.0
V
GS = 4 V
5
0
10 V
0.5
0
1
10
100
1000
−50
0
50
100
150
I
D - Drain Current - A
T
ch - Channel Temperature - ˚C
4
Data Sheet D14601EJ4V0DS
2SK3432
SOURCE TO DRAIN DIODE
FORWARD VOLTAGE
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE
1000
100
10
12
Pulsed
GS = 10 V
Pulsed
V
10
8
6
4
2
0
V
GS = 0 V
V
GS = 4 V
1
10 V
I
D
= 42 A
150
ch - Channel Temperature - ˚C
0.1
0
1.5
1.0
0.5
100
0
50
−50
VSD - Source to Drain Voltage - V
T
CAPACITANCE vs. DRAIN TO
SOURCE VOLTAGE
SWITCHING CHARACTERISTICS
10000
100000
10000
V
GS = 0 V
f = 1 MHz
t
r
1000
100
10
Ciss
t
d(off)
t
f
t
d(on)
C
oss
rss
1000
100
C
0.1
1
10
100
0.1
1
10
100
I
D
- Drain Current - A
V
DS - Drain to Source Voltage - V
REVERSE RECOVERY TIME vs.
DRAIN CURRENT
DYNAMIC INPUT/OUTPUT CHARACTERISTICS
50
40
30
10
1000
100
µ
di/dt = 100 A/ s
GS = 0 V
V
8
V
GS
V
DD = 32 V
20 V
6
4
8 V
20
10
1
2
10
0
V
DS
I = 83 A
D
20 40
Q
60 80 100 120 140 160
0
0.1
1.0
10
100
G
- Gate Charge - nC
I
F
- Drain Current - A
5
Data Sheet D14601EJ4V0DS
2SK3432
SINGLE AVALANCHE ENERGY
DERATING FACTOR
SINGLE AVALANCHE CURRENT vs.
INDUCTIVE LOAD
160
140
120
100
80
1000
100
V
R
V
I
DD = 20 V
= 25 Ω
GS = 20 → 0 V
AS ≤ 69 A
G
I
AS = 69A
EAS
=
476
mJ
60
10
1
40
V
DD = 20V
= 25 Ω
GS = 20→0 V
20
R
G
V
0
25
50
75
100
125
150
10
µ
100
µ
1m
10m
Starting Tch - Starting Channel Temperature - ˚C
L - Inductive Load - H
6
Data Sheet D14601EJ4V0DS
2SK3432
★
PACKAGE DRAWINGS (Unit: mm)
1) TO-220AB (MP-25)
2) TO-262 (MP-25 Fin Cut)
4.8 MAX.
1.3±0.2
10.6 MAX.
10.0 TYP.
4.8 MAX.
1.3±0.2
φ
3.6±0.2
10 TYP.
4
1
2
3
4
1
2 3
1.3±0.2
1.3±0.2
2.8±0.2
0.5±0.2
0.75±0.3
2.54 TYP.
2.54 TYP.
0.75±0.1
2.54 TYP.
0.5±0.2
1.Gate
2.Drain
3.Source
4.Fin (Drain)
2.8±0.2
1.Gate
2.Drain
3.Source
2.54 TYP.
4.Fin (Drain)
3) TO-263 (MP-25ZJ)
4) TO-220SMD (MP-25Z) Note
4.8 MAX.
10 TYP.
4
1.3±0.2
4.8 MAX.
10 TYP.
4
1.3±0.2
1
2
3
1
2
3
1.4±0.2
1.4±0.2
0.75±0.3
2.54 TYP.
0.5±0.2
0.7±0.2
2.54 TYP.
0.5±0.2
0.8R TYP.
2.54 TYP.
2.54 TYP.
1.Gate
1.Gate
2.Drain
3.Source
2.Drain
3.Source
4.Fin (Drain)
4.Fin (Drain)
Note This package is produced only in Japan.
EQUIVALENT CIRCUIT
Drain
Remark The diode connected between the gate and source of the transistor
serves as a protector against ESD. When this device actually used,
an additional protection circuit is externally required if a voltage
exceeding the rated voltage may be applied to this device.
Body
Diode
Gate
Gate
Protection
Diode
7
Data Sheet D14601EJ4V0DS
Source
2SK3432
•
The information in this document is current as of July, 2002. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
•
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
•
•
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
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agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
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M8E 00. 4
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