24LC64-/SN [ETC]
I2C Serial EEPROM ; I2C串行EEPROM\n
| 型号： | 24LC64-/SN |
| 厂家： | 
ETC |
| 描述： | I2C Serial EEPROM
|
| 文件： | 总12页 (文件大小：169K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
24AA64/24LC64
64K I2C™CMOS Serial EEPROM
DEVICE SELECTION TABLE
PACKAGE TYPE
8-LEAD PDIP
Part
Number
Vcc
Range
Max Clock
Frequency
Temp
Ranges
A0
1
8
Vcc
24AA64
1.8-5.5V
400 kHz†
C
A1
A2
2
3
7
6
WP
24LC64
†100 kHz for Vcc < 2.5V.
2.5-5.5V
400 kHz
I, E
SCL
Vss
4
5
SDA
FEATURES
• Low power CMOS technology
- Maximum write current 3 mA at 5.5V
- Maximum read current 400 µA at 5.5V
- Standby current 100 nA typical at 5.5V
• 2-wire serial interface bus, I2C compatible
• Cascadable for up to eight devices
• Self-timed ERASE/WRITE cycle
8-LEAD SOIC
1
8
7
6
5
A0
A1
Vcc
WP
2
3
4
SCL
SDA
A2
• 32-byte page or byte write modes available
• 5 ms max write cycle time
Vss
• Hardware write protect for entire array
• Output slope control to eliminate ground bounce
• Schmitt trigger inputs for noise suppression
• 1,000,000 erase/write cycles guaranteed
• Electrostatic discharge protection > 4000V
• Data retention > 200 years
8-LEAD TSSOP
8
7
6
5
1
WP
Vcc
A0
SCL
2
3
4
SDA
Vss
A2
A1
• 8-pin PDIP, SOIC (150 and 208 mil) and TSSOP
packages
• Temperature ranges:
- Commercial (C):
- Industrial (I):
BLOCK DIAGRAM
0° to
-40°C to +85°C
-40°C to +125°C
70°C
A0 A1 A2 WP
HV GENERATOR
- Automotive (E)
DESCRIPTION
I/O
CONTROL
LOGIC
MEMORY
CONTROL
LOGIC
EEPROM
ARRAY
XDEC
The Microchip Technology Inc. 24AA64/24LC64
(24xx64*) is a 8K x 8 (64K bit) Serial Electrically Eras-
able PROM capable of operation across a broad volt-
age range (1.8V to 5.5V). It has been developed for
advanced, low power applications such as personal
communications or data acquisition. This device also
has a page-write capability of up to 32 bytes of data.
This device is capable of both random and sequential
reads up to the 64K boundary. Functional address lines
allow up to eight devices on the same bus, for up to 512
Kbits address space. This device is available in the
standard 8-pin plastic DIP, 8-pin SOIC (150 and
208 mil), and 8-pin TSSOP.
PAGE LATCHES
I/O
SCL
YDEC
SDA
VCC
VSS
SENSE AMP
R/W CONTROL
I2C is a trademark of Philips Corporation.
*24xx64 is used in this document as a generic part number for the 24AA64/24LC64 devices.
2000 Microchip Technology Inc.
DS21189D-page 1
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24AA64/24LC64
TABLE 1-1
Name
PIN FUNCTION TABLE
Function
1.0
ELECTRICAL
CHARACTERISTICS
1.1
Maximum Ratings*
A0,A1,A2 User Configurable Chip Selects
VSS
SDA
SCL
WP
Ground
Vcc.................................................................................................7.0V
All inputs and outputs w.r.t. Vss .............................. -0.6V to Vcc +1.0V
Storage temperature ...................................................-65°C to +150°C
Ambient temp. with power applied ..............................-65°C to +125°C
Soldering temperature of leads (10 seconds) ...........................+300°C
ESD protection on all pins .................................................................≥ 4 kV
Serial Data
Serial Clock
Write Protect Input
*Notice: Stresses above those listed under “Maximum Ratings” may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is
not implied. Exposure to maximum rating conditions for extended peri-
ods may affect device reliability.
VCC
+1.8 to 5.5V (24AA64)
+2.5 to 5.5V (24LC64)
TABLE 1-2
DC CHARACTERISTICS
All parameters apply across the rec- Commercial (C): VCC = +1.8V to 5.5V
ommended operating ranges unless Industrial (I): VCC = +2.5V to 5.5V
otherwise noted. Automotive (E): VCC = +2.5V to 5.5V
Parameter
Tamb = 0°C to +70°C
Tamb = -40°C to +85°C
Tamb = -40°C to 125°C
Symbol
Min
Max
Units
Conditions
A0, A1, A2,
SCL, SDA, and WP pins:
High level input voltage
Low level input voltage
VIH
VIL
0.7 VCC
—
V
V
V
V
—
0.3 VCC
0.2 VCC
—
VCC ≥ 2.5V
VCC < 2.5V
VCC > 2.5V (Note)
Hysteresis of Schmitt Trigger
inputs (SDA, SCL pins)
Low level output voltage
VHYS
VOL
ILI
0.05 VCC
—
0.40
10
V
IOL = 3.0 mA @ VCC = 4.5V
IOL = 2.1 mA @ VCC = 2.5V
VIN = Vss to VCC, WP = VSS
VIN = Vss or VCC, WP = VCC
VOUT = Vss to VCC
Input leakage current
-10
µA
Output leakage current
Pin capacitance
ILO
CIN, COUT
-10
—
10
10
µA
pF
VCC = 5.0V (Note)
(all inputs/outputs)
Operating current
Tamb = 25°C, fc= 1 MHz
VCC = 5.5V
VCC = 5.5V, SCL = 400 kHz
SCL = SDA = VCC = 5.5V
A0, A1, A2, WP = VSS
ICC Write
ICC Read
ICCS
—
—
—
3
400
1
mA
µA
µA
Standby current
Note: This parameter is periodically sampled and not 100% tested.
FIGURE 1-1: BUS TIMING DATA
THIGH
VHYS
TF
TR
SCL
TSU:STA
TLOW
THD:DAT
TSU:DAT
TSU:STO
SDA
IN
THD:STA
TSP
TBUF
TAA
SDA
OUT
(protected)
THD:WP
WP
TSU:WP
(unprotected)
DS21189D-page 2
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24AA64/24LC64
TABLE 1-3
AC CHARACTERISTICS
All parameters apply across the spec-
ified operating ranges unless other-
wise noted.
Commercial (C): VCC = +1.8V to 5.5V
Industrial (I): VCC = +2.5V to 5.5V
Automotive (E): VCC = +2.5V to 5.5V
Tamb = 0°C to +70°C
Tamb = -40°C to +85°C
Tamb = -40°C to 125°C
Parameter
Symbol
FCLK
Min
Max
Units
kHz
Conditions
Clock frequency
—
—
100
400
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
Clock high time
Clock low time
THIGH
TLOW
TR
4000
600
—
—
ns
ns
ns
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
4700
1300
—
—
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
SDA and SCL rise time
(Note 1)
—
—
1000
300
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
SDA and SCL fall time
TF
—
300
ns
ns
(Note 1)
START condition hold time
THD:STA
4000
600
—
—
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
START condition setup time
TSU:STA
4700
600
—
—
ns
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
Data input hold time
Data input setup time
THD:DAT
TSU:DAT
0
—
ns
ns
(Note 2)
250
100
—
—
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
STOP condition setup time
WP setup time
TSU:STO
TSU:WP
THD:WP
TAA
4000
600
—
—
ns
ns
ns
ns
ns
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
4000
600
—
—
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
WP hold time
4000
1300
—
—
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
Output valid from clock
(Note 2)
—
—
3500
900
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
Bus free time: Time the bus must be
free before a new transmission can
start
TBUF
4700
1300
—
—
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
Output fall time from VIH
minimum to VIL maximum
TOF
TSP
TWC
10
250
50
ns
ns
C ≤ 100 pF (Note 1)
B
Input filter spike suppression
(SDA and SCL pins)
—
(Notes 1 and 3)
Write cycle time (byte or page)
Endurance
—
5
ms
1M
—
cycles 25°C, VCC = 5.0V, Block Mode (Note 4)
Note 1: Not 100% tested. C = total capacitance of one bus line in pF.
B
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum
300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise spike
suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please
consult the Total Endurance Model which can be obtained on Microchip’s BBS or website.
2000 Microchip Technology Inc.
DS21189D-page 3
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24AA64/24LC64
2.0
PIN DESCRIPTIONS
4.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
2.1
A0, A1, A2 Chip Address Inputs
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
The A0,A1,A2 inputs are used by the 24xx64 for multi-
ple device operation. The levels on these inputs are
compared with the corresponding bits in the slave
address. The chip is selected if the compare is true.
Up to eight devices may be connected to the same bus
by using different chip select bit combinations. These
inputs must be connected to either VCC or VSS.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
2.2
SDA Serial Data
4.1
Bus not Busy (A)
This is a bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open-
drain terminal, therefore, the SDA bus requires a pullup
resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for
400 kHz)
Both data and clock lines remain HIGH.
4.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi-
tions.
4.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must end with a STOP condition.
2.3
SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
4.4
Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
2.4
WP
This pin can be connected to either Vss, Vcc or left
floating. An internal pull-down resistor on this pin will
keep the device in the unprotected state if left floating.
If tied to Vss or left floating, normal memory operation
is enabled (read/write the entire memory 0000-1FFF).
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device.
If tied to VCC, WRITE operations are inhibited. Read
operations are not affected.
3.0
FUNCTIONAL DESCRIPTION
4.5
Acknowledge
The 24xx64 supports a bi-directional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, and a device
receiving data as a receiver. The bus must be con-
trolled by a master device which generates the serial
clock (SCL), controls the bus access, and generates
the START and STOP conditions while the 24xx64
works as a slave. Both master and slave can operate as
a transmitter or receiver but the master device deter-
mines which mode is activated.
Each receiving device, when addressed, is obliged to
generate an acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this acknowledge
bit.
Note: The 24xx64 does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable LOW during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. Dur-
ing reads, a master must signal an end of data to the
slave by NOT generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this case,
the slave (24xx64) will leave the data line HIGH to
enable the master to generate the STOP condition.
DS21189D-page 4
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24AA64/24LC64
FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
(B)
(D)
(D)
(C) (A)
SCL
SDA
START
CONDITION
ADDRESS OR
DATA
STOP
CONDITION
ACKNOWLEDGE ALLOWED
VALID
TO CHANGE
FIGURE 4-2: ACKNOWLEDGE TIMING
Acknowledge
Bit
1
2
3
4
5
6
7
8
9
1
2
3
SCL
SDA
Data from transmitter
Data from transmitter
Receiver must release the SDA line at this point
so the Transmitter can continue sending data.
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
2000 Microchip Technology Inc.
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24AA64/24LC64
FIGURE 5-1: CONTROL BYTE FORMAT
5.0
DEVICE ADDRESSING
A control byte is the first byte received following the
start condition from the master device (Figure 5-1). The
control byte consists of a four bit control code; for the
24xx64 this is set as 1010 binary for read and write
operations. The next three bits of the control byte are
the chip select bits (A2, A1, A0). The chip select bits
allow the use of up to eight 24xx64 devices on the
same bus and are used to select which device is
accessed. The chip select bits in the control byte must
correspond to the logic levels on the corresponding A2,
A1, and A0 pins for the device to respond. These bits
are in effect the three most significant bits of the word
address.
Read/Write Bit
Chip Select
Control Code
Bits
S
1
0
1
0
A2 A1 A0 R/W ACK
Slave Address
Acknowledge Bit
Start Bit
The last bit of the control byte defines the operation to
be performed. When set to a one a read operation is
selected, and when set to a zero a write operation is
selected. The next two bytes received define the
address of the first data byte (Figure 5-2). Because
only A12...A0 are used, the upper three address bits
are don’t care bits. The upper address bits are trans-
ferred first, followed by the less significant bits.
5.1
Contiguous Addressing Across
Multiple Devices
The chip select bits A2, A1, A0 can be used to expand
the contiguous address space for up to 512K bits by
adding up to eight 24xx64's on the same bus. In this
case, software can use A0 of the control byte as
address bit A13, A1 as address bit A14, and A2 as
address bit A15. It is not possible to sequentially read
across device boundaries.
Following the start condition, the 24xx64 monitors the
SDA bus checking the device type identifier being
transmitted. Upon receiving a 1010 code and appropri-
ate device select bits, the slave device outputs an
acknowledge signal on the SDA line. Depending on the
state of the R/W bit, the 24xx64 will select a read or
write operation.
FIGURE 5-2: ADDRESS SEQUENCE BIT ASSIGNMENTS
CONTROL BYTE
ADDRESS HIGH BYTE
ADDRESS LOW BYTE
A
A
2
A
1
A
0
A
A
10
A
9
A
8
A
7
A
0
•
•
•
•
•
•
1
0
1
0
R/W
X
X
X
12 11
CONTROL
CODE
CHIP
SELECT
BITS
X = Don’t Care Bit
DS21189D-page 6
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24AA64/24LC64
6.2
Page Write
6.0
WRITE OPERATIONS
The write control byte, word address and the first data
byte are transmitted to the 24xx64 in the same way as
in a byte write. But instead of generating a stop condi-
tion, the master transmits up to 31 additional bytes
which are temporarily stored in the on-chip page buffer
and will be written into memory after the master has
transmitted a stop condition. After receipt of each word,
the five lower address pointer bits are internally incre-
mented by one. If the master should transmit more than
32 bytes prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received, an inter-
nal write cycle will begin (Figure 6-2). If an attempt is
made to write to the array with the WP pin held high, the
device will acknowledge the command but no write
cycle will occur, no data will be written and the device
will immediately accept a new command.
6.1
Byte Write
Following the start condition from the master, the
control code (four bits), the chip select (three bits), and
the R/W bit (which is a logic low) are clocked onto the
bus by the master transmitter. This indicates to the
addressed slave receiver that the address high byte will
follow after it has generated an acknowledge bit during
the ninth clock cycle. Therefore, the next byte transmit-
ted by the master is the high-order byte of the word
address and will be written into the address pointer of
the 24xx64. The next byte is the least significant
address byte. After receiving another acknowledge sig-
nal from the 24xx64 the master device will transmit the
data word to be written into the addressed memory
location. The 24xx64 acknowledges again and the
master generates a stop condition. This initiates the
internal write cycle, and during this time the 24xx64 will
not generate acknowledge signals (Figure 6-1). If an
attempt is made to write to the array with the WP pin
held high, the device will acknowledge the command
but no write cycle will occur, no data will be written and
the device will immediately accept a new command.
After a byte write command, the internal address
counter will point to the address location following the
one that was just written.
6.3
Write Protection
The WP pin allows the user to write protect the entire
array (0000-1FFF) when the pin is tied to Vcc. If tied to
VSS or left floating, the write protection is disabled. The
WP pin is sampled at the STOP bit for every write com-
mand (Figure 1-1) Toggling the WP pin after the STOP
bit will have no effect on the execution of the write cycle.
FIGURE 6-1: BYTE WRITE
S
BUS ACTIVITY
T
S
T
O
P
CONTROL
BYTE
ADDRESS
HIGH BYTE
ADDRESS
LOW BYTE
MASTER
A
R
T
DATA
A A A
2 1 0
SDA LINE
X X X
S 1 0 1 0
0
P
A
C
K
A
C
K
A
C
K
A
C
K
BUS ACTIVITY
X = don’t care bit
FIGURE 6-2: PAGE WRITE
S
T
A
R
T
S
T
O
P
CONTROL
BYTE
ADDRESS
HIGH BYTE
ADDRESS
LOW BYTE
BUS ACTIVITY
MASTER
DATA BYTE 0
DATA BYTE 31
A A A
2 1 0
SDA LINE
X X X
P
S 1 0 1 0
0
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
BUS ACTIVITY
X = don’t care bit
2000 Microchip Technology Inc.
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24AA64/24LC64
FIGURE 7-1: ACKNOWLEDGE POLLING
FLOW
7.0
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com-
mand has been issued from the master, the device ini-
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master send-
ing a start condition followed by the control byte for a
write command (R/W = 0). If the device is still busy with
the write cycle, then no ACK will be returned. If no ACK
is returned, then the start bit and control byte must be
re-sent. If the cycle is complete, then the device will
return the ACK and the master can then proceed with
the next read or write command. See Figure 7-1 for
flow diagram.
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
NO
Acknowledge
(ACK = 0)?
YES
Next
Operation
DS21189D-page 8
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24AA64/24LC64
8.2
Random Read
8.0
READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
control byte is set to one. There are three basic types
of read operations: current address read, random read,
and sequential read.
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24xx64 as part of a write operation (R/W bit set to 0).
After the word address is sent, the master generates a
start condition following the acknowledge. This termi-
nates the write operation, but not before the internal
address pointer is set. Then the master issues the
control byte again but with the R/W bit set to a one. The
24xx64 will then issue an acknowledge and transmit
the 8-bit data word. The master will not acknowledge
the transfer but does generate a stop condition which
causes the 24xx64 to discontinue transmission
(Figure 8-2). After a random read command, the inter-
nal address counter will point to the address location
following the one that was just read.
8.1
Current Address Read
The 24xx64 contains an address counter that main-
tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous read
access was to address n (n is any legal address), the
next current address read operation would access data
from address n + 1.
Upon receipt of the control byte with R/W bit set to one,
the 24xx64 issues an acknowledge and transmits the
eight bit data word. The master will not acknowledge
the transfer but does generate a stop condition and the
24xx64 discontinues transmission (Figure 8-1).
8.3
Sequential Read
Sequential reads are initiated in the same way as a ran-
dom read except that after the 24xx64 transmits the
first data byte, the master issues an acknowledge as
opposed to the stop condition used in a random read.
This acknowledge directs the 24xx64 to transmit the
next sequentially addressed 8-bit word (Figure 8-3).
Following the final byte transmitted to the master, the
master will NOT generate an acknowledge but will gen-
erate a stop condition. To provide sequential reads the
24xx64 contains an internal address pointer which is
incremented by one at the completion of each opera-
tion. This address pointer allows the entire memory
contents to be serially read during one operation. The
internal address pointer will automatically roll over from
address 1FFF to address 0000 if the master acknowl-
edges the byte received from the array address 1FFF.
FIGURE 8-1: CURRENT ADDRESS READ
S
T
A
R
T
S
T
O
P
BUS ACTIVITY
MASTER
CONTROL
BYTE
DATA
BYTE
A A A
2 1 0
SDA LINE
S 1 0 1 0
1
P
A
C
K
N
O
BUS ACTIVITY
A
C
K
FIGURE 8-2: RANDOM READ
S
S
BUS ACTIVITY
MASTER
T
A
R
T
T
A
R
T
S
T
O
P
CONTROL
BYTE
ADDRESS
HIGH BYTE
ADDRESS
LOW BYTE
CONTROL
BYTE
DATA
BYTE
A A A
2 1 0
A A A
2 1 0
SDA LINE
X X X
S 1 0 1 0
0
S 1 0 1 0
1
P
A
C
K
A
C
K
A
C
K
N
O
A
C
K
A
C
K
BUS ACTIVITY
X = Don’t Care Bit
FIGURE 8-3: SEQUENTIAL READ
S
BUS ACTIVITY
CONTROL
T
DATA n
DATA n + 1
DATA n + 2
DATA n + X
MASTER
SDA LINE
O
P
BYTE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
BUS ACTIVITY
2000 Microchip Technology Inc.
DS21189D-page 9
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24AA64/24LC64
NOTES:
DS21189D-page 10
2000 Microchip Technology Inc.
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24AA64/24LC64
24xx64 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
24xx64 /P
—
P = Plastic DIP (300 mil Body), 8-lead
SN = Plastic SOIC (150 mil Body, EIAJ standard), 8-lead
SM = Plastic SOIC (208 mil Body, EIAJ standard), 8-lead
ST = TSSOP, 8-lead
Package:
Temperature
Range:
Blank = 0°C to +70°C
I = -40°C to +85°C
E = -40°C to +125°C
64K bit 1.8V I2C Serial EEPROM
64K bit 1.8V I2C Serial EEPROM (Tape and Reel)
64K bit 1.8V I2C Serial EEPROM
in alternate pinout (ST only)
24AA64
24AA64T
24AA64X
64K bit 1.8V I2C Serial EEPROM
in alternate pinout (ST only)
24AA64XT
Device:
64K bit 2.5V I2C Serial EEPROM
64K bit 2.5V I2C Serial EEPROM (Tape and Reel)
64K bit 2.5V I2C Serial EEPROM
in alternate pinout (ST only)
24LC64
24LC64T
24LC64X
64K bit 2.5V I2C Serial EEPROM
in alternate pinout (ST only)
24LC64XT
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 786-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2000 Microchip Technology Inc.
DS21189D-page 11
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WORLDWIDE SALES AND SERVICE
AMERICAS
AMERICAS (continued)
ASIA/PACIFIC (continued)
Corporate Office
Toronto
Singapore
Microchip Technology Singapore Pte Ltd.
200 Middle Road
#07-02 Prime Centre
Singapore 188980
Microchip Technology Inc.
Microchip Technology Inc.
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-786-7200 Fax: 480-786-7277
Technical Support: 480-786-7627
Web Address: http://www.microchip.com
5925 Airport Road, Suite 200
Mississauga, Ontario L4V 1W1, Canada
Tel: 905-405-6279 Fax: 905-405-6253
Tel: 65-334-8870 Fax: 65-334-8850
ASIA/PACIFIC
Beijing
Microchip Technology, Beijing
Unit 915, 6 Chaoyangmen Bei Dajie
Dong Erhuan Road, Dongcheng District
New China Hong Kong Manhattan Building
Beijing 100027 PRC
Taiwan, R.O.C
Microchip Technology Taiwan
10F-1C 207
Tung Hua North Road
Taipei, Taiwan, ROC
Atlanta
Microchip Technology Inc.
500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
Tel: 770-640-0034 Fax: 770-640-0307
Boston
EUROPE
Tel: 86-10-85282100 Fax: 86-10-85282104
Microchip Technology Inc.
5 Mount Royal Avenue
Marlborough, MA 01752
Tel: 508-480-9990 Fax: 508-480-8575
Hong Kong
Microchip Asia Pacific
Unit 2101, Tower 2
Denmark
Microchip Technology Denmark ApS
Regus Business Centre
Lautrup hoj 1-3
Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 852-2-401-1200 Fax: 852-2-401-3431
Ballerup DK-2750 Denmark
Tel: 45 4420 9895 Fax: 45 4420 9910
Chicago
Microchip Technology Inc.
333 Pierce Road, Suite 180
Itasca, IL 60143
France
India
Arizona Microchip Technology SARL
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
Tel: 630-285-0071 Fax: 630-285-0075
Dallas
Microchip Technology Inc.
4570 Westgrove Drive, Suite 160
Addison, TX 75248
Microchip Technology Inc.
India Liaison Office
No. 6, Legacy, Convent Road
Bangalore 560 025, India
Tel: 91-80-229-0061 Fax: 91-80-229-0062
Batiment A - ler Etage
91300 Massy, France
Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Tel: 972-818-7423 Fax: 972-818-2924
Japan
Germany
Microchip Technology Intl. Inc.
Benex S-1 6F
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa 222-0033 Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Arizona Microchip Technology GmbH
Gustav-Heinemann-Ring 125
D-81739 München, Germany
Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Dayton
Microchip Technology Inc.
Two Prestige Place, Suite 150
Miamisburg, OH 45342
Tel: 937-291-1654 Fax: 937-291-9175
Italy
Arizona Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Detroit
Microchip Technology Inc.
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: 248-538-2250 Fax: 248-538-2260
Korea
Microchip Technology Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea
Milan, Italy
Tel: 39-039-65791-1 Fax: 39-039-6899883
Tel: 82-2-554-7200 Fax: 82-2-558-5934
United Kingdom
Arizona Microchip Technology Ltd.
505 Eskdale Road
Winnersh Triangle
Wokingham
Los Angeles
Shanghai
Microchip Technology
Unit B701, Far East International Plaza,
No. 317, Xianxia Road
Shanghai, 200051 P.R.C
Microchip Technology Inc.
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: 949-263-1888 Fax: 949-263-1338
Berkshire, England RG41 5TU
Tel: 44 118 921 5858 Fax: 44-118 921-5835
New York
Tel: 86-21-6275-5700 Fax: 86-21-6275-5060
Microchip Technology Inc.
150 Motor Parkway, Suite 202
Hauppauge, NY 11788
Tel: 631-273-5305 Fax: 631-273-5335
01/05/00
San Jose
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950 Fax: 408-436-7955
All rights reserved. © 2000 Microchip Technology Incorporated. Printed in the USA. 1/00
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed
by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products
as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip
logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
DS21189D-page 12
2000 Microchip Technology Inc.
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相关型号：
24LC64-E/MCG
8K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 2 X 3 MM, 0.90 MM HEIGHT, LEAD FREE, PLASTIC, MO-229, DFN-8
MICROCHIP
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