24LC32ASM [ETC]
I2C Serial EEPROM ; I2C串行EEPROM\n
| 型号： | 24LC32ASM |
| 厂家： | 
ETC |
| 描述： | I2C Serial EEPROM
|
| 文件： | 总12页 (文件大小：184K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
24LC32A
32K 2.5V I2C™ Serial EEPROM
FEATURES
PACKAGE TYPES
• Single supply with operation down to 2.5V
- Maximum write current 3 mA at 6.0V
- Standby current 1 µA max at 2.5V
• 2-wire serial interface bus, I2C compatible
• 100 kHz (2.5V) and 400 kHz (5V) compatibility
• Self-timed ERASE and WRITE cycles
• Power on/off data protection circuitry
• Hardware write protect
• 1,000,000 Erase/Write cycles guaranteed
• 32 byte page or byte write modes available
• Schmitt trigger filtered inputs for noise suppres-
sion
PDIP
A0
A1
1
2
8
7
Vcc
WP
SCL
A2
3
4
6
5
Vss
SDA
• Output slope control to eliminate ground bounce
• 2 ms typical write cycle time, byte or page
• Up to eight devices may be connected to the
same bus for up to 256K bits total memory
• Electrostatic discharge protection > 4000V
• Data retention > 200 years
SOIC
1
8
A0
A1
A2
Vcc
2
3
4
7
6
5
WP
• 8-pin PDIP and SOIC packages
• Temperature ranges
SCL
SDA
- Commercial (C):
- Industrial (I):
0°C to +75°C
-40°C to +85°C
Vss
DESCRIPTION
The Microchip Technology Inc. 24LC32A is a 4K x 8
(32K bit) Serial Electrically Erasable PROM capable of
operation across a broad voltage range (2.5V to 6.0V).
It has been developed for advanced, low power appli-
cations such as personal communications or data
acquisition. The 24LC32A also has a page-write capa-
bility of up to 32 bytes of data. The 24LC32A is capable
of both random and sequential reads up to the 32K
boundary. Functional address lines allow up to eight
24LC32A devices on the same bus, for up to 256K bits
address space. Advanced CMOS technology and
broad voltage range make this device ideal for low-
power/low-voltage, nonvolatile code and data applica-
tions. The 24LC32A is available in the standard 8-pin
plastic DIP and both 150 mil and 200 mil SOIC packag-
ing.
BLOCK DIAGRAM
WP
A0 A1 A2
HV GENERATOR
I/O
CONTROL
LOGIC
MEMORY
CONTROL
LOGIC
EEPROM
ARRAY
XDEC
PAGE LATCHES
I/O
SCL
YDEC
SDA
VCC
VSS
SENSE AMP
R/W CONTROL
I2C is a trakemark of Philips Corporation.
1999 Microchip Technology Inc.
DS21144D-page 1
This Material Copyrighted by Its Respective Manufacturer
24LC32A
TABLE 1-1:
Name
PIN FUNCTION TABLE
Function
1.0
ELECTRICAL
CHARACTERISTICS
1.1
Maximum Ratings*
A0,A1,A2
VSS
User Configurable Chip Selects
Ground
VCC...................................................................................7.0V
All inputs and outputs w.r.t. VSS ............... -0.6V to VCC +1.0V
Storage temperature .....................................-65°C to +150°C
Ambient temp. with power applied ................-65°C to +125°C
Soldering temperature of leads (10 seconds) .............+300°C
ESD protection on all pins..................................................≥ 4 kV
SDA
Serial Address/Data I/O
Serial Clock
SCL
WP
Write Protect Input
+2.5V to 6.0V Power Supply
VCC
*Notice: Stresses above those listed under “Maximum Ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-2:
DC CHARACTERISTICS
VCC = +2.5V to 6.0V
Commercial (C): Tamb = 0°C to +70°C
Industrial (I):
Tamb = -40°C to +85°C
Parameter
Symbol
Min
Typ
Max
Units
Conditions
A0, A1, A2, SCL , SDA and WP
pins:
High level input voltage
Low level input voltage
VIH
VIL
.7 VCC
—
.3 Vcc
—
V
V
V
—
Hysteresis of Schmitt Trigger
inputs
VHYS
.05
VCC
(Note)
Low level output voltage
Input leakage current
VOL
ILI
—
-10
-10
—
.40
10
10
10
V
IOL = 3.0 mA
µA
µA
pF
VIN = .1V to VCC
VOUT = .1V to VCC
Output leakage current
ILO
Pin capacitance
CIN,COUT
VCC = 5.0V (Note)
(all inputs/outputs)
Tamb = 25°C, Fc = 1 MHz
Operating current
ICC Write
ICC Read
ICCS
—
—
—
3
0.5
5
mA
mA
µA
VCC = 6.0V
VCC = 6.0V, SCL = 400 KHz
SCL = SDA = VCC = 5.5V
Standby current
1
ICCS
1
µA
VCC = 2.5V (Note)
WP = VSS, A0, A1, A2 = VSS
Note:
This parameter is periodically sampled and not 100% tested.
FIGURE 1-1: BUS TIMING START/STOP
VHYS
SCL
THD:STA
TSU:STA
TSU:STO
SDA
STOP
START
DS21144D-page 2
1999 Microchip Technology Inc.
This Material Copyrighted by Its Respective Manufacturer
24LC32A
TABLE 1-3:
AC CHARACTERISTICS
Vcc = 2.5-6.0V
Standard Mode
Vcc = 4.5-6.0V
Fast Mode
Parameter
Symbol
Units
Remarks
Min
Max
Min
Max
Clock frequency
FCLK
THIGH
TLOW
TR
—
4000
4700
—
100
—
—
600
1300
—
400
—
kHz
ns
Clock high time
Clock low time
—
—
ns
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
1000
300
—
300
300
—
ns
(Note 1)
TF
—
—
ns
(Note 1)
THD:STA
4000
600
ns
After this period the first
clock pulse is generated
START condition setup
time
TSU:STA
4700
—
600
—
ns
Only relevant for repeated
START condition
Data input hold time
Data input setup time
THD:DAT
TSU:DAT
0
—
—
0
—
—
ns
ns
ns
ns
ns
250
4000
—
100
600
—
STOP condition setup time TSU:STO
—
—
Output valid from clock
Bus free time
TAA
3500
—
900
—
(Note 2)
TBUF
4700
1300
Time the bus must be free
before a new transmission
can start
Output fall time from VIH
min to VIL max
TOF
TSP
—
—
250
50
20
+0.1CB
250
50
ns
ns
(Note 1), CB ≤ 100 pF
Input filter spike suppres-
sion (SDA and SCL pins)
—
(Note 3)
Write cycle time
Endurance
TWR
—
5
—
5
ms
Byte or Page mode
—
1M
—
1M
—
cycles 25°C, Vcc = 5.0V, Block
Mode Cycle (Note 4)
Note 1: Not 100% tested. CB = Total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined TSP and VHYS specifications are due to Schmitt trigger inputs which provide improved noise
and spike suppression. This eliminates the need for a Ti specification for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our website.
FIGURE 1-2: BUS TIMING DATA
TR
TF
THIGH
TLOW
SCL
TSU:STA
THD:DAT
TSU:DAT
TSU:STO
THD:STA
SDA
IN
TSP
TAA
THD:STA
TAA
TBUF
SDA
OUT
1999 Microchip Technology Inc.
DS21144D-page 3
This Material Copyrighted by Its Respective Manufacturer
24LC32A
3.4
Data Valid (D)
2.0
FUNCTIONAL DESCRIPTION
The 24LC32A supports a Bi-directional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus must be controlled
by a master device which generates the Serial Clock
(SCL), controls the bus access, and generates the
START and STOP conditions, while the 24LC32A
works as slave. Both master and slave can operate as
transmitter or receiver but the master device deter-
mines which mode is activated.
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device.
3.0
BUS CHARACTERISTICS
3.5
Acknowledge
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
Each receiving device, when addressed, is obliged to
generate an acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this acknowledge
bit.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Note: The 24LC32A does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable LOW during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. Dur-
ing reads, a master must signal an end of data to the
slave by NOT generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this case,
the slave (24LC32A) will leave the data line HIGH to
enable the master to generate the STOP condition.
3.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
3.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
(B)
(D)
(D)
(C)
(A)
SCL
SDA
START
CONDITION
ADDRESS OR
DATA
STOP
CONDITION
ACKNOWLEDGE ALLOWED
VALID
TO CHANGE
DS21144D-page 4
1999 Microchip Technology Inc.
This Material Copyrighted by Its Respective Manufacturer
24LC32A
Following the start condition, the 24LC32A monitors
the SDA bus checking the device type identifier being
transmitted. Upon receiving a 1010 code and appropri-
ate device select bits, the slave device outputs an
acknowledge signal on the SDA line. Depending on the
state of the R/W bit, the 24LC32A will select a read or
write operation.
3.6
Device Addressing
A control byte is the first byte received following the
start condition from the master device. The control byte
consists of a 4-bit control code; for the 24LC32A this is
set as 1010 binary for read and write (R/W) operations.
The next three bits of the control byte are the device
select bits (A2, A1, A0). They are used by the master
device to select which of the eight devices are to be
accessed. These bits are in effect the three most signif-
icant bits of the word address. The last bit of the control
byte defines the operation to be performed. When set
to a one a read operation is selected, and when set to
a zero a write operation is selected. The next two bytes
received define the address of the first data byte
(Figure 3-3). Because only A11...A0 are used, the
upper four address bits must be zeros. The most signif-
icant bit of the most significant byte of the address is
transferred first.
Control
Code
Operation
Device Select
R/W
Read
Write
1010
1010
Device Address
Device Address
1
0
FIGURE 3-2: CONTROL BYTE
ALLOCATION
START
READ/WRITE
R/W
A
SLAVE ADDRESS
1
0
1
0
A2
A1
A0
FIGURE 3-3: ADDRESS SEQUENCE BIT ASSIGNMENTS
ADDRESS BYTE 1
CONTROL BYTE
ADDRESS BYTE 0
A
2
A
1
A
0
A
11
A
10
A
9
A
8
A
7
A
0
•
•
•
•
•
•
1
0
1
0
R/W
0
0
0
0
SLAVE
ADDRESS
DEVICE
SELECT
BUS
1999 Microchip Technology Inc.
DS21144D-page 5
This Material Copyrighted by Its Respective Manufacturer
24LC32A
4.2
Page Write
4.0
WRITE OPERATION
The write control byte, word address and the first data
byte are transmitted to the 24LC32A in the same way
as in a byte write. But instead of generating a stop con-
dition, the master transmits up to 32 bytes which are
temporarily stored in the on-chip page buffer and will be
written into memory after the master has transmitted a
stop condition. After receipt of each word, the five lower
address pointer bits are internally incremented by one.
If the master should transmit more than 32 bytes prior
to generating the stop condition, the address counter
will roll over and the previously received data will be
overwritten. As with the byte write operation, once the
stop condition is received, an internal write cycle will
begin. (Figure 4-2).
4.1
Byte Write
Following the start condition from the master, the con-
trol code (four bits), the device select (three bits), and
the R/W bit which is a logic low are clocked onto the bus
by the master transmitter. This indicates to the
addressed slave receiver that a byte with a word
address will follow after it has generated an acknowl-
edge bit during the ninth clock cycle. Therefore, the
next byte transmitted by the master is the high-order
byte of the word address and will be written into the
address pointer of the 24LC32A. The next byte is the
least significant address byte. After receiving another
acknowledge signal from the 24LC32A the master
device will transmit the data word to be written into the
addressed memory location.
Note: Page write operations are limited to writing
bytes within a single physical page, regard-
less of the number of bytes actually being
written. Physical page boundaries start at
addresses that are integer multiples of the
page buffer size (or ‘page size’) and end at
addresses that are integer multiples of
[page size - 1]. If a page write command
attempts to write across a physical page
boundary, the result is that the data wraps
around to the beginning of the current page
(overwriting data previously stored there),
instead of being written to the next page as
might be expected. It is therefore neces-
sary for the application software to prevent
page write operations that would attempt to
cross a page boundary.
The 24LC32A acknowledges again and the master
generates a stop condition. This initiates the internal
write cycle, and during this time the 24LC32A will not
generate acknowledge signals (Figure 4-1).
FIGURE 4-1: BYTE WRITE
S
T
S
BUS ACTIVITY
MASTER
ADDRESS
T
ADDRESS
HIGH BYTE
A
R
T
CONTROL
BYTE
LOW BYTE
DATA
O
P
S
0 0 0 0
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
BUS ACTIVITY
FIGURE 4-2: PAGE WRITE
S
S
T
O
P
T
BUS ACTIVITY
MASTER
A
R
T
CONTROL
BYTE
ADDRESS
HIGH BYTE
ADDRESS
LOW BYTE
DATA BYTE 31
DATA BYTE 0
0 0 0 0
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
A
C
K
BUS ACTIVITY
DS21144D-page 6
1999 Microchip Technology Inc.
This Material Copyrighted by Its Respective Manufacturer
24LC32A
5.0
ACKNOWLEDGE POLLING
6.0
READ OPERATION
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com-
mand has been issued from the master, the device ini-
tiates the internally timed write cycle. Acknowledge
Polling (ACK) can be initiated immediately. This
involves the master sending a start condition followed
by the control byte for a write command (R/W = 0). If the
device is still busy with the write cycle, then NO ACK
will be returned. If the cycle is complete, then the
device will return the ACK and the master can then pro-
ceed with the next read or write command. See
Figure 5-1 for flow diagram.
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random read,
and sequential read.
6.1
Current Address Read
The 24LC32A contains an address counter that main-
tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous access
(either a read or write operation) was to address n (n is
any legal address), the next current address read oper-
ation would access data from address n + 1. Upon
receipt of the slave address with R/W bit set to one, the
24LC32A issues an acknowledge and transmits the
eight bit data word. The master will not acknowledge
the transfer but does generate a stop condition and the
24LC32A discontinues transmission (Figure 6-1).
FIGURE 5-1: ACKNOWLEDGE POLLING
FLOW
Send
Write Command
6.2
Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24LC32A as part of a write operation (R/W bit set to
zero). After the word address is sent, the master gen-
erates a start condition following the acknowledge. This
terminates the write operation, but not before the inter-
nal address pointer is set. Then the master issues the
control byte again but with the R/W bit set to a one. The
24LC32A will then issue an acknowledge and transmit
the 8-bit data word. The master will not acknowledge
the transfer but does generate a stop condition which
causes the 24LC32A to discontinue transmission
(Figure 6-2).
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
NO
Acknowledge
(ACK = 0)?
6.3
Contiguous Addressing Across
Multiple Devices
YES
Next
Operation
The device select bits A2, A1, A0 can be used to
expand the contiguous address space for up to 256K
bits by adding up to eight 24LC32A’s on the same bus.
In this case, software can use A0 of the control byte as
address bit A12, A1 as address bit A13, and A2 as
address bit A14.
1999 Microchip Technology Inc.
DS21144D-page 7
This Material Copyrighted by Its Respective Manufacturer
24LC32A
To provide sequential reads the 24LC32A contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows the entire memory contents to be serially read
during one operation. The internal address pointer will
automatically roll over from address 0FFF to address
000 if the master acknowledges the byte received from
the array address 0FFF.
6.4
Sequential Read
Sequential reads are initiated in the same way as a ran-
dom read except that after the 24LC32A transmits the
first data byte, the master issues an acknowledge as
opposed to the stop condition used in a random read.
This acknowledge directs the 24LC32A to transmit the
next sequentially addressed 8-bit word (Figure 6-3).
Following the final byte transmitted to the master, the
master will NOT generate an acknowledge but will gen-
erate a stop condition.
FIGURE 6-1: CURRENT ADDRESS READ
S
T
A
R
T
S
T
O
P
BUS ACTIVITY
MASTER
CONTROL BYTE
DATA BYTE
SDA LINE
S
P
A
C
K
N
O
BUS ACTIVITY
A
C
K
FIGURE 6-2: RANDOM READ
S
S
T
A
R
T
T
S
T
O
P
BUS ACTIVITY
MASTER
A
R
T
CONTROL
BYTE
ADDRESS
HIGH BYTE
ADDRESS
LOW BYTE
CONTROL
BYTE
DATA
BYTE
0 0 0 0
P
SDA LINE
S
S
A
C
K
A
C
K
A
C
K
A
C
K
N
O
BUS ACTIVITY
A
C
K
FIGURE 6-3: SEQUENTIAL READ
S
T
O
P
BUS ACTIVITY
CONTROL
DATA n
DATA n + 1
DATA n + 2
DATA n + x
MASTER
BYTE
P
SDA LINE
A
C
K
A
C
K
A
C
K
A
C
K
N
O
BUS ACTIVITY
A
C
K
DS21144D-page 8
1999 Microchip Technology Inc.
This Material Copyrighted by Its Respective Manufacturer
24LC32A
7.0
PIN DESCRIPTIONS
8.0
NOISE PROTECTION
The SCL and SDA inputs have filter circuits which sup-
press noise spikes to ensure proper device operation
even on a noisy bus. All I/O lines incorporate Schmitt
triggers for 400 kHz (Fast Mode) compatibility.
7.1
A0, A1, A2 Chip Address Inputs
The A0..A2 inputs are used by the 24LC32A for multi-
ple device operation and conform to the 2-wire bus
standard. The levels applied to these pins define the
address block occupied by the device in the address
map. A particular device is selected by transmitting the
corresponding bits (A2, A1, A0) in the control byte
(Figure 3-3).
9.0
POWER MANAGEMENT
This design incorporates a power standby mode when
the device is not in use and automatically powers off
after the normal termination of any operation when a
stop bit is received and all internal functions are com-
plete. This includes any error conditions, i.e., not
receiving an acknowledge or stop condition per the 2-
wire bus specification. The device also incorporates
VDD monitor circuitry to prevent inadvertent writes
(data corruption) during low-voltage conditions. The
VDD monitor circuitry is powered off when the device is
in standby mode in order to further reduce power con-
sumption.
7.2
SDA Serial Address/Data Input/Output
This is a Bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pullup
resistor to VCC (typical 10KΩ for 100 kHz, 2 KΩ for
400 kHz)
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL HIGH are
reserved for indicating the START and STOP condi-
tions.
7.3
SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
7.4
WP
This pin must be connected to either VSS or VCC.
If tied to VSS, normal memory operation is enabled
(read/write the entire memory 000-FFF).
If tied to VCC, WRITE operations are inhibited. The
entire memory will be write-protected. Read operations
are not affected.
1999 Microchip Technology Inc.
DS21144D-page 9
This Material Copyrighted by Its Respective Manufacturer
24LC32A
NOTES:
DS21144D-page 10
1999 Microchip Technology Inc.
This Material Copyrighted by Its Respective Manufacturer
24LC32A
24LC32A Product Identification System
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.
24LC32A
-
/P
P = Plastic DIP (300 mil Body), 8-lead
Package:
SN = Plastic SOIC (150 mil Body, EIAJ standard), 8-lead
SM = Plastic SOIC (207 mil Body, EIAJ standard), 8-lead
Temperature
Range:
Blank =
0°C to +70°C
I = -40°C to +85°C
32K I2C Serial EEPROM (100 kHz, 400 kHz)
32K I2C Serial EEPROM (Tape and Reel)
Device:
24LC32A
24LC32AT
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
1999 Microchip Technology Inc.
DS21144D-page 11
This Material Copyrighted by Its Respective Manufacturer
WORLDWIDE SALES AND SERVICE
AMERICAS
AMERICAS (continued)
ASIA/PACIFIC (continued)
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Kwai Fong, N.T., Hong Kong
Tel: 852-2-401-1200 Fax: 852-2-401-3431
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
Tel: 770-640-0034 Fax: 770-640-0307
Boston
EUROPE
Microchip Technology Inc.
5 Mount Royal Avenue
Marlborough, MA 01752
Tel: 508-480-9990 Fax: 508-480-8575
Beijing
United Kingdom
Microchip Technology, Beijing
Unit 915, 6 Chaoyangmen Bei Dajie
Dong Erhuan Road, Dongcheng District
New China Hong Kong Manhattan Building
Beijing 100027 PRC
Arizona Microchip Technology Ltd.
505 Eskdale Road
Winnersh Triangle
Wokingham
Berkshire, England RG41 5TU
Tel: 44 118 921 5858 Fax: 44-118 921-5835
Denmark
Microchip Technology Denmark ApS
Regus Business Centre
Lautrup hoj 1-3
Ballerup DK-2750 Denmark
Tel: 45 4420 9895 Fax: 45 4420 9910
Chicago
Microchip Technology Inc.
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 86-10-85282100 Fax: 86-10-85282104
India
Tel: 630-285-0071 Fax: 630-285-0075
Dallas
Microchip Technology Inc.
4570 Westgrove Drive, Suite 160
Addison, TX 75248
Microchip Technology Inc.
India Liaison Office
No. 6, Legacy, Convent Road
Bangalore 560 025, India
Tel: 91-80-229-0061 Fax: 91-80-229-0062
Tel: 972-818-7423 Fax: 972-818-2924
Dayton
Microchip Technology Inc.
Two Prestige Place, Suite 150
Miamisburg, OH 45342
Tel: 937-291-1654 Fax: 937-291-9175
Detroit
Microchip Technology Inc.
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: 248-538-2250 Fax: 248-538-2260
Japan
France
Microchip Technology Intl. Inc.
Benex S-1 6F
Arizona Microchip Technology SARL
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa 222-0033 Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Batiment A - ler Etage
91300 Massy, France
Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Germany
Arizona Microchip Technology GmbH
Gustav-Heinemann-Ring 125
D-81739 München, Germany
Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Korea
Microchip Technology Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea
Tel: 82-2-554-7200 Fax: 82-2-558-5934
Shanghai
Microchip Technology
RM 406 Shanghai Golden Bridge Bldg.
2077 Yan’an Road West, Hong Qiao District
Shanghai, PRC 200335
Italy
Los Angeles
Arizona Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Microchip Technology Inc.
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: 949-263-1888 Fax: 949-263-1338
New York
Microchip Technology Inc.
150 Motor Parkway, Suite 202
Hauppauge, NY 11788
Tel: 631-273-5305 Fax: 631-273-5335
Milan, Italy
Tel: 39-039-65791-1 Fax: 39-039-6899883
Tel: 86-21-6275-5700 Fax: 86 21-6275-5060
11/15/99
San Jose
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950 Fax: 408-436-7955
All rights reserved. © 1999 Microchip Technology Incorporated. Printed in the USA. 11/99
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed
by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products
as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip
logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
1999 Microchip Technology Inc.
This Material Copyrighted by Its Respective Manufacturer
相关型号：
24LC32AT-E/MCG
4K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 2 X 3 MM, 0.90 MM HEIGHT, LEAD FREE, PLASTIC, MO-229, DFN-8
MICROCHIP
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