24C02C/P [ETC]
SERIAL EEPROM|256X8|CMOS|DIP|8PIN|PLASTIC ; 串行EEPROM | 256X8 | CMOS | DIP | 8PIN |塑料\n
| 型号： | 24C02C/P |
| 厂家： | 
ETC |
| 描述： | SERIAL EEPROM|256X8|CMOS|DIP|8PIN|PLASTIC
|
| 文件： | 总13页 (文件大小：179K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
24C02C
2K 5.0V I2C™ Serial EEPROM
FEATURES
PACKAGE TYPES
PDIP/SOIC
• Single supply with operation from 4.5 to 5.5V
• Low power CMOS technology
- 1 mA active current typical
A0
1
8
Vcc
- 10 µA standby current typical at 5.5V
• Organized as a single block of 256 bytes (256 x 8)
• Hardware write protection for upper half of array
• 2-wire serial interface bus, I2C compatible
• 100 kHz and 400 kHz compatibility
A1
A2
2
3
7
6
WP
SCL
Vss
4
5
SDA
• Page-write buffer for up to 16 bytes
• Self-timed write cycle (including auto-erase)
• Fast 1 mS write cycle time for byte or page mode
• Address lines allow up to eight devices on bus
• 1,000,000 erase/write cycles guaranteed
• ESD protection > 4,000V
TSSOP
• Data retention > 200 years
• 8-pin PDIP, SOIC or TSSOP packages
• Available for extended temperature ranges
1
8
A0
A1
VCC
2
7
- Commercial (C):
- Industrial (I):
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
WP
3
4
6
5
A2
VSS
SCL
SDA
- Automotive (E):
DESCRIPTION
The Microchip Technology Inc. 24C02C is a 2K bit
Serial Electrically Erasable PROM with a voltage range
of 4.5V to 5.5V. The device is organized as a single
block of 256 x 8-bit memory with a 2-wire serial inter-
face. Low current design permits operation with typical
standby and active currents of only 10 µA and 1 mA
respectively. The device has a page-write capability for
up to 16 bytes of data and has fast write cycle times of
only 1 mS for both byte and page writes. Functional
address lines allow the connection of up to eight
24C02C devices on the same bus for up to 16K bits of
contiguous EEPROM memory. The device is available
in the standard 8-pin PDIP, 8-pin SOIC (150 mil), and
TSSOP packages.
BLOCK DIAGRAM
WP
A0 A1 A2
HV Generator
I/O
Control
Logic
Memory
Control
Logic
EEPROM
Array
XDEC
SDA
SCL
Vcc
Vss
Write Protect
Circuitry
YDEC
SENSE AMP
R/W CONTROL
I2C is a trademark of Philips Corporation.
1999 Microchip Technology Inc.
DS21202C-page 1
24C02C
TABLE 1-1:
Name
PIN FUNCTION TABLE
Function
1.0
ELECTRICAL
CHARACTERISTICS
1.1
Maximum Ratings*
VSS
SDA
Ground
Serial Data
VCC........................................................................7.0V
All inputs and outputs w.r.t. VSS .....-0.6V to VCC +1.0V
Storage temperature ..........................-65°C to +150°C
Ambient temp. with power applied......-65°C to +125°C
Soldering temperature of leads (10 seconds) ..+300°C
ESD protection on all pins ..................................... ≥ 4 kV
SCL
Serial Clock
VCC
+4.5V to 5.5V Power Supply
Chip Selects
A0, A1, A2
WP
Hardware Write Protect
*Notice: Stresses above those listed under “Maximum ratings” may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is
not implied. Exposure to maximum rating conditions for extended peri-
ods may affect device reliability.
TABLE 1-2:
All parameters apply across the speci-
fied operating ranges unless otherwise Commercial (C):
DC CHARACTERISTICS
VCC = +4.5V to +5.5V
Tamb = 0°C to +70°C
noted.
Industrial (I):
Automotive (E):
Tamb = -40°C to +85°C
Tamb = -40°C to +125°C
Parameter
Symbol
Min.
Max.
Units
Conditions
SCL and SDA pins:
High level input voltage
VIH
VIL
0.7 VCC
—
—
0.3 VCC
—
V
V
Low level input voltage
Hysteresis of Schmitt trigger inputs
Low level output voltage
Input leakage current
VHYS
VOL
0.05 VCC
—
V
(Note)
0.40
10
V
IOL = 3.0 mA, Vcc = 4.5V
VIN = 0.1V to 5.5V, WP = Vss
VOUT = 0.1V to 5.5V
ILI
-10
µA
µA
pF
Output leakage current
ILO
-10
10
CIN, COUT
—
10
VCC = 5.0V (Note)
Tamb = 25°C, f = 1 MHz
Pin capacitance (all inputs/outputs)
ICC Read
ICC Write
ICCS
—
—
—
1
3
mA
mA
µA
VCC = 5.5V, SCL = 400 kHz
VCC = 5.5V
Operating current
Standby current
50
VCC = 5.5V, SDA = SCL = VCC
WP = VSS
Note: This parameter is periodically sampled and not 100% tested.
DS21202C-page 2
1999 Microchip Technology Inc.
24C02C
TABLE 1-3:
AC CHARACTERISTICS
All parameters apply across the specified oper- Vcc = 4.5V to 5.5V
ating ranges unless otherwise noted.
Commercial (C):
Industrial (I):
Automotive (E):
Tamb = 0°C to +70°C
Tamb = -40°C to +85°C
Tamb = -40°C to +125°C
Tamb > +85°C -40°C ≤ Tamb ≤ +85°C
Parameter
Clock frequency
Symbol
Units
Remarks
Min.
Max.
Min.
Max.
FCLK
THIGH
TLOW
TR
—
4000
4700
—
100
—
—
600
1300
—
400
—
kHz
ns
Clock high time
Clock low time
—
—
ns
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
1000
300
—
300
300
—
ns
(Note 1)
(Note 1)
TF
—
—
ns
THD:STA
4000
600
ns
After this period the first
clock pulse is generated
START condition setup time TSU:STA 4700
—
600
—
ns
Only relevant for repeated
START condition
Data input hold time
Data input setup time
STOP condition setup time
Output valid from clock
Bus free time
THD:DAT
TSU:DAT
0
—
—
0
—
—
ns
ns
ns
ns
ns
(Note 2)
250
100
600
—
TSU:STO 4000
—
—
TAA
—
3500
—
900
—
(Note 2)
TBUF
4700
1300
Time the bus must be free
before a new transmission
can start
Output fall time from VIH
minimum to VIL maximum
TOF
TSP
TWR
—
—
250 20 + 0.1 CB
250
50
ns
ns
(Note 1), CB ≤ 100 pF
Input filter spike suppression
(SDA and SCL pins)
50
—
(Note 3)
Write cycle time
Endurance
—
1.5
—
—
1
ms Byte or Page mode
1M
1M
—
cycles 25°C, VCC = 5.0V, Block
Mode (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined TSP and VHYS specifications are due to Schmitt trigger inputs which provide improved noise
spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our website.
FIGURE 1-1: BUS TIMING DATA
THIGH
TF
TR
SCL
TSU:STA
TLOW
THD:DAT
TSU:DAT
TSU:STO
SDA
IN
THD:STA
TSP
TBUF
TAA
SDA
OUT
1999 Microchip Technology Inc.
DS21202C-page 3
24C02C
2.0
PIN DESCRIPTIONS
3.0
FUNCTIONAL DESCRIPTION
The 24C02C supports a bi-directional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCL), controls the bus access, and generates the
START and STOP conditions, while the 24C02C works
as slave. Both master and slave can operate as trans-
mitter or receiver but the master device determines
which mode is activated.
2.1
SDA Serial Data
This is a bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pull-up
resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for
400 kHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi-
tions.
2.2
SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
2.3
A0, A1, A2
The levels on these inputs are compared with the cor-
responding bits in the slave address. The chip is
selected if the compare is true.
Up to eight 24C02C devices may be connected to the
same bus by using different chip select bit combina-
tions. These inputs must be connected to either VCC or
VSS.
2.4
WP
This is the hardware write protect pin. It must be tied to
VCC or VSS. If tied to Vcc, the hardware write protection
is enabled. If the WP pin is tied to Vss the hardware
write protection is disabled.
2.5
Noise Protection
The 24C02C employs a VCC threshold detector circuit
which disables the internal erase/write logic if the VCC
is below 3.8 volts at nominal conditions.
The SCL and SDA inputs have Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.
DS21202C-page 4
1999 Microchip Technology Inc.
24C02C
The data on the line must be changed during the LOW
period of the clock signal. There is one bit of data per
clock pulse.
4.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last six-
teen will be stored when doing a write operation. When
an overwrite does occur it will replace data in a first in
first out fashion.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.1
Both data and clock lines remain HIGH.
4.2 Start Data Transfer (B)
Bus not Busy (A)
4.5
Acknowledge
Each receiving device, when addressed, is required to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
Note: The 24C02C does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
4.3
Stop Data Transfer (C)
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the
master to generate the STOP condition (Figure 4-2).
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
4.4
Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS CHARACTERISTICS
(A)
(B)
(C)
(D)
(C)
(A)
SCL
SDA
START
CONDITION
STOP
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
FIGURE 4-2: ACKNOWLEDGE TIMING
Acknowledge
Bit
1
2
3
4
5
6
7
8
9
1
2
3
SCL
SDA
Data from transmitter
Data from transmitter
Receiver must release the SDA line at this point
so the Transmitter can continue sending data.
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
1999 Microchip Technology Inc.
DS21202C-page 5
24C02C
FIGURE 5-1: CONTROL BYTE FORMAT
5.0
DEVICE ADDRESSING
Read/Write Bit
A control byte is the first byte received following the
start condition from the master device (Figure 5-1). The
control byte consists of a four bit control code; for the
24C02C this is set as 1010 binary for read and write
operations. The next three bits of the control byte are
the chip select bits (A2, A1, A0). The chip select bits
allow the use of up to eight 24C02C devices on the
same bus and are used to select which device is
accessed. The chip select bits in the control byte must
correspond to the logic levels on the corresponding A2,
A1, and A0 pins for the device to respond. These bits
are in effect the three most significant bits of the word
address.
Chip Select
Control Code
Bits
S
1
0
1
0
A2 A1 A0 R/W ACK
Slave Address
Acknowledge Bit
Start Bit
5.1
Contiguous Addressing Across
Multiple Devices
The last bit of the control byte defines the operation to
be performed. When set to a one a read operation is
selected, and when set to a zero a write operation is
selected. Following the start condition, the 24C02C
monitors the SDA bus checking the control byte being
transmitted. Upon receiving a 1010 code and appropri-
ate chip select bits, the slave device outputs an
acknowledge signal on the SDA line. Depending on the
state of the R/W bit, the 24C02C will select a read or
write operation.
The chip select bits A2, A1, A0 can be used to expand
the contiguous address space for up to 16K bits by add-
ing up to eight 24C02C devices on the same bus. In this
case, software can use A0 of the control byte as
address bit A8, A1 as address bit A9, and A2 as
address bit A10. It is not possible to write or read
across device boundaries.
DS21202C-page 6
1999 Microchip Technology Inc.
24C02C
once the stop condition is received an internal write
cycle will begin (Figure 6-2). If an attempt is made to
write to the protected portion of the array when the
hardware write protection has been enabled, the device
will acknowledge the command but no data will be writ-
ten. The write cycle time must be observed even if the
write protection is enabled.
6.0
WRITE OPERATIONS
6.1
Byte Write
Following the start signal from the master, the device
code(4 bits), the chip select bits (3 bits), and the R/W
bit which is a logic low is placed onto the bus by the
master transmitter. The device will acknowledge this
control byte during the ninth clock pulse. The next byte
transmitted by the master is the word address and will
be written into the address pointer of the 24C02C. After
receiving another acknowledge signal from the
24C02C the master device will transmit the data word
to be written into the addressed memory location. The
24C02C acknowledges again and the master gener-
ates a stop condition. This initiates the internal write
cycle, and during this time the 24C02C will not gener-
ate acknowledge signals (Figure 6-1). If an attempt is
made to write to the protected portion of the array when
the hardware write protection has been enabled, the
device will acknowledge the command but no data will
be written. The write cycle time must be observed even
if the write protection is enabled.
Note: Page write operations are limited to writing
bytes within a single physical page, regard-
less of the number of bytes actually being
written. Physical page boundaries start at
addresses that are integer multiples of the
page buffer size (or ‘page size’) and end at
addresses that are integer multiples of
[page size - 1]. If a page write command
attempts to write across a physical page
boundary, the result is that the data wraps
around to the beginning of the current page
(overwriting data previously stored there),
instead of being written to the next page as
might be expected. It is therefore neces-
sary for the application software to prevent
page write operations that would attempt to
cross a page boundary.
6.2
Page Write
The write control byte, word address and the first data
byte are transmitted to the 24C02C in the same way as
in a byte write. But instead of generating a stop condi-
tion, the master transmits up to 15 additional data bytes
to the 24C02C which are temporarily stored in the on-
chip page buffer and will be written into the memory
after the master has transmitted a stop condition. After
the receipt of each word, the four lower order address
pointer bits are internally incremented by one. The
higher order four bits of the word address remains con-
stant. If the master should transmit more than 16 bytes
prior to generating the stop condition, the address
counter will roll over and the previously received data
will be overwritten. As with the byte write operation,
6.3
WRITE PROTECTION
The WP pin must be tied to VCC or VSS. If tied to VCC,
the upper half of the array (080-0FF) will be write pro-
tected. If the WP pin is tied to VSS, then write opera-
tions to all address locations are allowed.
FIGURE 6-1: BYTE WRITE
S
T
A
R
T
S
T
O
P
BUS ACTIVITY
MASTER
CONTROL
BYTE
WORD
ADDRESS
DATA
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
BUS ACTIVITY
FIGURE 6-2: PAGE WRITE
S
T
S
T
O
P
BUS ACTIVITY
MASTER
A
R
T
CONTROL
BYTE
WORD
ADDRESS (n)
DATA n
DATA n +1
DATA n + 15
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
BUS ACTIVITY
1999 Microchip Technology Inc.
DS21202C-page 7
24C02C
FIGURE 7-1: ACKNOWLEDGE POLLING
FLOW
7.0
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com-
mand has been issued from the master, the device ini-
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master send-
ing a start condition followed by the control byte for a
write command (R/W = 0). If the device is still busy with
the write cycle, then no ACK will be returned. If no ACK
is returned, then the start bit and control byte must be
re-sent. If the cycle is complete, then the device will
return the ACK and the master can then proceed with
the next read or write command. See Figure 7-1 for
flow diagram.
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
NO
Acknowledge
(ACK = 0)?
YES
Next
Operation
DS21202C-page 8
1999 Microchip Technology Inc.
24C02C
address is sent, the master generates a start condition
following the acknowledge. This terminates the write
operation, but not before the internal address pointer is
set. Then the master issues the control byte again but
with the R/W bit set to a one. The 24C02C will then
issue an acknowledge and transmits the eight bit data
word. The master will not acknowledge the transfer but
does generate a stop condition and the 24C02C dis-
continues transmission (Figure 8-2). After this com-
mand, the internal address counter will point to the
address location following the one that was just read.
8.0
READ OPERATIONS
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random read,
and sequential read.
8.1
Current Address Read
The 24C02C contains an address counter that main-
tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous read
access was to address n, the next current address read
operation would access data from address n + 1. Upon
receipt of the slave address with the R/W bit set to one,
the 24C02C issues an acknowledge and transmits the
eight bit data word. The master will not acknowledge
the transfer but does generate a stop condition and the
24C02C discontinues transmission (Figure 8-1).
8.3
Sequential Read
Sequential reads are initiated in the same way as a ran-
dom read except that after the 24C02C transmits the
first data byte, the master issues an acknowledge as
opposed to a stop condition in a random read. This
directs the 24C02C to transmit the next sequentially
addressed 8-bit word (Figure 8-3).
To provide sequential reads the 24C02C contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows the entire memory contents to be serially read
during one operation. The internal address pointer will
automatically roll over from address FF to address 00.
8.2
Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24C02C as part of a write operation. After the word
FIGURE 8-1: CURRENT ADDRESS READ
S
T
S
BUS ACTIVITY
MASTER
CONTROL
BYTE
A
R
T
T
DATA
O
P
SDA LINE
P
S
A
C
K
N
O
BUS ACTIVITY
A
C
K
FIGURE 8-2: RANDOM READ
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY
MASTER
CONTROL
BYTE
WORD
ADDRESS (n)
CONTROL
BYTE
DATA (n)
S
P
S
SDA LINE
A
C
K
A
C
K
A
C
K
N
O
BUS ACTIVITY
A
C
K
FIGURE 8-3: SEQUENTIAL READ
S
T
O
P
BUS ACTIVITY
CONTROL
DATA n
DATA n + 1
DATA n + 2
DATA n + X
MASTER
BYTE
P
SDA LINE
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
BUS ACTIVITY
1999 Microchip Technology Inc.
DS21202C-page 9
24C02C
NOTES:
DS21202C-page 10
1999 Microchip Technology Inc.
24C02C
24C02C PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
24C02C /P
—
P = Plastic DIP (300 mil Body), 8-lead
SN = Plastic SOIC, (150 mil Body), 8-lead
ST = TSSOP (4.4 mm Body), 8-lead
Package:
Temperature
Range:
Blank = 0°C to +70°C
I = –40°C to +85°C
E = –40°C to +125°C
24C02C
24C02CT
2K I2C Serial EEPROM
Device:
2K I2C Serial EEPROM (Tape and Reel)
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
1999 Microchip Technology Inc.
DS21202C-page 11
®
Note the following details of the code protection feature on PICmicro MCUs.
•
•
The PICmicro family meets the specifications contained in the Microchip Data Sheet.
Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,
when used in the intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowl-
edge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet.
The person doing so may be engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable”.
•
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of
our product.
If you have any further questions about this matter, please contact the local sales office nearest to you.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical com-
ponents in life support systems is not authorized except with
express written approval by Microchip. No licenses are con-
veyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, FilterLab,
KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER,
PICSTART, PRO MATE, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip Tech-
nology Incorporated in the U.S.A. and other countries.
dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode
and Total Endurance are trademarks of Microchip Technology
Incorporated in the U.S.A.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2002, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
2002 Microchip Technology Inc.
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WORLDWIDE SALES AND SERVICE
Japan
AMERICAS
ASIA/PACIFIC
Microchip Technology Japan K.K.
Benex S-1 6F
3-18-20, Shinyokohama
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Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Corporate Office
Australia
2355 West Chandler Blvd.
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Technical Support: 480-792-7627
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Australia
Tel: 61-2-9868-6733 Fax: 61-2-9868-6755
Korea
Rocky Mountain
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Microchip Technology Korea
168-1, Youngbo Bldg. 3 Floor
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Seoul, Korea 135-882
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Unit 915
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Atlanta
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Far East International Plaza
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Rm. 1315, 13/F, Shenzhen Kerry Centre,
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Denmark
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Lautrup hoj 1-3
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Tri-Atria Office Building
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Parc d’Activite du Moulin de Massy
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New York
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Tel: 631-273-5305 Fax: 631-273-5335
San Jose
Hong Kong
Italy
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
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Unit 901-6, Tower 2, Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 852-2401-1200 Fax: 852-2401-3431
Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
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Toronto
Milan, Italy
Tel: 39-039-65791-1 Fax: 39-039-6899883
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Tel: 905-673-0699 Fax: 905-673-6509
India
Microchip Technology Inc.
India Liaison Office
United Kingdom
Arizona Microchip Technology Ltd.
505 Eskdale Road
Winnersh Triangle
Wokingham
Divyasree Chambers
1 Floor, Wing A (A3/A4)
No. 11, O’Shaugnessey Road
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Tel: 91-80-2290061 Fax: 91-80-2290062
Berkshire, England RG41 5TU
Tel: 44 118 921 5869 Fax: 44-118 921-5820
01/18/02
2002 Microchip Technology Inc.
相关型号：
24C02C/SNVA0
256 X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 0.150 INCH, LEAD FREE, PLASTIC, MS-012, SOIC-8
MICROCHIP
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