16F6144 [ETC]

TRANSISTOR MOSFET D-PAK ; 晶体管MOSFET D- PAK\n


型号：	16F6144
厂家：	ETC
描述：	TRANSISTOR MOSFET D-PAK 晶体管MOSFET D- PAK\n 晶体晶体管
文件：	总10页 (文件大小：254K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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by MTD10N10EL/D

SEMICONDUCTOR TECHNICAL DATA

Motorola Preferred Device

TMOS POWER FET

10 AMPERES

100 VOLTS

N–Channel Enhancement–Mode Silicon Gate

This advanced TMOS E–FET is designed to withstand high

energy in the avalanche and commutation modes. The new energy

efficient design also offers a drain–to–source diode with a fast

recovery time. Designed for low voltage, high speed switching

applications in power supplies, converters and PWM motor

controls, these devices are particularly well suited for bridge circuits

where diode speed and commutating safe operating areas are

critical and offer additional safety margin against unexpected

voltage transients.

= 0.22 OHM

DS(on)

•

Avalanche Energy Specified

Source–to–Drain Diode Recovery Time Comparable to a Discrete

Fast Recovery Diode

•

Diode is Characterized for Use in Bridge Circuits

CASE 369A–13, Style 2

DPAK Surface Mount

and V Specified at Elevated Temperature

DSS

DS(on)

Surface Mount Package Available in 16 mm, 13–inch/2500

Unit Tape & Reel, Add T4 Suffix to Part Number

MAXIMUM RATINGS (T = 25°C unless otherwise noted)

Rating

Symbol

Value

Unit

Drain–to–Source Voltage

100

Vdc

DSS

Drain–to–Gate Voltage (R

= 1.0 MΩ)

Gate–to–Source Voltage — Continuous

DGR

100

±15

±20

Vdc

Vpk

Gate–to–Source Voltage — Non–Repetitive (t ≤ 10 ms)

GSM

Drain Current — Continuous

Drain Current — Continuous @ 100°C

Drain Current — Single Pulse (t ≤ 10 µs)

6.0

Adc

Apk

Total Power Dissipation @ T = 25°C

Derate above 25°C

0.32

1.75

Watts

W/°C

Watts

Total Power Dissipation @ T = 25°C, when mounted to minimum recommended pad size

Operating and Storage Temperature Range

T , T

J stg

–55 to 150

°C

Single Pulse Drain–to–Source Avalanche Energy — Starting T = 25°C

= 25 Vdc, V = 5.0 Vdc, I = 10 Apk, L = 1.0 mH, R =25 Ω)

GS L G

Thermal Resistance — Junction to Case

Thermal Resistance — Junction to Ambient

Thermal Resistance — Junction to Ambient, when mounted to minimum recommended pad size

θJC

θJA

3.13

100

71.4

°C/W

Maximum Temperature for Soldering Purposes, 1/8″ from case for 10 seconds

260

°C

Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit

curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.

E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.

Thermal Clad is a trademark of the Bergquist Company.

Preferred devices are Motorola recommended choices for future use and best overall value.

Motorola TMOS Power MOSFET Transistor Device Data

Motorola, Inc. 1995

ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)

Characteristic

Symbol

Min

Typ

Max

Unit

OFF CHARACTERISTICS

Drain–to–Source Breakdown Voltage

Vdc

(BR)DSS

= 0 Vdc, I = 0.25 mAdc)

100

—

115

—

Temperature Coefficient (Positive)

mV/°C

µAdc

Zero Gate Voltage Drain Current

DSS

= 100 Vdc, V

= 0 Vdc)

= 0 Vdc, T = 125°C)

—

100

Gate–Body Leakage Current (V

= ± 15 Vdc, V

= 0 Vdc)

—

100

nAdc

Vdc

GSS

ON CHARACTERISTICS (1)

Gate Threshold Voltage

GS(th)

= V , I = 250 µAdc)

1.0

—

1.45

4.0

2.0

—

Threshold Temperature Coefficient (Negative)

mV/°C

Ohm

Vdc

Static Drain–to–Source On–Resistance (V

Drain–to–Source On–Voltage

= 5.0 Vdc, I = 5.0 Adc)

—

0.17

0.22

DS(on)

= 5.0 Vdc, I = 10 Adc)

—

1.85

—

2.6

2.3

= 5.0 Vdc, I = 5.0 Adc, T = 125°C)

Forward Transconductance (V

= 15 Vdc, I = 5.0 Adc)

2.5

7.9

—

mhos

DYNAMIC CHARACTERISTICS

Input Capacitance

—

741

175

18.9

1040

250

iss

= 25 Vdc, V = 0 Vdc,

f = 1.0 MHz)

Output Capacitance

oss

Reverse Transfer Capacitance

rss

SWITCHING CHARACTERISTICS (2)

Turn–On Delay Time

—

150

—

d(on)

= 50 Vdc, I = 10 Adc,

Rise Time

= 5.0 Vdc,

Turn–Off Delay Time

Fall Time

d(off)

= 9.1 Ω)

Gate Charge

(See Figure 8)

9.3

2.56

4.4

4.66

= 80 Vdc, I = 10 Adc,

= 5.0 Vdc)

—

SOURCE–DRAIN DIODE CHARACTERISTICS

Forward On–Voltage (1)

Vdc

(I = 10 Adc, V

= 0 Vdc)

= 0 Vdc, T = 125°C)

—

0.98

0.898

1.6

—

Reverse Recovery Time

(See Figure 14)

—

124.7

—

(I = 10 Adc, V

= 0 Vdc,

dI /dt = 100 A/µs)

38.7

0.539

Reverse Recovery Stored Charge

µC

INTERNAL PACKAGE INDUCTANCE

Internal Drain Inductance

(Measured from the drain lead 0.25″ from package to center of die)

—

4.5

7.5

—

Internal Source Inductance

(Measured from the source lead 0.25″ from package to source bond pad)

(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.

(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

TYPICAL ELECTRICAL CHARACTERISTICS

7 V

= 10 V

= 25°C

≥ 5 V

5 V

–55°C

4.5 V

25°C

4 V

= 100°C

3.5 V

3 V

2 V

, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

, GATE–TO–SOURCE VOLTAGE (VOLTS)

Figure 1. On–Region Characteristics

Figure 2. Transfer Characteristics

0.35

0.25

0.15

0.05

0.25

0.2

= 10 V

= 25°C

100°C

= 5 V

= 25°C

10 V

0.15

0.1

–55°C

, DRAIN CURRENT (AMPS)

Figure 3. On–Resistance versus Drain Current

and Temperature

Figure 4. On–Resistance versus Drain Current

and Gate Voltage

100

= 5 V

= 5 A

= 0 V

T = 125°C

1.5

100°C

0.5

–50

–25

100

125

150

100

T , JUNCTION TEMPERATURE (

, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 5. On–Resistance Variation with

Temperature

Figure 6. Drain–To–Source Leakage

Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted

by recognizing that the power MOSFET is charge controlled.

The lengths of various switching intervals (∆t) are deter-

mined by how fast the FET input capacitance can be charged

by current from the generator.

Thecapacitance(C )isreadfromthecapacitancecurveata

iss

voltage corresponding to the off–state condition when calcu-

lating t

and is read at a voltage corresponding to the on–

d(on)

state when calculating t

d(off)

At high switching speeds, parasitic circuit elements com-

plicate the analysis. The inductance of the MOSFET source

lead, inside the package and in the circuit wiring which is

common to both the drain and gate current paths, produces a

voltage at the source which reduces the gate drive current.

The voltage is determined by Ldi/dt, but since di/dt is a func-

tion of drain current, the mathematical solution is complex.

The MOSFET output capacitance also complicates the

mathematics. And finally, MOSFETs have finite internal gate

resistance which effectively adds to the resistance of the

driving source, but the internal resistance is difficult to mea-

sure and, consequently, is not specified.

The resistive switching time variation versus gate resis-

tance (Figure 9) shows how typical switching performance is

affected by the parasitic circuit elements. If the parasitics

were not present, the slope of the curves would maintain a

value of unity regardless of the switching speed. The circuit

used to obtain the data is constructed to minimize common

inductance in the drain and gate circuit loops and is believed

readily achievable with board mounted components. Most

power electronic loads are inductive; the data in the figure is

taken with a resistive load, which approximates an optimally

snubbed inductive load. Power MOSFETs may be safely op-

erated into an inductive load; however, snubbing reduces

switching losses.

The published capacitance data is difficult to use for calculat-

ing rise and fall because drain–gate capacitance varies great-

ly with applied voltage. Accordingly, gate charge data is used.

In most cases, a satisfactory estimate of average input current

) can be made from a rudimentary analysis of the drive

G(AV)

circuit so that

t = Q/I

G(AV)

During the rise and fall time interval when switching a resistive

load, V remains virtually constant at a level known as the

plateau voltage, V

. Therefore, rise and fall times may be

SGP

approximated by the following:

t = Q x R /(V

– V )

GSP

t = Q x R /V

GSP

where

= the gate drive voltage, which varies from zero to V

= the gate drive resistance

and Q and V

GSP

are read from the gate charge curve.

Duringtheturn–onandturn–offdelaytimes, gatecurrentisnot

constant. The simplest calculation uses appropriate values

fromthecapacitancecurvesinastandardequationforvoltage

change in an RC network. The equations are:

= R

In [V

/(V

GG GG

– V

)]

GSP

d(on)

iss

In (V

GG GSP

)

d(off)

iss

1800

1600

1400

1200

= 0 V

T = 25°C

iss

1000

800

iss

rss

600

400

oss

200

rss

GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

1000

100

= 25°C

= 10 A

= 100 V

= 5 V

d(off)

= 25°C

= 10 A

d(on)

, GATE RESISTANCE (OHMS)

100

, TOTAL GATE CHARGE (nC)

Figure 8. Gate–To–Source and Drain–To–Source

Voltage versus Total Charge

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

DRAIN–TO–SOURCE DIODE CHARACTERISTICS

= 0 V

= 25°C

0.5

0.6

0.7

0.8

0.9

1.0

, SOURCE–TO–DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define

the maximum simultaneous drain–to–source voltage and

drain current that a transistor can handle safely when it is for-

ward biased. Curves are based upon maximum peak junc-

able operation, the stored energy from circuit inductance dis-

sipated in the transistor while in avalanche must be less than

the rated limit and adjusted for operating conditions differing

from those specified. Although industry practice is to rate in

terms of energy, avalanche energy capability is not a con-

stant. The energy rating decreases non–linearly with an in-

crease of peak current in avalanche and peak junction

temperature.

tion temperature and a case temperature (T ) of 25°C. Peak

repetitive pulsed power limits are determined by using the

thermal response data in conjunction with the procedures

discussed in AN569, “Transient Thermal Resistance–Gener-

al Data and Its Use.”

Although many E–FETs can withstand the stress of drain–

to–source avalanche at currents up to rated pulsed current

Switching between the off–state and the on–state may tra-

verse any load line provided neither rated peak current (I

)

) is exceeded and the transition time

), the energy rating is specified at rated continuous cur-

nor rated voltage (V

DSS

rent (I ), in accordance with industry custom. The energy rat-

(t ,t ) do not exceed 10 µs. In addition the total power aver-

r f

ing must be derated for temperature as shown in the

accompanying graph (Figure 12). Maximum energy at cur-

aged over a complete switching cycle must not exceed

– T )/(R ).

J(MAX)

θJC

rents below rated continuous I can safely be assumed to

A Power MOSFET designated E–FET can be safely used

in switching circuits with unclamped inductive loads. For reli-

Motorola TMOS Power MOSFET Transistor Device Data

equal the values indicated.

SAFE OPERATING AREA

100

= 20 V

= 10 A

SINGLE PULSE

= 25

°C

10 µs

100 µs

1 ms

10 ms

LIMIT

THERMAL LIMIT

PACKAGE LIMIT

DS(on)

0.1

100

125

150

T , STARTING JUNCTION TEMPERATURE (

, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

Figure 12. Maximum Avalanche Energy versus

Starting Junction Temperature

1.0

D = 0.5

0.2

0.1

(pk)

0.05

0.1

(t) = r(t) R

JC θJC

D CURVES APPLY FOR POWER

PULSE TRAIN SHOWN

READ TIME AT t

0.02

0.01

SINGLE PULSE

– T = P

R (t)

(pk) θJC

J(pk)

DUTY CYCLE, D = t /t

1 2

0.01

0.00001

0.0001

0.001

0.01

t, TIME (ms)

0.1

1.0

Figure 13. Thermal Response

di/dt

TIME

0.25 I

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE

RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS

Surface mount board layout is a critical portion of the total

design. The footprint for the semiconductor packages must be

the correct size to ensure proper solder connection interface

between the board and the package. With the correct pad

geometry, the packages will self align when subjected to a

solder reflow process.

0.165

4.191

0.118

3.0

0.100

2.54

0.063

1.6

0.190

4.826

0.243

6.172

inches

POWER DISSIPATION FOR A SURFACE MOUNT DEVICE

The power dissipation for a surface mount device is a

dissipation can be increased. Although one can almost double

the power dissipation with this method, one will be giving up

area on the printed circuit board which can defeat the purpose

of using surface mount technology. For example, a graph of

function of the drain pad size. These can vary from the

minimum pad size for soldering to a pad size given for

maximum power dissipation. Power dissipation for a surface

mount device is determined by T

junction temperature of the die, R

θJA

, the maximum rated

, the thermal resistance

versus drain pad area is shown in Figure 15.

J(max)

θJA

from the device junction to ambient, and the operating

temperature, T . Using the values provided on the data sheet,

100

Board Material = 0.0625

″

G–10/FR–4, 2 oz Copper

can be calculated as follows:

1.75 Watts

= 25°C

– T

J(max)

θJA

3.0 Watts

The values for the equation are found in the maximum

ratings table on the data sheet. Substituting these values into

the equation for an ambient temperature T of 25°C, one can

calculate the power dissipation of the device. For a DPAK

device, P is calculated as follows.

5.0 Watts

A, AREA (SQUARE INCHES)

150°C – 25°C

= 1.75 Watts

71.4°C/W

Figure 15. Thermal Resistance versus Drain Pad

Area for the DPAK Package (Typical)

The 71.4°C/W for the DPAK package assumes the use of

the recommended footprint on a glass epoxy printed circuit

board to achieve a power dissipation of 1.75 Watts. There are

other alternatives to achieving higher power dissipation from

thesurfacemountpackages. Oneistoincreasetheareaofthe

drain pad. By increasing the area of the drain pad, the power

Another alternative would be to use a ceramic substrate or

an aluminum core board such as Thermal Clad . Using a

board material such as Thermal Clad, an aluminum core

board, the power dissipation can be doubled using the same

footprint.

Motorola TMOS Power MOSFET Transistor Device Data

SOLDER STENCIL GUIDELINES

Prior to placing surface mount components onto a printed

packages. The pattern of the opening in the stencil for the

drain pad is not critical as long as it allows approximately 50%

of the pad to be covered with paste.

circuit board, solder paste must be applied to the pads. Solder

stencils are used to screen the optimum amount. These

stencils are typically 0.008 inches thick and may be made of

brass or stainless steel. For packages such as the SC–59,

SC–70/SOT–323, SOD–123, SOT–23, SOT–143, SOT–223,

SO–8, SO–14, SO–16, and SMB/SMC diode packages, the

stencil opening should be the same as the pad size or a 1:1

SOLDER PASTE

OPENINGS

registration. This is not the case with the DPAK and D PAK

packages. If one uses a 1:1 opening to screen solder onto the

drain pad, misalignment and/or “tombstoning” may occur due

to an excess of solder. For these two packages, the opening

in the stencil for the paste should be approximately 50% of the

tab area. The opening for the leads is still a 1:1 registration.

STENCIL

Figure 16. Typical Stencil for DPAK and

D PAK Packages

Figure 16 shows a typical stencil for the DPAK and D PAK

SOLDERING PRECAUTIONS

The melting temperature of solder is higher than the rated

temperature of the device. When the entire device is heated

to a high temperature, failure to complete soldering within a

short time could result in device failure. Therefore, the

following items should always be observed in order to

minimize the thermal stress to which the devices are

subjected.

• When shifting from preheating to soldering, the maximum

temperature gradient shall be 5°C or less.

• After soldering has been completed, the device should be

allowed to cool naturally for at least three minutes.

Gradual cooling should be used as the use of forced

cooling will increase the temperature gradient and result

in latent failure due to mechanical stress.

• Always preheat the device.

• The delta temperature between the preheat and soldering

should be 100°C or less.*

• Mechanical stress or shock should not be applied during

cooling.

• When preheating and soldering, the temperature of the

leads and the case must not exceed the maximum

temperature ratings as shown on the data sheet. When

using infrared heating with the reflow soldering method,

the difference shall be a maximum of 10°C.

* Soldering a device without preheating can cause excessive

thermal shock and stress which can result in damage to the

device.

* Due to shadowing and the inability to set the wave height to

• The soldering temperature and time shall not exceed

260°C for more than 10 seconds.

incorporate other surface mount components, the D PAK is

not recommended for wave soldering.

Motorola TMOS Power MOSFET Transistor Device Data

TYPICAL SOLDER HEATING PROFILE

For any given circuit board, there will be a group of control

line on the graph shows the actual temperature that might be

experienced on the surface of a test board at or near a central

solder joint. The two profiles are based on a high density and

a low density board. The Vitronics SMD310 convection/in-

frared reflow soldering system was used to generate this

profile. The type of solder used was 62/36/2 Tin Lead Silver

with a melting point between 177–189°C. When this type of

furnace is used for solder reflow work, the circuit boards and

solder joints tend to heat first. The components on the board

are then heated by conduction. The circuit board, because it

has a large surface area, absorbs the thermal energy more

efficiently, then distributes this energy to the components.

Because of this effect, the main body of a component may be

up to 30 degrees cooler than the adjacent solder joints.

settings that will give the desired heat pattern. The operator

must set temperatures for several heating zones, and a figure

for belt speed. Taken together, these control settings make up

a heating “profile” for that particular circuit board. On

machines controlled by a computer, the computer remembers

these profiles from one operating session to the next. Figure

17 shows a typical heating profile for use when soldering a

surface mount device to a printed circuit board. This profile will

vary among soldering systems but it is a good starting point.

Factors that can affect the profile include the type of soldering

system in use, density and types of components on the board,

typeofsolderused, andthetypeofboardorsubstratematerial

being used. This profile shows temperature versus time. The

STEP 5

HEATING

ZONES 4 & 7

“SPIKE”

STEP 6

VENT

STEP 7

COOLING

STEP 1

PREHEAT

ZONE 1

“RAMP”

STEP 4

HEATING

ZONES 3 & 6

“SOAK”

STEP 2

VENT

“SOAK” ZONES 2 & 5

“RAMP”

STEP 3

HEATING

205

PEAK AT

SOLDER JOINT

° TO 219°C

200

170°C

DESIRED CURVE FOR HIGH

MASS ASSEMBLIES

160°C

150°C

150°

SOLDER IS LIQUID FOR

40 TO 80 SECONDS

(DEPENDING ON

100°C

140°C

MASS OF ASSEMBLY)

100

DESIRED CURVE FOR LOW

MASS ASSEMBLIES

50°

TIME (3 TO 7 MINUTES TOTAL)

MAX

Figure 17. Typical Solder Heating Profile

Motorola TMOS Power MOSFET Transistor Device Data

PACKAGE DIMENSIONS

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

SEATING

PLANE

–T–

2. CONTROLLING DIMENSION: INCH.

INCHES

MILLIMETERS

DIM

MIN

MAX

0.250

0.265

0.094

0.035

0.040

0.047

MIN

5.97

6.35

2.19

0.69

0.84

0.94

MAX

6.35

6.73

2.38

0.88

1.01

1.19

0.235

0.250

0.086

0.027

0.033

0.037

0.180 BSC

4.58 BSC

0.034

0.018

0.102

0.040

0.023

0.114

0.87

0.46

2.60

1.01

0.58

2.89

0.090 BSC

2.29 BSC

0.175

0.020

0.030

0.138

0.215

0.050

–––

0.050

–––

4.45

0.51

0.77

3.51

5.46

1.27

–––

1.27

–––

STYLE 2:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

D 2 PL

0.13 (0.005)

CASE 369A–13

ISSUE W

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,

andspecifically disclaims any and all liability, includingwithoutlimitationconsequentialorincidentaldamages. “Typical” parameters can and do vary in different

applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does

not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in

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associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.

Motorola and

are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

Literature Distribution Centers:

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ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.

Motorola TMOS Power MOSFET Transistor Device Data

MTD10N10EL/D

◊

16F6144 [ETC]

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