020-2954-XX [ETC]
DDR Memory Bus Electrical Validation and Analysis Software; DDR存储器总线的电气验证和分析软件
| 型号： | 020-2954-XX |
| 厂家： | 
ETC |
| 描述： | DDR Memory Bus Electrical Validation and Analysis Software |
| 文件： | 总8页 (文件大小：693K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DDR Memory Bus Electrical Validation and Analysis
Software
Applications
DDR1
DDR2
DDR3
LPDDR
LPDDR2
GDDR5
Option DDRA accelerates the analysis, validation, and conformance testing
of memory systems based on JEDEC Test Recommendations.
A single license of DDRA provides support for multiple generations of the
JEDEC DDR Standard; beginning with DDR1, DDR2, DDR3, while including
DDR derivatives LPDDR, LPDDR2, and GDDR5. Option DDRA supports
the common data rates in these standards alongside custom data rates up
to and beyond 2133 MT/s. Whether you are doing intensive signal integrity
analysis or debugging a specific memory transaction, DDRA will speed
your ability to trigger on and identify read and write bursts in the acquired
Features & Benefits
data record and then perform parametric measurements on the signals of
interest.
Auto-configuration Wizard Guides Easy Setup and Test Configuration
Analyze All Read/Write Bursts in the Entire Acquisition
Plot DQS and DQ Eye Diagrams for Reads and Writes
Perform JEDEC Conformance Tests with Pass/Fail Limits
Use Chip Select to Qualify Multi-rank Measurements
DDRA Wizard for Easy Test Selection and
Configuration
The wizard consolidates Tektronix experience and expertise in DDR testing
into a simple, easy-to-follow test selection interface. The user selects which
DDR technology, speed grade, and measurement group (reads, writes,
clocks, address, and control lines) they are testing, using check boxes to
select some or all measurements in a category. DDRA can then automate
oscilloscope scale selection, DQ and DQS level selections, and threshold
detection, then automate burst identification using search and mark. Search
and mark (for read/write measurements) data is used to identify and
separate all read vs. write bursts across the entire acquisition and qualify
measurement zones for use by DPOJET Advanced Jitter and Eye Analysis.
DPOJET will generate an eye diagram of the data and perform JEDEC
standard measurements qualified on read or write bursts. Measurement
configurations and JEDEC pass/fail limits are automatically applied for the
selected measurements. Every edge in each identified burst is measured,
then measurement results are included in statistics and plots for a complete
analysis of the acquired waveform.
Navigate and Time Stamp Reads and Writes in an Acquired Record
using Search and Mark
Use Pinpoint Triggering, Visual Trigger, and DPX to Quickly Identify
Infrequent Anomalies
Easily Move between Conformance-test and Analysis/Debug Tools
Automatically Produce Consolidated Reports with Pass/Fail Information,
Statistical Measurement Results, and Test-setup Information
On MSO70000, Use Address/Command Bus to Precisely Qualify Read
and Write Bursts or Other Events
On MSO70000, Perform Bus Timing Measurements on the
Address/Command Bus
Datasheet
feature now adds additional tools for setting precise trigger conditions to
capture specific bit patterns or other waveform events, based on keep-in
and keep-out areas.
JEDEC Measurements Supported for DDR3
Write Bursts
Data Eye Width
Data Eye Height
Differential DQS
InputSlew-Diff-Fall(DQS)
InputSlew-Diff-Rise(DQS)
tDH-Diff(base)
Clock(Diff)
tCH(abs)
tCH(avg)
tCK(abs)
tCK(avg)
tCL(abs)
tCL(avg)
tDVAC(CK)
tERR
Vix(ac)DQS
VSEH(AC)DQS#
VSEH(AC)DQS
VSEH(DQS#)
VSEH(DQS)
DDR Analysis Menu
JEDEC-conforming Measurements and Conformance Testing
DDR Specification Conformance
VSEL(AC)DQS#
VSEL(AC)DQS
VSEL(DQS#)
VSEL(DQS)
DDR
JESD79E (May 2005)
DDR2
JESD79-2F (November 2009)
JESD79-3D (July 2010)
JESD209A (February 2009)
JESD209-2E (April 2011)
JESD212 (December 2009)
tDH-Diff(derated)
tDQSH
DDR3
LPDDR
LPDDR2
GDDR5
tDQSL
tJIT(cc)
DQS (Single Ended,
Read)
AC-OvershootArea(DQ)
AC-UndershootArea(DQ)
AC-Overshoot(DQ)
tDQSS-Diff
tDS-Diff(base)
tDS-Diff(derated)
tDSH-Diff
tJIT(duty)
tJIT(per)
Clock(Single Ended)
AC-Overshoot(CK#)
AC-Overshoot(CK)
Comprehensive Measurements for JEDEC
Conformance Testing
AC-Undershoot(DQ)
tDSS-Diff
AC-OvershootArea(DQS)
Option DDRA adds a long list of JEDEC-specific measurements to the
rich toolset of generic jitter, timing, and signal-quality measurements
already present in DPOJET. In addition to the measurements shown below
(for DDR3 in this example), Option DDRA also covers other application
standards like DDR1, DDR2, LPDDR, LPDDR3, and GDDR5. DDRA also
performs de-rating of Setup and Hold pass/fail limits based on the result
of slew rate measurements, as stipulated by JEDEC in the test specs for
DDR2 and DDR3 (JESD79-2F, JESD79-3D as of this writing).
tDVAC(DQS)
AC-OvershootArea(CK#) AC-UndershootArea(DQS)
Single Ended DQS
tDIPW-SE
AC-OvershootArea(CK)
AC-Undershoot(CK#)
AC-Undershoot(CK)
AC-Overshoot(DQS)
AC-Undershoot(DQS)
AC-OvershootArea(DQS#)
tDQSS-SE
tDSH-SE
AC-UndershootArea(CK#) AC-UndershootArea(DQS#)
tDSS-SE
AC-UndershootArea(CK)
Vix(ac)CK
AC-Overshoot(DQS#)
AC-Undershoot(DQS#)
Precharge
Slew Rate DQ
Slew Rate-Hold-Rise(DQ)
Slew Rate-Hold-Fall(DQ)
VSEH(AC)CK#
VSEH(AC)CK
VSEH(CK#)
tRP(ACT)
Easily Switch between Conformance Testing
and Advanced Debug Tools
Slew
tRP(MRS)
Rate-Setup-Rise(DQ)
Slew Rate-Setup-Fall(DQ)
VSEH(CK)
Address/Command
Measurements
DDRA gives you the option to easily switch between conformance testing
and advanced analysis and debug modes. The power of the DPOJET
analysis engine allows you flexibility to reconfigure existing measurements
or add new measurements not specifically required by JEDEC and to create
new user-specified test limits. You can also use features like logging, filters,
histograms, and time trends in addition to the information produced by the
DDRA wizard.
tWPRE
VSEL(AC)CK#
VSEL(AC)CK
AC-Overshoot
AC-OvershootArea
AC-Undershoot
tWPST
Read Bursts
Data Eye Width
Data Eye Height
Differential DQS
SRQdiff-Fall(DQS)
VSEL(CK#)
VSEL(CK)
AC-UndershootArea
InputSlew-Diff-Fall(CK)
InputSlew-Diff-Rise(CK)
DQS(Single Ended)
AC-OvershootArea(DQ)
AC-UndershootArea(DQ)
Slew
Rate-Hold-Fall(Addr/Cmd)
Fast Fault Identification using Pinpoint®
Triggers and DPX Technology
SRQdiff-Rise(DQS)
tDQSCK-Diff
AC-Overshoot(DQ)
AC-Undershoot(DQ)tDSH
AC-Overshoot(DQS#)
Slew
Rate-Hold-Rise(Addr/Cmd)
Slew
In addition to all of the measurement and analysis tools that DDRA offers,
you can use Pinpoint® triggering and DPX® to find infrequent signal events.
Pinpoint® triggering allows you to trigger on reads or writes so that only
relevant bursts can be shown. Once you have set the hardware triggering
on a read or write condition, you can use DPX®, the industry’s highest
waveform acquisition rate for signal integrity testing and to determine
specific DDR read/write signal characteristics. DPX® enables quick
identification of infrequent events by using a color-graded display to see
both frequent and infrequent waveform events, such as areas where there
is bus contention, reflections, or system timing issues. New Visual Trigger
Rate-Setup-Fall(Addr/Cmd)
tDQSQ-Diff
Slew
Rate-Setup-Rise(Addr/Cmd)
tQH
tDVAC(DQS)
SRQdiff-Fall(CK)
SRQdiff-Rise(CK)
tRPRE
AC-Overshoot(DQS)
AC-OvershootArea(DQS#)
AC-OvershootArea(DQS)
AC-Undershoot(DQS#)
AC-Undershoot(DQS)
tIH(base)
tIH(derated)
tIPW-High
tIPW-Low
tIS(base)
tPST
AC-UndershootArea(DQS#)
AC-UndershootArea(DQS)
tIS(derated)
2
www.tektronix.com
DDR Memory Bus Electrical Validation and Analysis Software
Additional Capabilities using a Performance
MSO (Mixed-Signal Oscilloscope)
Full Bus Analysis using Logic Analyzer and
Oscilloscope
The MSO70000 Series Performance MSOs allow you to probe more signals
on the DDR bus and to trigger on and view specific bus events. Up to 16
digital channels can be used to view logic states of command and address
signals such as RAS, CAS, WE, CE, CS, etc. Signal integrity of these
16 inputs can be analyzed using the iCapture™ multiplexing feature, which
allows any of the digital input signals to be internally routed to one of the
scope’s four analog channels. Measurements involving command-bus cycle
timing can also be analyzed using the bus-decode features of the MSO
and DDRA software.
When full protocol analysis or probing of the entire memory bus is required,
a logic analyzer can provide this additional capability. The TLA7000 Series
logic analyzers can also be linked with Tektronix oscilloscopes to provide
an integrated test setup using tools such as iCapture mentioned above.
This eliminates the need for double probing and allows full analog capture
of any signals probed by the logic analyzer. In addition, the iView™ display
interface allows transfer of the oscilloscope data to the logic analyzer
display, so that data from both instruments are analyzed and time-aligned
on one display screen.
Characteristics
Bandwidth Recommendations for Each DDR Standard
DDR Type
Maximum Data
Rate (JEDEC)
Clock Rate
5th Harmonic
of Clock
Max SE Slew
Rate (JEDEC)
Typical Signal
Swing
Oscilloscope
Rise Time
10% - 90%*1
Recommended
Oscilloscope
BW*2
DDR
400 MT/s
800 MT/s
2133 MT/s
5 GT/s
200 MHz
400 MHz
1066 MHz
2.5 GHz
1 GHz
2 GHz
5 V/ns
5 V/ns
5 V/ns
N/A
1.8 V
1.25 V
1.0 V
0.8 V
89 ps
62 ps
49 ps
18 ps
4 GHz
6 GHz
DDR2
DDR3
GDDR5
5.3 GHz
12.5 GHz
8 GHz
20 GHz*3
*1 For 3% maximum error on rise-time measurement.
*2 For less stringent applications, a one-step reduction in scope bandwidth may be acceptable.
*3 Based on 5 GT/s system; lower BW scope may suffice for lower data rates.
Ordering Information
To upgrade an existing DPO5000, MSO5000, DPO7000,
DPO70000, DSA70000, or MSO70000 Series:
DDRA
Order
Description
DDR Memory Bus Electrical Validation and Analysis Oscilloscope Software.
DPO-UP DDRA
Upgrade to Option DDRA (requires Opt. ASM and
DJA)
To order on a new DPO5000, MSO5000, DPO7000, DPO70000,
DSA70000*4, or MSO70000 Series:
DPO-UP DJAE
DPO-UP DJAM
DPO-UP DJAH
Upgrade MSO/DPO5000 Series with DPOJET Jitter
and Eye Diagram Analysis (Opt. DJA)
Upgrade DPO7000 with DPOJET Jitter and Eye
Diagram Analysis (Opt. DJA)
Upgrade DPO70404 - DPO70804 or MSO70404 -
MSO70804 with DPOJET Jitter and Eye Diagram
Analysis (Opt. DJA)
Upgrade DPO71254 - DPO73304 or MSO71254 -
MSO72004 with DPOJET Jitter and Eye Diagram
Analysis (Opt. DJA)
Order
Description
Opt. DDRA
Preinstall on a new DPO5000*5, MSO5000*5,
DPO7000*5, DPO70000*5, DSA70000, or
MSO70000*5 Series oscilloscope
DPOFL-DDRA
DDR Memory Technology Analysis Package –
Floating License
DPO-UP DJAU
DPO-UP DJUP
*4 Note: Opt. DJA and ASM are standard on the DSA70000 Series oscilloscopes.
*5 Note: Opt. ASM (Advanced Event Search and Mark) and Opt. DJA (DPOJET) are required.
DJA DPOJET software for scopes with both
TDSJIT3 and TDSRTE licenses
Note: Software is supplied on the internal hard drive of the DPO5000, MSO5000, DPO7000, DPO70000,
DSA70000, and MSO70000 Series oscilloscopes. User documentation (online or user manual) is part of the
oscilloscope documentation.
To order a floating license for an existing DPO5000, MSO5000,
DPO7000, DPO70000, DSA70000, or MSO70000 Series:
Order
Description
DPOFL-DDRA
DDR Memory Technology Analysis Package –
Floating License
DPOFL-DJA
DPOJET Jitter and Eye Diagram Analysis – Floating
License
www.tektronix.com
3
Datasheet
Recommended Accessories
Order
Description
P7500 Series
020-2955-xx
020-3022-xx
020-2954-xx
P6780
TriMode™ Differential Probe
Micro-coax Tips (TriMode) for P7500 Probes
Micro-coax Tips (TriMode) for P7500 Probes*6
Socket Cable for P7500 Probes
Differential Logic Probe for MSO70000
TDP3500
Differential Probe for MSO/DPO5000 and
DPO7000 Series Oscilloscopes
Recommended Nexus Technology Accessories
NEX-DDR3MP78BSC
NEX-DDR3MP78BSCSK
NEX-DDR3MP96BSC
NEX-DDR3MP96BSCSK
NEX-DDR2MP60BSC
NEX-DDR2MP60BSCSK
NEX-DDR2MP84BSC
NEX-DDR2MP84BSCSK
BGA Interposer for DDR3 x4/x8-solder Version
BGA Interposer for DDR3 x4/x8-socket Version
BGA Interposer for DDR3 x16-solder Version
BGA Interposer for DDR3 x16-socket Version
BGA Interposer for DDR2 x4/x8-solder Version
BGA Interposer for DDR2 x4/x8-socket Version
BGA Interposer for DDR2 x16-solder Version
BGA Interposer for DDR2 x16-socket Version
P7500 Series TriMode™ probe.
Note: For more detailed information contact http://www.nexustechnology.com
*6 For use with BGA Interposers only.
BGA Interposer probing solution for DDR2/DDR3
TLA7000 Series logic analyzer and Logic Probes Connection to the oscilloscope
through Analog Mux. See www.tektronix.com/logic_analyzers
020-2955-xx Micro-Coax tips soldered to DIMM.
Tektronix is registered to ISO 9001 and ISO 14001 by SRI Quality System Registrar.
Product(s) complies with IEEE Standard 488.1-1987, RS-232-C, and with Tektronix
Standard Codes and Formats.
4
www.tektronix.com
DDR Memory Bus Electrical Validation and Analysis Software
www.tektronix.com
5
Datasheet
6
www.tektronix.com
DDR Memory Bus Electrical Validation and Analysis Software
www.tektronix.com
7
Contact Tektronix:
ASEAN / Australasia (65) 6356 3900
Austria 00800 2255 4835*
Datasheet
Balkans, Israel, South Africa and other ISE Countries +41 52 675 3777
Belgium 00800 2255 4835*
Brazil +55 (11) 3759 7627
Canada 1 800 833 9200
Central East Europe and the Baltics +41 52 675 3777
Central Europe & Greece +41 52 675 3777
Denmark +45 80 88 1401
Finland +41 52 675 3777
France 00800 2255 4835*
Germany 00800 2255 4835*
Hong Kong 400 820 5835
India 000 800 650 1835
Italy 00800 2255 4835*
Japan 81 (3) 6714 3010
Luxembourg +41 52 675 3777
Mexico, Central/South America & Caribbean 52 (55) 56 04 50 90
Middle East, Asia, and North Africa +41 52 675 3777
The Netherlands 00800 2255 4835*
Norway 800 16098
People’s Republic of China 400 820 5835
Poland +41 52 675 3777
Portugal 80 08 12370
Republic of Korea 001 800 8255 2835
Russia & CIS +7 (495) 7484900
South Africa +41 52 675 3777
Spain 00800 2255 4835*
Sweden 00800 2255 4835*
Switzerland 00800 2255 4835*
Taiwan 886 (2) 2722 9622
United Kingdom & Ireland 00800 2255 4835*
USA 1 800 833 9200
* European toll-free number. If not accessible, call: +41 52 675 3777
Updated 10 February 2011
For Further Information. Tektronix maintains a comprehensive, constantly expanding
collection of application notes, technical briefs and other resources to help engineers working
on the cutting edge of technology. Please visit www.tektronix.com
Copyright © Tektronix, Inc. All rights reserved. Tektronix products are covered by U.S. and foreign patents,
issued and pending. Information in this publication supersedes that in all previously published material.
Specification and price change privileges reserved. TEKTRONIX and TEK are registered trademarks of
Tektronix, Inc. All other trade names referenced are the service marks, trademarks, or registered trademarks
of their respective companies.
28 Jun 2012
55W-22329-7
www.tektronix.com
相关型号：
020-3%-FA3-90PPM-CARDPACK
Fixed Resistor, Wire Wound, 3W, 0.02ohm, 130V, 3% +/-Tol, -90,90ppm/Cel,
VISHAY
©2020 ICPDF网 联系我们和版权申明