MCDP2800-BBT [ETC]
DisplayPort1.2a to HDMI2.0 Level Shifter/Protocol Converter;
| 型号： | MCDP2800-BBT |
| 厂家： | 
ETC |
| 描述： | DisplayPort1.2a to HDMI2.0 Level Shifter/Protocol Converter |
| 文件： | 总33页 (文件大小：598K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MCDP28x0
DisplayPort1.2a to HDMI2.0
Level Shifter/Protocol Converter
[LSPCON]
Datasheet
Rev B
MegaChips’ Proprietary Information
MegaChips reserves the right to make any change herein at any time without prior notice. MegaChips
does not assume any responsibility or liability arising out of application or use of any product or
service described herein except as explicitly agreed upon.
MegaChips’ Proprietary Information
Page 1 of 33
MCDP28x0
– All other 3D formats forwarded as is
Features
•
Audio forwarding
•
DisplayPort® (DP) ver. 1.2a receiver
– Link rate HBR2/HBR/RBR
– 2-ch, 768 kHz 24bps HBR audio
– Up to 8-ch, 192 kHz, 24bps LPCM audio,
AC3, DTS
– 1, 2, or 4 lanes configuration
– AUX CH 1 Mbps, HPD out
•
•
Secure communication
– Supports eDP ASSR scrambler operation
– Intel secure communication protocol
compliant with LSPCON spec
•
HDMI ver. 2.0 transmitter
– Max data rate up to 6.0 Gbps/ch
– Deep color up to 16 bits per color
– 3D video timings, CEC, HPD in
– Supports High Dynamic Range (HDR)
HDCP content protection
– Embedded HDCP keys
– HDCP2.2 transmitter
– HDCP1.x repeater
– Supports scrambling for the higher data
rate
•
Metadata handling
– HDMI TX DVI/HDMI mode setting (DPCD
register)
•
Level shifter operation (up to 3.4Gbps/ch)
– AC-coupled HDMI1.4b to DC-coupled
HDMI1.4b
– YCbCr444-420 conversion (DPCD register)
– IEC60958 BYTE3 channel status overwrite
– CEA861F INFOFRAME generation
– PHY analog repeater (re-driver or re-timer)
– 3.3 V DDC/AUX CH signaling support with
auto detect
– CEA861-3 HDR and Mastering InfoFrame
•
•
SCDC read request handling
– 3.3 V DDC to 5V DDC buffering
– Polling enabled for HDMI sinks not
supporting read request
– I2C-over-AUX to 5V DDC translation
– DP HPD_OUT matched to HDMI HPD_IN
AUX to I2C bridge for EDID/MCCS pass
through
•
Protocol converter operation (up to 6.0
Gbps/ch)
•
•
CEC tunneling over AUX CH
Device configuration options
– DP SST-to-HDMI format conversion
– Video and audio forwarding
– SPI flash for firmware binary image storage
required
– Pixel encoding format conversion from
YCbCr444 to YCbCr420
– AUX CH, I2C host interface (optional)
– Horizontal expansion of VESA CVT to
CEA-861 timings
•
•
EMI reduction support
– Meta data handing
– Spread spectrum for DP input
•
•
Level shifter – Protocol converter mode
switching
– Scrambler for DP input and HDMI2.0a
output
– Via sideband communication (AUX CH/
DDC)
Low power operation
– 412 mW in protocol converter mode
– 100 mW in Level shifter mode
– 0.1 mW in connected standby mode
Max video resolution and color depth
– 4Kp60Hz, RGB/YCbCr444, 8bpc
– 4Kp60Hz, YCbCr420, up to 16bpc
– 4Kp30Hz, RGB/YCbCr444, up to 16bpc
•
•
•
ESD specification
– +/-6.5 KV HBM, 500 V CDM
•
•
YCbCr420 support
Package
– YCbCr444-to-420 conversion, up to 16 bpc
– YCbCr420 pass through, up to 16 bpc
– 64 LFBGA (7 x 7 mm)
Power supply voltages
– 3.3 V I/O; 1.2 V core
Stereoscopic 3D forwarding
– Conversion from frame sequential over DP
to stacked top-bottom 3D over HDMI
C28x0-DAT-01p
MegaChips’ Proprietary Information
Page 2 of 33
MCDP28x0
Applications
•
•
PC notebook/ tablet motherboard
DP/USB Type-C docking station, dongle
Figure 1. MCDP28x0 internal block diagram
HPD Out
3.3V Tol
HPD In
HPD 5V SAFE
(3.3V IO)
HPD 5V SAFE
(3.3V IO)
From OCM
To OCM
5V Tol
I2C bypass path
HDMI DDC
5V Tol
AUX, AC 3.3V
I2C DC 3.3V
I2C Level
Shifter
AUX/I2C
Detector
To / From OCM
AUX to I2C
Converter
Protocol converter path
HDMI 2.0
Output
Analog repeater path
DP++ Input
DP Dual Mode
Receiver
HDMI Transmitter
1.2V AC,
5.4Gbps
DP to HDMI
AV Format Converter
HDCP RX/ TX/Repeater
Protocol converter path
DC, 3.3V, 6Gbps
UART_RX
UART_TX
SCL
XTAL
TCLK
UART
Clock
Generation
VDD12_ON
VDD12_ON
OCM
V186
CEC
CEC
I2C Slave
RESETN
Reset
SDA
SPI_CLK
SPI_DI
SPI_DO
SPI_CSN
CONFIG
GPIO
GPIO
SPI Controller
C28x0-DAT-01p
MegaChips’ Proprietary Information – Strictly Confidential
Page 3 of 33
MCDP28x0
Contents
1.
2.
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Application overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1
2.2
Motherboard-down topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Adaptor topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.
4.
BGA footprint and pin lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1
3.2
Ball grid array diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Signal mapping sorted by ball (pin) number . . . . . . . . . . . . . . . . . . . . . . . 12
Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.1
4.2
4.3
Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Bootstrap configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
RESETN connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.
6.
Package specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1
5.2
5.3
5.4
Package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
LFBGA 7 x 7 dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Marking field template and descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Classification reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1
6.2
6.3
6.4
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Power Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.4.1
6.4.2
6.4.3
6.4.4
DisplayPort receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
HDMI transmitter I/O specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
I2C interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
SPI interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.
8.
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
C28x0-DAT-01p
MegaChips’ Proprietary Information
Page 4 of 33
MCDP28x0
List of Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
DisplayPort receiver pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
HDMI output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
System interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power and ground pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Bootstrap configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Field descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
IO DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Maximum speed of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DisplayPort receiver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
HDMI transmitter I/O specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
HDMI transmitter AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
I2C interface timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
SPI interface timing, VDD = 3.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
C28x0-DAT-01p
MegaChips’ Proprietary Information
Page 5 of 33
MCDP28x0
List of Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
MCDP28x0 internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
MCDP2800 motherboard-down use case. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
MCDP2850 adaptor (dongle) use case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
MCDP28x0 BGA diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
RESETN Connection to MCDP28x0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
MCDP28x0 package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
MCDP28x0 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Marking template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
I2C timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
C28x0-DAT-01p
MegaChips’ Proprietary Information
Page 6 of 33
MCDP28x0
1. Description
The MCDP28x0 is a power-optimized DisplayPort1.2a-to-HDMI 2.0 converter device targeted for
desktop/mobile PC motherboard-down applications and for DP or USB type-C adaptor (dongle, docking
station) applications. This device functions as a level shifter as well as an active protocol converter.
In level shifter mode, the device functions as a PHY repeater with optional jitter removal capability. This
operating mode provides a low-power means of using an AC-coupled TMDS signal from a dual mode DP
(DP++) source to be repeated to the HDMI output. The maximum TMDS character clock frequency in this
mode is limited to 340 Mchar/s (per HDMI1.4b specification).
In Protocol Converter (PCON) mode, MCDP28x0 functions as a DP branch device receiving AC coupled
DisplayPort stream and converting it to HDMI output. The maximum TMDS character clock frequency
supported in this mode is up to 600 Mchar/s (as per the HDMI2.0a specification).
The MCDP28x0 operates with two power supply voltages: 1.2 V and 3.3 V. It consumes:
• 100 mW in PHY analog repeater mode
• 412 mW in protocol converter mode
• 0.1 mW in connected standby mode (1.2 V power rail disabled)
The MCDP28x0 has a DisplayPort1.2a dual-mode receiver and HDMI 2.0a transmitter. The upstream
main link can receive DP input at HBR2 rate over 4 lanes and AC-coupled TMDS signal up to
340Mchar/s. It supports DP SST stream on its main link and Manchester-coded AUX signaling or native
3.3 I2C signaling as the side band channel with the DP++ source. The downstream HDMI TX port is
HDMI 2.0 specification compliant.
The MCDP28x0 is capable of supporting Ultra High-Definition video formats, resolutions as high as 4096
x 2160@60 Hz. It supports RGB/YCbCr video color formats with a color depth of 16 bpc (or 48 bits per
pixel) as long as it fits within the DP1.2 and HDMI2.0a link rate. In addition, this device also supports pixel
encoding conversion from YCbCr444 to YCbCr420 and YcbCr420 pass-through from a DP input to an
HDMI output. High Dynamic Range (HDR) with deep color up to 12bpc at 4Kp60Hz is supported through
the conversion of YCbCr444 CVT timing over DP link with horizontal expansion to YCbCr420 CEA timing
on the HDMI TX output.
This device offers secure reception and transmission of high bandwidth digital audio and video content
with HDCP 1.x content protection for the upstream DP interface and HDCP2.2 for the downstream HDMI
interface. It also operates as an HDCP1.x repeater between the source and the sink. In addition, it
conforms to the secure communication protocol specified in the Intel “LSPCON Security Requirements
C28x0-DAT-01p
MegaChips’ Proprietary Information
Page 7 of 33
MCDP28x0
Architecture Specification” document. The MCDP28x0 comes with embedded HDCP keys that are stored
in encrypted form.
The MCDP28x0 uses an external crystal of 27 MHz as a reference clock for its operation and it has a
reset input which provides the chip reset during system power up. The device has an on-chip
microcontroller with SPI, UART, and I2C interfaces for system level communication and debug. It
requires an external SPI flash memory for storing device configuration firmware. The firmware update is
done through the DP AUX channel or through UART interface. An 8 Mbit SPI flash memory is
recommended for storing the firmware with a backup option as fail-safe during in-system-programming.
C28x0-DAT-01p
MegaChips’ Proprietary Information
Page 8 of 33
MCDP28x0
2. Application overview
Two important target applications of MCDP28x0 are:
• Mobile PC motherboard application. This is referred as motherboard-down topology and the
part number that supports this topology is MCDP2800.
• Accessory application (dongle, docking station etc.). This is referred as adaptor topology and
the part number for this topology is MCDP2850.
2.1 Motherboard-down topology
In a Motherboard-down topology, the MCDP2800 resides next to the source (CPU/GPU) device on a
same PCB with relatively short copper tracks connecting directly to the source. These tracks are typically
micro stripes with controlled impedance of 100 Ω. In this configuration, the source device is aware of the
presence and capabilities of the MCDP2800. The source communicates with MCDP2800 through
AUX/DDC interface via I2C-over-AUX or native I2C (3.3V) messaging. In this topology, typically the
MCDP2800 operates as a re-driving or re-timing analog repeater for AC-coupled TMDS input for speeds
below 3.4Gbps and as a DisplayPort to HDMI protocol converter for speeds above 3.4 Gbps up to 6.0
Gbps. The analog repeater mode saves the active power consumption during low frequency oeprtation.
MCDP2800 however is capable of operating as DP to HDMI protocol converter for the entire operating
range up to 6 Gbps. The motherboard-down topology supports transmitting both HDCP1.x and HDCP2.2
protected content over the HDMI output.
Figure 2. MCDP2800 motherboard-down use case
HDMI Cable
Source SoC
MCDP2800
HDMI Sink
2.2 Adaptor topology
In an adaptor topology, the MCDP2850 is part of the source side adaptor or docking station that plugs
into the PC/NB via a DP++ connector. In this case, a typical source sends out a DP signal to the adaptor
and the adaptor converts it into HDMI 2.0 output for the entire operating frequency range. However, a
source which is aware of the presence and capabilities of the MCDP2850 can choose to send an AC-
C28x0-DAT-01p
MegaChips’ Proprietary Information
Page 9 of 33
MCDP28x0
coupled TMDS signal at lower speeds (below 3.4 Gbps) and a DP signal at higher speeds (above 3.4
Gbps) similar to a motherboard-down topology. In the adaptor application, the MCDP2850 dynamically
decides whether to use I2C-over-AUX or native I2C messaging at the time of connectivity with the
source. MCDP2850 only supports HDCP1.x repeater/transmitter functionality; no HDCP2.2 transmitter
function allowed in this topology.
Note:
In an adaptor topology, signal degradation is higher compared to in a motherboard-down
topology due to longer traces and multiple connectors in the path.
Figure 3. MCDP2850 adaptor (dongle) use case
Dongle
HDMI Cable
Source SoC
MCDP2850
HDMI Sink
C28x0-DAT-01p
MegaChips’ Proprietary Information
Page 10 of 33
MCDP28x0
3. BGA footprint and pin lists
3.1 Ball grid array diagram
The ball grid array (BGA) diagrams give the allocation of signals to the balls of the package, shown from
the top looking down using the PCB footprint.
Some signal names in BGA diagrams have been abbreviated. Refer to the pin list for full signal names
sorted by pin number.
Figure 4. MCDP28x0 BGA diagram
1
2
3
4
5
6
7
8
DPRX
L3N
DPRX
L3P
DPRX
L2N
DPRX
L2P
DPRX
L1N
DPRX
L1P
DPRX
L0N
DPRX
L0P
A
B
C
D
E
A
B
C
D
E
DPRX
HPD_OUT
VDD33
RX
VDD12
RX
VDD12
RX
VDD12
PLL
GND
GND
RESETN
VDD33
RX
VDD33
AUX
DPRX
AUXP
DPRX
AUXN
SPI_CSN
SPI_DO
SPI_DI
SPI_CLK
SPI_WP
GPIO1
R_EXT
VDD33
IO
VDD12
DIG
GND
GND
GND
GND
UART_TX
UART_RX
C_EXT
TEST
XTꢀ>
dꢁ><
HDMITX
DDC_SCL
VDD33
IO
I2C_SDA
I2C_SCL
GND
HDMITX
DDC_SDA
HDMI
CEC
VDD12
OSC
VDD12
DIG
CONFIG1
GND
F
F
HDMITX
HPD_IN
VDD33
TX
VDD33
TX
VDD12
TX
VDD12
TX
VDD12
ON
G
H
G
H
HDMITX
CLKN
HDMITX
CLKP
HDMITX
CH0N
HDMITX
CH0P
HDMITX
CH1N
HDMITX
CH1P
HDMITX
CH2N
HDMITX
CH2P
1
2
3
4
5
6
7
8
HDMI_TX
Power 3.3V
DP_RX
Power 1.2V
SYS_DIGITAL
Power Return
SYS_ANALOG
8kV pads
C28x0-DAT-01p
MegaChips’ Proprietary Information
Page 11 of 33
MCDP28x0
3.2 Signal mapping sorted by ball (pin) number
Table 1. Pin list
Pin number
Net name
A1
A2
A3
A4
A5
A6
A7
A8
B1
B2
B3
B4
B5
B6
B7
B8
C1
C2
C3
C4
C5
C6
C7
C8
D1
D2
D3
D4
D5
D6
D7
D8
E1
E2
DPRX_L3N
DPRX_L3P
DPRX_L2N
DPRX_L2P
DPRX_L1N
DPRX_L1P
DPRX_L0N
DPRX_L0P
DPRX_HPD_OUT
VDD33_RX
GND
VDD12_RX
VDD12_RX
GND
VDD12_PLL
RESETN
SPI_CSN
SPI_DI
GPIO1
VDD33_RX
VDD33_AUX
R_EXT
DPRX_AUXP
DPRX_AUXN
SPI_DO
SPI_CLK
VDD33_IO
GND
GND
VDD12_DIG
UART_TX
TEST
HDMITX_DDC_SCL
SPI_WP
C28x0-DAT-01p
MegaChips’ Proprietary Information
Page 12 of 33
MCDP28x0
Table 1. Pin list (continued)
Net name
Pin number
E3
E4
E5
E6
E7
E8
F1
F2
F3
F4
F5
F6
F7
F8
G1
G2
G3
G4
G5
G6
G7
G8
H1
H2
H3
H4
H5
H6
H7
H8
VDD33_IO
GND
GND
I2C_SDA
UART_RX
XTAL
HDMITX_DDC_SDA
HDMI_CEC
CONFIG1
VDD12_OSC
VDD12_DIG
I2C_SCL
C_EXT
TCLK
HDMITX_HPD_IN
VDD33_TX
GND
VDD33_TX
VDD12_TX
GND
VDD12_TX
VDD12_ON
HDMITX_CLKN
HDMITX_CLKP
HDMITX_CH0N
HDMITX_CH0P
HDMITX_CH1N
HDMITX_CH1P
HDMITX_CH2N
HDMITX_CH2P
C28x0-DAT-01p
MegaChips’ Proprietary Information
Page 13 of 33
MCDP28x0
4. Connections
4.1 Pin list
I/O Legend:
I = Input; O = Output; P = Power; G = Ground; IO = Bi-direction; AI = Analog input
Table 2. DisplayPort receiver pins
VDD
Pin
Assignment
I/O
Description
Domain
DisplayPort receiver main link Lane 3 negative analog
input.
A1
DPRX_L3N
I
1.2 V
AC-coupled internal pull up to VDD12_RX through 50
ꢀ resistor.
DisplayPort receiver main link Lane 3 positive analog
input.
A2
A3
A4
A5
A6
A7
A8
DPRX_L3P
DPRX_L2N
DPRX_L2P
DPRX_L1N
DPRX_L1P
DPRX_L0N
DPRX_L0P
I
I
I
I
I
I
I
1.2 V
1.2 V
1.2 V
1.2 V
1.2 V
1.2 V
1.2 V
AC-coupled internal pull up to VDD12_RX through 50
ꢀ resistor.
DisplayPort receiver main link Lane 2 negative analog
input.
AC-coupled internal pull up to VDD12_RX through 50
ꢀ resistor.
DisplayPort receiver main link Lane 2 positive analog
input.
AC-coupled internal pull up to VDD12_RX through 50
ꢀ resistor.
DisplayPort receiver main link Lane 1 negative analog
input.
AC-coupled internal pull up to VDD12_RX through 50
ꢀ resistor.
DisplayPort receiver main link Lane 1 positive analog
input.
AC-coupled internal pull up to VDD12_RX through 50
ꢀ resistor.
DisplayPort receiver main link Lane 0 negative analog
input.
AC-coupled internal pull up to VDD12_RX through 50
ꢀ resistor.
DisplayPort receiver main link Lane 0 positive analog
input.
AC-coupled internal pull up to VDD12_RX through 50
ꢀ resistor.
C28x0-DAT-01p
MegaChips’ Proprietary Information
Page 14 of 33
MCDP28x0
VDD
Domain
Pin
Assignment
I/O
Description
DisplayPort receiver auxiliary channel positive analog
input/output. Common mode voltage = 3.3 V
C7
DPRX_AUXP
IO
3.3 V
3.3V
3.3 V
1.2 V
3.3V
AC-coupled internal pull up to VDD33_AUX through 50
ꢀ resistor. Also functions as DDC_SCL.
DisplayPort receiver auxiliary channel negative analog
input/output. Common mode voltage = 3.3 V
C8
B1
C6
F3
DPRX_AUXN
DPRX_HPD_OUT
R_EXT
IO
O
AC-coupled internal pull up to VDD33_AUX through 50
ꢀ resistor. Also functions as DDC_SDA.
To the upstream HPD signal pin (DP source), to be
externally pulled down (100K ohm recommended) as
per DP1.2a spec.
Termination calibration reference resistor; 249 ꢀ 1%
resistor should be connected from this pin to
VDD12_RX (1.2 V analog power supply).
IO
IO
General purpose IO. Connects to DP upstream
connector pin 13 in Adaptor topology. Optional in
Motherboard-down topology. Default POR state is
INPUT use weak pull-down when not used.
CONFIG1
Table 3. HDMI output pins
VDD
Pin
Assignment
I/O
Description
Domain
H1
HDMITX_CLKN
O
O
O
O
O
O
O
O
3.3 V
HDMI transmitter CLOCK_N to TX connector
H2
H3
H4
H5
H6
H7
H8
HDMITX_CLKP
HDMITX_CH0N
HDMITX_CH0P
HDMITX_CH1N
HDMITX_CH1P
HDMITX_CH2N
HDMITX_CH2P
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
HDMI transmitter CLOCK_P to TX connector
HDMI transmitter DATA0_N to TX connector
HDMI transmitter DATA0_P to TX connector
HDMI transmitter DATA1_N to TX connector
HDMI transmitter DATA1_P to TX connector
HDMI transmitter DATA2_N to TX connector
HDMI transmitter DATA2_P to TX connector
C28x0-DAT-01p
MegaChips’ Proprietary Information
Page 15 of 33
MCDP28x0
VDD
Domain
Pin
Assignment
I/O
Description
3.3 V, 5 V HDMI TX DDC I2C master SCL. 3.3 V logic level, 5 V
Tol tolerant. Open drain, external 2.2 K pull up to +5 V.
E1
HDMITX_DDC_SCL
O
3.3 V, 5 V HDMI TX DDC I2C master SDA. 3.3 V logic level, 5 V
F1
F2
G1
HDMITX_DDC_SDA
HDMI_CEC
IO
IO
I
Tol
tolerant. Open drain, external 2.2 K pull up to +5 V.
CEC input. 3.3 V open drain IO. Connect to HDMI
CEC pin, to be externally pulled up to 3.3 V (27K
Ohm recommended) as per HDMI1.4b spec.
3.3 V
3.3 V logic level, 5 V tolerant input from HDMI
connector. To be externally pulled down via resistor.
(47K Ohm recommended)
3.3 V, 5 V
Tol
HDMITX_HPD_IN
Table 4. System interface pins
VDD
Pin
Assignment
I/O
Reset State
Description
Domain
Power-ON chip reset (active low)
input signal
B8
RESETN
I
3.3 V
Input
Connects to 3.3V VDD through 2.2K
+/-10% resistor
Connect to 27 MHz crystal oscillator
with 22 pF to VDD12_OSC
E8
F8
F7
G8
XTAL
IO
IO
O
O
1.2 V
1.2 V
3.3V
NA
Connect to 27 MHz crystal oscillator
with 22 pF to VDD12_OSC
TCLK
NA
Capacitor for filtering internal 2.5V
LDOR. Connect to GND through
2.2uF capacitor.
C_EXT
VDD12_ON
NA
1.2 V power control signal to control
external 1.2 V power as shown in
Figure 4. Reset State definition
3.3 V
Output
assumes 3.3 V Rail is ramped up to
full voltage.
C28x0-DAT-01p
MegaChips’ Proprietary Information
Page 16 of 33
MCDP28x0
VDD
Pin
Assignment
I/O
Reset State
Description
Domain
Test select. Tie to GND for mission
mode
D8
TEST
IO
3.3 V
3.3 V
3.3 V
3.3 V
NA
Host I2C interface data line.
External pull-up required for I2C
operation.
Input, Internal
PU
E6
F6
C3
C1
C2
D1
D2
E2
D7
I2C_SDA
I2C_SCL
GPIO1
IO
Leave NC when not used.
Host I2C interface clock line.
External pull-up required for I2C
operation.
Input, Internal
PU
I
Leave NC when not used.
General purpose input/output.
Input, Internal Applicable for CONFIG2 if needed.
IO
O
I
PU
Default POR state is INPUT; use
weak pull-down when not used.
Input, Internal Serial peripheral interface chip
SPI_CSN
SPI_DI
3.3 V
PU
select
3.3 V
Input, Internal
PD
Serial peripheral interface data input
3.3 V
Input, Internal Serial peripheral interface data
SPI_DO
SPI_CLK
SPI_WP
UART_TX
O
O
O
O
PD
output
Input, Internal
PD
3.3 V
3.3 V
3.3 V
Serial peripheral interface clock
Input, Internal Serial peripheral interface write
PD
protect
Universal asynchronous serial Tx
output.
Input, Internal
PU
Leave NC when not used.
C28x0-DAT-01p
MegaChips’ Proprietary Information
Page 17 of 33
MCDP28x0
VDD
Pin
Assignment
I/O
Reset State
Description
Domain
Universal asynchronous serial Rx
input.
Input, Internal
PU
E7
UART_RX
I
3.3 V
Leave NC when not used.
Table 5. Power and ground pins
Pin
Assignment
Voltage Level
Description
DisplayPort RX analog power
B2, C4
VDD33_RX
L3.3 V
B4, B5
C5
VDD12_RX
VDD33_AUX
VDD12_PLL
VDD12_OSC
VDD33_TX
VDD12_TX
VDD12_DIG
VDD33_IO
1.2 V
3.3 V
1.2 V
1,2 V
3.3 V
1.2 V
1.2 V
3.3 V
DisplayPort RX analog power
DisplayPort AUX analog power
PLL analog power
B7
F4
Oscillator circuit power
HDMI TX analog power
HDMI TX analog power
Core and 1.2V IO power
3.3V IO power
G2, G4
G5, G7
D6, F5
D3, E3
B3, B6, D4, D5, E4,
E5, G3, G6
GND
GND
Power return for all supplies
4.2 Bootstrap configuration
Other than the normal operating mode (mission mode), the MCDP28x0 is configured in testing and
debugging mode during factory testing and chip bring-up. For this purpose, the chip is configured during
the boot operation using several bootstrap configurations. DC levels on these bootstrap pins are latched
during the de-asserting edge of power-on reset (RESETN goes HIGH). The levels specified below must
be adhered to for the normal function of the device.
Table 6. Bootstrap configuration
Bootstrap signal
Internal PU/PD Pin assignment
Function
name
0: Reserved for ATE test
Bootstrap_0
PULL UP
UART_TX (D7)
1: Normal operation (mission mode)
C28x0-DAT-01p
MegaChips’ Proprietary Information
Page 18 of 33
MCDP28x0
0: Normal operation (mission mode)
1: OCM debug mode
Bootstrap_1
Bootstrap_2
Bootstrap_3
PULL DN
PULL DN
SPI_WP (E2)
SPI_CLK (D2)
0: (Default) Internal ROM is enabled and mapped to top
32 K of OCM memory map. OCM boots from IROM.
Normal mode (mission mode).
1: Internal ROM is disabled. External ROM includes the
address range reserved for IROM. OCM boots from
EXTROM. Debug mode.
0: Default. Reserved (mission mode)
1: Reserved for testing
PULL DN
PULL UP
SPI_DO (D1)
0: Select external CLK on XTAL pin (used in ATE).
Bootstrap_4
SPI_CSN (C1)
1: (Default) Select crystal and internal oscillator. Normal
operation (mission mode).
Note:
When the pin corresponding to a specific bootstrap is left NC, the pin takes the value of the
assigned by the internal PULLUP (Level 1) or PULLDN (Level 0). The internal resistor used
is around 50 k Ω. To select a non-default value on a bootstrap, an external PULLUP or
PULLDN resistor tied to the opposite direction that overcomes the internal PULLUP or
PULLDN needs to be used.
4.3 RESETN connection
The RESETN pin must be pulled up to 3.3 V via a 2.2 kohm +/- 10% resistor as shown below. The chip
also supports an active low, external reset pulse to RESETN allowing a system host controller to reset
the system. The recommended way to drive RESETN is through an open-drain output. Alternately, if an
open-drain output is not available, the series resistor shown in the figure below is required.
Figure 5. RESETN Connection to MCDP28x0
3.3V
MCDP28x0
External Reset
Control (optional)
2.2Kohm
RESETN
External Reset
Switch (for debug)
External 1.5K to 3Kohm
+/‐1% series resistor
System Host
Capacitor Value
should not exceed
50pF
C28x0-DAT-01p
MegaChips’ Proprietary Information
Page 19 of 33
MCDP28x0
5. Package specifications
Package type: LFBGA (7 x 7 x 1.4 mm, 64 F8 x 8 Pitch 0.8 Ball 0.4)
5.1 Package drawing
Figure 6. MCDP28x0 package drawing
C28x0-DAT-01p
MegaChips’ Proprietary Information
Page 20 of 33
MCDP28x0
5.2 LFBGA 7 x 7 dimensions
Figure 7. MCDP28x0 package dimensions
DIMENSIONS
DATABOOK
(mm)
DRAWING
(mm)
REF.
MIN.
0.25
TYP.
MAX.
MIN.
TYP.
MAX.
NOTES
(1)
A
A1
A2
A4
b
D
D1
E
1.4
1.24
0.35
0.32
0.60
0.45
7.05
0.25
0.24
0.57
0.35
6.95
0.30
0.28
0.585
0.40
7.00
5.60
7.00
5.60
0.80
0.70
0.29
0.60
0.45
7.05
0.35
6.95
0.40
7.00
5.60
7.00
5.60
0.80
0.70
(2)
6.95
7.05
6.95
7.05
E1
e
Z
ddd
eee
fff
0.08
0.09
0.05
0.08
0.09
0.05
(4)
(5)
NOTES:
(1) - LFBGA stands for Low profile Fine Pitch Ball Grid Array.
- Thin profile: 1.00mm < A 1.20mm / Fine pitch: e < 1.00mm pitch.
- The total profile height (Dim A) is measured from the seating plane to the top of the component
- The maximum total package height is calculated by the following methodology:
A Max = A1 Typ + A2 Typ + A4 Typ +¥ (A1² + A2² + A4² tolerance values)
(2) – The typical ball diameter before mounting is 0.40mm.
(3) – LFBGA with 0.40mm pitch is not yet registered into JEDEC Publications.
(4) - The tolerance of position that controls the location of the pattern of balls with respect to datums A and B.
For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true position
with respect to datums A and B as defined by e. The axis perpendicular to datum C of each ball must lie
within this tolerance zone.
(5) - The tolerance of position that controls the location of the balls within the matrix with respect to each other.
For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position
as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone.
Each tolerance zone fff in the array is contained entirely in the respective zone eee above
The axis of each ball must lie simultaneously in both tolerance zones.
(6) - The terminal A1 corner must be identified on the top surface by using a corner chamfer,
ink or metallized markings, or other feature of package body or integral heatslug.
- A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1
corner. Exact shape of each corner is optional.
5.3 Marking field template and descriptors
The MCDP28x0 marking template is shown below.
C28x0-DAT-01p
MegaChips’ Proprietary Information
Page 21 of 33
MCDP28x0
Figure 8. Marking template
Field descriptors are shown below.
Table 7.Field descriptors
Field
Description
Marking
A
MegaChips logo
MegaChips
One of the codes below:
MCDP2800BB
B
Product code
MCDP2850BB
MCDP2800BC
MCDP2850BC
C
D
E
F
G
H
I
2-character diffusion plant code
3-digit wafer start date
VQ
“YWW”
“ABC”
99
3-character FE sequence code
2-character assembly plant code
3-character BE sequence code
Optional marking
“XYZ”
<blank> or ES(1)
MYS
3-character country of origin code
2-digit test plant code
J
8U
K
L
1-digit assembly year
“Y”
2-digit assembly week
“WW”
a DOT
M
Ball A1 identifier
1. Marked ES for Engineering Samples, used for development purposes.
5.4 Classification reflow profile
Please refer to the DisplayPort Application Note: Classification reflow profile for SMD devices (C0353-
APN-06) for reflow diagram and details.
C28x0-DAT-01p
MegaChips’ Proprietary Information
Page 22 of 33
MCDP28x0
6. Electrical specifications
6.1 Absolute maximum ratings
Applied conditions greater than those listed under “Absolute maximum ratings” may cause permanent
damage to the device. The device should never exceed absolute maximum conditions since it may affect
device reliability.
Table 8. Absolute maximum ratings
Parameter
Symbol
Min
Typ
Max
Units
3.3 V supply voltages (1,2)
1.2 V supply voltages (1.2)
VVDD_3.3
VVDD_1.2
-0.3
-0.3
-0.3
-0.3
3.3
1.2
3.96
1.44
5.5
V
V
V
V
Input voltage tolerance for 3.3 V, 5 V tolerant I/O pins VIN5tol
Input voltage tolerance for 3.3 V I/O pins
VIN3V3
3.63
ESD – Human Body Model (HBM) [JESD22-A114
spec] For all pins
VESD
+/- 2.0
+/- 6.5
kV
kV
ESD – Human Body Model (HBM) [IEC61000-4 spec]
For DP and HDMI connector-facing pins
VESD
-
-
ESD – Charged Device Model (CDM)
Latch-up (3,4)
VESD
ILA
-
-
+/- 500
+/- 100
70
V
-
-
mA
C
Ambient operating temperature
Storage temperature
TA
0
-
TSTG
TJ
-40
-
150
C
Operating junction temperature
Thermal resistance (Junction to Ambient)(5)
Thermal resistance (Junction to Case)(5)
Peak IR reflow soldering temperature
0
-
75
-
125
C
JA
49.0
20.1
260
C/W
C/W
C
JC
TSOL
-
-
-
-
Note (1): All voltages are measured with respect to GND.
Note (2): Absolute maximum voltage ranges are for transient voltage excursions.
Note (3): For connector facing pins CONFIG1 and DPRX_HPD_OUT, a series resistor of 100 ohms is
recommended. Refer to the MCDP28x0 Layout Guideline appnote.
Note (4): JEDEC Class1.
Note (5): These are simulated results under the following conditions: Four layer JEDEC PCB, no heat
spreader, Air flow = 0 m/s.
C28x0-DAT-01p
MegaChips’ Proprietary Information
Page 23 of 33
MCDP28x0
6.2 Power Connections
From 3.3V regulator
FB
01uF
FB
0.1uF
FB= FERRITE BEAD
120Ohms@100MHz
B2
VDD33_RX
C5
C4
VDD33_RX
D3
VDD33_AUX
VDD33_IO
VDD33_IO
VDD33_TX
0.1uF
E3
G4
G2
FB
REXT
C6
B4
VDD33_TX
0.1uF
1.2V REGULATOR
249ohm/1%
V_IN
R1
G8
V_ON
VDD12ON
R2
0.01uF
FB
VDD12_RX
MCDP28x0
V_OUT
B5
F4
GND
VDD12_RX
FB
0.1uF
G5
G7
VDD12_OSC
0.1uF
VDD12_TX
VDD12_TX
F8
E8
0.1uF
TCLK
XTAL
B7
F5
VDD12_PLL
FB
FB
VDD12_DIG
CEXT
F7
2.2uF
GND
VDD12_DIG
22pF
0.1uF
D6
B3, B6, D4, D5, E4,
E5, G3, G6, D8
0.1uF
0.1uF
0.1uF
C28x0-DAT-01p
MegaChips’ Proprietary Information
Page 24 of 33
MCDP28x0
6.3 DC characteristics
Table 9. DC characteristics
Parameter
Symbol
Min
Typ
Max
Units
3.3 V supply voltages (analog and digital)
1.2 V supply voltages (analog and digital)
Power
VVDD_3.3
VVDD_1.2
3.14
1.14
3.3
1.2
3.47
1.26
V
V
Protocol converter Mode
Measurement condition:
412
460
mW
Nominal corner, 25°C, Nominal power supply
4k x 2k / 60 Hz 4L HBR2 to HDMI test pattern:
ON-OFF dot Moire attributes-based rendering
Analog PHY repeater mode
Sleep State
100
18
120
20
mW
mW
mW
Connected standby mode
0.1
0.2
Supply current
Measurement conditions:
Nominal corner, 25°C, Nominal power supply
4k x 2k @60 MHz
mA
4L HBR to HDMI2.0a
VDD (analog and digital) 3.3V
VDD (analog and digital) 1.2V
30
300
Note:
Ripple amplitude for power supplies should be 30 mV or lower with max ripple frequency of
up to 30 MHz.
Table 10. IO DC characteristics
Parameter
Symbol
Min
Typ
Max
Units
Inputs 3.3 V IO signals, 5 V tolerant open drain type
High voltage
VIH
2.0
5.5
0.8
V
Low voltage
VIL
-0.3
300
V
Input Hysteresis voltage
High current (VIN = 3.3 V)
Low current (VIN = 0.8 V)
Input capacitance
VHYST
IIH
mV
A
A
pF
+/- 10
+/- 10
IIL
CIN
5
Outputs 3.3 V IO signals, 5 V tolerant open drain type
C28x0-DAT-01p
MegaChips’ Proprietary Information
Page 25 of 33
MCDP28x0
Low Current (VOL = 0.2 V)
Tri-state leakage current
IOL
IOZ
4
mA
10
A
VDD12_ON output
Output Low Voltage (IOL=0.25mA)
Output High Voltage(IOH=0.25mA)
Low Level output Current
VOL
VOH
IOL
0.4
V
V
2.9
0.25
0.25
High Level Output Current
IOH
Inputs 3.3 V IO signals, 3.3 V tolerant, TRISTATE
High voltage
VIH
VIL
2.0
V
Low voltage
0.8
V
Input Hysteresis voltage
High current (VIN = 3.3 V)
Low current (VIN = 0.8 V)
Input capacitance
VHYST
IIH
300
mV
A
A
pF
±10
±10
IIL
CIN
1.0
50
50
Outputs 3.3 V IO signals, 3.3 V tolerant, TRISTATE
Output
Impedance,
Rout
ꢀ
VOL=0.3V
Output
Impedance,
Rout
ꢀ
VDDE3V3-
0.3V
Tri-state leakage current
IOZ
±10
A
6.4 AC characteristics
Table 11. Maximum speed of operation
Max speed of operation
Clock domain
Reference Input Clock (TCLK)
Reference Internal Clock (RCLK)
27 MHz
324 MHz
On-Chip Microcontroller Clock (OCLK)
2-Wire Serial Slave (SLAVE_SCL)
2-Wire Serial Master (MSTRx_SCL)
SPI Clock
150 MHz
400 kHz
400 kHz
50 MHz
C28x0-DAT-01p
MegaChips’ Proprietary Information
Page 26 of 33
MCDP28x0
6.4.1 DisplayPort receiver
Table 12. DisplayPort receiver characteristics
Parameter
Symbol
Min
Typ
Max
Units
Comments
Receiver operating range
VRX_DIF_PP_RANG
Differential Input Voltage Range
0.04~1
V
E
RX Termination Control Range RRX_TERM_RANGE
DisplayPort receiver system parameters
80 ~120
ohm
HBR2 unit interval (5.4Gbps)
HBR unit interval (2.7Gbps)
RBR unit interval (1.62Gbps)
Link clock down spreading
UIHBR2
UIHBR
UIRBR
185
370
617
ps
ps
ps
%
Modulation frequency
range 0f 30 kHz to 33 kHz
0
0.5
DisplayPort receiver TP3 parameters
Receiver Eye TP3 RBR
TRBR_EYE_TP3
0.25
0.4
UI
UI
UI
@ 40mV V_diff_pp
@ 135mV V_diff_pp
@ 70mV V_diff_pp
Receiver Eye TP3_EQ HBR THBR_EYE_TP3EQ
Receiver Eye TP3_EQ HBR2 THBR2_EYE_TP3EQ 0.3
TSKEW_INTRA_RBR
Lane intra-pair skew tolerance TSKEW_INTRA_HBR
TSKEW_INTRA_HBR2
260
60
ps
ps
ps
Skew contribution from the
cable in addition to the
stressed EYE at TP3.
50
1.62Gbps signal @
package pins
DJ Non-ISI at 1.62 Gbps
DJ Non-ISI at 2.7 Gbps
DJ at 5.4 Gbps
TRX_DJ_RBR
TRX_DJ_HBR
TRX_DJ_HBR2
TRX_TJ_RBR
TRX_TJ_HBR
TRX_TJ_HBR2
0.186 UI
0.339 UI
2.7Gbps signal @
package pins
5.4 Gbps signal @
package pins
0.57
0.78
0.53
0.7
UI
UI
UI
UI
1.62Gbps signal @
package pins
TJ at 1.62 Gbps
2.7Gbps signal @
package pins
TJ at 2.7 Gbps
5.4 Gbps signal @
package pins
TJ at 5.4 Gbps
C28x0-DAT-01p
MegaChips’ Proprietary Information
Page 27 of 33
MCDP28x0
Parameter
Symbol
Min
Typ
Max
Units
Comments
AUX parameters
Differential Input Voltage
Range
VAUX_RX_DIF_RANG
0.14~1
40~60
0~1
V
E
RX Termination Control Range RAUX_TERM_RANGE
ohms
V
7.8125mV/step in 128
steps
AUX TX peak-peak Range
VAUX_TX_DIF_PP
6.4.2 HDMI transmitter I/O specifications
Table 13. HDMI transmitter I/O specifications
Parameters
Symbol
Min
Typ
Max
Unit
Comments
Differential output: single ended swing
amplitude
VTX_PP
0.4
0.5
0.6
V
Differential output: Differential swing
amplitude
VTX_DIF_PP
0.8
1
1.2
V
V
V
Differential high level output
Differential low level output
VTX_DIF_HIGH
VTX_DIF_LOW
3.12
3.12
3.3
3.49
3.49
Table 14. HDMI transmitter AC characteristics
Parameters
Symbol
Min
Typ
Max
Unit
Comments
TMDS Character Clock
fTX_CHR_CLK
25
600
MHz
mV
Programmable
In 128 steps
Differential Output Voltage
TX Edge Rate
VTX_DIF_PP
0
1200
145
1V VTX_DIF_PP and
Premphasis at 0dB
in 8 steps
tTX_ER
75
0
pS
1V VTX_DIF_PP in 16
steps
TX Pre-Emphasis Level
APREMPH
6
dB
Programmable
Termination
TX Termination Control Range RTX_TERM_RANGE 100
600
60
70
35
45
ohms
pS
TX Jitter <1.65Gbps for Pattern
TTX_J_D102_LF
D10.2
TX Jitter <1.65Gbps for
TTX_J_PRBS7_LF
pS
PatternPRBS7
TX Jitter >1.65Gbps, <
TTX_J_D102_MF
pS
3.4Gbps for PatternD10.2
TX Jitter >1.65Gbps, <
TTX_J_PRBS7_MF
pS
3.4Gbps for PatternPRBS7
C28x0-DAT-01p
MegaChips’ Proprietary Information
Page 28 of 33
MCDP28x0
TX Jitter >3.4Gbps for
PatternD10.2
TTX_J_D102_HF
30
35
pS
pS
TX Jitter >3.4Gbps for
PatternPRBS7
TTX_J_PRBS7_HF
6.4.3 I2C interface timing
Table 15. I2C interface timing
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fSCL
SCL clock rate
Fast mode
0
-
400
kHz
After this period, the
1
tHD-STA
Hold time START
1.2
-
-
s
st clock starts
tLOW
tHIGH
Low period of clock
High period of clock
SCL
SCL
1.3
1.2
-
-
-
-
s
s
Set up time for a
repeated START
Tsu;STA
1.2
-
-
s
tHD;DAT
tSU;DAT
Data hold time
Data setup time
For master
0.7
-
-
0.9(1)
-
s
380
ns
Bus free time between
STOP and START
TBUF
Cb
1.3
-
-
-
s
Capacitance load for
each bus line
100
400
pF
tr
tf
Rise time
Fall time
220
60
-
-
300
300
ns
ns
Noise margin at high
level
Vnh
Vnl
0.25VDD
0.2VDD
-
-
-
-
V
Noise margin at low
level
Note:
The maximum tHD;DAT only has to be met if the device does not stretch the low period
tLOW of the SCL signal. In the diagram below, S = start, P = stop, Sr = Repeated start, and
SP= Repeated stop conditions.
2
Figure 9. I C timing
SDA
tf
tf
tSU;DAT
tSP
tr
tLOW
tr
tHD;STA
tBUF
SCL
tSU;STA
tSU;STO
tHD;STA
Sr
S
tHIGH
tHD;DAT
P
S
C28x0-DAT-01p
MegaChips’ Proprietary Information
Page 29 of 33
MCDP28x0
6.4.4 SPI interface timing
Table 16. SPI interface timing, VDD = 3.3 V
Symbol
Parameter
Min
Typ
Max
Units
FCLK
SPI_CLK output clock frequency
50
MHz
ns
TSCKH
Serial clock high time
20
20
TSCKL
Serial clock low time
ns
TR_SPI_CLK
TF_SPI_CLK
TMEM_CLK_F
SPI_CLK rise time @10mA drive 10pF load
SPI_CLK fall time @10mA drive 10pF load
Device speed
2.8
3.2
ns
ns
75
MHz
ns
TMEM_CSN_SU Device CSN input setup time requirement
TMEM_CSN_HLD Device CSN input setup time requirement
7
7
6
3
5
ns
TMEM_DO_PD
TMEM_DI_SU
TMEM_DI_SU
Device DO out propagation delay
Device DI setup time
ns
ns
Device DI hold time
ns
C28x0-DAT-01p
MegaChips’ Proprietary Information
Page 30 of 33
MCDP28x0
7. Ordering information
Table 17. Order codes
Part number
Description
64 LFBGA (7 x 7 x 1.4 mm) for motherboard-down
application. Engineering samples, for development
purpose only. (Rev BB silicon)
MCDP2800-BBES
64 LFBGA (7 x 7 x 1.4 mm) for motherboard-down
application. Mass production parts. Delivered in trays.
(Rev BB silicon)
MCDP2800-BB
MCDP2800-BBT
64 LFBGA (7 x 7 x 1.4 mm) for motherboard-down
application. Mass production parts. Delivered in tape
and reel. (Rev BB silicon)
64 LFBGA (7 x 7 x 1.4 mm) for dongle application.
Delivered in trays. (Rev BB silicon)
MCDP2850-BB
MCDP2850-BBT
64 LFBGA (7 x 7 x 1.4 mm) for dongle application.
Delivered in tape and reel. (Rev BB silicon)
64 LFBGA (7 x 7 x 1.4 mm) for motherboard-down
application. Mass production parts. Delivered in trays.
(Rev BC silicon)
MCDP2800-BC
MCDP2800-BCT
64 LFBGA (7 x 7 x 1.4 mm) for motherboard-down
application. Mass production parts. Delivered in tape
and reel. (Rev BC silicon)
64 LFBGA (7 x 7 x 1.4 mm) for dongle application.
Delivered in trays. (Rev BC silicon)
MCDP2850-BC
MCDP2850-BCT
64 LFBGA (7 x 7 x 1.4 mm) for dongle application.
Delivered in tape and reel. (Rev BC silicon)
C28x0-DAT-01p
MegaChips’ Proprietary Information
Page 31 of 33
MCDP28x0
8. Revision history
Table 18. Document revision history
Changes
Date
Revision
09-Mar-2016
A
Initial version.
Updated HDMI2.0 to HDMI2.0a throughout the datasheet. Added sub-bullet to
Features section.
07-Apr-2016
B
C28x0-DAT-01p
MegaChips’ Proprietary Information
Page 32 of 33
MCDP28x0
Notice
Semiconductor products may possibly experience breakdown or malfunction. Adequate care should be taken with respect to the safety design
of equipment in order to prevent the occurrence of human injury, fire or social loss in the event of breakdown or malfunction of semiconductor
products
The overview of operations and illustration of applications described in this document indicate the conceptual method of use of the
semiconductor product and do not guarantee operability in equipment in which the product is actually used.
The names of companies and trademarks stated in this document are registered trademarks of the relevant companies.
MegaChips Co. provides no guarantees nor grants any implementation rights with respect to industrial property rights, intellectual property
rights and other such rights belonging to third parties or/and MegaChips Co. in the use of products and of technical information including
information on the overview of operations and the circuit diagrams that are described in this document.
The product described in this document may possibly be considered goods or technology regulated by the Foreign Currency and Foreign
Trade Control Law. In the event such law applies, export license will be required under said law when exporting the product. This regulation
shall be valid in Japan domestic.
In the event the intention is to use the product described in this document in applications that require an extremely high standard of reliability
such as nuclear systems, aerospace equipment or medical equipment for life support, please contact the sales department of MegaChips
Co. in advance.
All information contained in this document is subject to change without notice.
Copyright ©2016 MegaChips Corporation All rights reserved
MegaChips Corporation
MegaChips Corporation
Head Quarters
Taiwan Branch
1-1-1 Miyahara, Yodogawa-ku Osaka 532-0003, Japan
TEL: +81-6-6399-2884
RM. B 2F, Worldwide House, No.129,
Min Sheng E. Rd., Sec. 3, Taipei 105, Taiwan
TEL: +886-2-2547-1297
MegaChips Corporation
Tokyo Office
MegaChips Corporation
Tainan Office
17-6 Ichiban-cho, Chiyoda-ku, Tokyo 102-0082, Japan
TEL: +81-3-3512-5080
RM. 2, 8F, No.24, Da Qiao 2 Rd., Yong Kang Dist.,
Tainan 710, Taiwan
TEL: +886-6-302-2898
MegaChips Corporation
MegaChips Corporation
Makuhari Office
Zhunan Office
1-3 Nakase Mihama-ku Chiba 261-8501, Japan
TEL: +81-43-296-7414
No.118, Chung-Hua Rd., Chu-Nan, Miao-Li 350, Taiwan
TEL: +886-37-666-156
MegaChips Corporation
MegaChips Corporation
Shenzhen Office
San Jose Office
2033 Gateway Place, Suite 400, San Jose, CA 95110 U.S.A.
TEL: +1-408-570-0555
Room 6307, Office Tower, Shun Hing Square, 5002
Shen Nan Dong Road, Luohu District,
Shenzhen 518000, P. R. China
TEL: +86-755-3664-6990
MegaChips Corporation
India Branch
17th Floor, Concorde Block UB City,
Vittal Mallya Road, Bangalore 560-001, India
TEL: +91-80-4041-3999
C28x0-DAT-01p
MegaChips’ Proprietary Information
Page 33 of 33
相关型号：
©2020 ICPDF网 联系我们和版权申明