K24C020-SERG-S [ESTEK]
8-lead PDIP, 8-lead SOP and 8-lead TSSOP Packages; 8引脚PDIP ， 8引脚SOP和8引脚TSSOP封装
| 型号： | K24C020-SERG-S |
| 厂家： | 
Estek Electronics Co. Ltd |
| 描述： | 8-lead PDIP, 8-lead SOP and 8-lead TSSOP Packages |
| 文件： | 总13页 (文件大小：1114K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
24C02 / 24C04 / 24C08 / 24C16
Features
Wide Voltage Operation
1 MHz (5V), 400 kHz (1.8V, 2.5V, 2.7V) Compatibility
- VCC = 1.8V to 5.5V
Write Protect Pin for Hardware Data Protection
8-byte Page (2K), 16-byte Page (4K, 8K, 16K) Write Modes
Partial Page Writes Allowed
。
。
Operating Ambient Temperature: -40 C to +85 C
Internally Organized:
-
-
-
-
24C02, 256 X 8 (2K bits)
Self-timed Write Cycle (5 ms max)
High-reliability
24C04, 512 X 8 (4K bits)
24C08, 1024 X 8 (8K bits)
- Endurance: 1 Million Write Cycles
- Data Retention: 100 Years
24C16, 2048 X 8 (16K bits)
Two-wire Serial Interface
8-lead PDIP, 8-lead SOP and 8-lead TSSOP Packages
Die Sales: Wafer Form, Waffle Pack
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
General Description
The
24C02/ 24C04/ 24C08/ 24C16 provides 2048/4096/8192/16384 bits of serial electrically erasable and
programmable read-only memory (EEPROM) organized as 256/512/1024/2048 words of 8 bits each. The device is
optimized for use in many industrial and commercial applications where low-power and low-voltage operation are
essential. The 24C02/ 24C04/ 24C08/ 24C16 is available in space-saving 8-lead PDIP, 8-lead SOP, and 8-lead
TSSOP packages and is accessed via a two-wire serial interface.
Pin Configuration
8-lead PDIP
8-lead SOP
8-lead TSSOP
C16 / C08 / C04 / C02
NC / NC / NC / A0
NC / NC / A1 / A1
NC / A2 / A2 / A2
C16 / C08 / C04 / C02
NC / NC / NC / A0
NC / NC / A1 / A1
NC / A2 / A2 / A2
GND
C16 / C08 / C04 / C02
NC / NC / NC / A0
NC / NC / A1 / A1
NC / A2 / A2 / A2
GND
1
2
3
4
8
7
6
5
VCC
1
2
3
4
8
7
6
5
VCC
1
2
3
4
8
7
6
5
VCC
WP
WP
WP
SCL
SDA
SCL
SDA
SCL
SDA
GND
Pin Descriptions
Table 1: Pin Configuration
Pin Designation
Type
Name and Functions
Address Inputs
A0 - A2
I
SDA
SCL
WP
Serial Data
Serial Clock Input
Write Protect
Ground
I/O & Open-drain
I
I
GND
P
V
CC
P
Power Supply
No Connect
NC
NC
BEIJING ESTEK ELECTRONICS CO.,LTD
1
24C02 / 24C04 / 24C08 / 24C16
Block Diagram
VCC
GND
WP
SCL
SDA
START STOP
LOGIC
EN
SERIAL CONTROL
LOGIC
HIGH VOLTAGE
PUMP/TIMING
LOAD
COMP
DATA RECOVERY
DEVICE ADDRESS
COMPARATOR
C16 / C08 / C04 / C02
NC / NC / NC / A0
NC / NC / A1 / A1
NC / A2 / A2 / A2
LOAD
INC
DATA WORD
ADDRESS COUNTER
EEPROM
Y DECODER
SERIAL MUX
DIN
DOUT/ACKNOWLEDGE
DOUT
BEIJING ESTEK ELECTRONICS CO.,LTD
2
24C02 / 24C04 / 24C08 / 24C16
Pin Descriptions
DEVICE/PAGE ADDRESSES (A2, A1 and A0): The A2, A1 and A0 pins are device address inputs that are hard
wired for the 24C02. Eight 2K devices may be addressed on a single bus system (device addressing is discussed in
detail under the Device Addressing section).
The 24C04 uses the A2 and A1 inputs for hard wire addressing and a total of four 4K devices may be addressed on a
single bus system. The A0 pin is a no connect and can be connected to ground.
The 24C08 only uses the A2 input for hardwire addressing and a total of two 8K devices may be addressed on a single
bus system. The A0 and A1 pins are no connects and can be connected to ground.
The 24C16 does not use the device address pins, which limits the number of devices on a single bus to one. The A0,
A1 and A2 pins are no connects and can be connected to ground.
SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven and may be
wire-ORed with any number of other open-drain or open- collector devices.
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative
edge clock data out of each device.
WRITE PROTECT (WP): The 24C02/ 24C04/ 24C08/ 24C16 has a Write Protect pin that provides hardware data
protection. The Write Protect pin allows normal read/write operations when connected to ground (GND). When the Write
Protect pin is connected to VCC, the write protection feature is enabled and operates as shown in the following Table 2.
Table 2: Write Protect
Part of the Array Protected
WP Pin Status
24C02
24C04
24C08
24C16
At VCC
Full (2K) Array
Full (4K) Array
Full (8K) Array
Full (16K) Array
At GND
Normal Read / Write Operations
Memory Organization
24C02, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each, the 2K requires an 8-bit data
word address for random word addressing.
24C04, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each, the 4K requires a 9-bit data
word address for random word addressing.
24C08, 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes each, the 8K requires a 10-bit data
word address for random word addressing.
24C16, 16K SERIAL EEPROM: Internally organized with 128 pages of 16 bytes each, the 16K requires an 11-bit
data word address for random word addressing.
BEIJING ESTEK ELECTRONICS CO.,LTD
3
24C02 / 24C04 / 24C08 / 24C16
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA
pin may change only during SCL low time periods (see to Figure 1 on page 4). Data changes during SCL high periods
will indicate a start or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other
command (see to Figure 2 on page 4).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop
command will place the EEPROM in a standby power mode (see Figure 2 on page 4).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The
EEPROM sends a "0" to acknowledge that it has received each word. This happens during the ninth clock cycle.
STANDBY MODE: The 24C02/ 24C04/ 24C08/ 24C16 features a low-power standby mode which is enabled: (a)
upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operations
MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be reset by
following these steps:
1. Clock up to 9 cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition.
Figure 1: Data Validity
SDA
SCL
DATA STABLE
DATA STABLE
DATA
CHANGE
Figure 2: Start and Stop Definition
SDA
SCL
START
STOP
BEIJING ESTEK ELECTRONICS CO.,LTD
4
24C02 / 24C04 / 24C08 / 24C16
Figure 3: Output Acknowledge
1
8
9
SCL
DATA IN
DATA OUT
START
ACKNOWLEDGE
Device Addressing
The 2K, 4K, 8K and 16K EEPROM devices all require an 8-bit device address word following a start condition to enable
the chip for a read or write operation (see to Figure 4 on page 7).
The device address word consists of a mandatory "1", "0" sequence for the first four most significant bits as shown.
This is common to all the Serial EEPROM devices.
The next 3 bits are the A2, A1 and A0 device address bits for the 2K EEPROM. These 3 bits must compare to their
corresponding hardwired input pins.
The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a memory page address bit. The
two device address bits must compare to their corresponding hardwired input pins. The A0 pin is no connect.
The 8K EEPROM only uses the A2 device address bit with the next 2 bits being for memory page addressing. The A2 bit
must compare to its corresponding hard-wired input pin. The A1 and A0 pins are no connect.
The 16K does not use any device address bits but instead the 3 bits are used for memory page addressing. These page
addressing bits on the 4K, 8K and 16K devices should be considered the most significant bits of the data word address
which follows. The A0, A1 and A2 pins are no connect.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high
and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a "0". If a compare is not made, the chip will return to a
standby state.
BEIJING ESTEK ELECTRONICS CO.,LTD
5
24C02 / 24C04 / 24C08 / 24C16
Write Operations
BYTE WRITE: A write operation requires an 8-bit data word address following the device address word and
acknowledgment. Upon receipt of this address, the EEPROM will again respond with a "0" and then clock in the first 8-
bit data word. Following receipt of the 8-bit data word, the EEPROM will output a "0" and the addressing device, such
as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an
internally timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the
EEPROM will not respond until the write is complete (see Figure 5 on page 7).
PAGE WRITE: The 2K EEPROM is capable of an 8-byte page write, and the 4K, 8K and 16K devices are capable of
16-byte page writes.
A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first
data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can
transmit up to seven (2K) or fifteen (4K, 8K, 16K) more data words. The EEPROM will respond with a "0" after each
data word received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 6 on
page 7).
The data word address lower three (2K) or four (4K, 8K, 16K) bits are internally incremented following the receipt of
each data word. The higher data word address bits are not incremented, retaining the memory page row location. When
the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the
same page. If more than eight (2K) or sixteen (4K, 8K, 16K) data words are transmitted to the EEPROM, the data word
address will "roll over" and previous data will be overwritten.
ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are disabled,
acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The
read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM
respond with a "0", allowing the read or write sequence to continue.
Read Operations
Read operations are initiated the same way as write operations with the exception that the read/write select bit in the
device address word is set to "1". There are three read operations: current address read, random address read and
sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during
the last read or write operation, incremented by one. This address stays valid between operations as long as the chip
power is maintained. The address "roll over" during read is from the last byte of the last memory page to the first byte
of the first page. The address "roll over" during write is from the last byte of the current page to the first byte of the
same page.
Once the device address with the read/write select bit set to "1" is clocked in and acknowledged by the EEPROM, the
current address data word is serially clocked out. The microcontroller does not respond with an input "0" but does
generate a following stop condition (see Figure 7 on page 8).
BEIJING ESTEK ELECTRONICS CO.,LTD
6
24C02 / 24C04 / 24C08 / 24C16
Read Operations
RANDOM READ: A random read requires a "dummy" byte write sequence to load in the data word address. Once the
device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller
must generate another start condition. The microcontroller now initiates a current address read by sending a device
address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the
data word. The microcontroller does not respond with a "0" but does generate a following stop condition (see Figure 8
on page 8).
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After
the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an
acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When
the memory address limit is reached, the data word address will "roll over" and the sequential read will continue. The
sequential read operation is terminated when the microcontroller does not respond with a "0" but does generate a
following stop condition (see Figure 9 on page 8).
Figure 4: Device Address
2K
4K
1
MSB
1
0
0
0
0
1
1
1
1
0
0
0
0
A2
A2
A2
P2
A1
A1
P1
P1
A0
P0
P0
P0
R/W
LSB
R/W
8K
1
1
R/W
R/W
16K
Figure 5: Byte Write
S
T
A
R
T
W
R
I
T
E
S
T
O
DEVICE
ADDRESS
WORD
ADDRESS
DATA
P
SDA LINE
M
S
B
L R AM
S / C S
BWKB
L A
SC
B K
A
C
K
Figure 6: Page Write
S
T
A
R
T
W
R
I
T
E
S
T
O
DEVICE
ADDRESS
WORD
ADDRESS(n)
DATA( n )
DATA( n+1 )
DATA( n+x )
P
SDA LINE
M
S
B
L R AM
S / C S
BWKB
L A
SC
B K
A
C
K
A
C
K
A
C
K
BEIJING ESTEK ELECTRONICS CO.,LTD
7
24C02 / 24C04 / 24C08 / 24C16
Figure 7: Current Address Read
S
T
A
R
T
R
E
A
D
S
T
O
DEVICE
ADDRESS
DATA
P
SDA LINE
N
O
M
S
B
L R A
S / C
BWK
A
C
K
Figure 8: Random Read
S
T
A
R
T
W
R
I
T
E
S
R
S
T
O
T
A
R
T
E
A
D
DEVICE
ADDRESS
WORD
ADDRESS(n)
DEVICE
ADDRESS
DATA( n )
P
SDA LINE
N
O
M
S
B
L R AM
S / C S
BWKB
L A
SC
B K
M
S
B
L R A
S / C
BWK
A
C
K
DUMMY WRITE
Figure 9: Sequential Read
R
E
A
D
S
T
O
P
DEVICE
ADDRESS
DATA( n )
DATA( n+1 )
DATA( n+2 )
DATA( n+x )
SDA LINE
N
O
R A
/ C
WK
A
C
K
A
C
K
A
C
K
A
C
K
BEIJING ESTEK ELECTRONICS CO.,LTD
8
24C02 / 24C04 / 24C08 / 24C16
Electrical Characteristics
Absolute Maximum Stress Ratings
Comments
Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to this device. These are stress
ratings only. Functional operation of this device at these or any
other conditions above those indicated in the operational sections
of this specification is not implied or intended. Exposure to the
absolute maximum rating conditions for extended periods may
affect device reliability.
DC Supply Voltage . . . . . . . . . . . . . . . . .-0.3V to +6.5V
Input / Output Voltage . . . . . . . .GND-0.3V to VCC+0.3V
。
。
Operating Ambient Temperature . . . . . -40 C to +85 C
。
。
Storage Temperature . . . . . . . . . . . . -65 C to +150 C
DC Electrical Characteristics
。
。
Applicable over recommended operating range from: T
A
= -40 C to +85 C, VCC = +1.8V to +5.5V (unless otherwise noted)
Parameter
Supply Voltage
Symbol
Min.
1.8
Typ.
-
Max.
5.5
Unit
V
Condition
VCC
Supply Current VCC = 5.0V
Supply Current VCC = 5.0V
Standby Current
I
I
CC1
CC2
-
0.4
1.0
3.0
mA
mA
A
READ at 100 kHz
WRITE at 100 kHz
-
2.0
I
SB
LI
LO
IL
IH
-
-
1.0
VIN = VCC or GND
VIN = VCC or GND
VOUT = VCC or GND
Input Leakage Current
Output Leakage Current
Input Low Level
I
-
-
3.0
A
I
-
0.05
3.0
A
V
-0.6
-
-
-
-
-
V
CC X 0.3
V
Input High Level
V
V
CC X 0.7
V
CC + 0.5
V
Output Low Level VCC =5.0V
Output Low Level VCC =3.0V
Output Low Level VCC =1.8V
V
V
V
OL3
OL2
OL1
-
-
-
0.4
V
IOL = 3.0 mA
IOL = 2.1 mA
IOL = 0.15 mA
0.4
V
0.2
V
Pin Capacitance
。
Applicable over recommended operating range from T = 25 C, f = 1.0 MHz, VCC = +1.8V
A
Parameter
Symbol
Min.
-
Typ.
-
Max.
8
Unit
pF
Condition
Input/Output Capacitance (SDA)
C
I/O
V
I/O = 0V
Input Capacitance (A0, A1, A2,
SCL)
C
IN
-
-
6
pF
VIN = 0V
BEIJING ESTEK ELECTRONICS CO.,LTD
9
24C02 / 24C04 / 24C08 / 24C16
AC Electrical Characteristics
。
。
Applicable over recommended operating range from T
100 pF (unless otherwise noted)
A
= -40 C to +85 C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and
1.8-volt
5.0-volt
Typ.
-
Parameter
Symbol
Units
Min.
-
Typ.
-
Max.
400
Min.
-
Max.
1000
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Noise Suppression Time
Clock Low to Data Out Valid
f
SCL
LOW
HIGH
kHz
t
1.2
0.6
-
-
-
-
-
-
-
0.6
0.4
-
-
-
-
-
-
-
s
s
s
s
t
t
I
50
0.9
40
0.55
0.05
t
AA
0.05
Time the bus must be free before
a new transmission can start
t
BUF
1.2
-
-
0.5
-
-
s
Start Hold Time
t
HD.STA
SU.STA
HD.DAT
SU.DAT
0.6
0.6
0
-
-
-
-
-
-
-
-
-
-
-
0.25
-
-
-
-
-
-
-
-
-
-
-
s
Start Setup Time
Data In Hold Time
Data In Setup Time
Inputs Rise Time(1)
Inputs Fall Time(1)
Stop Setup Time
Data Out Hold Time
Write Cycle Time
t
-
0.25
-
s
t
-
0
-
s
t
100
-
-
0.3
300
-
100
-
0.3
100
-
ns
t
R
-
s
t
F
-
-
0.25
50
-
ns
t
SU.STO
DH
WR
0.6
50
-
s
ns
t
-
-
t
5
5
ms
。
5.0V, 25 C, Byte Mode
Endurance
1M
-
-
-
Write Cycles
Note
1. This parameter is characterized and is not 100% tested.
2. AC measurement conditions:
RL (connects to VCC): 1.3 k (2.5V, 5V), 10 k (1.8V)
Input pulse voltages: 0.3 VCC to 0.7 VCC
Input rise and fall time: 50 ns
Input and output timing reference voltages: 0.5 VCC
The value of R should be concerned according to the actual loading
L
on the user's system.
BEIJING ESTEK ELECTRONICS CO.,LTD
10
24C02 / 24C04 / 24C08 / 24C16
Bus Timing
Figure 10: SCL: Serial Clock, SDA: Serial Data I/O
tHIGH
tF
tR
tLOW
tLOW
SCL
tSU.STA
tHD.STA
tHD.DAT
tSU.DAT
tSU.STO
SDA_IN
tAA
tDH
tBUF
SDA_OUT
Write Cycle Timing
Figure 11: SCL: Serial Clock, SDA: Serial Data I/O
SCL
8th BIT
ACK
SDA
(1)
tWR
STOP
START
CONDITION
CONDITION
Note
1. The write cycle time tWR is the time from a valid stop condition
of a write sequence to the end of the internal clear/write cycle.
BEIJING ESTEK ELECTRONICS CO.,LTD
11
24C02 / 24C04 / 24C08 / 24C16
Ordering Information
Code Number
Part Number
K
24
XXX
X
-
X
X
X
X
-
X
1
2
3
4
5
6
7
8
9
1.Prefix
4.Design Option
6. Temperature Range
8.Plating Technology
。
。
o= (Blank)
C = Com Temp(0 C-70 C)
Blank = Standard SnPb plating
G = ECOPACK(RoHS compliant)
2.Series Name
。
。
I = Ind Temp(-40 C-85 C)
5.Package Type
D = DIP
24: Two-wire (I2C) Interface
。
。
E = Exp Temp(-40 C-125 C)
9.Operating Voltage
S=2.7~5.5
3.EEPROM Density
C02=2K bits
S = SOP
7.Pack Type
T = Tube
R = TSSOP
W = Wafer/die
A=1.8~5.5
C04=4K bits
R = Tape & Reel
C08=8K bits
C16=16K bits
Product Datasheet Change Notice
Datasheet Revision History
Version
1.0
Content
Date
Datasheet
Jan., 2007
BEIJING ESTEK ELECTRONICS CO.,LTD
12
24C02 / 24C04 / 24C08 / 24C16
Disclaimers
The information in this publication has been carefully checked and is believed to be entirely accurate at
the time of publication. HHIE assumes no responsibility, however, for possible errors or omissions, or for
any consequences resulting from the use of the information contained herein.
HHIE reserves the right to make changes in its products or product specifications with the intent to
improve function or design at any time and without notice and is not required to update this
documentation to reflect such changes.
This publication does not convey to a purchaser of semiconductor devices described herein any license
under the patent rights of HHIE or others.
HHIE makes no warranty, representation, or guarantee regarding the suitability of its products for any
particular purpose, nor does HHIE assume any liability arising out of the application or use of any product
or circuit and specifically disclaims any and all liability, including without limitation any consequential or
incidental damages.
" Typ. " parameters can and do vary in different applications. All operating parameters, including " Typ. "
must be validated for each customer application by the customer's technical experts.
HHIE products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, for other applications intended to support or sustain life, or for any other
application in which the failure of the HHIE product could create a situation where personal injury or death
may occur.
Should the Buyer purchase or use a HHIE product for any such unintended or unauthorized application,
the Buyer shall indemnify and hold HHIE and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising
out of, either directly or indirectly, any claim of personal injury or death that may be associated with such
unintended or unauthorized use, even if such claim alleges that HHIE was negligent regarding the design
or manufacture of said product.
24C Series (I2C Bus) Serial EEPROM
Data Sheet, Revision 1.0
2007 HHIE
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or
transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or
otherwise, without the prior written consent of HHIE.
BEIJING ESTEK ELECTRONICS CO.,LTD
13
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SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
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