ESP32-C3FN4 [ESPRESSIF]
UltraLowPower SoC with RISCV SingleCore CPU Supporting 2.4 GHz WiFi and Bluetooth LE;
| 型号： | ESP32-C3FN4 |
| 厂家： | 
ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD. |
| 描述： | UltraLowPower SoC with RISCV SingleCore CPU Supporting 2.4 GHz WiFi and Bluetooth LE |
| 文件： | 总40页 (文件大小：619K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ESP32C3 Family
Datasheet
UltraLowPower SoC with RISCV SingleCore CPU
Supporting 2.4 GHz WiFi and Bluetooth LE
Including:
ESP32-C3
ESP32-C3FN4
ESP32-C3FH4
Prerelease version 0.6
Espressif Systems
Copyright © 2021
www.espressif.com
Product Overview
ESP32-C3 family is an ultra-low-power and highly-integrated MCU-based SoC solution that supports 2.4 GHz
Wi-Fi and Bluetooth® Low Energy (Bluetooth LE). It has:
• A complete Wi-Fi subsystem that complies with
IEEE 802.11b/g/n protocol and supports Station
mode, SoftAP mode, SoftAP + Station mode,
and promiscuous mode
SPI, and QPI interfaces that allow connection to
external flash
• Reliable security features ensured by
– Cryptographic hardware accelerators that
support AES-128/256, Hash, RSA, HMAC,
digital signature and secure boot
• A Bluetooth LE subsystem that supports features
of Bluetooth 5 and Bluetooth mesh
• State-of-the-art power and RF performance
– Random number generator
• 32-bit RISC-V single-core processor with a
four-stage pipeline that operates at up to 160
MHz
– Permission control on accessing internal
memory, external memory, and peripherals
– External memory encryption and decryption
• 400 KB of SRAM (16 KB for cache) and 384 KB
of ROM on the chip, and SPI, Dual SPI, Quad
• Rich set of peripheral interfaces and GPIOs, ideal
for various scenarios and complex applications
Block Diagram
Espressif’s ESP32-C3 Wi-Fi + BLE SoC
Main CPU
JTAG
ROM
WLAN
RF
BLE 5.0
link
RF receiver
Wi-Fi MAC
RISC-V
32-bit
Microprocessor
controller
Clock
generator
Cache
SRAM
BLE 5.0
Wi-Fi
baseband
baseband
RF
transmitter
Peripherals and Sensors
RTC
Switch
Balun
Embedded
I2C
PMU
RTC memory
flash
SPI
GPIO
I2S
UART
Cryptographic Hardware Acceleration
LED PWM
TWAI
ADC
SHA
AES
RSA
Timers
GDMA
RNG
HMAC
Digital signature
RMT
XTS-AES-128 flash encryption
Temperature sensor
Figure 1: Block Diagram of ESP32C3
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Features
Member Comparison)
WiFi
• SPI, Dual SPI, Quad SPI, and QPI interfaces that
allow connection to multiple external flash
• IEEE 802.11 b/g/n-compliant
• Supports 20 MHz, 40 MHz bandwidth in 2.4
GHz band
Advanced Peripheral Interfaces
• 1T1R mode with data rate up to 150 Mbps
• Wi-Fi Multimedia (WMM)
• 22 × programmable GPIOs
• 2 × 12-bit SAR ADCs, up to 6 channels
• 1 × temperature sensor
• 3 × SPI
• TX/RX A-MPDU, TX/RX A-MSDU
• Immediate Block ACK
• Fragmentation and defragmentation
• Transmit opportunity (TXOP)
• 2 × UART
• 1 × I2C
• Automatic Beacon monitoring (hardware TSF)
• 4 × virtual Wi-Fi interfaces
• 1 × I2S
• Remote control peripheral, with 2 transmit
channels and 2 receive channels
• Simultaneous support for Infrastructure BSS in
Station mode, SoftAP mode, Station + SoftAP
mode, and promiscuous mode
• LED PWM controller, up to 6 channels
Note that when ESP32-C3 family scans in Station
mode, the SoftAP channel will change along with
the Station channel
• General DMA controller, with 3 transmit channels
and 3 receive channels
• 1 × TWAITM controller (compatible with ISO
11898-1)
• Antenna diversity
• 802.11mc FTM
Low Power Management
Bluetooth
• Power Management Unit with five power modes
• Bluetooth LE: Bluetooth 5, Bluetooth mesh
• Speed: 125 Kbps, 500 Kbps, 1 Mbps, 2 Mbps
• Advertising extensions
Security
• Secure boot
• Flash encryption
• Multiple advertisement sets
• 4096-bit OTP, up to 1792 bits for users
• Cryptographic hardware acceleration:
– AES-128/256 (FIPS PUB 197)
• Permission Control
• Channel selection algorithm #2
CPU and Memory
• 32-bit RISC-V single-core processor, up to 160
MHz
• SHA Accelerator (FIPS PUB 180-4)
• RSA Accelerator
• 384 KB ROM
• 400 KB SRAM (16 KB for cache)
• 8 KB SRAM in RTC
• Random Number Generator (RNG)
• HMAC
• Embedded flash (see details in Chapter 1 Family
• Digital signature
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Applications (A Nonexhaustive List)
With ultra-low power consumption, ESP32-C3 family is an ideal choice for IoT devices in the following
areas:
• Smart Home
– Light control
– Wi-Fi and Bluetooth speaker
– Logger toys and proximity sensing toys
– Smart button
– Smart plug
• Smart Agriculture
– Smart greenhouse
– Smart irrigation
– Indoor positioning
• Industrial Automation
– Industrial robot
– Agriculture robot
• Retail and Catering
– Mesh network
– POS machines
– Human machine interface (HMI)
– Industrial field bus
• Health Care
– Service robot
• Audio Device
– Internet music players
– Live streaming devices
– Internet radio players
• Generic Low-power IoT Sensor Hubs
• Generic Low-power IoT Data Loggers
– Health monitor
– Baby monitor
• Consumer Electronics
– Smart watch and bracelet
– Over-the-top (OTT) devices
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Contents
Contents
Product Overview
Block Diagram
1
1
2
3
Features
Applications
1 Family Member Comparison
1.1 Family Nomenclature
8
8
8
1.2 Comparison
2 Pin Definition
2.1 Pin Layout
9
9
2.2 Pin Description
2.3 Power Scheme
2.4 Strapping Pins
9
11
12
3 Functional Description
3.1 CPU and Memory
15
15
15
15
15
16
16
17
17
17
17
17
17
17
17
18
18
19
19
19
19
19
20
20
20
20
21
21
3.1.1 CPU
3.1.2 Internal Memory
3.1.3 External Flash
3.1.4 Address Mapping Structure
3.1.5 Cache
3.2 System Clocks
3.2.1 CPU Clock
3.2.2 RTC Clock
3.3 Analog Peripherals
3.3.1 Analog-to-Digital Converter (ADC)
3.3.2 Temperature Sensor
3.4 Digital Peripherals
3.4.1 General Purpose Input / Output Interface (GPIO)
3.4.2 Serial Peripheral Interface (SPI)
3.4.3 Universal Asynchronous Receiver Transmitter (UART)
3.4.4 I2C Interface
3.4.5 I2S Interface
3.4.6 Remote Control Peripheral
3.4.7 LED PWM Controller
3.4.8 General DMA Controller
3.4.9 TWAITM Controller
3.5 Radio and Wi-Fi
3.5.1 2.4 GHz Receiver
3.5.2 2.4 GHz Transmitter
3.5.3 Clock Generator
3.5.4 Wi-Fi Radio and Baseband
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Contents
3.5.5 Wi-Fi MAC
21
22
22
22
22
23
23
23
23
24
24
24
25
3.5.6 Networking Features
3.6 Bluetooth LE
3.6.1 Bluetooth LE Radio and PHY
3.6.2 Bluetooth LE Link Layer Controller
3.7 Low Power Management
3.8 Timers
3.8.1 General Purpose Timers
3.8.2 System Timer
3.8.3 Watchdog Timers
3.9 Cryptographic Hardware Accelerators
3.10 Physical Security Features
3.11 Peripheral Pin Configurations
4 Electrical Characteristics
4.1 Absolute Maximum Ratings
4.2 Recommended Operating Conditions
4.3 VDD_SPI Output Characteristics
4.4 DC Characteristics (3.3 V, 25 °C)
4.5 ADC Characteristics
27
27
27
27
28
28
28
29
30
30
31
32
32
34
4.6 Current Consumption
4.7 Reliability
4.8 Wi-Fi Radio
4.8.1 Wi-Fi RF Transmitter (TX) Specifications
4.8.2 Wi-Fi RF Receiver (RX) Specifications
4.9 Bluetooth LE Radio
4.9.1 Bluetooth LE RF Transmitter (TX) Specifications
4.9.2 Bluetooth LE RF Receiver (RX) Specifications
5 Package Information
36
37
38
Revision History
Solutions, Documentation and Legal Information
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List of Tables
List of Tables
1
2
3
4
5
6
7
8
9
ESP32-C3 Family Member Comparison
8
9
Pin Description
Description of ESP32-C3 Family Power-up and Reset Timing Parameters
Strapping Pins
12
13
14
18
25
27
27
27
28
28
29
29
29
30
30
30
31
31
32
32
32
33
33
33
34
34
35
35
Parameter Descriptions of Setup and Hold Times for the Strapping Pin
Connection Between ESP32-C3 Family and External Flash
Peripheral Pin Configurations
Absolute Maximum Ratings
Recommended Operating Conditions
10 VDD_SPI Output Characteristics
11 DC Characteristics (3.3 V, 25 °C)
12 ADC Characteristics
13 Current Consumption Depending on RF Modes
14 Current Consumption Depending on Work Modes
15 Reliability Qualifications
16 Frequency
17 TX Power with Spectral Mask and EVM Meeting 802.11 Standards
18 TX EVM Test
19 RX Sensitivity
20 Maximum RX Level
21 RX Adjacent Channel Rejection
22 Transmitter General Characteristics
23 Transmitter Characteristics - Bluetooth LE 1M
24 Transmitter Characteristics - Bluetooth LE 2M
25 Transmitter Characteristics - Bluetooth LE 125K
26 Transmitter Characteristics - Bluetooth LE 500K
27 Receiver Characteristics - Bluetooth LE 1M
28 Receiver Characteristics - Bluetooth LE 2M
29 Receiver Characteristics - Bluetooth LE 125K
30 Receiver Characteristics - Bluetooth LE 500K
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List of Figures
List of Figures
1
2
3
4
5
6
7
8
Block Diagram of ESP32-C3
1
8
ESP32-C3 Family Nomenclature
ESP32-C3 Pin Layout (Top View)
ESP32-C3 Family Power Scheme
ESP32-C3 Family Power-up and Reset Timing
Setup and Hold Times for the Strapping Pin
Address Mapping Structure
9
11
12
13
16
36
QFN32 (5×5 mm) Package
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1
Family Member Comparison
1. Family Member Comparison
1.1 Family Nomenclature
ESP32-C3
F
Hꢀꢁ
x
Flash ꢀꢁꢂꢃꢄꢅꢆꢇꢈ
Flash temperature
H: High temperature
N: Normal temperature
Embedded flash
Chip family
Figure 2: ESP32C3 Family Nomenclature
1.2 Comparison
Table 1: ESP32C3 Family Member Comparison
Ordering Code
ESP32-C3
Embedded Flash Ambient Temperature (°C) Package (mm)
—
–40 ∼ 105
–40 ∼ 85
–40 ∼ 105
QFN32 (5*5)
QFN32 (5*5)
QFN32 (5*5)
ESP32-C3FN4
ESP32-C3FH4
4 MB
4 MB
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2
Pin Definition
2. Pin Definition
2.1 Pin Layout
LNA_IN
VDD3P3
1
2
3
4
5
6
7
8
24 SPIQ
23 SPID
VDD3P3
22 SPICLK
21 SPICS0
20 SPIWP
19 SPIHD
XTAL_32K_P
XTAL_32K_N
GPIO2
ESP32-C3 Family
CHIP_EN
GPIO3
18 VDD_SPI
17 VDD3P3_CPU
33 GND
Figure 3: ESP32C3 Pin Layout (Top View)
Table 2: Pin Description
2.2 Pin Description
Name
No.
1
Type
Power Domain Function
LNA_IN
I/O
PA
—
RF input and output
VDD3P3
VDD3P3
XTAL_32K_P
2
—
—
Analog power supply
Analog power supply
3
PA
4
I/O/T
VDD3P3_RTC
GPIO0, ADC1_CH0, XTAL_32K_P
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Pin Definition
Name
No.
5
Type
I/O/T
I/O/T
Power Domain Function
XTAL_32K_N
GPIO2
VDD3P3_RTC
VDD3P3_RTC
GPIO1, ADC1_CH1, XTAL_32K_N
6
GPIO2, ADC1_CH2, FSPIQ
High: on, enables the chip.
CHIP_EN
7
I
VDD3P3_RTC
Low: off, the chip powers off.
Note: Do not leave the CHIP_PU pin floating.
GPIO3, ADC1_CH3
GPIO3
8
I/O/T
I/O/T
I/O/T
PD
VDD3P3_RTC
VDD3P3_RTC
VDD3P3_RTC
—
MTMS
9
GPIO4, ADC1_CH4, FSPIHD,
GPIO5, ADC2_CH0, FSPIWP,
Input power supply for RTC
MTMS
MTDI
MTDI
10
11
12
13
14
15
16
VDD3P3_RTC
MTCK
I/O/T
I/O/T
I/O/T
I/O/T
I/O/T
PD
VDD3P3_CPU
VDD3P3_CPU
VDD3P3_CPU
VDD3P3_CPU
VDD3P3_CPU
—
GPIO6,
GPIO7,
GPIO8
GPIO9
GPIO10,
FSPICLK,
FSPID,
MTCK
MTDO
MTDO
GPIO8
GPIO9
GPIO10
FSPICS0
VDD3P3_CPU 17
Input power supply for CPU IO
VDD_SPI
SPIHD
SPIWP
SPICS0
SPICLK
SPID
18 I/O/T/PD
VDD3P3_CPU
VDD3P3_CPU
VDD3P3_CPU
VDD3P3_CPU
VDD3P3_CPU
VDD3P3_CPU
VDD3P3_CPU
VDD3P3_CPU
VDD3P3_CPU
VDD3P3_CPU
VDD3P3_CPU
—
GPIO11, output power supply for flash
GPIO12, SPIHD
GPIO13, SPIWP
GPIO14, SPICS0
GPIO15, SPICLK
GPIO16, SPID
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
I/O/T
I/O/T
I/O/T
I/O/T
I/O/T
I/O/T
I/O/T
I/O/T
I/O/T
I/O/T
—
SPIQ
GPIO17, SPIQ
GPIO18
GPIO19
U0RXD
U0TXD
XTAL_N
XTAL_P
VDDA
GPIO18
GPIO19
GPIO20, U0RXD
GPIO21, U0TXD
External crystal output
External crystal input
Analog power supply
Analog power supply
Ground
—
—
PA
—
VDDA
PA
—
GND
G
—
1
PA: analog power supply; PD: power supply for RTC IO; I: input; O: output; T: high impedance.
2
Ports of embedded flash correspond to pins of ESP32-C3FN4 and ESP32-C3FH4 as follows:
• CS# = SPICS0
• IO0/DI = SPID
• IO1/DO = SPIQ
• CLK = SPICLK
• IO2/WP# = SPIWP
• IO3/HOLD# = SPIHD
These pins are not recommended for other uses.
3
4
For the data port connection between ESP32-C3 family and external flash please refer to Section 3.4.2
Serial Peripheral Interface (SPI).
The pin function in this table refers only to some fixed settings and do not cover all cases for signals that
can be input and output through the GPIO matrix.
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Pin Definition
2.3 Power Scheme
Digital pins of ESP32-C3 family are divided into four different power domains:
• VDD3P3_CPU
• VDD_SPI
• VDD3P3_RTC
VDD3P3_CPU is the input power supply for CPU.
VDD_SPI can be an input power supply or an output power supply.
VDD3P3_RTC is the input power supply for RTC analog domain and CPU.
The power scheme diagram is shown in Figure 4.
VDD3P3_RTC
VDD3P3_CPU
LDO
LDO
1.1 V
RSPI
1.1 V
VDD_SPI
3.3 V
RTC
CPU
VDD_SPI
Domain
RTC IO
Domain
Domain
Figure 4: ESP32C3 Family Power Scheme
When working as an output power supply, VDD_SPI can be powered by VDD3P3_CPU via RSP I (nominal 3.3 V).
VDD_SPI can be powered off via software to minimize the current leakage of flash in Deep-sleep mode.
Notes on CHIP_PU:
Figure 5 shows the power-up and reset timing of ESP32-C3 family. Details about the parameters are listed in
Table 3.
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Pin Definition
t
t
0
1
2.8 V
VDDA,
VDD3P3,
VDD3P3_RTC,
VDD3P3_CPU
VIL_nRST
CHIP_PU
Figure 5: ESP32C3 Family Powerup and Reset Timing
Table 3: Description of ESP32C3 Family Powerup and Reset Timing Parameters
Min
(µs)
Parameter Description
Time between bringing up the VDDA, VDD3P3, VDD3P3_RTC, and
t0
t1
50
50
VDD3P3_CPU rails, and activating CHIP_PU
Duration of CHIP_PU signal level < VIL_nRST (refer to its value in
Table 11) to reset the chip
2.4 Strapping Pins
ESP32-C3 family has three strapping pins:
• GPIO8
• GPIO9
• GPIO10
Software can read the values of corresponding bits from the register ”GPIO_STRAPPING”.
During the chip’s system reset, the latches of the strapping pins sample the voltage level as strapping bits of ”0”
or ”1”, and hold these bits until the chip is powered down or shut down.
Types of system reset include:
• power-on-reset
• RTC watchdog reset
• brownout reset
• analog super watchdog reset
• crystal clock glitch detection reset
By default GPIO9 is connected to the chip’s internal pull-up. Consequently, if GPIO9 is unconnected or the
connected external circuit is high-impedance, the internal weak pull-up/pull-down will determine its default input
level.
To change the strapping bit values, you can apply the external pull-down/pull-up resistances, or use the host
MCU’s GPIOs to control the voltage level of these pins when powering on ESP32-C3 family.
After reset, the strapping pins work as normal-function pins.
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Pin Definition
Refer to Table 4 for a detailed boot-mode configuration of the strapping pins.
Table 4: Strapping Pins
Booting Mode 1
Pin
Default
N/A
SPI Boot
Don’t care
1
Download Boot
GPIO8
GPIO9
1
0
Pull-up
Enabling/Disabling ROM Code Print During Booting
Functionality
Pin
Default
N/A
When the value of eFuse bit UART_PRINT_CONTROL is
0, print is enabled and not controlled by GPIO8.
1, if GPIO8 is 0, print is enabled; if GPIO8 is 1, it is disabled.
2, if GPIO8 is 0, print is disabled; if GPIO8 is 1, it is enabled.
3, print is disabled and not controlled by GPIO8.
Controlling JTAG Signal Source During Booting
Functionality
GPIO8
Pin
Default
When the value of eFuse bit EFUSE_JTAG_SEL_ENABLE is
0, JTAG signals cannot be used.
GPIO10 N/A
1, if GPIO10 is 0, JTAG signals come from chip pins;
if GPIO10 is 1, JTAG signals cannot be used.
1
The strapping combination of GPIO8 = 0 and GPIO9 = 0 is invalid and will trigger unexpected
behavior.
Figure 6 shows the setup and hold times for the strapping pin before and after the CHIP_PU signal goes high.
Details about the parameters are listed in Table 5.
t
t
0
1
VIL_nRST
CHIP_PU
VIH
Strapping pin
Figure 6: Setup and Hold Times for the Strapping Pin
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Pin Definition
Table 5: Parameter Descriptions of Setup and Hold Times for the Strapping Pin
Min
(ms)
Parameter
Description
t0
t1
Setup time before CHIP_PU goes from low to high
Hold time after CHIP_PU goes high
0
3
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Functional Description
3. Functional Description
This chapter describes the functions of ESP32-C3 family.
3.1 CPU and Memory
3.1.1 CPU
ESP32-C3 family has a low-power 32-bit RISC-V single-core microprocessor with the following features:
• four-stage pipeline that supports a clock frequency of up to 160 MHz
• RV32IMC ISA
• 32-bit multiplier and 32-bit divider
• up to 32 vectored interrupts at seven priority levels
• up to 8 hardware breakpoints/watchpoints
• up to 16 PMP regions
• JTAG for debugging
3.1.2 Internal Memory
ESP32-C3’s internal memory includes:
• 384 KB of ROM: for booting and core functions.
• 400 KB of onchip SRAM: for data and instructions. Of the 400 KB SRAM, 16 KB is configured for cache
• RTC memory: 8 KB of SRAM that can be accessed by the main CPU. It can retain data in Deep-sleep
mode.
• 4 Kbit of eFuse: 1792 bits are reserved for user data, such as encryption key and device ID.
• Embedded flash : See details in Chapter 1 Family Member Comparison.
3.1.3 External Flash
ESP32-C3 family supports SPI, Dual SPI, Quad SPI, and QPI interfaces that allow connection to multiple external
flash.
CPU’s instruction memory space and read-only data memory space can map into external flash of ESP32-C3,
whose size can be 16 MB at most. ESP32-C3 family supports hardware encryption/decryption based on
XTS-AES to protect developers’ programs and data in flash.
Through high-speed caches, ESP32-C3 family can support at a time up to:
• 8 MB of instruction memory space which can map into flash as individual blocks of 64 KB. 8-bit, 16-bit and
32-bit reads are supported.
• 8 MB of data memory space which can map into flash as individual blocks of 64 KB. 8-bit, 16-bit and
32-bit reads are supported.
Note:
After ESP32-C3 family is initialized, software can customize the mapping of external RAM into the CPU address space.
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Functional Description
3.1.4 Address Mapping Structure
0x0000_0000
0x3BFF_FFFF
0x3C00_0000
0x3C7F_FFFF
0x3C80_0000
0x3FC7_FFFF
0x3FC8_0000
0x3FCD_FFFF
0x3FCE_0000
0x3FEF_FFFF
cache
0x3FF0_0000
0x3FF1_FFFF
0x3FF2_0000
0x3FFF_FFFF
0x4000_0000
0x4005_FFFF
Internal Memory
GDMA
0x4006_0000
0x4037_BFFF
MMU
External Memory
0x4037_C000
0x403D_FFFF
0x403E_0000
0x41FF_FFFF
0x4200_0000
0x427F_FFFF
0x4280_0000
0x4FFF_FFFF
0x5000_0000
0x5000_1FFF
0x5002_0000
0x5FFF_FFFF
0x6000_0000
0x600D_0FFF
Peripheral
0x600D_1000
0xFFFF_FFFF
Figure 7: Address Mapping Structure
Note:
The memory space with gray background is not available for use.
3.1.5 Cache
ESP32-C3 family has an eight-way set associative cache. This cache is read-only and has the following
features:
• size: 16 KB
• block size: 32 bytes
• pre-load function
• lock function
• critical word first and early restart
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Functional Description
3.2 System Clocks
3.2.1 CPU Clock
The CPU clock has three possible sources:
• external main crystal clock
• internal 20 MHz oscillator
• PLL clock
The application can select the clock source from the three clocks above. The selected clock source drives the
CPU clock directly, or after division, depending on the application.
3.2.2 RTC Clock
The RTC slow clock is used for RTC counter, RTC watchdog and low-power controller. It has three possible
sources:
• external low-speed (32 kHz) crystal clock
• internal RC oscillator (typically about 150 kHz, and adjustable)
• internal 78.125 kHz clock (derived from the internal 20 MHz oscillator divided by 256)
The RTC fast clock is used for RTC peripherals and sensor controllers. It has two possible sources:
• external main crystal clock divided by 2
• internal 20 MHz oscillator
3.3 Analog Peripherals
3.3.1 AnalogtoDigital Converter (ADC)
ESP32-C3 family integrates two 12-bit SAR ADCs and supports measurements on 6 channels (analog-enabled
pins).
3.3.2 Temperature Sensor
The temperature sensor generates a voltage that varies with temperature. The voltage is internally converted via
an ADC into a digital value.
The temperature sensor has a range of –40 °C to 125 °C. It is designed primarily to sense the temperature
changes inside the chip. The temperature value depends on factors like microcontroller clock frequency or I/O
load. Generally, the chip’s internal temperature is higher than the ambient temperature.
3.4 Digital Peripherals
3.4.1 General Purpose Input / Output Interface (GPIO)
ESP32-C3 family has 22 GPIO pins which can be assigned various functions by configuring corresponding
registers. Besides digital signals, some GPIOs can be also used for analog functions, such as ADC.
All GPIOs have selectable internal pull-up or pull-down, or can be set to high impedance. When these GPIOs are
configured as an input, the input value can be read by software through the register. Input GPIOs can also be set
to generate edge-triggered or level-triggered CPU interrupts. All digital IO pins are bi-directional, non-inverting
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and tristate, including input and output buffers with tristate control. These pins can be multiplexed with other
functions, such as the UART, SPI, etc. For low-power operations, the GPIOs can be set to holding state.
The IO MUX and the GPIO matrix are used to route signals from peripherals to GPIO pins. Together they provide
highly configurable I/O. Using GPIO Matrix, peripheral input signals can be configured from any IO pins while
peripheral output signals can be configured to any IO pins.
3.4.2 Serial Peripheral Interface (SPI)
ESP32-C3 family features three SPI interfaces (SPI0, SPI1, and SPI2). SPI0 and SPI1 can only be configured to
operate in SPI memory mode, while SPI2 can be configured to operate in both SPI memory and general-purpose
SPI modes.
• SPI Memory mode
In SPI memory mode, SPI0, SPI1 and SPI2 interface with external SPI memory. Data is transferred in bytes.
Up to four-line STR reads and writes are supported. The clock frequency is configurable to a maximum of
120 MHz in STR mode.
• SPI2 Generalpurpose SPI (GPSPI) mode
When SPI2 acts as a general-purpose SPI, it can operate in master and slave modes. SPI2 supports
two-line full-duplex communication and single-/two-/four-line half-duplex communication in both master
and slave modes. The host’s clock frequency is configurable. Data is transferred in bytes. The clock
polarity (CPOL) and phase (CPHA) are also configurable. The SPI2 interface can connect to GDMA.
– In two-line full-duplex mode, the clock frequency of host and slave is configurable to 80 MHz at most.
Four modes of SPI transfer format are supported.
– In single-/two-/four-line half-duplex mode, the host’s clock frequency is configurable to 80 MHz at
most and the four modes of SPI transfer format are supported.
– In single-/two-/four-line half-duplex mode, the slave’s clock frequency is configurable to 60 MHz at
most, and the four modes of SPI transfer format are also supported.
In most cases, the data port connection between ESP32-C3 family and external flash is as follows:
Table 6: Connection Between ESP32C3 Family and External Flash
External Flash Data Port
Chip Pin
SPI SingleLine Mode SPI TwoLine Mode SPI FourLine Mode
SPID (SPID)
DI
DO
IO0
IO1
—
IO0
IO1
IO2
IO3
SPIQ (SPIQ)
SPIWP (SPIWP)
SPIHD (SPIHD)
WP#
HOLD#
—
3.4.3 Universal Asynchronous Receiver Transmitter (UART)
ESP32-C3 family has two UART interfaces, i.e. UART0 and UART1, which support IrDA and asynchronous
communication (RS232 and RS485) at a speed of up to 5 Mbps. The UART controller provides hardware flow
control (CTS and RTS signals) and software flow control (XON and XOFF). Both UART interfaces connect to
GDMA via UHCI0, and can be accessed by the GDMA controller or directly by the CPU.
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3.4.4 I2C Interface
ESP32-C3 family has an I2C bus interface which is used for I2C master mode or slave mode, depending on the
user’s configuration. The I2C interface supports:
• standard mode (100 Kbit/s)
• fast mode (400 Kbit/s)
• up to 800 Kbit/s (constrained by SCL and SDA pull-up strength)
• 7-bit and 10-bit addressing mode
• double addressing mode
• 7-bit broadcast address
Users can configure instruction registers to control the I2C interface for more flexibility.
3.4.5 I2S Interface
ESP32-C3 family includes a standard I2S interface. This interface can operate as a master or a slave in
full-duplex mode or half-duplex mode, and can be configured for 8-bit, 16-bit, 24-bit, or 32-bit serial
communication. BCK clock frequency, from 10 kHz up to 40 MHz, is supported.
The I2S interface supports TDM PCM, TDM MSB alignment, TDM standard, and PDM TX interface. It connects
to the GDMA controller.
3.4.6 Remote Control Peripheral
The Remote Control Peripheral (RMT) supports two channels of infrared remote transmission and two channels
of infrared remote reception. By controlling pulse waveform through software, it supports various infrared and
other single wire protocols. All four channels share a 192 × 32-bit memory block to store transmit or receive
waveform.
3.4.7 LED PWM Controller
The LED PWM controller can generate independent digital waveform on six channels. The LED PWM
controller:
• can generate digital waveform with configurable periods and duty cycle. The accuracy of duty cycle can be
up to 18 bits.
• has multiple clock sources, including APB clock and external main crystal clock.
• can operate when the CPU is in Light-sleep mode.
• supports gradual increase or decrease of duty cycle, which is useful for the LED RGB color-gradient
generator.
3.4.8 General DMA Controller
ESP32-C3 family has a general DMA controller (GDMA) with six independent channels, i.e. three transmit
channels and three receive channels. These six channels are shared by peripherals with DMA feature, and
support dynamic priority.
The GDMA controller controls data transfer using linked lists. It allows peripheral-to-memory and
memory-to-memory data transfer at a high speed. All channels can access internal RAM.
Peripherals on ESP32-C3 family with DMA feature are SPI2, UHCI0, I2S, AES, SHA, and ADC.
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3.4.9 TWAITM Controller
ESP32-C3 family has a TWAITM controller with the following features:
• compatible with ISO 11898-1 protocol
• standard frame format (11-bit ID) and extended frame format (29-bit ID)
• bit rates from 1 Kbit/s to 1 Mbit/s
• multiple modes of operation: Normal, Listen Only, and Self-Test (no acknowledgment required)
• 64-byte receive FIFO
• acceptance filter (single and dual filter modes)
• error detection and handling: error counters, configurable error interrupt threshold, error code capture,
arbitration lost capture
3.5 Radio and WiFi
The ESP32-C3 family radio consists of the following blocks:
• 2.4 GHz receiver
• 2.4 GHz transmitter
• bias and regulators
• balun and transmit-receive switch
• clock generator
3.5.1 2.4 GHz Receiver
The 2.4 GHz receiver demodulates the 2.4 GHz RF signal to quadrature baseband signals and converts them to
the digital domain with two high-resolution, high-speed ADCs. To adapt to varying signal channel conditions,
ESP32-C3 family integrates RF filters, Automatic Gain Control (AGC), DC offset cancelation circuits, and
baseband filters.
3.5.2 2.4 GHz Transmitter
The 2.4 GHz transmitter modulates the quadrature baseband signals to the 2.4 GHz RF signal, and drives the
antenna with a high-powered CMOS power amplifier. The use of digital calibration further improves the linearity of
the power amplifier.
Additional calibrations are integrated to cancel any radio imperfections, such as:
• carrier leakage
• I/Q amplitude/phase matching
• baseband nonlinearities
• RF nonlinearities
• antenna matching
These built-in calibration routines reduce the cost, time, and specialized equipment required for product
testing.
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3.5.3 Clock Generator
The clock generator produces quadrature clock signals of 2.4 GHz for both the receiver and the transmitter. All
components of the clock generator are integrated into the chip, including inductors, varactors, filters, regulators
and dividers.
The clock generator has built-in calibration and self-test circuits. Quadrature clock phases and phase noise are
optimized on chip with patented calibration algorithms which ensure the best performance of the receiver and the
transmitter.
3.5.4 WiFi Radio and Baseband
The ESP32-C3 family Wi-Fi radio and baseband support the following features:
• 802.11b/g/n
• 802.11n MCS0-7 that supports 20 MHz and 40 MHz bandwidth
• 802.11n MCS32
• 802.11n 0.4 µs guard interval
• data rate up to 150 Mbps
• RX STBC (single spatial stream)
• adjustable transmitting power
• antenna diversity
ESP32-C3 family supports antenna diversity with an external RF switch. This switch is controlled by one or
more GPIOs, and used to select the best antenna to minimize the effects of channel imperfections.
3.5.5 WiFi MAC
ESP32-C3 family implements the full 802.11 b/g/n Wi-Fi MAC protocol. It supports the Basic Service Set (BSS)
STA and SoftAP operations under the Distributed Control Function (DCF). Power management is handled
automatically with minimal host interaction to minimize the active duty period.
The ESP32-C3 family Wi-Fi MAC applies the following low-level protocol functions automatically:
• 4 × virtual Wi-Fi interfaces
• infrastructure BSS in Station mode, SoftAP mode, Station + SoftAP mode, and promiscuous mode
• RTS protection, CTS protection, Immediate Block ACK
• fragmentation and defragmentation
• TX/RX A-MPDU, TX/RX A-MSDU
• transmit opportunity (TXOP)
• Wi-Fi multimedia (WMM)
• GCMP, CCMP, TKIP, WAPI, WEP, BIP, WPA2-PSK/WPA2-Enterprise, and WPA3-PSK/WPA3-Enterprise
• automatic beacon monitoring (hardware TSF)
• 802.11mc FTM
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3.5.6 Networking Features
Espressif provides libraries for TCP/IP networking, ESP-WIFI-MESH networking, and other networking protocols
over Wi-Fi. TLS 1.0, 1.1 and 1.2 is also supported.
3.6 Bluetooth LE
ESP32-C3 family includes a Bluetooth Low Energy subsystem that integrates a hardware link layer controller, an
RF/modem block and a feature-rich software protocol stack. It supports the core features of Bluetooth 5 and
Bluetooth mesh.
3.6.1 Bluetooth LE Radio and PHY
Bluetooth Low Energy radio and PHY in ESP32-C3 family support:
• 1 Mbps PHY
• 2 Mbps PHY for high transmission speed and high data throughput
• coded PHY for high RX sensitivity and long range (125 Kbps and 500 Kbps)
• listen before talk (LBT), implemented in hardware
• antenna diversity with an external RF switch
This switch is controlled by one or more GPIOs, and used to select the best antenna to minimize the effects
of channel imperfections.
3.6.2 Bluetooth LE Link Layer Controller
Bluetooth Low Energy Link Layer Controller in ESP32-C3 family support:
• LE advertising extensions, to enhance broadcasting capacity and broadcast more intelligent data
• multiple advertisement sets
• simultaneous advertising and scanning
• multiple connections in simultaneous central and peripheral roles
• adaptive frequency hopping and channel assessment
• LE channel selection algorithm #2
• connection parameter update
• high duty cycle non-connectable advertising
• LE privacy 1.2
• LE data packet length extension
• link layer extended scanner filter policies
• low duty cycle directed advertising
• link layer encryption
• LE Ping
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3.7 Low Power Management
With the use of advanced power-management technologies, ESP32-C3 family can switch between different
power modes.
• Active mode: CPU and chip radio are powered on. The chip can receive, transmit, or listen.
• Modem-sleep mode: The CPU is operational and the clock speed can be reduced. Wi-Fi base band,
Bluetooth LE base band, and radio are disabled, but Wi-Fi and Bluetooth LE connection can remain active.
• Light-sleep mode: The CPU is paused. Any wake-up events (MAC, host, RTC timer, or external interrupts)
will wake up the chip. Wi-Fi and Bluetooth LE connection can remain active.
• Deep-sleep mode: CPU and most peripherals are powered down. Only the RTC memory is powered on.
Wi-Fi connection data are stored in the RTC memory.
• Hibernation mode: The internal 20-MHz oscillator is disabled. Only one RTC timer on the slow clock is
active. The RTC timer or the RTC GPIOs can wake up the chip from the Hibernation mode.
3.8 Timers
3.8.1 General Purpose Timers
ESP32-C3 family is embedded with two 54-bit general-purpose timers, which are based on 16-bit prescalers
and 54-bit auto-reload-capable up/down-timers.
The timers’ features are summarized as follows:
• a 16-bit clock prescaler, from 1 to 65536
• a 54-bit time-base counter programmable to be incrementing or decrementing
• able to read real-time value of the time-base counter
• halting and resuming the time-base counter
• programmable alarm generation
• level interrupt generation
3.8.2 System Timer
ESP32-C3 family integrates a 52-bit system timer, which has two 52-bit counters and three comparators. The
system timer has the following features:
• counters with a fixed clock frequency of 16 MHz
• three types of independent interrupts generated according to alarm value
• two alarm modes: target mode and period mode
• 52-bit target alarm value and 26-bit periodic alarm value
• automatic reload of counter value
• counters can be stalled if the CPU is stalled or in OCD mode
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3.8.3 Watchdog Timers
The ESP32-C3 family contains three watchdog timers: one in each of the two timer groups (called Main System
Watchdog Timers, or MWDT) and one in the RTC module (called the RTC Watchdog Timer, or RWDT).
During the flash boot process, RWDT and the MWDT in timer group 0 (TIMG0) are enabled automatically in order
to detect and recover from booting errors.
Watchdog timers have the following features:
• four stages, each with a programmable timeout value. Each stage can be configured, enabled and
disabled separately
• interrupt, CPU reset, or core reset for MWDT upon expiry of each stage; interrupt, CPU reset, core reset, or
system reset for RWDT upon expiry of each stage
• 32-bit expiry counter
• write protection, to prevent RWDT and MWDT configuration from being altered inadvertently
• flash boot protection
If the boot process from an SPI flash does not complete within a predetermined period of time, the
watchdog will reboot the entire main system.
3.9 Cryptographic Hardware Accelerators
ESP32-C3 family is equipped with hardware accelerators of general algorithms, such as AES-128/AES-256 (FIPS
PUB 197), ECB/CBC/OFB/CFB/CTR (NIST SP 800-38A), SHA1/SHA224/SHA256 (FIPS PUB 180-4), RSA3072,
and ECC. The chip also supports independent arithmetic, such as Big Integer Multiplication and Big Integer
Modular Multiplication. The maximum operation length for RSA and Big Integer Modular Multiplication is 3072
bits. The maximum factor length for Big Integer Multiplication is 1536 bits.
3.10 Physical Security Features
• transparent external flash encryption (AES-XTS algorithm) with software inaccessible key prevents
unauthorized readout of user application code or data.
• secure boot feature uses a hardware root of trust to ensure only signed firmware (with RSA-PSS signature)
can be booted.
• HMAC module can use a software inaccessible MAC key to generate MAC signatures for identity
verification and other purposes.
• Digital Signature module can use a software inaccessible secure key to generate RSA signatures for identity
verification.
• World Controller provides two running environments for software. All hardware and software resources are
sorted to two groups, and placed in either secure or general world. The secure world cannot be accessed
by hardware in the general world, thus establishing a security boundary.
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3.11 Peripheral Pin Configurations
Table 7: Peripheral Pin Configurations
Interface
Signal
Pin
Function
ADC
ADC1_CH0
ADC1_CH1
ADC1_CH2
ADC1_CH3
ADC1_CH4
ADC2_CH0
MTDI
XTAL_32K_P
XTAL_32K_N
GPIO2
GPIO3
MTMS
MTDI
Two 12-bit SAR ADCs
JTAG
UART
MTDI
JTAG for software debugging
MTCK
MTCK
MTMS
MTMS
MTDO
MTDO
U0RXD_in
Any GPIO pins Two UART channels with hardware flow control
and GDMA
U0CTS_in
U0DSR_in
U0TXD_out
U0RTS_out
U0DTR_out
U1RXD_in
U1CTS_in
U1DSR_in
U1TXD_out
U1RTS_out
U1DTR_out
I2CEXT0_SCL_in
I2CEXT0_SDA_in
I2CEXT1_SCL_in
I2CEXT1_SDA_in
I2CEXT0_SCL_out
I2CEXT0_SDA_out
I2CEXT1_SCL_out
I2CEXT1_SDA_out
ledc_ls_sig_out0~5
I2S0O_BCK_in
I2S_MCLK_in
I2SO_WS_in
I2SI_SD_in
I2C
Any GPIO pins One I2C channel in slave or master mode
LED PWM
I2S
Any GPIO pins Six independent PWM channels
Any GPIO pins Stereo input and output from/to the audiocodec
I2SI_BCK_in
I2SI_WS_in
I2SO_BCK_out
I2S_MCLK_out
I2SO_WS_out
I2SO_SD_out
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Interface
Signal
Pin
Function
I2SI_BCK_out
I2SI_WS_out
I2SO_SD1_out
Remote Control RMT_SIG_IN0~1
Any GPIO pins Two channels for an IR transceiver of various
waveforms
Peripheral
SPI0/1
RMT_SIG_OUT0~1
SPICLK_out_mux
SPICS0_out
SPICLK
SPICS0
Any GPIO pins
SPID
Support Standard SPI, Dual SPI, Quad SPI, and
QPI that allow connection to external flash
SPICS1_out
SPID_in/_out
SPIQ_in/_out
SPIQ
SPIWP_in/_out
SPIHD_in/_out
SPIWP
SPIHD
• Master mode and slave mode of SPI, Dual
SPI, Quad SPI, and QPI
SPI2
FSPICLK_in/_out_mux Any GPIO pins
FSPICS0_in/_out
• Connection to external flash, RAM, and
other SPI devices
FSPICS1~5_out
FSPID_in/_out
• Four modes of SPI transfer format
• Configurable SPI frequency
• 64-byte FIFO or GDMA buffer
FSPIQ_in/_out
FSPIWP_in/_out
FSPIHD_in/_out
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Electrical Characteristics
4. Electrical Characteristics
4.1 Absolute Maximum Ratings
Stresses beyond the absolute maximum ratings listed in the table below may cause permanent damage to the
device. These are stress ratings only, and do not refer to the functional operation of the device.
Table 8: Absolute Maximum Ratings
Symbol
Parameter
Min
–0.3
–40
Max
3.6
Unit
V
VDDA, VDD3P3, VDD3P3_RTC, Voltage applied to power supply pins
VDD3P3_CPU, VDD_SPI
TST ORE
per power domain
Storage temperature
150
°C
4.2 Recommended Operating Conditions
Table 9: Recommended Operating Conditions
Parameter Min
Symbol
Typ
Max
Unit
VDDA, VDD3P3
VDD3P3_RTC
Voltage applied to power supply
pins per power domain
3.0
3.0
3.3
3.3
3.6
V
VDD_SPI (working as
input power supply)1
VDD3P3_CPU2
—
3.6
V
Voltage applied to power supply pin
3.0
0.5
3.3
—
3.6
—
V
A
3
IV DD
Current delivered by external power supply
ESP32-C3
Ambient
105
85
TA
ESP32-C3FN4
temperature
–40
—
°C
ESP32-C3FH4
105
1
For more information, please refer to Section 2.3 Power Scheme.
2
When VDD_SPI is used to drive peripherals, VDD3P3_CPU should comply with the peripherals’ specifica-
tions. For more information, please refer to Table 10.
3
If you use a single power supply, the recommended output current is 500 mA or more.
4.3 VDD_SPI Output Characteristics
Table 10: VDD_SPI Output Characteristics
Symbol
Parameter
On-resistance in 3.3 V mode
Typ
7.5
Unit
RSP I
Ω
In real-life applications, when VDD_SPI works in 3.3 V output mode, VDD3P3_CPU may be affected
by RSP I. For example, when VDD3P3_CPU is used to drive a 3.3 V flash, it should comply with the
following specifications:
VDD3P3_CPU > VDD_flash_min + I_flash_max*RSP I
Among which, VDD_flash_min is the minimum operating voltage of the flash, and I_flash_max the
maximum current.
For more information, please refer to section 2.3 Power Scheme.
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4.4 DC Characteristics (3.3 V, 25 °C)
Table 11: DC Characteristics (3.3 V, 25 °C)
Symbol
CIN
VIH
VIL
Parameter
Min
Typ
Max
Unit
pF
V
Pin capacitance
—
2
—
High-level input voltage
Low-level input voltage
High-level input current
Low-level input current
High-level output voltage
Low-level output voltage
High-level source current (VDD1= 3.3 V,
VOH >= 2.64 V, PAD_DRIVER = 3)
Low-level sink current (VDD1= 3.3 V, VOL
0.495 V, PAD_DRIVER = 3)
Pull-up resistor
0.75 × VDD1
—
—
—
—
—
—
VDD1+ 0.3
0.25 × VDD1
–0.3
V
IIH
—
50
50
nA
nA
V
IIL
—
0.8 × VDD1
—
2
VOH
—
2
VOL
0.1 × VDD1
V
IOH
IOL
—
—
40
28
—
—
mA
mA
=
RP U
RP D
—
—
45
45
—
—
—
—
kΩ
kΩ
V
Pull-down resistor
VIH_nRST Chip reset release voltage
0.75 × VDD1
VDD1+ 0.3
0.25 × VDD1
VIL_nRST Chip reset voltage
–0.3
V
1
VDD is the I/O voltage for a particular power domain of pins.
VOH and VOL are measured using high-impedance load.
2
4.5 ADC Characteristics
Table 12: ADC Characteristics
Symbol
Parameter
Min
–7
–12
Max
Unit
ADC connected to an external
DNL (Differential nonlinearity)1
7
LSB
LSB
100 nF capacitor; DC signal input;
ambient temperature at 25 °C;
INL (Integral nonlinearity)
Sampling rate
12
Wi-Fi off
—
—
0
2
750
Msps
mV
ATTEN0
ATTEN1
ATTEN2
ATTEN3
0
1050
1300
2500
mV
Effective Range
0
mV
0
mV
1
To get better DNL results, you can sample multiple times and apply a filter, or calculate the average value.
4.6 Current Consumption
The current consumption measurements are taken with a 3.3 V supply at 25 °C of ambient temperature at the RF
port. All transmitters’ measurements are based on a 100% duty cycle.
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Table 13: Current Consumption Depending on RF Modes
Description
802.11b, 1 Mbps, @21 dBm
Peak
(mA)
325
272
260
262
84
Work mode
802.11g, 54 Mbps, @19 dBm
802.11n, HT20, MCS 7, @18.5 dBm
802.11n, HT40, MCS 7, @18.5 dBm
802.11b/g/n, HT20
TX
Active (RF working)
RX
802.11n, HT40
87
Table 14: Current Consumption Depending on Work Modes
Description
Work mode
Typ
20
15
130
5
Unit
mA
mA
µA
The CPU is
160 MHz
Modem-sleep1, 2
powered on3 Normal speed: 80 MHz
Light-sleep
Deep-sleep
Power off
1
—
RTC timer + RTC memory
µA
CHIP_PU is set to low level, the chip is powered off
1
µA
The current consumption figures in Modem-sleep mode are for cases where the CPU is powered on and
the cache idle.
2
3
When Wi-Fi is enabled, the chip switches between Active and Modem-sleep modes. Therefore, current
consumption changes accordingly.
In Modem-sleep mode, the CPU frequency changes automatically. The frequency depends on the CPU
load and the peripherals used.
4.7 Reliability
Table 15: Reliability Qualifications
Reliability test
Standard
Test conditions
Result
Electro-Static Discharge Sensitivity
(ESD), Charge Device Mode (CDM)1
Electro-Static Discharge Sensitivity
(ESD), Human Body Mode (HBM)2
JEDEC EIA/JESD22-C101 ±1000 V, all pins
Pass
JEDEC EIA/JESD22-A114
JEDEC STANDARD NO.78
JEDEC STANDARD NO.78
J-STD-020, MSL 3
±2000 V, all pins
Pass
Pass
Pass
Pass
±50 mA ~ ±200 mA, room
temperature, test for IO
1.5 × VDDmax, room
Latch-up (Over-current test)
Latch-up (Over-voltage test)
temperature, test for Vsupply
30 °C, 60% RH, 192 hours,
IR × 3 @260 °C
Moisture Sensitivity Level (MSL)
1
JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control
process.
2
JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control
process.
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4.8 WiFi Radio
Table 16: Frequency
Min
(MHz) (MHz) (MHz)
2412 2484
Typ
Max
Parameter
Center frequency of operating channel
—
4.8.1 WiFi RF Transmitter (TX) Specifications
Table 17: TX Power with Spectral Mask and EVM Meeting 802.11 Standards
Min
Typ
Max
Rate
(dBm) (dBm) (dBm)
802.11b, 1 Mbps
—
—
—
—
—
—
—
—
21.0
21.0
21.0
19.0
20.0
18.5
20.0
18.5
—
—
—
—
—
—
—
—
802.11b, 11 Mbps
802.11g, 6 Mbps
802.11g, 54 Mbps
802.11n, HT20, MCS 0
802.11n, HT20, MCS 7
802.11n, HT40, MCS 0
802.11n, HT40, MCS 7
Table 18: TX EVM Test
Min
(dB)
Typ
SL1
(dB)
–10
Rate
(dB)
802.11b, 1 Mbps, @21 dBm
—
–24.8
–24.7
–22.1
–28.0
–26.4
–29.4
–27.8
–29.3
802.11b, 11 Mbps, @21 dBm
802.11g, 6 Mbps, @21 dBm
—
—
—
—
—
—
—
–10
–5
802.11g, 54 Mbps, @19 dBm
802.11n, HT20, MCS 0, @20 dBm
802.11n, HT20, MCS 7, @18.5 dBm
802.11n, HT40, MCS 0, @20 dBm
802.11n, HT40, MCS 7, @18.5 dBm
–25
–5
–27
–5
–27
1
SL stands for standard limit value.
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Electrical Characteristics
4.8.2 WiFi RF Receiver (RX) Specifications
Table 19: RX Sensitivity
Min
Typ
Max
Rate
(dBm) (dBm) (dBm)
802.11b, 1 Mbps
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
–98.4
–96.0
–93.0
–88.6
–93.8
–92.2
–91.0
–88.4
–85.8
–82.0
–78.0
–76.6
–93.6
–90.8
–88.4
–85.0
–81.8
–77.8
–76.0
–74.8
–90.0
–88.0
–85.2
–82.0
–78.8
–74.6
–73.0
–71.4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
802.11b, 2 Mbps
802.11b, 5.5 Mbps
802.11b, 11 Mbps
802.11g, 6 Mbps
802.11g, 9 Mbps
802.11g, 12 Mbps
802.11g, 18 Mbps
802.11g, 24 Mbps
802.11g, 36 Mbps
802.11g, 48 Mbps
802.11g, 54 Mbps
802.11n, HT20, MCS 0
802.11n, HT20, MCS 1
802.11n, HT20, MCS 2
802.11n, HT20, MCS 3
802.11n, HT20, MCS 4
802.11n, HT20, MCS 5
802.11n, HT20, MCS 6
802.11n, HT20, MCS 7
802.11n, HT40, MCS 0
802.11n, HT40, MCS 1
802.11n, HT40, MCS 2
802.11n, HT40, MCS 3
802.11n, HT40, MCS 4
802.11n, HT40, MCS 5
802.11n, HT40, MCS 6
802.11n, HT40, MCS 7
Table 20: Maximum RX Level
Min
Typ
Max
Rate
(dBm) (dBm) (dBm)
802.11b, 1 Mbps
—
—
—
—
—
—
5
5
5
0
5
0
—
—
—
—
—
—
802.11b, 11 Mbps
802.11g, 6 Mbps
802.11g, 54 Mbps
802.11n, HT20, MCS 0
802.11n, HT20, MCS 7
Cont’d on next page
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Electrical Characteristics
Table 20 – cont’d from previous page
Min Typ
(dBm) (dBm) (dBm)
Max
Rate
802.11n, HT40, MCS 0
802.11n, HT40, MCS 7
—
—
5
0
—
—
Table 21: RX Adjacent Channel Rejection
Min
(dB)
Typ
(dB)
Max
(dB)
Rate
802.11b, 1 Mbps
—
35
35
31
14
31
13
19
8
—
802.11b, 11 Mbps
—
—
—
—
—
—
—
—
—
—
—
—
—
—
802.11g, 6 Mbps
802.11g, 54 Mbps
802.11n, HT20, MCS 0
802.11n, HT20, MCS 7
802.11n, HT40, MCS 0
802.11n, HT40, MCS 7
4.9 Bluetooth LE Radio
4.9.1 Bluetooth LE RF Transmitter (TX) Specifications
Table 22: Transmitter General Characteristics
Parameter
Min Typ Max
Unit
dBm
dB
RF transmit power
Gain control step
RF power control range
—
0
3
—
—
—
–27
—
18 dBm
Table 23: Transmitter Characteristics Bluetooth LE 1M
Parameter
Description
Min
Typ
Max
Unit
dBm
dBm
dBm
kHz
kHz
—
F = F0 ± 2 MHz
F = F0 ± 3 MHz
F = F0 ± > 3 MHz
∆ f1avg
—
–37.62
–41.95
–44.48
245.00
208.00
0.93
—
In-band emissions
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Modulation characteristics ∆ f2max
∆ f2avg/∆ f1avg
Carrier frequency offset
—
–9.00
1.17
kHz
kHz
kHz
kHz
|f0 − fn|
Carrier frequency drift
|f1 − f0|n=2, 3, 4, ..k
0.30
|fn − fn−5
|
4.90
n=6, 7, 8, ..k
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Electrical Characteristics
Table 24: Transmitter Characteristics Bluetooth LE 2M
Parameter
Description
Min
Typ
Max
Unit
dBm
dBm
dBm
kHz
kHz
—
F = F0 ± 4 MHz
F = F0 ± 5 MHz
F = F0 ± > 5 MHz
∆ f1avg
—
–43.55
–45.26
–47.00
497.00
398.00
0.95
—
In-band emissions
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Modulation characteristics ∆ f2max
∆ f2avg/∆ f1avg
Carrier frequency offset
—
–9.00
0.46
kHz
kHz
kHz
kHz
|f0 − fn|
Carrier frequency drift
|f1 − f0|n=2, 3, 4, ..k
0.70
|fn − fn−5
|
6.80
n=6, 7, 8, ..k
Table 25: Transmitter Characteristics Bluetooth LE 125K
Parameter
Description
F = F0 ± 2 MHz
F = F0 ± 3 MHz
F = F0 ± > 3 MHz
∆ f1avg
Min
Typ
Max
Unit
dBm
dBm
dBm
kHz
kHz
kHz
kHz
kHz
kHz
—
–37.90
–41.00
–42.50
252.00
200.00
–13.70
1.52
—
—
—
—
—
—
—
—
—
In-band emissions
—
—
—
—
—
—
—
—
Modulation characteristics
Carrier frequency offset
∆ f1max
—
|f0 − fn|
Carrier frequency drift
|f0 − f3|n=1, 2, 3, ..k
0.65
|fn − fn−3
|
0.70
n=7, 8, 9, ..k
Table 26: Transmitter Characteristics Bluetooth LE 500K
Parameter
Description
F = F0 ± 2 MHz
F = F0 ± 3 MHz
F = F0 ± > 3 MHz
∆ f2avg
Min
Typ
Max
Unit
dBm
dBm
dBm
kHz
kHz
kHz
kHz
kHz
kHz
—
–37.90
–41.30
–42.80
220.00
205.00
–11.90
1.37
—
—
—
—
—
—
—
—
—
In-band emissions
—
—
—
—
—
—
—
—
Modulation characteristics
Carrier frequency offset
∆ f2max
—
|f0 − fn|
Carrier frequency drift
|f0 − f3|n=1, 2, 3, ..k
1.09
|fn − fn−3
|
0.51
n=7, 8, 9, ..k
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Electrical Characteristics
4.9.2 Bluetooth LE RF Receiver (RX) Specifications
Table 27: Receiver Characteristics Bluetooth LE 1M
Parameter
Description
Min
Typ
–97
Max
Unit
dBm
dBm
dB
Sensitivity @30.8% PER
Maximum received signal @30.8% PER
Co-channel C/I
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
10
8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
F = F0 + 1 MHz
F = F0 – 1 MHz
F = F0 + 2 MHz
F = F0 – 2 MHz
F ≥ F0 + 3 MHz(1)
F ≤ F0 – 3 MHz
—
–4
dB
–3
dB
–32
–36
—
dB
Adjacent channel selectivity C/I
dB
dB
–39
–29
–38
–34
–9
dB
Image frequency
dB
F = Fimage + 1 MHz
F = Fimage – 1 MHz
30 MHz ~ 2000 MHz
2003 MHz ~ 2399 MHz
2484 MHz ~ 2997 MHz
3000 MHz ~ 12.75 GHz
—
dB
Adjacent channel to image frequency
dB
dBm
dBm
dBm
dBm
dBm
–18
–16
–6
Out-of-band blocking performance
Intermodulation
–44
1
Refer to the value of Adjacent channel to image frequency when F = Fimage – 1 MHz.
Table 28: Receiver Characteristics Bluetooth LE 2M
Parameter
Description
Min
Typ
–94
Max
Unit
dBm
dBm
dB
Sensitivity @30.8% PER
Maximum received signal @30.8% PER
Co-channel C/I
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
–1
10
—
F = F0 + 2 MHz
F = F0 – 2 MHz
F = F0 + 4 MHz(1)
F = F0 – 4 MHz
F ≥ F0 + 6 MHz
F ≤ F0 – 6 MHz
—
–7
dB
–7
dB
—
dB
Adjacent channel selectivity C/I
–34
–39
–39
–27
–39
—
dB
dB
dB
Image frequency
dB
F = Fimage + 2 MHz
F = Fimage – 2 MHz(2)
30 MHz ~ 2000 MHz
2003 MHz ~ 2399 MHz
2484 MHz ~ 2997 MHz
3000 MHz ~ 12.75 GHz
—
dB
Adjacent channel to image frequency
dB
–17
–19
–16
–22
–40
dBm
dBm
dBm
dBm
dBm
Out-of-band blocking performance
Intermodulation
1
Refer to the value of Image frequency.
2
Refer to the value of Adjacent channel selectivity C/I when F = F0 + 2 MHz.
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Electrical Characteristics
Table 29: Receiver Characteristics Bluetooth LE 125K
Parameter
Description
—
Min
Typ
–105
10
Max
Unit
dBm
dBm
dB
Sensitivity @30.8% PER
Maximum received signal @30.8% PER
Co-channel C/I
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
F = F0 + 1 MHz
F = F0 – 1 MHz
F = F0 + 2 MHz
F = F0 – 2 MHz
F ≥ F0 + 3 MHz(1)
F ≤ F0 – 3 MHz
—
–6
dB
–5
dB
–40
–42
—
dB
Adjacent channel selectivity C/I
dB
dB
–46
–34
–44
–37
dB
Image frequency
dB
F = Fimage + 1 MHz
F = Fimage – 1 MHz
dB
Adjacent channel to image frequency
dB
1
Refer to the value of Adjacent channel to image frequency when F = Fimage – 1 MHz.
Table 30: Receiver Characteristics Bluetooth LE 500K
Parameter
Description
—
Min
Typ
–100
10
Max
Unit
dBm
dBm
dB
Sensitivity @30.8% PER
Maximum received signal @30.8% PER
Co-channel C/I
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3
F = F0 + 1 MHz
F = F0 – 1 MHz
F = F0 + 2 MHz
F = F0 – 2 MHz
F ≥ F0 + 3 MHz(1)
F ≤ F0 – 3 MHz
—
–5
dB
–7
dB
–39
–40
—
dB
Adjacent channel selectivity C/I
dB
dB
–40
–34
–43
–38
dB
Image frequency
dB
F = Fimage + 1 MHz
F = Fimage – 1 MHz
dB
Adjacent channel to image frequency
dB
1
Refer to the value of Adjacent channel to image frequency when F = Fimage – 1 MHz.
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Package Information
5. Package Information
Figure 8: QFN32 (5×5 mm) Package
Note:
For information about tape, reel, and product marking, please refer to Espressif Chip-Packing Information.
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Revision History
Revision History
Date
Version
Release Notes
• Clarified that of the 400 KB SRAM, 16 KB is configured as cache;
• Updated maximum value to standard limit value in Table Wi-Fi RF Trans-
mitter (TX) Specifications in Section 4.8.1 Wi-Fi RF Transmitter (TX) Spec-
ifications.
2021-01-18
V0.6
• Updated information about Wi-Fi;
• Added connection between embedded flash ports and chip pins to ta-
ble notes in Section 2.2 Pin Description;
• Updated Figure ESP32-C3 Family Power Scheme, added Figure ESP32-
C3 Family Power-up and Reset Timing and Table Power Scheme in Sec-
tion 2.3 Power Scheme;
2021-01-13
V0.5
• Added Figure Setup and Hold Times for the Strapping Pin and Table
Strapping Pins in Section 2.4 Strapping Pins;
• Updated Table Peripheral Pin Configurations in Section 3.11 Peripheral
Pin Configurations;
• Added Chapter 4 Electrical Characteristics;
• Added Chapter 5 Package Information.
2020-11-27
V0.4
Preliminary version.
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NO WARRANTY IS PROVIDED TO THIS DOCUMENT FOR ITS MERCHANTABILITY, NON-
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