M12L2561616A-6TIG2K [ESMT]
Synchronous DRAM, 16MX16, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, LEAD FREE, TSOP2-54;
| 型号： | M12L2561616A-6TIG2K |
| 厂家： | 
ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. |
| 描述： | Synchronous DRAM, 16MX16, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, LEAD FREE, TSOP2-54 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总45页 (文件大小：933K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ESMT
M12L2561616A (2K)
Operation Temperature Condition -40°C~85°C
SDRAM
4M x 16 Bit x 4 Banks
Synchronous DRAM
FEATURES
ORDERING INFORMATION
y
y
y
y
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
- CAS Latency ( 2 & 3 )
- Burst Length ( 1, 2, 4, 8 & full page )
- Burst Type ( Sequential & Interleave )
All inputs are sampled at the positive going edge of
the system clock
Burst Read single write operation
DQM for masking
Product ID
Max Freq. Package Comments
M12L2561616A-5TIG2K 200MHz
M12L2561616A-5BIG2K 200MHz
M12L2561616A-6TIG2K 166MHz
M12L2561616A-6BIG2K 166MHz
M12L2561616A-7TIG2K 143MHz
M12L2561616A-7BIG2K 143MHz
TSOP II
BGA
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
TSOP II
BGA
y
TSOP II
BGA
y
y
y
y
Auto & self refresh
64ms refresh period (8K cycle)
GENERAL DESCRIPTION
The M12L2561616A is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 4,194,304 words by 16 bits.
Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system applications.
PIN CONFIGURATION (TOP VIEW)
(TSOPII 54L, 400milX875mil Body, 0.8mm Pin Pitch)
BALL CONFIGURATION (TOP VIEW)
(BGA54, 8mmX8mmX1mm Body, 0.8mm Ball Pitch)
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
1
V
DD
DQ15
2
DQ0
V
SSQ
3
V
DDQ
DQ1
DQ2
1
2
3
4
5
6
7
8
9
DQ14
DQ13
4
5
V
DDQ
6
VDDQ
V
SSQ
DQ3
DQ4
A
B
C
D
E
F
VSS
DQ15
VSSQ
DQ0
VDD
DQ12
DQ11
7
8
VSSQ
VDDQ
DQ2
DQ4
DQ1
DQ3
DQ14
DQ12
DQ13
DQ11
VDDQ
VSSQ
V
SSQ
9
V
DDQ
DQ5
DQ6
DQ10
DQ9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
V
DDQ
V
SSQ
DQ8
DQ7
VSSQ
VDD
VDDQ
VSS
DQ6
DQ10
DQ8
DQ9
NC
DQ5
DQ7
V
SS
V
DD
NC
LDQM
WE
LDQM
UDQM
CLK
CKE
CAS
RAS
CS
UDQM
A12
CLK
A11
CKE
A9
CAS
BA0
RAS
BA1
WE
CS
A
A
A
A
A
A
A
A
V
12
11
9
BA0
BA1
G
H
J
8
A
10/AP
A8
A0
A3
A10
A7
A5
A6
A4
A1
A2
7
A
A
A
A
0
1
2
3
6
VSS
VDD
5
4
SS
V
DD
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.4 1/45
ESMT
M12L2561616A (2K)
Operation Temperature Condition -40°C~85°C
BLOCK DIAGRAM
CLK
Clock
Generator
Bank D
Bank C
CKE
Bank B
Row
Address
Address
Buffer
&
Refresh
Counter
Bank A
Mode
Register
Sense Amplifier
L(U)DQM
Column
Address
Buffer
&
CS
Column Decoder
RAS
CAS
WE
Data Control Circuit
Counter
DQ
PIN DESCRIPTION
PIN
NAME
INPUT FUNCTION
Active on the positive going edge to sample all inputs
CLK
System Clock
Disables or enables device operation by masking or enabling all
inputs except CLK , CKE and L(U)DQM
Chip Select
CS
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior new command.
Disable input buffers for power down in standby.
CKE
Clock Enable
Address
Row / column address are multiplexed on the same pins.
Row address : RA0~RA12, column address : CA0~CA8
A0 ~ A12
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
BA1, BA0
RAS
Bank Select Address
Row Address Strobe
Latches row addresses on the positive going edge of the CLK with
RAS low. (Enables row access & precharge.)
Latches column address on the positive going edge of the CLK with
CAS low. (Enables column access.)
Column Address Strobe
Write Enable
CAS
WE
Enables write operation and row precharge.
Latches data in starting from CAS , WE active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
L(U)DQM
Data Input / Output Mask
DQ0 ~ DQ15
VDD / VSS
Data Input / Output
Data inputs / outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Power Supply / Ground
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
VDDQ / VSSQ
NC
Data Output Power / Ground
No Connection
This pin is recommended to be left No Connection on the device.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.4 2/45
ESMT
M12L2561616A (2K)
Operation Temperature Condition -40°C~85°C
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
VIN, VOUT
VDD, VDDQ
TA
Value
Unit
V
Voltage on any pin relative to VSS
Voltage on VDD supply relative to VSS
Operating ambient temperature
Storage temperature
-1.0 ~ 4.6
-1.0 ~ 4.6
-40 ~ +85
V
°C
°C
W
TSTG
PD
-55 ~ +150
Power dissipation
1
Short circuit current
IOS
50
mA
Note:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITION
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -40 to 85 °C )
Parameter
Supply voltage
Symbol
VDD, VDDQ
VIH
Min
3.0
2.0
-0.3
2.4
-
Typ
3.3
3.0
0
Max
Unit
V
Note
3.6
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
VDD+0.3
V
1
VIL
0.8
-
V
2
VOH
-
V
IOH = -2mA
IOL = 2mA
3
VOL
-
0.4
5
V
IIL
-5
-
μ A
Output leakage current
IOL
-5
-
5
μ A
4
Note:
1. VIH(max) = 4.6V AC for pulse width ≤ 10ns acceptable.
2. VIL(min) = -1.5V AC for pulse width ≤ 10ns acceptable.
3. Any input 0V ≤ VIN ≤ VDD, all other pins are not under test = 0V.
4. Dout is disabled, 0V
VOUT ≤ VDD
.
≤
CAPACITANCE (VDD = 3.3V, TA = 25 °C , f = 1MHz)
Parameter
Symbol
Min
Max
Unit
Input capacitance (A0 ~ A12, BA0 ~ BA1)
Input capacitance (CLK)
CIN1
1.5
2
3
3
pF
pF
CCLK
Input capacitance
CIN2
1.5
2
4.5
4.5
pF
pF
(CKE, CS , RAS , CAS , WE & L(U)DQM)
Data input/output capacitance (DQ0 ~ DQ15)
COUT
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.4 3/45
ESMT
M12L2561616A (2K)
Operation Temperature Condition -40°C~85°C
DC CHARACTERISTICS
Recommended operating condition unless otherwise noted，TA = -40 to 85 °C
Version
Parameter
Symbol
Test Condition
Unit Note
-5
-6
-7
Operating Current
(One Bank Active)
ICC1
Burst Length = 2, tRC = tRC(min), IOL = 0 mA
90
80
70
mA
1,2
Precharge Standby
Current in power-down
mode
ICC2P
CKE = VIL(max), tCC = 10ns
3
3
mA
mA
ICC2PS
CKE & CLK=VIL(max), tCC = ∞
CKE=VIH(min), CS = VIH(min), tCC = 10ns
Input signals are changed one time during 2CLK
CKE=VIH(min), CLK=VIL(max), tCC = ∞
input signals are stable
ICC2N
15
5
mA
mA
Precharge Standby
Current in non
power-down mode
ICC2NS
Active Standby
Current in power-down
mode
ICC3P
CKE=VIL(max), tCC =10ns
8
8
mA
mA
ICC3PS
CKE & CLK=VIL(max), tCC = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns
Input signals are changed one time during 2 CLKs
All other pins ≥ VDD-0.2V or ≤ 0.2V
CKE=VIH(min), CLK=VIL(max), tCC = ∞
input signals are stable
Active Standby
Current in non
power-down mode
(One Bank Active)
ICC3N
28
mA
ICC3NS
20
mA
mA
IOL = 0 mA, Page Burst, 4 Banks activated,
Operating Current
(Burst Mode)
ICC4
110
150
100
90
1,2
t
CCD = 2 CLKs
Refresh Current
ICC5
ICC6
140
5
130
mA
mA
tRFC ≥ tRFC(min)
Self Refresh Current
CKE=0.2V
Note: 1. Measured with outputs open.
2. Input signals are changed one time during 2 CLKs.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.4 4/45
ESMT
M12L2561616A (2K)
Operation Temperature Condition -40°C~85°C
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V ，TA = -40 to 85 °C )
Parameter
Input levels (Vih/Vil)
Value
2.4/0.4
1.4
Unit
V
Input timing measurement reference level
Input rise and fall-time
V
tr/tf = 1/1
1.4
ns
V
Output timing measurement reference level
Output load condition
See Fig. 2
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
Parameter
Symbol
Unit
Note
-5
10
15
-6
12
18
-7
14
20
Row active to row active delay
tRRD(min)
tRCD(min)
ns
ns
1
1
RAS to CAS delay
Row precharge time
tRP(min)
15
40
18
42
100
60
60
1
20
45
ns
ns
1
1
tRAS(min)
Row active time
t
RAS(max)
tRC(min)
RFC(min)
us
@ Operating
Row cycle time
55
55
63
70
ns
1
1,5
2
@ Auto refresh
t
ns
Last data in to col. address delay
Last data in to row precharge
Last data in to burst stop
tCDL(min)
tRDL(min)
tBDL(min)
tREF(max)
tCCD(min)
CLK
ns
10
12
1
14
1,2
2
CLK
ms
CLK
Refresh period (8,192 rows)
Col. address to col. address delay
64
1
6
3
CAS latency = 3
CAS latency = 2
2
Number of valid
Output data
ea
4
1
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. A new command may be given tRFC after self refresh exit.
6. A maximum of eight consecutive AUTO REFRESH commands (with tRFCmin) can be posted to any given SDRAM, and the
maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is
8x7.8μ s.)
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.4 5/45
ESMT
M12L2561616A (2K)
Operation Temperature Condition -40°C~85°C
AC CHARACTERISTICS (AC operating condition unless otherwise noted)
-5
-6
-7
Parameter
Symbol
Unit
Note
Min
Max
Min
Max
Min
Max
CAS latency = 3
5
10
-
6
10
-
7
10
-
CLK cycle time
tCC
tSAC
tOH
1000
1000
1000
ns
ns
ns
1
1,2
2
CAS latency = 2
CAS latency = 3
CAS latency = 2
CAS latency = 3
CAS latency = 2
CLK to valid
output delay
4.5
5.4
-
5.4
5.4
-
5.4
5.4
-
-
-
-
Output data
hold time
2
2
2
2
2
-
2
2.5
2.5
1.5
0.8
1
-
2
2.5
2.5
1.5
0.8
1
-
CLK high pulse width
CLK low pulse width
Input setup time
tCH
tCL
-
-
-
ns
ns
ns
ns
ns
3
3
3
3
2
2
-
-
-
-
-
-
tSS
tSH
tSLZ
1.5
0.8
1
Input hold time
-
-
-
CLK to output in Low-Z
-
-
-
CAS latency = 3
CAS latency = 2
-
4.5
-
5.4
-
5.4
CLK to output
in Hi-Z
tSHZ
ns
-
-
5.4
-
5.4
-
5.4
Note:
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns. (tr/2 - 0.5) ns should be considered.
3. Assumed input rise and fall time (tr & tf) =1ns.
If tr & tf is longer than 1ns. transient time compensation should be considered.
i.e., [(tr + tf)/2 – 1] ns should be added to the parameter.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.4 6/45
ESMT
M12L2561616A (2K)
Operation Temperature Condition -40°C~85°C
SIMPLIFIED TRUTH TABLE
A12~A11,
A9~A0
BA0,
BA1
COMMAND
CKEn-1 CKEn
DQM
X
A10/AP
Note
CS RAS CAS
WE
L
Register
Refresh
Mode Register set
Auto Refresh
H
H
X
H
L
L
L
L
L
L
L
OP CODE
1,2
3
H
X
X
Entry
3
Self
L
H
L
H
X
L
H
X
H
H
X
H
X
X
X
3
Refresh
Exit
L
H
X
X
3
Bank Active & Row Addr.
Auto Precharge Disable
H
V
V
Row Address
Column
L
4
4,5
4
Read &
H
X
L
H
L
H
X
Address
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
H
Column Address
(A0~A8)
Column
L
Write &
H
H
H
X
X
X
L
L
L
H
H
L
L
H
H
L
L
L
X
X
X
V
Address
H
4,5
6
Column Address
(A0~A8)
Burst Stop
X
Bank Selection
All Banks
V
X
L
Precharge
X
H
H
L
X
V
X
X
H
X
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
Exit
H
L
L
H
L
X
X
X
Clock Suspend or
Active Power Down
X
X
H
L
Entry
H
Precharge Power Down Mode
X
H
L
Exit
L
H
H
H
X
X
V
X
V
X
DQM
X
X
7
H
L
X
H
X
H
X
H
No Operating Command
(V = Valid, X = Don’t Care. H = Logic High, L = Logic Low)
Note: 1.OP Code: Operating Code
A0~A12 & BA0~BA1: Program keys. (@ MRS)
2.MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3.Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge of command is meant by “Auto”.
Auto/self refresh can be issued only at all banks idle state.
4.BA0~BA1: Bank select addresses.
If BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected.
If BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank B is selected.
If BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank C is selected.
If BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected
If A10/AP is “High” at row precharge, BA0 and BA1 is ignored and all banks are selected.
5.During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6.Burst stop command is valid at every burst length.
7.DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (write DQM latency is 0), but makes
Hi-Z state the data-out of 2 CLK cycles after.(Read DQM latency is 2)
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.4 7/45
ESMT
M12L2561616A (2K)
Operation Temperature Condition -40°C~85°C
MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with MRS
Address
Function
BA0~BA1
RFU
A12~A10/AP
RFU
A9
A8
A7
A6
A5
A4
A3
BT
A2
A1
A0
W.B.L.
TM
CAS Latency
Burst Length
Test Mode
CAS Latency
Burst Type
Burst Length
A8
0
A7
Type
A6
A5
0
A4
0
Latency
Reserved
Reserved
2
A3
Type
A2
0
A1
0
A0
0
BT = 0
BT = 1
0
1
0
1
Mode Register Set
Reserved
0
0
0
0
1
1
1
1
0
1
Sequential
Interleave
1
2
4
8
1
2
4
8
0
0
1
0
0
1
1
Reserved
1
0
0
1
0
1
Reserved
1
1
3
0
1
1
Write Burst Length
Length
0
0
Reserved
Reserved
Reserved
Reserved
1
0
0
Reserved Reserved
Reserved Reserved
Reserved Reserved
Full Page Reserved
A9
0
0
1
1
0
1
Burst
1
0
1
1
0
1
Single Bit
1
1
1
1
1
Full Page Length: 512
Note:
1. RFU (Reserved for future use) should stay “0” during MRS cycle.
2. If A9 is high during MRS cycle, “Burst Read single write” function will be enabled.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.4
8/45
ESMT
M12L2561616A (2K)
Operation Temperature Condition -40°C~85°C
BURST SEQUENCE (BURST LENGTH = 4)
Initial Address
Sequential
Interleave
A1
A0
0
0
0
1
2
3
1
2
3
0
2
3
0
1
3
0
1
2
0
1
2
3
1
0
3
2
2
3
0
1
3
2
1
0
0
1
1
0
1
1
BURST SEQUENCE (BURST LENGTH = 8)
Initial Address
Sequential
Interleave
A2
A1
A0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
0
2
3
4
5
6
7
0
1
3
4
5
6
7
0
1
2
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
6
0
1
0
3
2
5
4
7
6
2
3
2
1
0
7
6
5
4
4
5
6
7
0
1
2
3
5
4
7
6
1
0
3
2
6
7
6
5
4
3
2
1
0
7
0
1
2
3
4
5
1
2
3
4
5
6
7
3
0
1
6
7
4
5
7
4
5
2
3
0
1
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.4 9/45
ESMT
M12L2561616A (2K)
Operation Temperature Condition -40°C~85°C
DEVICE OPERATIONS
CLOCK (CLK)
POWER-UP
The clock input is used as the reference for all SDRAM
operations. All operations are synchronized to the positive
going edge of the clock. The clock transitions must be
monotonic between VIL and VIH. During operation with CKE
high all inputs are assumed to be in valid state (low or high) for
the duration of setup and hold time around positive edge of the
clock for proper functionality and ICC specifications.
1.Apply power and start clock, Attempt to maintain CKE =
“H”, DQM = “H” and the other pins are NOP condition at
the inputs.
2.Maintain stable power, stable clock and NOP input
condition for minimum of 200us.
3.Issue precharge commands for all banks of the devices.
4.Issue 2 or more auto-refresh commands.
5.Issue a mode register set command to initialize the
mode register.
cf.) Sequence of 4 & 5 is regardless of the order.
CLOCK ENABLE(CKE)
The clock enable (CKE) gates the clock onto SDRAM. If CKE
goes low synchronously with clock (set-up and hold time same
as other inputs), the internal clock suspended from the next
clock cycle and the state of output and burst address is frozen
as long as the CKE remains low. All other inputs are ignored
from the next clock cycle after CKE goes low. When all banks
are in the idle state and CKE goes low synchronously with
clock, the SDRAM enters the power down mode from the next
clock cycle. The SDRAM remains in the power down mode
ignoring the other inputs as long as CKE remains low. The
power down exit is synchronous as the internal clock is
suspended. When CKE goes high at least “1CLK + tSS” before
the high going edge of the clock, then the SDRAM becomes
active from the same clock edge accepting all the input
commands.
The device is now ready for normal operation.
MODE REGISTER SET (MRS)
The mode register stores the data for controlling the
various operating modes of SDRAM. It programs the CAS
latency, burst type, burst length, test mode and various
vendor specific options to make SDRAM useful for variety
of different applications. The default value of the mode
register is not defined, therefore the mode register must
be written after power up to operate the SDRAM. The
mode register is written by asserting low on CS , RAS ,
CAS and WE (The SDRAM should be in active mode
with CKE already high prior to writing the mode register).
The state of address pins A0~A12 and BA0~BA1 in the
BANK ADDRESSES (BA0~BA1)
same cycle as CS , RAS , CAS and WE going low is
the data written in the mode register. Two clock cycles is
required to complete the write in the mode register. The
mode register contents can be changed using the same
command and clock cycle requirements during operation
as long as all banks are in the idle state. The mode
register is divided into various fields into depending on
functionality. The burst length field uses A0~A2, burst type
uses A3, CAS latency (read latency from column address)
use A4~A6, vendor specific options or test mode use
A7~A8, A10/AP~A12 and BA0~BA1. The write burst
length is programmed using A9. A7~A8, A10/AP~A12 and
BA0~BA1 must be set to low for normal SDRAM
operation. Refer to the table for specific codes for various
burst length, burst type and CAS latencies.
This SDRAM is organized as four independent banks of
4,194,304 words x 16 bits memory arrays. The BA0~BA1
inputs are latched at the time of assertion of RAS and CAS
to select the bank to be used for the operation. The banks
addressed BA0~BA1 are latched at bank active, read, write,
mode register set and precharge operations.
ADDRESS INPUTS (A0~A12)
The 22 address bits are required to decode the 4,194,304
word locations are multiplexed into 13 address input pins
(A0~A12). The 13 row addresses are latched along with RAS
and BA0~BA1 during bank active command. The 9 bit column
addresses are latched along with CAS , WE and BA0~BA1
during read or with command.
BANK ACTIVATE
NOP and DEVICE DESELECT
The bank activate command is used to select a random
row in an idle bank. By asserting low on RAS and CS
with desired row and bank address, a row access is
initiated. The read or write operation can occur after a
time delay of tRCD(min) from the time of bank activation.
tRCD is the internal timing parameter of SDRAM, therefore
it is dependent on operating clock frequency. The
minimum number of clock cycles required between bank
activate and read or write command should be calculated
by dividing tRCD(min) with cycle time of the clock and then
When RAS , CAS and WE are high , The SDRAM
performs no operation (NOP). NOP does not initiate any new
operation, but is needed to complete operations which require
more than single clock cycle like bank activate, burst read,
auto refresh, etc. The device deselect is also a NOP and is
entered by asserting CS high. CS high disables the
command decoder so that RAS , CAS , WE and all the
address inputs are ignored.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.4
10/45
ESMT
M12L2561616A (2K)
Operation Temperature Condition -40°C~85°C
DEVICE OPERATIONS (Continued)
rounding of the result to the next higher integer. The SDRAM
has four internal banks in the same chip and shares part of the
internal circuitry to reduce chip area, therefore it restricts the
activation of four banks simultaneously. Also the noise
generated during sensing of each bank of SDRAM is high
requiring some time for power supplies to recover before
another bank can be sensed reliably. tRRD(min) specifies the
minimum time required between activating different bank. The
number of clock cycles required between different bank
activation must be calculated similar to tRCD specification. The
minimum time required for the bank to be active to initiate
sensing and restoring the complete row of dynamic cells is
determined by tRAS(min). Every SDRAM bank activate
DQM OPERATION
The DQM is used mask input and output operations. It
works similar to OE during operation and inhibits writing
during write operation. The read latency is two cycles from
DQM and zero cycle for write, which means DQM masking
occurs two cycles later in read cycle and occurs in the
same cycle during write cycle. DQM operation is
synchronous with the clock. The DQM signal is important
during burst interrupts of write with read or precharge in
the SDRAM. Due to asynchronous nature of the internal
write, the DQM operation is critical to avoid unwanted or
incomplete writes when the complete burst write is
required. Please refer to DQM timing diagram also.
command must satisfy
tRAS(min) specification before a
precharge command to that active bank can be asserted. The
maximum time any bank can be in the active state is
determined by tRAS(max) and tRAS(max) can be calculated
similar to tRCD specification.
PRECHARGE
The precharge is performed on an active bank by
asserting low on clock cycles required between bank
activate and clock cycles required between bank activate
BURST READ
and CS , RAS , WE and A10/AP with valid BA0~BA1
of the bank to be procharged. The precharge command
can be asserted anytime after tRAS(min) is satisfy from the
bank active command in the desired bank. tRP is defined
as the minimum number of clock cycles required to
complete row precharge is calculated by dividing tRP with
clock cycle time and rounding up to the next higher
integer. Care should be taken to make sure that burst
write is completed or DQM is used to inhibit writing before
precharge command is asserted. The maximum time any
bank can be active is specified by tRAS(max). Therefore,
each bank has to be precharge with tRAS(max) from the
bank activate command. At the end of precharge, the
bank enters the idle state and is ready to be activated
again. Entry to power-down, Auto refresh, Self refresh and
Mode register set etc. is possible only when all banks are
in idle state.
The burst read command is used to access burst of data on
consecutive clock cycles from an active row in an active bank.
The burst read command is issued by asserting low on CS
and RAS with WE being high on the positive edge of the
clock. The bank must be active for at least tRCD(min) before the
burst read command is issued. The first output appears in CAS
latency number of clock cycles after the issue of burst read
command. The burst length, burst sequence and latency from
the burst read command is determined by the mode register
which is already programmed. The burst read can be initiated
on any column address of the active row. The address wraps
around if the initial address does not start from a boundary
such that number of outputs from each I/O are equal to the
burst length programmed in the mode register. The output
goes into high-impedance at the end of burst, unless a new
burst read was initiated to keep the data output gapless. The
burst read can be terminated by issuing another burst read or
burst write in the same bank or the other active bank or a
precharge command to the same bank. The burst stop
command is valid at every page burst length.
AUTO PRECHARGE
The precharge operation can also be performed by using
auto precharge. The SDRAM internally generates the
timing to satisfy tRAS(min) and “tRP” for the programmed
burst length and CAS latency. The auto precharge
command is issued at the same time as burst write by
asserting high on A10/AP, the bank is precharge command
is asserted. Once auto precharge command is given, no
new commands are possible to that particular bank until
the bank achieves idle state.
BURST WRITE
The burst write command is similar to burst read command
and is used to write data into the SDRAM on consecutive clock
cycles in adjacent addresses depending on burst length and
burst sequence. By asserting low on CS , CAS and WE
with valid column address, a write burst is initiated. The data
inputs are provided for the initial address in the same clock
cycle as the burst write command. The input buffer is
deselected at the end of the burst length, even though the
internal writing can be completed yet. The writing can be
complete by issuing a burst read and DQM for blocking data
inputs or burst write in the same or another active bank. The
burst stop command is valid at every burst length. The write
burst can also be terminated by using DQM for blocking data
and precharge the bank tRDL after the last data input to be
written into the active row. See DQM OPERATION also.
FOUR BANKS PRECHARGE
Four banks can be precharged at the same time by using
Precharge all command. Asserting low on CS , RAS ,
and WE with high on A10/AP after all banks have
satisfied tRAS(min) requirement, performs precharge on all
banks. At the end of tRP after performing precharge all, all
banks are in idle state.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.4
11/45
ESMT
M12L2561616A (2K)
Operation Temperature Condition -40°C~85°C
DEVICE OPERATIONS (Continued)
AUTO REFRESH
SELF REFRESH
The storage cells of SDRAM need to be refreshed every 64ms
to maintain data. An auto refresh cycle accomplishes refresh of
a single row of storage cells. The internal counter increments
automatically on every auto refresh cycle to refresh all the
rows. An auto refresh command is issued by asserting low on
The self refresh is another refresh mode available in the
SDRAM. The self refresh is the preferred refresh mode for
data retention and low power operation of SDRAM. In self
refresh mode, the SDRAM disables the internal clock and
all the input buffers except CKE. The refresh addressing
and timing is internally generated to reduce power
consumption.
CS , RAS and CAS with high on CKE and WE . The auto
refresh command can only be asserted with all banks being in
idle state and the device is not in power down mode (CKE is
high in the previous cycle). The time required to complete the
auto refresh operation is specified by tRFC(min). The minimum
number of clock cycles required can be calculated by driving
tRFC with clock cycle time and them rounding up to the next
higher integer. The auto refresh command must be followed by
NOP’s until the auto refresh operation is completed. The auto
refresh is the preferred refresh mode when the SDRAM is
being used for normal data transactions. The auto refresh
cycle can be performed once in 7.8us.
The self refresh mode is entered from all banks idle state
by asserting low on CS , RAS , CAS and CKE with
high on WE . Once the self refresh mode is entered, only
CKE state being low matters, all the other inputs including
clock are ignored to remain in the refresh.
The self refresh is exited by restarting the external clock
and then asserting high on CKE. This must be followed by
NOP’s for a minimum time of tRFC before the SDRAM
reaches idle state to begin normal operation. 8K cycles of
burst auto refresh is required immediately before self
refresh entry and immediately after self refresh exit.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.4
12/45
ESMT
M12L2561616A (2K)
Operation Temperature Condition -40°C~85°C
CLK
COMMANDS
H
CKE
Mode register set command
CS
RAS
( CS ,RAS , CAS , WE = Low)
CAS
The M12L2561616A has a mode register that defines how the device operates.
In this command, A0~A12, BA0 and BA1 are the data input pins. After power on, the
mode register set command must be executed to initialize the device.
The mode register can be set only when all banks are in idle state.
During 2CLK following this command, the M12L2561616A cannot accept any
other commands.
WE
BA0, BA1
A10
Add
Fig. 1 Mode register set
command
CLK
Activate command
H
CKE
CS
( CS ,RAS = Low, CAS , WE = High)
RAS
The M12L2561616A has four banks, each with 8,192 rows.
This command activates the bank selected by BA1 and BA0 (BS) and a row
address selected by A0 through A12.
CAS
WE
This command corresponds to a conventional DRAM’s RAS falling.
BA0, BA1
(Bank select)
A10
Row
Row
Add
Fig. 2 Row address strobe and
bank active command
Precharge command
CLK
H
( CS ,RAS , WE = Low, CAS = High )
CKE
CS
This command begins precharge operation of the bank selected by BA1 and BA0
(BS). When A10 is High, all banks are precharged, regardless of BA1 and BA0.
When A10 is Low, only the bank selected by BA1 and BA0 is precharged.
After this command, the M12L2561616A can’t accept the activate command to
the precharging bank during tRP (precharge to activate command period).
RAS
CAS
This command corresponds to a conventional DRAM’s RAS rising.
WE
BA0, BA1
(Bank select)
A10
(Precharge select)
Add
Fig. 3 Precharge command
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Publication Date: Jun. 2012
Revision: 1.4
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ESMT
M12L2561616A (2K)
Operation Temperature Condition -40°C~85°C
CLK
Write command
H
CKE
CS
( CS , CAS , WE = Low, RAS = High)
If the mode register is in the burst write mode, this command sets the burst start
address given by the column address to begin the burst write operation. The first
write data in burst can be input with this command with subsequent data on following
clocks.
RAS
CAS
WE
BA0,BA1
(Bank select)
A10
Add
Col.
Fig. 4 Column address and
write command
CLK
Read command
H
CKE
CS
RAS
CAS
( CS , CAS = Low, RAS , WE = High)
Read data is available after CAS latency requirements have been met.
This command sets the burst start address given by the column address.
WE
BA0,BA1
(Bank select)
A10
Add
Col.
Fig. 5 Column address and
read command
CLK
CBR (auto) refresh command
H
CKE
CS
( CS ,RAS , CAS = Low, WE , CKE = High)
This command is a request to begin the CBR refresh operation. The refresh
address is generated internally.
Before executing CBR refresh, all banks must be precharged.
After this cycle, all banks will be in the idle (precharged) state and ready for a
row activate command.
RAS
CAS
WE
During tRFC period (from refresh command to refresh or activate command), the
M12L2561616A cannot accept any other command.
BA0,BA1
(Bank select)
A10
Add
Fig. 6 Auto refresh command
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.4
14/45
ESMT
M12L2561616A (2K)
Operation Temperature Condition -40°C~85°C
CLK
CKE
Self refresh entry command
( CS ,RAS , CAS , CKE = Low , WE = High)
CS
After the command execution, self refresh operation continues while CKE
remains low. When CKE goes to high, the M12L2561616A exits the self refresh
mode.
RAS
CAS
WE
During self refresh mode, refresh interval and refresh operation are performed
internally, so there is no need for external control.
Before executing self refresh, all banks must be precharged.
BA0, BA1
(Bank select)
A10
Add
Fig. 7 Self refresh entry
command
CLK
CKE
Burst stop command
H
( CS , WE = Low, RAS , CAS = High)
CS
RAS
CAS
This command terminates the current burst operation.
Burst stop is valid at every burst length.
WE
BA0, BA1
(Bank select)
A10
Add
Fig. 8 Burst stop command
CLK
No operation
CKE
CS
H
( CS = Low, RAS , CAS , WE = High)
This command is not an execution command. No operations begin or terminate
by this command.
RAS
CAS
WE
BA0, BA1
(Bank select)
A10
Add
Fig. 9 No operation
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Publication Date: Jun. 2012
Revision: 1.4 15/45
ESMT
M12L2561616A (2K)
Operation Temperature Condition -40°C~85°C
BASIC FEATURE AND FUNCTION DESCRIPTIONS
1. CLOCK Suspend
1 ) C l o c k S u s p e n d e d D u r i n g W r i t e ( B L = 4 )
CL K
2 ) C l o c k S u s p e n d e d D u r i n g R e a d ( B L = 4 )
C M D
C K E
W R
R D
M as k e d b y CK E
I nt ern al
CLK
D2
D 3
D Q ( C L 2 )
D Q ( C L 3 )
D 0
D0
Q3
Q3
D 1
D 1
Q1
Q1
Q0
Q2
Q2
D 2
D 3
Q0
N ot W ri t t e n
Suspe nded Dout
2. DQM Operation
2 ) R e a d M a s k ( B L = 4 )
1 ) W r i t e M a s k ( B L = 4 )
CL K
C M D
R D
W R
D Q M
DQ ( C L 2 )
DQ ( C L 3 )
M a s k e d b y D Q M
M a s k e d b y D Q M
H i - Z
D0
D1
Q2
Q3
Q2
D3
Q0
H i - Z
D3
D1
D0
Q1
Q3
DQ M t o D at a-i n M ask = 0
DQ M to D at a- ou t M ask = 2
* N o t e 2
3 ) D Q M w i t h c l c o k s u s p e n d e d ( F u l l P a g e R e a d )
CLK
R D
C M D
CK E
I nter na l
CLK
D Q M
H i - Z
H i - Z
H i - Z
H i - Z
H i - Z
Q4
Q3
Q6
Q5
Q7
Q6
Q2
Q8
Q7
Q0
DQ ( C L 2 )
DQ ( C L 3 )
H i - Z
Q1
*Note: 1. CKE to CLK disable/enable = 1CLK.
2. DQM masks data out Hi-Z after 2CLKs which should masked by CKE ”L”.
3. DQM masks both data-in and data-out.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.4 16/45
ESMT
M12L2561616A (2K)
Operation Temperature Condition -40°C~85°C
3. CAS Interrupt (I)
* N o t e 1
1 )R e a d i n t e r ru p t e d b y R e a d (B L =4 )
CL K
C MD
R D
A
R D
B
AD D
DQ (C L 2 )
D Q( CL 3 )
QA0
QB1 QB2 QB3
QB0
QB1 QB2 QB3
QA0 QB0
t C CD
* N o t e
2
2 ) W r i t e i n t e r r u p t e d b y W ri t e (B L = 2 )
3 ) W r i t e in t e r ru p t e d b y R e a d (B L = 2 )
C L K
C MD
WR
WR
W R
R D
tC CD * N o t e
2
t CC D * No t e
2
A
ADD
D Q
A
B
B
DQ (C L 2 )
D B1
DB0
D A0 DB0 D B1
tC D L
D A0
DA0
D B0
D Q( CL 3 )
* No t e
3
D B1
tC D L
* No t e
3
*Note: 1. By “interrupt” is meant to stop burst read/write by external before the end of burst.
By ” CAS interrupt ”, to stop burst read/write by CAS access ; read and write.
2. tCCD: CAS to CAS delay. (=1CLK)
3. tCDL: Last data in to new column address delay. (=1CLK)
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Revision: 1.4 17/45
ESMT
M12L2561616A (2K)
Operation Temperature Condition -40°C~85°C
4. CAS Interrupt (II): Read Interrupted by Write & DQM
( a) CL =2 , B L= 4
CLK
i ) C M D
W R
D0
R D
R D
R D
R D
D Q M
D Q
D2
D1
D3
i i ) C M D
W R
D Q M
D Q
H i - Z
D3
D2
D1
D0
D1
D2
i i i ) C M D
W R
D Q M
D Q
H i - Z
D0
D1
D3
i v ) C M D
W R
D Q M
D Q
H i - Z
Q0
D2
D0
D3
* N o t e 1
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Publication Date: Jun. 2012
Revision: 1.4
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ESMT
M12L2561616A (2K)
Operation Temperature Condition -40°C~85°C
(b) CL = 3 , B L= 4
CLK
i ) C M D
W R
D0
R D
R D
R D
R D
R D
D Q M
D Q
D1
D2
D3
W R
i i ) C M D
D Q M
D Q
D0
D1
D2
D3
i i i ) C M D
W R
D Q M
D Q
D3
D2
D1
D0
D2
D1
W R
i v ) C M D
D Q M
D Q
H i - Z
D0
D1
D3
v ) C M D
W R
D Q M
D Q
H i - Z
D2
D3
Q0
D0
* N o t e 1
*Note: 1. To prevent bus contention, there should be at least one gap between data in and data out.
5. Write Interrupted by Precharge & DQM
C L K
* N o t e 3
C M D
D Q M
W R
D 0
P R E
* N o t e 2
D Q
D 3
D 1
t
R D L ( m i n )
M a s k e d b y D Q M
*Note: 1. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out.
2. To inhibit invalid write, DQM should be issued.
3. This precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt
but only another bank precharge of four banks operation.
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Publication Date: Jun. 2012
Revision: 1.4 19/45
ESMT
M12L2561616A (2K)
Operation Temperature Condition -40°C~85°C
6. Precharge
1 ) N o r m a l W r i t e ( B L = 4 )
2 ) N o r m a l R e a d ( B L = 4 )
CLK
C M D
D Q
CL K
C M D
PR E CL= 2
R D
PR E
W R
D0
* N o t e 2
DQ ( C L 2 )
C M D
Q0
Q1
Q3
Q2
PR E
Q1
D1
D2
D3
tR D L
* N o t e 1
CL= 3
* N o t e 2
Q2
DQ ( C L 3 )
Q0
Q3
.
7. Auto Precharge
1 ) N o r m a l W r i t e ( B L = 4 )
2 ) N o r m a l R e a d ( B L = 4 )
CLK
CLK
C M D
C M D
D Q
W R
R D
D3
D2
D3
D1
DQ ( C L 2 )
DQ ( C L 3 )
D0
D1
D0
D2
D1
D0
D2
tR D L ( m i n )
D3
* N o t e 3
Auto Pr ech arge st art s
* N o t e 3
Auto Pr ech arge st art s
*Note: 1. tRDL: Last data in to row precharge delay.
2. Number of valid output data after row precharge: 1, 2 for CAS Latency = 2, 3 respectively.
3. The row active command of the precharge bank can be issued after tRP from this point.
The new read/write command of other activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.
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ESMT
M12L2561616A (2K)
Operation Temperature Condition -40°C~85°C
8. Burst Stop & Interrupted by Precharge
1 ) W r i t e B u r s t S t o p ( B L = 8 )
1 ) W r i t e i n t e r r u p t e d b y p r e c h a r g e ( B L = 4 )
C L K
C L K
* N o t e 3
C M D
C M D
P R E
W R
S T O P
W R
t
R D L
* N o t e 4
D Q M
D Q M
D Q
D Q
D 0
D 0
D 1
D 1
M a s k
M a s k
D 2
D 3
D 5
D 4
* N o t e 1
t
B D L
2 ) R e a d B u r s t S t o p ( B L = 4 )
2 ) R e a d i n t e r r u p t e d b y p r e c h a r g e ( B L = 4 )
C L K
C LK
* N o t e 5
C M D
C M D
R D
P R E
R D
S T O P
Q 0
* N o t e 2
D Q ( C L 2 )
D Q ( C L 3 )
Q1
Q 0
D Q ( C L 2 )
D Q ( C L 3 )
Q 0
Q1
Q 0
Q2
Q1
Q 3
Q 2
* N o t e 2
Q 1
Q 3
9. MRS
1 ) M o d e R e g i s t e r S e t
CLK
* N o t e 4
C M D
A C T
PR E
M R S
tR P
2 C L K
*Note: 1. tBDL: 1 CLK; Last data in to burst stop delay.
Read or write burst stop command is valid at every burst length.
2. Number of valid output data after burst stop: 1, 2 for CAS latency = 2, 3 respectiviely.
3. Write burst is terminated. tBDL determinates the last data write.
4. DQM asserted to prevent corruption of locations D2 and D3.
5. Precharge can be issued here or earlier (satisfying tRAS min delay) with DQM.
6. PRE: All banks precharge, if necessary.
MRS can be issued only at all banks precharge state.
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Revision: 1.4 21/45
ESMT
M12L2561616A (2K)
Operation Temperature Condition -40°C~85°C
10. Clock Suspend Exit & Power Down Exit
1 ) C l o c k S u s p e n d ( = Ac t i v e P o w e r D o w n ) E x i t
2 ) P o w e r D o w n ( = P r e c h a r g e P o w e r D o w n )
CLK
CK E
CLK
CK E
tS S
tS S
Inter nal
Internal
CLK
* N o t e 1
* N o t e 2
CLK
C M D
R D
C M D
A C T
NO P
11. Auto Refresh & Self Refresh
* N o t e 3
1 ) A u t o R e f r e s h
&
S e l f R e f r e s h
C L K
* N o t e 4
* N o t e 5
CM D
P R E
A R
CM D
C K E
t
R P
t
R F C
* N o t e 6
2 ) S e l f R e f r e s h
C L K
* N o t e 4
CM D
S R
P R E
C M D
C K E
t
R P
t
R F C
*Note: 1. Active power down: one or more banks active state.
2. Precharge power down: all banks precharge state.
3. The auto refresh is the same as CBR refresh of conventional DRAM.
No precharge commands are required after auto refresh command.
During tRFC from auto refresh command, any other command can not be accepted.
4. Before executing auto/self refresh command, all banks must be idle state.
5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.
6. During self refresh entry, refresh interval and refresh operation are performed internally.
After self refresh entry, self refresh mode is kept while CKE is low.
During self refresh entry, all inputs expect CKE will be don’t cared, and outputs will be in Hi-Z state.
For the time interval of tRFC from self refresh exit command, any other command can not be accepted.
8K cycles of burst auto refresh is required immediately before self refresh entry and immediately after self refresh exit.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.4 22/45
ESMT
M12L2561616A (2K)
Operation Temperature Condition -40°C~85°C
12. About Burst Type Control
At MRS A3 = “0”. See the BURST SEQUENCE TABLE. (BL = 4,8)
BL = 1, 2, 4, 8 and full page.
Sequential Counting
Basic
MODE
At MRS A3 = “1”. See the BURST SEQUENCE TABLE. (BL = 4,8)
BL = 4, 8 At BL =1, 2 interleave Counting = Sequential Counting
Interleave Counting
Every cycle Read/Write Command with random column address can realize Random
Column Access.
That is similar to Extended Data Out (EDO) Operation of conventional DRAM.
Random Random Column Access
MODE
tCCD = 1 CLK
13. About Burst Length Control
At MRS A210 = “000”
At auto precharge. tRAS should not be violated.
1
2
At MRS A210 = “001”
At auto precharge. tRAS should not be violated.
Basic
MODE
4
8
At MRS A210 = “010”
At MRS A210 = “011”
At MRS A210 = “111”
At the end of the burst length, burst is warp-around.
Full Page
At MRS A9 = “1”
Read burst = 1,2,4,8, full page write burst =1
At auto precharge of write, tRAS should not be violated.
Special
MODE
BRSW
t
BDL = 1, Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively.
Random
MODE
Burst Stop
Using burst stop command, any burst length control is possible.
Before the end of burst. Row precharge command of the same bank stops read /write burst
with auto precharge.
RAS Interrupt
(Interrupted by
Precharge)
t
RDL = 1 with DQM , Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively.
During read/write burst with auto precharge, RAS interrupt can not be issued.
Interrupt
MODE
Before the end of burst, new read/write stops read/write burst and starts new read/write
burst.
CAS Interrupt
During read/write burst with auto precharge, CAS interrupt can not be issued.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.4 23/45
ESMT
M12L2561616A (2K)
Operation Temperature Condition -40°C~85°C
FUNCTION TRUTH TABLE (TABLE 1)
Current
State
WE
BA
ADDR
ACTION
Note
CS RAS CAS
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
X
H
H
H
L
L
L
L
X
H
H
H
H
L
X
H
H
L
H
H
L
X
H
L
X
H
L
H
L
X
H
L
H
L
H
L
X
X
H
L
H
L
H
L
X
X
H
L
H
L
H
L
X
X
H
L
X
X
X
X
H
L
X
X
X
BA
BA
BA
X
X
X
X
NOP
NOP
ILLEGAL
2
2
IDLE
CA, A10/AP ILLEGAL
RA
A10/AP
Row (&Bank) Active ; Latch RA
NOP
Auto Refresh or Self Refresh
Mode Register Access
NOP
NOP
ILLEGAL
4
5
5
X
L
OP code
X
OP code
X
H
H
L
X
X
X
X
X
2
2
Row
Active
BA
BA
BA
BA
X
X
X
X
BA
BA
BA
BA
X
X
X
X
BA
BA
BA
BA
X
X
X
X
BA
BA
X
X
X
CA, A10/AP Begin Read ; latch CA ; determine AP
CA, A10/AP Begin Write ; latch CA ; determine AP
RA
A10/AP
L
H
H
L
X
H
H
L
ILLEGAL
Precharge
ILLEGAL
L
L
X
X
X
X
X
H
H
H
H
L
NOP (Continue Burst to End Æ Row Active)
NOP (Continue Burst to End Æ Row Active)
Term burst Æ Row active
Read
Write
CA, A10/AP Term burst, New Read, Determine AP
CA, A10/AP Term burst, New Write, Determine AP
RA
A10/AP
L
3
2
H
H
L
X
H
H
L
ILLEGAL
L
L
Term burst, Precharge timing for Reads
ILLEGAL
NOP (Continue Burst to End Æ Row Active)
NOP (Continue Burst to End Æ Row Active)
Term burst Æ Row active
X
X
X
X
X
H
H
H
H
L
CA, A10/AP Term burst, New Read, Determine AP
CA, A10/AP Term burst, New Write, Determine AP
RA
A10/AP
3
3
2
3
L
H
H
L
X
H
H
L
H
L
X
H
H
L
ILLEGAL
L
L
Term burst, Precharge timing for Writes
ILLEGAL
NOP (Continue Burst to End Æ Row Active)
NOP (Continue Burst to End Æ Row Active)
ILLEGAL
X
X
X
X
X
H
H
H
L
Read with
Auto
Precharge
CA, A10/AP ILLEGAL
RA, RA10
ILLEGAL
ILLEGAL
2
2
L
X
X
X
X
X
H
H
H
L
NOP (Continue Burst to End Æ Row Active)
NOP (Continue Burst to End Æ Row Active)
ILLEGAL
Write with
Auto
Precharge
X
X
X
X
BA
BA
X
CA, A10/AP ILLEGAL
RA, RA10
X
H
L
ILLEGAL
ILLEGAL
L
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.4
24/45
ESMT
M12L2561616A (2K)
Operation Temperature Condition -40°C~85°C
Current
State
BA
ADDR
ACTION
Note
CS RAS CAS WE
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
X
H
H
H
L
X
H
H
L
H
H
L
X
H
H
L
H
H
L
X
H
L
H
L
X
H
H
L
X
H
L
X
H
L
X
X
H
L
X
H
L
X
X
X
X
X
X
X
H
L
X
X
X
BA
BA
BA
X
X
X
X
BA
BA
BA
X
X
X
X
X
X
X
X
X
X
CA
RA
A10/AP
NOP Æ Idle after tRP
NOP Æ Idle after tRP
ILLEGAL
ILLEGAL
ILLEGAL
NOP Æ Idle after tRP
ILLEGAL
NOP Æ Row Active after tRCD
NOP Æ Row Active after tRCD
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
NOP Æ Idle after tRFC
NOP Æ Idle after tRFC
ILLEGAL
ILLEGAL
ILLEGAL
Read with
Auto
Precharge
2
2
2
4
L
L
X
X
X
X
X
H
H
H
L
L
L
X
H
H
L
Row
Activating
2
2
2
2
CA
RA
A10/AP
X
X
X
X
X
X
X
X
X
X
X
Refreshing
L
X
H
H
H
L
NOP Æ Idle after 2clocks
NOP Æ Idle after 2clocks
ILLEGAL
ILLEGAL
ILLEGAL
Mode
Register
Accessing
X
X
X
X
X
X
X
Abbreviations:
RA = Row Address
NOP = No Operation Command
BA = Bank Address
CA = Column Address
AP = Auto Precharge
*Note: 1. All entries assume the CKE was active (High) during the precharge clock and the current clock cycle.
2. Illegal to bank in specified state; Function may be legal in the bank indicated by BA, depending on the state of the bank.
3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
4. NOP to bank precharge or in idle state. May precharge bank indicated by BA (and A10/AP).
5. Illegal if any bank is not idle.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.4 25/45
ESMT
M12L2561616A (2K)
Operation Temperature Condition -40°C~85°C
FUNCTION TRUTH TABLE (TABLE2)
Current
State
CKE
( n-1 )
CKE
n
ADDR
ACTION
Note
CS RAS CAS WE
H
L
L
L
L
L
L
H
L
L
X
H
H
H
H
H
L
X
H
H
H
H
H
L
H
L
L
L
L
L
L
L
L
X
H
L
L
L
X
X
H
H
H
L
X
X
X
H
H
H
L
X
X
X
H
H
H
L
X
X
H
H
L
X
X
X
X
H
H
L
X
X
X
X
H
H
L
H
H
L
X
X
H
L
X
X
X
X
X
H
L
X
X
X
X
X
H
L
X
H
H
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
INVALID
Exit Self Refresh Æ Idle after tRFC (ABI)
Exit Self Refresh Æ Idle after tRFC (ABI)
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Maintain Self Refresh)
INVALID
Exit Self Refresh Æ ABI
Exit Self Refresh Æ ABI
ILLEGAL
6
6
Self
Refresh
L
X
X
H
L
L
L
All
Banks
Precharge
Power
7
7
L
L
L
L
ILLEGAL
ILLEGAL
Down
L
X
X
H
L
L
L
L
L
L
L
X
X
X
X
X
NOP (Maintain Low Power Mode)
Refer to Table1
Enter Power Down
Enter Power Down
ILLEGAL
ILLEGAL
Row (& Bank) Active
NOP
Enter Self Refresh
Mode Register Access
NOP
Refer to Operations in Table 1
Begin Clock Suspend next cycle
Exit Clock Suspend next cycle
Maintain Clock Suspend
H
H
H
H
H
H
H
H
H
L
8
8
X
X
X
RA
X
X
All
Banks
Idle
L
L
L
X
X
X
X
X
8
L
OP Code
L
H
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Any State
other than
Listed
H
H
L
9
9
above
L
Abbreviations: ABI = All Banks Idle, RA = Row Address
*Note: 6.CKE low to high transition is asynchronous.
7.CKE low to high transition is asynchronous if restart internal clock.
A minimum setup time 1CLK + tSS must be satisfy before any command other than exit.
8.Power down and self refresh can be entered only from the all banks idle state.
9.Must be a legal command.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.4
26/45
ESMT
M12L2561616A (2K)
Operation Temperature Condition -40°C~85°C
Single Bit Read-Write-Read Cycle (Same Page) @ CAS Latency = 3, Burst Length = 1
t
C H
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
C L O C K
t
C L
t
C C
H I G H
C K E
t
R A S
R C
t
t
S
H
* N o t e 1
C S
t
R C D
t R P
t
S S
t
S H
R A S
C A S
t
C C D
t
S S
t
S H
t
S S
t
S H
A D D R
C a
C b
R a
C c
R b
t
S S
* N o t e 2
* N o t e 2 , 3
* N o t e 4
* N o t e 2 , 3
* N o t e 2
* N o t e 2 , 3
BS
B S
B S
BA0,BA1
A10/AP
BS
BS
B S
* N o t e 3
* N o t e 3
* N o t e 4
R b
* N o t e 3
R a
t
S H
t
S A C
Q a
D b
D Q
Q c
t
S L Z
t
S S
t
O H
t
S H
W E
t
S S
t
S S
t
S H
D Q M
R o w A ct i ve
R e ad
Re a d
R o w A c t i v e
W r i t e
P r ec ha rg e
: D o n ' t C a r e
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.4 27/45
ESMT
M12L2561616A (2K)
Operation Temperature Condition -40°C~85°C
Note:
1. All input expect CKE & DQM can be don’t care when CS is high at the CLK high going edge.
2. Bank active @ read/write are controlled by BA0~BA1.
BA0
BA1
Active & Read/Write
Bank A
0
0
1
1
0
1
0
1
Bank B
Bank C
Bank D
3. Enable and disable auto precharge function are controlled by A10/AP in read/write command
A10/AP
BA0
0
BA1
0
Operating
Disable auto precharge, leave A bank active at end of burst.
Disable auto precharge, leave B bank active at end of burst.
Disable auto precharge, leave C bank active at end of burst.
Disable auto precharge, leave D bank active at end of burst.
Enable auto precharge, precharge bank A at end of burst.
Enable auto precharge, precharge bank B at end of burst.
Enable auto precharge, precharge bank C at end of burst.
Enable auto precharge, precharge bank D at end of burst.
0
1
0
1
0
1
1
0
0
0
1
1
1
0
1
1
4. A10/AP and BA0~BA1 control bank precharge when precharge is asserted.
A10/AP
BA0
0
BA1
0
Precharge
Bank A
0
0
0
0
1
0
1
Bank B
1
0
Bank C
1
1
Bank D
X
X
All Banks
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Publication Date: Jun. 2012
Revision: 1.4 28/45
ESMT
M12L2561616A (2K)
Operation Temperature Condition -40°C~85°C
Power Up Sequence
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.4
29/45
ESMT
M12L2561616A (2K)
Operation Temperature Condition -40°C~85°C
Read & Write Cycle at Same Bank @ Burst Length = 4
13
14
15
16
17
18
19
0
1
2
3
4
5
6
7
8
9
11
12
10
C L O C K
H I GH
C K E
* N o t e 1
t
R C
C S
t
R C D
R A S
* N o t e 2
C A S
A D D R
BA0
Cb
Ca
R b
R a
BA1
A10/AP
C L = 2
Ra
Rb
Q a0 Q a1
D b 0 D b 1 D b 2 Db 3
D b0 Db 1 Db 2 Db 3
Q a 2 Q a 3
* N o t e 3
D Q
t
R D L
C L = 3
Qa 0 Qa 1
Q a3
Q a2
* N o t e 3
t
R D L
W E
DQ M
Precharge
( A - Bank )
Read
( A - Bank )
Row Active
( A - Bank )
Write
( A - Bank )
Row Active
( A - Bank )
Pr ec ha r ge
( A Ba nk )
-
: D o n ' t C a r e
*Note:
1. Minimum row cycle times is required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row
precharge. Last valid output will be Hi-Z (tSHZ) after the clock.
3. Output will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst)
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Publication Date: Jun. 2012
Revision: 1.4 30/45
ESMT
M12L2561616A (2K)
Operation Temperature Condition -40°C~85°C
Page Read & Write Cycle at Same Bank @ Burst Length = 4
Note: 1. To Write data before burst read ends. DQM should be asserted three cycles prior to write command to avoid bus
contention.
2. Row precharge will interrupt writing. Last data input, tRDL before row precharge , will be written.
3. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input
data after Row precharge cycle will be masked internally.
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Publication Date: Jun. 2012
Revision: 1.4 31/45
ESMT
M12L2561616A (2K)
Operation Temperature Condition -40°C~85°C
Page Read Cycle at Different Bank @ Burst Length = 4
Note: 1. CS can be don’t cared when RAS , CAS and WE are high at the clock high going edge.
2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
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ESMT
M12L2561616A (2K)
Operation Temperature Condition -40°C~85°C
Page Write Cycle at Different Bank @ Burst Length = 4
*Note: 1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.
2. To interrupt burst write by Row precharge, both the write and the precharge banks must be the same.
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Publication Date: Jun. 2012
Revision: 1.4 33/45
ESMT
M12L2561616A (2K)
Operation Temperature Condition -40°C~85°C
Read & Write Cycle at Different Bank @ Burst Length = 4
*Note: 1. tCDL should be met to complete write.
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Publication Date: Jun. 2012
Revision: 1.4
34/45
ESMT
M12L2561616A (2K)
Operation Temperature Condition -40°C~85°C
Read & Write cycle with Auto Precharge @ Burst Length = 4
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Publication Date: Jun. 2012
Revision: 1.4
35/45
ESMT
M12L2561616A (2K)
Operation Temperature Condition -40°C~85°C
Clock Suspension & DQM Operation Cycle @ CAS Latency = 2, Burst Length = 4
*Note: 1. DQM is needed to prevent bus contention
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Publication Date: Jun. 2012
Revision: 1.4 36/45
ESMT
M12L2561616A (2K)
Operation Temperature Condition -40°C~85°C
Read interrupted by Precharge Command & Read Burst Stop Cycle @ Burst Length = Full page
*Note: 1. About the valid DQs after burst stop, it is same as the case of RAS interrupt.
Both cases are illustrated above timing diagram. See the label 1, 2 on them.
But at burst write, Burst stop and RAS interrupt should be compared carefully.
Refer the timing diagram of “Full page write burst stop cycles”.
2. Burst stop is valid at every burst length.
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Publication Date: Jun. 2012
Revision: 1.4 37/45
ESMT
M12L2561616A (2K)
Operation Temperature Condition -40°C~85°C
Write interrupted by Precharge Command & Write Burst Stop Cycle @ Burst Length = Full page
*Note: 1. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by
AC parameter of tRDL
.
DQM at write interrupted by precharge command is needed to prevent invalid write.
DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input
data after Row precharge cycle will be masked internally.
2. Burst stop is valid at every burst length.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.4 38/45
ESMT
M12L2561616A (2K)
Operation Temperature Condition -40°C~85°C
Active/Precharge Power Down Mode @ CAS Latency = 2, Burst Length = 4
1 0
11
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
0
1
2
3
4
5
6
7
8
9
C L O C K
C K E
* N o t e 2
t
S S
t
S S
t
S S
* N o t e 1
* N o t e 3
C S
R A S
C A S
A D D R
R a
C a
B A 0
B A 1
A 1 0 / A P
R a
t
S H Z
DQ
Q a 0 Q a 1 Q a 2
W E
D Q M
R e a d
P r e c h a r g e
P re c h a rg e
P o we r -D o wn
En tr y
R o w A c t i v e
P re ch a rg e
P ower -D own
E xi t
A c t i v e
P o w e r - d o w n
E x i t
A ct i v e
P o w e r -d o w n
E n t r y
:
D o n ' t c a r e
*Note: 1. All banks should be in idle state prior to entering precharge power down mode.
2. CKE should be set high at least 1CLK + tSS prior to Row active command.
3. Can not violate minimum refresh specification.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.4 39/45
ESMT
M12L2561616A (2K)
Operation Temperature Condition -40°C~85°C
Self Refresh Entry & Exit Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
C L O C K
C K E
* N o t e 4
* N o t e 2
t
R F C mi n
* N o t e 1
* N o t e 6
* N o t e 3
t
S S
C S
* N o t e 5
R A S
* N o t e 7
C A S
A D D R
B A 0 , B A 1
A10/AP
DQ
Hi -Z
Hi -Z
W E
D Q M
S e l f R e f r e s h E x i t
S e l f R e f r e s h E n t r y
A u t o R e f r e s h
:
D o n ' t c a r e
*Note:
TO ENTER SELF REFRESH MODE
1. CS , RAS & CAS with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE.
3. The device remains in self refresh mode as long as CKE stays “Low”.
cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System clock restart and be stable before returning CKE high.
5. CS starts from high.
6. Minimum tRFC is required after CKE going high to complete self refresh exit.
7. 8K cycles of burst auto refresh is required immediately before self refresh entry and immediately after self refresh exit.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.4 40/45
ESMT
M12L2561616A (2K)
Operation Temperature Condition -40°C~85°C
Mode Register Set Cycle
Auto Refresh Cycle
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
8
9
1 0
C L O C K
C K E
C S
H I G H
H I G H
* N o t e 2
t
R F C
R A S
* N o t e 1
C A S
* N o t e 3
A D D R
K e y
R a
H I - Z
H I - Z
D Q
W E
D Q M
N e w
C o m m a n d
M R S
N e w C o m m a n d
: D o n ' t C a r e
Au t o Ref re sh
All banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
MODE REGISTER SET CYCLE
*Note: 1. CS , RAS , CAS , & WE activation at the same clock cycle with address key will set internal mode register.
2. Minimum 2 clock cycles should be met before new RAS activation.
3. Please refer to Mode Register Set table.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.4 41/45
ESMT
M12L2561616A (2K)
Operation Temperature Condition -40°C~85°C
PACKING DIMENSIONS
54-LEAD TSOP(II) SDRAM (400mil) (1:3)
A
D
A2
28
54
see detail A
B
B
θ
L
L1
DETAIL "A"
Pin 1 identifier
b
27
1
b1
BASE METAL
-C-
WITH PLANTING
SECTION B-B
e
b
Y
Seating plane
Symbol
Dimension in mm
Norm
Dimension in inch
Norm
Min
Max
Min
Max
A
A1
A2
b
b1
c
c1
D
E
1.20
0.15
1.05
0.45
0.40
0.21
0.16
0.047
0.006
0.041
0.018
0.016
0.008
0.006
0.05
0.95
0.30
0.30
0.12
0.10
0.10
1.00
0.002
0.037
0.012
0.012
0.005
0.004
0.004
0.039
0.35
0.014
0.127
0.005
22.22 BSC
11.76 BSC
10.16 BSC
0.50
0.875 BSC
0.463 BSC
0.400 BSC
0.020
E1
L
0.40
0.60
0.016
0.024
L1
e
0.80 REF
0.80 BSC
0.031 REF
0.031 BSC
Y
Θ
0.1
8°
0.004
8°
0°
0°
Controlling dimension : Millimeter
(Revision date : May 25 2012)
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.4 42/45
ESMT
M12L2561616A (2K)
Operation Temperature Condition -40°C~85°C
PACKING
54-BALL
DIMENSIONS
SDRAM ( 8x8 mm )
Symbol
Dimension in mm
Dimension in inch
Min
Norm
Max
1.00
0.30
0.71
0.40
8.10
8.10
Min
Norm
Max
A
A1
A2
Φb
D
0.039
0.012
0.028
0.016
0.319
0.319
0.20
0.61
0.30
7.90
7.90
0.25
0.66
0.35
8.00
8.00
6.40
6.40
0.80
0.008
0.024
0.012
0.311
0.311
0.010
0.026
0.014
0.315
0.315
0.252
0.252
0.031
E
D1
E1
e
Controlling dimension : Millimeter.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.4
43/45
ESMT
M12L2561616A (2K)
Operation Temperature Condition -40°C~85°C
Revision History
Revision
1.0
Date
Description
2010.01.13
2010.03.22
Original
1.1
Modify the specification of ICC6
1. Modify packing dimensions of BGA
2. Add package description into pin/ball configuration
1. Add operating ambient temperature into absolute maximum
ratings
2. Modify the specification of tOH for speed grade -6 and -7
3. Add note 1 into tRDL(min)
1.2
1.3
2010.05.03
2011.01.03
4. Modify TSOPII packing dimension
Modify Page 42
θ=10 to 8°
1.4
2012.06.07
b,b1=0.25 to 0.3mm
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.4 44/45
ESMT
M12L2561616A (2K)
Operation Temperature Condition -40°C~85°C
Important Notice
All rights reserved.
No part of this document may be reproduced or duplicated in any form or by any means
without the prior permission of ESMT.
The contents contained in this document are believed to be accurate at the time of
publication. ESMT assumes no responsibility for any error in this document, and reserves
the right to change the products or specification in this document without notice.
The information contained herein is presented only as a guide or examples for the
application of our products. No responsibility is assumed by ESMT for any infringement of
patents, copyrights, or other intellectual property rights of third parties which may result
from its use. No license, either express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of ESMT or others.
Any semiconductor devices may have inherently a certain rate of failure. To minimize
risks associated with customer's application, adequate design and operating safeguards
against injury, damage, or loss from such failure, should be provided by the customer
when making application designs.
ESMT's products are not authorized for use in critical applications such as, but not limited
to, life support devices or system, where failure or abnormal operation may directly affect
human lives or cause physical injury or property damage. If products described here are
to be used for such kinds of application, purchaser must do its own quality assurance
testing appropriate to such applications.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.4 45/45
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