M12L16161A-8T [ESMT]
512K x 16Bit x 2Banks Synchronous DRAM; 512K X 16位X 2Banks同步DRAM
| 型号： | M12L16161A-8T |
| 厂家： | 
ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. |
| 描述： | 512K x 16Bit x 2Banks Synchronous DRAM |
| 文件： | 总27页 (文件大小：568K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M12L16161A
512K x 16Bit x 2Banks Synchronous DRAM
FEATURES
GENERAL DESCRIPTION
JEDEC standard 3.3V power supply
The M12L16161A is 16,777,216 bits synchro-
nous high data rate Dynamic RAM organized as
2 x 524,288 words by 16 bits, fabricated with
high performance CMOS technology. Synchro-
nous design allows precise cycle control with the
use of system clock I/O transactions are possible
on every clock cycle. Range of operating fre-
LVTTL compatible with multiplexed address
Dual banks operation
MRS cycle with address key programs
-
-
-
CAS Latency (2 & 3 )
Burst Length (1, 2, 4, 8 & full page)
Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge quencies, programmable burst length and pro-
of the system clock
Burst Read Single-bit Write operation
DQM for masking
grammable latencies allow the same device to be
useful for a variety of high bandwidth, high
performance memory system applications.
Auto & self refresh
32ms refresh period (2K cycle)
ORDERING INFORMATION
Part NO.
MAX Freq. Interface
233MHz
200MHz
Package
M12L16161A-4.3T
M12L16161A-5T
M12L16161A-5.5T
M12L16161A-6T
M12L16161A-7T
M12L16161A-8T
183MHz
166MHz
50
TSOP(II)
LVTTL
143MHz
125MHz
PIN CONFIGURATION (TOP VIEW)
DD
SS
V
1
V
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
DQ0
DQ1
2
DQ15
DQ14
3
SSQ
V
SSQ
V
4
DQ2
DQ3
VDDQ
DQ4
DQ5
5
DQ13
DQ12
VDDQ
DQ11
DQ10
6
7
8
9
SSQ
V
SSQ
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
DQ6
DQ7
DQ9
DQ8
DDQ
V
DDQ
V
LDQM
WE
CAS
RAS
CS
N.C/RFU
UDQM
CLK
CKE
N.C
A9
BA
A10/AP
A0
A8
A7
A1
A6
A2
A5
A3
A4
50PIN TSOP(II)
(400mil x 825mil)
(0.8 mm PIN PITCH)
VDD
VSS
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Publication Da te J an. 2000
Elite Semiconductor Memory Technology Inc.
P.1
:
Revis ion 1.3u
M12L16161A
FUNCTIONAL BLOCK DIAGRAM
LWE
Bank Select
Data Input Register
LDQM
512K x 16
512K x 16
DQi
CLK
ADD
Column Decoder
Latency & Burst Length
LCKE
Programming Register
LWCBR
LRAS LCBR
LWE
LDQM
LCAS
Timing Register
CKE
CLK
L(U)DQM
RAS
CAS
WE
CS
PIN FUNCTION DESCRIPTION
Pin
CLK
Name
System Clock
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and L(U)DQM.
CS
Chip Select
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE
Clock Enable
Row / column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10, column address : CA0 ~ CA7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
A0 ~ A10/AP Address
BA
Bank Select Address
Latches row addresses on the positive going edge of the CLK with RAS
low.
Row Address Strobe
RAS
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with
Column Address Strobe
CAS
CAS low.
Enables column access.
Enables write operation and row precharge.
Write Enable
WE
Latches data in starting from CAS , WE active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
L(U)DQM
Data Input / Output Mask
DQ0 ~ 15
VDD/VSS
Data Input / Output
Power Supply/Ground
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
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Elite Semiconductor Memory Technology Inc.
P.2
:
Revis ion 1.3u
M12L16161A
Isolated power supply and ground for the output buffers to provide improved
noise immunity.
VDDQ/VSSQ
N.C/RFU
Data Output Power/Ground
No Connection/
Reserved for Future Use
This pin is recommended to be left No Connection on the device.
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to VSS
Voltage on VDD supply relative to VSS
Storage temperature
Symbol
VIN,VOUT
VDD,VDDQ
TSTG
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ + 150
1
Unit
V
V
°C
W
Power dissipation
PD
Short circuit current
IOS
50
MA
Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
C
Recommended operating conditions (Voltage referenced to VSS = 0V, TA=0 to 70 °
)
Parameter
Supply voltage
Symbol
VDD,VDDQ
VIH
Min
3.0
2.0
-0.3
2.4
-
Typ
3.3
3.0
0
-
-
-
-
Max
3.6
VDD+0.3
Unit
V
V
V
V
V
uA
uA
Note
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
1
2
VIL
VOH
VOL
IIL
0.8
-
0.4
5
IOH =-2mA
IOL = 2mA
-5
-5
3
4
Output leakage current
IOL
5
Note : 1.VIH (max) = 4.6V AC for pulse width
10ns acceptable.
10ns acceptable.
≤
≤
2.VIL (min) = -1.5V AC for pulse width
3.Any input 0V VIN ≤ VDD+ 0.3V, all other pins are not under test = 0V.
≤
4.Dout is disabled, 0V
VOUT ≤ VDD.
≤
CAPACITANCE (VDD = 3.3V, TA = 25 °C , f = 1MHz)
Pin
Symbol
Min
Max
Unit
CLOCK
CCLK
2.5
4.0
pF
RAS , CAS , WE , CS , CKE, LDQM,
CIN
2.5
5.0
pF
UDQM
ADDRESS
DQ0 ~DQ15
CADD
COUT
2.5
4.0
5.0
6.5
pF
pF
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Publication Da te J an. 2000
Elite Semiconductor Memory Technology Inc.
P.3
:
Revis ion 1.3u
M12L16161A
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70 °C VIH(min)/VIL(max)=2.0V/0.8V)
CAS
Latency
Version
Parameter
Symbol
Test Condition
Unit Note
-4.3 -5 -5.5 -6 -7 -8
Operating Current
(One Bank Active)
Burst Length = 1
tRC tRC (min), tCC tCC (min), IOL= 0mA
ICC1
250 230 210 190 160 140 mA
1
≥
≥
mA
ICC2
P
2
2
Precharge Standby
Current in power-down
mode
CKE VIL(max), tCC =15ns
≤
ICC2PS
CKE VIL(max), CLK VIL(max), tCC
=
∞
≤
≤
CKE VIH(min), CS VIH(min), tCC =15ns
Input signals are changed one time during 30ns
≥
≥
30
2
mA
ICC2
N
Precharge Standby
Current in non power-
down mode
CKE VIH(min), CLK VIL(max), tCC
=
∞
≥
≤
mA
mA
ICC2NS
Input signals are stable
ICC3
P
10
10
CKE VIL(max), tCC =15ns
≤
Active Standby Current
in power-down mode
ICC3PS
CKE
VIL(max), CLK VIL(max), tCC = ∞
≤
≤
CKE VIH(min), CS VIH(min), tCC=15ns
≥
≥
ICC3
N
40
10
mA
Active Standby Current
in non power-down
mode
Input signals are changed one time during 30ns
CKE VIH (min), CLK VIL(max), tCC ∞
=
≥
≤
ICC3NS
mA
mA
(One Bank Active)
Input signals are stable
1
IOL= 0Ma, Page Burst
All Band Activated, tCCD = tCCD
(min)
3
2
270 250 230 210 180 160
270 250 230 210 180 160
Operating Current
(Burst Mode)
I
I
CC4
Refresh Current
tRC tRC(min)
≥
CC5
270 250 230 210 180 160 mA
mA
2
Self Refresh Current
ICC6
CKE 0.2V
1
≤
Note: 1.Measured with outputs open. Addresses are changed only one time during tCC(min).
2.Refresh period is 32ms. Addresses are changed only one time during tCC(min).
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Publication Da te J an. 2000
Elite Semiconductor Memory Technology Inc.
P.4
:
Revis ion 1.3u
M12L16161A
AC OPERATING TEST CONDITIONS (VDD=3.3V ± 0.3V,TA= 0 to 70 C )
°
Parameter
Input levels (Vih/Vil)
Value
2.4 / 0.4
1.4
tr / tf = 1 / 1
1.4
Unit
V
V
ns
V
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
See Fig.2
3.3V
Vtt =1.4V
1200
50
Ou tput
VOH(DC) = 2.4V, IOH = -2m A
VOL(DC) = 0.4V, IOL = 2m A
Ou tput
Z0=50
30 pF
870
30 pF
(Fig.2) AC Ou tpu t Load Circu it
(Fig.1) DC Ou tpu t Load circu it
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
-4.3 -5 -5.5 -6
Parameter
Symbol
Unit
Note
-7
-8
Row active to row active delay
8.6
10
11
16
16
40
12
16
18
42
14
16
ns
ns
ns
ns
us
1
1
1
1
tRRD(min)
12.9 15
12.9 15
34.4 40
16
20
42
20
20
48
tRCD(min)
tRP(min)
RAS to CAS delay
Row precharge time
tRAS(min)
tRAS(max)
Row active time
100
Row cycle time
47.3 55
60
60
63
68
ns
1
2
2
2
3
tRC(min)
Last data in to new col. Address delay
Last data in to row precharge
Last data in to burst stop
1
1
1
1
CLK
CLK
CLK
CLK
tCDL(min)
tRDL(min)
tBDL(min)
Col. Address to col. Address delay
Number of valid output data
tCCD(min)
CAS latency=3
CAS latency=2
1
1
ea
4
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
4. Minimum delay is required to complete write.
4. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks.
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Publication Da te J an. 2000
Elite Semiconductor Memory Technology Inc.
P.5
:
Revis ion 1.3u
M12L16161A
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
-4.3
-5
-5.5
-6
-7
-8
Parameter
Symbol
Unit Note
Min Max Min Max Min Max Min Max Min Max Min Max
CAS Latency =3
4.3
6
5
7
-
5.5
7.5
-
6
8
-
7
8
10
-
tCC
ns
ns
1
1
CLK cycle time
1000
1000
1000
1000
1000
1000
CAS Latency =2
CAS Latency =3
CAS Latency =2
8.6
-
-
4
5
4.5
5
5
6
5.5
6
6
6
6
7
CLK to valid
output delay
tSAC
-
-
-
-
-
-
Output data hold time
CLK high pulse width
CLK low pulse width
Input setup time
ns
ns
ns
ns
ns
ns
2
3
3
3
3
2
2
1.7
1.7
1.7
1
2
2
2
2
1
2.5
2
2.5
2
2.5
2.5
2.5
2
2.5
3
tOH
tCH
tCL
tSS
2
2
3
2
2
2.5
1
Input hold time
1
1
1
tSH
tSLZ
CLK to output in Low-Z
1
-
1
-
1
-
1
-
1
-
1
-
4
5
4.5
5
5
6
5.5
6
6
6
6
7
CAS Latency =3
CAS latency =2
CLK to output
in Hi-Z
ns
tSHZ
-
-
-
-
-
-
*All AC parameters are measured from half to half.
Note: 1.Parameters depend on programmed CAS latency.
2.If clock rising time is longer than 1ns,(tr/2-0.5)ns should be added to the parameter.
3.Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr+ tf)/2-1]ns should be added to
the parameter.
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Publication Da te J an. 2000
Elite Semiconductor Memory Technology Inc.
P.6
:
Revis ion 1.3u
M12L16161A
FREQUENCY vs. AC PARAMENTER RELATIONAHIP TABLE
(Unit: number of clock)
M12L16161A-4.3T
tRC
47.3ns
tRAS
34.3ns
tRP
12.9ns
tRRD
8.6ns
tRCD
12.9ns
tCCD
4.3ns
tCDL
4.3ns
tRDL
4.3ns
CAS Latency
Frequency
233MHz(4.3ns)
200MHz(5.0ns)
183MHz(5.5ns)
166MHz(6.0ns)
143MHz(7.0ns)
3
3
3
3
2
11
10
10
9
8
7
7
6
5
3
3
3
3
2
2
2
2
2
2
3
3
3
3
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
7
(Unit: number of clock)
M12L16161A-5T
tRC
55ns
11
10
10
9
tRAS
tRP
tRRD
tRCD
tCCD
tCDL
tRDL
CAS Latency
Frequency
40ns
15ns
10ns
15ns
5ns
1
5ns
1
5ns
1
200MHz(5.0ns)
183MHz(5.5ns)
166MHz(6.0ns)
143MHz(7.0ns)
125MHz(8.0ns)
111MHz(9.0ns)
3
3
3
2
2
2
8
8
7
6
5
5
3
3
3
3
2
2
2
2
2
2
2
2
3
3
3
3
2
2
1
1
1
1
1
1
1
1
1
7
1
1
1
7
1
1
1
(Unit: number of clock)
M12L16161A-5.5T
tRC
60ns
11
10
9
tRAS
tRP
tRRD
tRCD
tCCD
tCDL
tRDL
CAS Latency
Frequency
40ns
16ns
11ns
16ns
5.5ns
5.5ns
5.5ns
183MHz(5.5ns)
166MHz(6.0ns)
143MHz(7.0ns)
125MHz(8.0ns)
111MHz(9.0ns)
3
3
2
2
2
8
7
6
5
5
3
3
3
2
2
2
2
2
2
2
3
3
3
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
8
7
(Unit: number of clock)
M12L16161A-6T
tRC
60ns
tRAS
42ns
tRP
18ns
tRRD
12ns
tRCD
16ns
tCCD
6ns
tCDL
6ns
tRDL
6ns
CAS Latency
Frequency
166MHz(6.0ns)
143MHz(7.0ns)
125MHz(8.0ns)
111MHz(9.0ns)
100MHz(10.0ns)
3
3
2
2
2
10
9
7
6
6
5
5
3
3
3
2
2
2
2
2
2
2
3
3
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
9
7
7
(Unit: number of clock)
M12L16161A-7T
tRC
tRAS
tRP
tRRD
tRCD
tCCD
tCDL
tRDL
CAS Latency
Frequency
62ns
42ns
20ns
14ns
16ns
7ns
1
7ns
1
7ns
1
143MHz(7.0ns)
125MHz(8.0ns)
111MHz(9.0ns)
100MHz(10.0ns)
83MHz(12.0ns)
3
3
2
2
2
9
9
8
7
6
6
6
5
5
4
3
3
3
2
2
2
2
2
2
2
3
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
(Unit: number of clock)
M12L16161A-8T
tRC
tRAS
tRP
tRRD
tRCD
tCCD
tCDL
tRDL
CAS Latency
Frequency
68ns
48ns
20ns
16ns
20ns
8ns
1
8ns
1
8ns
1
125MHz(8.0ns)
111MHz(9.0ns)
100MHz(10.0ns)
83MHz(12.0ns)
75MHz(13.0ns)
3
3
2
2
2
9
9
7
6
6
6
6
5
4
4
3
3
2
2
2
2
2
2
2
2
3
3
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
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Elite Semiconductor Memory Technology Inc.
P.7
:
Revis ion 1.3u
M12L16161A
Mode Register
11 10
9
0
9
1
8
7
1
7
0
6
6
5
5
4
4
3
2
2
1
0
0
0
0
0
JEDEC Standard Test Set (refresh counter test)
11 10
8
3
WT
1
BL
x
x
0
LTMODE
Burst Read and Single Write (for Write
Through Cache)
11 10
9
8
7
6
5
4
3
2
1
0
1
0
Use in future
11 10
9
x
9
0
8
1
8
0
7
1
7
0
6
v
6
5
v
5
4
v
4
3
v
3
2
v
2
1
v
1
BL
0
v
0
x
x
Vender Specific
v =Valid
11 10
0
0
LTMODE
WT
Mode Register Set
x =Don’t care
Bit2-0
000
001
010
011
100
101
110
111
WT=0
WT=1
1
2
4
8
R
R
R
1
2
4
Burst length
8
R
R
R
R
Full page
0
1
Sequential
Interleave
Wrap type
Bits6-4
CAS Latency
000
001
010
011
100
101
110
111
R
R
2
Latency mode
3
R
R
R
R
Mode Register Write Timing
Remark R : Reserved
CLOCK
CKE
CS
RAS
CAS
WE
A0-A11
Mod e Regis ter Write
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Publication Da te J an. 2000
Elite Semiconductor Memory Technology Inc.
P.8
:
Revis ion 1.3u
M12L16161A
Burst Length and Sequence
(Burst of Two)
Starting Address
Sequential Addressing
Interleave Addressing
(column address A0 binary)
Sequence (decimal)
Sequence (decimal)
0
1
0,1
1,0
0,1
1,0
(Burst of Four)
Starting Address
(column address A1-A0, binary)
Sequential Addressing
Sequence (decimal)
0,1,2,3
Interleave Addressing
Sequence (decimal)
0,1,2,3
00
01
10
11
1,2,3,0
2,3,0,1
3,0,1,2
1,0,3,2
2,3,0,1
3,2,1,0
(Burst of Eight)
Starting Address
(column address A2-A0, binary)
Sequential Addressing
Sequence (decimal)
0,1,2,3,4,5,6,7
1,2,3,4,5,6,7,0
2,3,4,5,6,7,0,1
3,4,5,6,7,0,1,2
4,5,6,7,0,1,2,3
5,6,7,0,1,2,3,4
6,7,0,1,2,3,4,5
7,0,1,2,3,4,5,6
Interleave Addressing
Sequence (decimal)
0,1,2,3,4,5,6,7
1,0,3,2,5,4,7,6
2,3,0,1,6,7,4,5
3,2,1,0,7,6,5,4
4,5,6,7,0,1,2,3
5,4,7,6,1,0,3,2
6,7,4,5,2,3,0,1
7,6,5,4,3,2,1,0
000
001
010
011
100
101
110
111
Full page burst is an extension of the above tables of Sequential Addressing, with the length being 256 for 1Mx16 divice.
POWER UP SEQUENCE
1.Apply power and start clock, attempt to maintain CKE= “H”, L(U)DQM = “H” and the other pin are NOP condition at the
inputs.
2.Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3.Issue precharge commands for all banks of the devices.
4.Issue 2 or more auto-refresh commands.
5.Issue mode register set command to initialize the mode register.
Cf.)Sequence of 4 & 5 is regardless of the order.
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Publication Da te J an. 2000
Elite Semiconductor Memory Technology Inc.
P.9
:
Revis ion 1.3u
M12L16161A
SIMPLIFIED TRUTH TABLE
COMMAND
CKEn-1 CKEn
DQM BA A10/AP A9~A0 Note
CS RAS CAS WE
Register
Refresh
Mode Register Set
Auto Refresh
H
X
H
L
L
L
L
L
X
OP CODE
1,2
3
3
H
L
L
L
H
X
X
Entry
Self Refresh
L
H
L
H
X
L
H
X
H
H
X
H
3
3
Exit
L
H
H
H
X
X
X
X
X
X
Bank Active & Row Addr.
V
V
Row Address
Column
Address
4
Auto Precharge Disable
L
Read &
Column Address
L
H
L
H
4,5
Auto Precharge Enable
Auto Precharge Disable
(A0~A7)
H
Column
Address
(A0~A7)
L
4
Write & Column
Address
H
X
L
H
L
L
X
V
Auto Precharge Enable
H
4,5
Burst Stop
H
H
X
X
L
L
H
L
H
H
L
L
X
X
X
6
4
4
Bank Selection
Both Banks
V
X
L
X
H
Precharge
H
L
X
H
L
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Clock Suspend or
Active Power Down
Entry
Exit
H
L
L
H
L
X
X
X
X
Entry
H
Precharge Power Down Mode
X
H
L
Exit
L
H
X
V
X
DQM
H
H
H
X
X
7
H
L
X
H
X
H
No Operation Command
X
(V= Valid, X= Don’t Care, H= Logic High , L = Logic Low)
Note:1 OP Code: Operation Code
A0~ A10/AP, BA: Program keys.(@MRS)
2. MRS can be issued only at both banks precharge state.
A new command can be issued after 2 clock cycle of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by “Auto”.
Auto / self refresh can be issued only at both banks precharge state.
4. BA: Bank select address.
If “Low”: at read, write, row active and precharge, bank A is selected.
If “High”: at read, write, row active and precharge, bank B is selected.
If A10/AP is “High” at row precharge, BA ignored and both banks are selected.
5.During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read /write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6.Burst stop command is valid at every burst length.
7.DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0), but
makes
Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
:
Publication Da te J an. 2000
Elite Semiconductor Memory Technology Inc.
P.10
:
Revis ion 1.3u
M12L16161A
Single Bit Read-Write-Read Cycle (Same Page) @CAS Latency=3, Burst Length=1
t C H
0
1
2
3
4
5
6
7
8
9
10
11
12
1 3
14
15
1 6
17
18
1 9
C L O C K
t C L
t C C
H IG H
C K E
C S
t R A S
t R C
*Note1
t S H
t R C D
t R P
t S S
t S H
R A S
C A S
t C C D
t S S
t S H
t S S
t S
H
t S S
C b
A D D R
R a
t S S
R b
C a
C c
t S
H
*Note2
*Note2,3
*Note2,3
*Note2,3 *Note4
*Note2
B S
B S
B S
B S
B S
B A
B S
*Note
3
*Note
3
*Note
3
*Note4
R a
R b
A 1 0 / A P
t R A C
t S A C
t S
H
DQ
Q c
D b
Q a
t O H
t S
L Z
t S S
t S
H
W E
t S S
t S S
t S
H
D Q M
R o w A c t i v e
R e a d
P r e c h a r g e
W r i t e
R o w A c t i v e
R e a d
: D o n ' t C a r e
:
Publication Da te J an. 2000
Elite Semiconductor Memory Technology Inc.
P.11
:
Revis ion 1.3u
M12L16161A
*Note: 1. All inputs expect CKE & DQM can be don’t care when CS is high at the CLK high going edge.
2. Bank active & read/write are controlled by BA.
BA
0
Active & Read/Write
Bank A
1
Bank B
3.Enable and disable auto precharge function are controlled by A10/AP in read/write command.
A10/AP BA
Operation
0
1
0
1
Disable auto precharge, leave bank A active at end of burst.
Disable auto precharge, leave bank B active at end of burst.
Enable auto precharge, precharge bank A at end of burst.
Enable auto precharge, precharge bank B at end of burst.
0
1
4.A10/AP and BA control bank precharge when precharge command is asserted.
A10/AP BA
precharge
Bank A
Bank B
0
0
1
0
1
X
Both Banks
:
Publication Da te J an. 2000
Elite Semiconductor Memory Technology Inc.
P.12
:
Revis ion 1.3u
M12L16161A
Power Up Sequence
0
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
C L O C K
C K E
H i g h l e v e l i s n e c e s s a r y
CS
t R C
t R C
t R P
RAS
CAS
A D D R
R A a
K e y
K e y
BA
A 1 0 / A P
D Q
R A a
K e y
H i g h - Z
WE
D Q M
H i g h l e v e l i s n e c e s s a r y
M o d e R e g i s t e r S e t
P r e c h a r g e
A l l B a n k s
A u t o R e f r e s h
A u t o R e f r e s h
( A - B a n k )
R o w A c t i v e
:
D o n ' t c a r e
:
Publication Da te J an. 2000
Elite Semiconductor Memory Technology Inc.
P.13
:
Revis ion 1.3u
M12L16161A
Read & Write Cycle at Same Bank @Burst Length = 4
0
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
C LO C K
HIG H
C KE
*Note 1
tRC
CS
RAS
CAS
tRCD
*Note 2
ADDR
R b
C a 0
R a
C b 0
BA
A1 0 / AP
C L=2
R b
R a
t O H
Q a 1
Q a 2
Q a 3
Q a 2
D b 3
D b 2
D b 1
Q a 0
D b 0
D b 0
tRAC
*Note 4
tS H Z
QC
*Note 3
tS AC
t R D L
t O H
C L=3
D b 2
Q a 0
Q a 1
Q a 3
D b 3
D b 1
tRAC
*Not e4
tS AC
t S H Z
*Note 3
t R D L
WE
DQM
Pr ec h a r g e
(A-B a n k )
Pr e c h a r g e
(A-B a n k )
Ro w Ac tive
(A-Ba n k )
Ro w Ac t ive
(A-Ba n k )
R ea d
(A-B a n k )
Wr it e
(A-B a n k )
: D o n 't c a r e
1.Minimum row cycle times is required to complete internal DRAM operation.
*Note:
2.Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row
precharge. Last valid output will be Hi-Z(tSHZ) after the clock.
3.Access time from Row active command. tcc*(tRCD +CAS latency-1)+tSAC
4.Ouput will be Hi-Z after the end of burst.(1,2,4,8 bit burst)
Burst can’t end in Full Page Mode.
:
Publication Da te J an. 2000
Elite Semiconductor Memory Technology Inc.
P.14
:
Revis ion 1.3u
M12L16161A
Page Read & Write Cycle at Same Bank @ Burst Length=4
5
6
9
15
16
0
1
3
4
12
7
2
8
10
11
13
19
14
17
18
CLOCK
CKE
HIGH
CS
tRCD
RAS
*Note2
CAS
ADDR
BA
Ra
Cc0
Cd0
Ca0
Cb0
A10/ AP
CL=2
Ra
tRDL
Qa1
Qa0
Dd0
Dd0
Qa0
Qb0
Qa1
Qb1
Qb1
Dc0
Dc0
Dc1
Dd1
Qb2
Qb2
DQ
Dc1
Dd2
CL=3
tCDL
WE
*Note3
*Note1
DQM
Read
Write
Read
Write
Prech arge
(A-Ban k)
Row Active
(A-Bank)
(A-Bank)
(A-Bank)
(A-Bank)
(A-Bank)
: Don 't care
1.To write data before burst read ends, DQM should be asserted three cycle prior to write command to avoid bus
contention.
*Note :
2.Row precharge will interrupt writing. Last data input, RDL before Row precharge, will be written.
t
3.DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst.
Input data after Row precharge cycle will be masked internally.
:
Publication Da te J an. 2000
Elite Semiconductor Memory Technology Inc.
P.15
:
Revis ion 1.3u
M12L16161A
Page Read Cycle at Different Bank @ Burst Length=4
5
6
9
15
1 6
0
1
3
4
12
7
2
8
10
11
13
19
1 4
17
18
CLOCK
CKE
HIGH
*Note1
CS
RAS
*Note2
CAS
ADDR
BA
RAa
CAa
CAc
CBd
CAe
RBb
CBb
RAa
RBb
A10/ AP
CL=2
QAa 0 QAa 1 QAa2 QAa3 QBb 0 QBb1 QBb 2 QBb3 QAc0 QAc1 QBd 0 QBd1 QAe0 QAe1
D Q
CL=3
QAa0 QAa1 QAa2 QAa3 QBb0 QBb 1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1
WE
DQM
Rea d
Rea d
Rea d
Row Active
(A-Bank)
Prech arge
(A-Ba n k)
Rea d
Read
(B-Ban k)
(A-Ba nk)
(B-Ban k)
(A-Ba nk )
(A-Bank)
Row Active
(B-Ban k)
: Don 't care
*Note: 1. CS can be don’t cared when RAS , CAS and WE are high at the clock high going dege.
2.To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
:
Publication Da te J an. 2000
Elite Semiconductor Memory Technology Inc.
P.16
:
Revis ion 1.3u
M12L16161A
Page Write Cycle at Different Bank @Burst Length = 4
10
1 1
1
2
3
5
6
9
13
16
17
0
4
8
15
18
19
12
7
14
CLOCK
CKE
HIGH
CS
RAS
CAS
*Note2
ADDR
BA
RAa
CAa
CBb
CBd
RBb
CAc
RAa
RBb
A10/ AP
DQ
DAa1 DAa2
DBb0
DBd1
DAa0
DAa3
DBb1 DBb2 DBb3 DAc0 DAc1 DBd0
tCDL
tRDL
WE
*Note1
DQM
Prech arge
Row Active
(A-Bank)
Write
Row Active
(B-Ba n k)
Write
Write
(A-Bank)
Write
(Both Banks )
(B-Ban k)
(A-Bank)
(B-Ban k)
: Don 't care
*Note: 1.To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.
2.To interrupt burst write by row precharge, both the write and the precharge banks must be the same.
:
Publication Da te J an. 2000
Elite Semiconductor Memory Technology Inc.
P.17
:
Revis ion 1.3u
M12L16161A
Read & Write Cycle at Different Bank @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1 8
1
5
1
6
1
7
1 9
CLOCK
CKE
HIGH
C S
R A S
CAS
RAc
ADDR
CAa
CBb
CAc
RAa
RBb
BA
RBb
RAa
RAc
A10/AP
CL=2
*Note1
tCDL
QAa1 QAa2 QAa3
DBb1 DBb2
QAa0
DBb0
DBb3
QAc0 QAc1
QAc2
DQ
QAa1
CL=3
WE
QAa0
QAa2 QAa3
DBb0 DBb1 DBb2 DBb3
QAc0 QAc1
DQM
Write
(B-Bank)
Read
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Row Active
(A-Bank)
Row Active
(A-Bank)
Row Active
(B-Bank)
: D o n ' t C a r e
*Note: 1. CDL should be met to complete write.
t
:
Publication Da te J an. 2000
Elite Semiconductor Memory Technology Inc.
P.18
:
Revis ion 1.3u
M12L16161A
Read & Write Cycle with auto Precharge @ Burst Length =4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
C L O C K
H IG H
C K E
C S
R A S
C A S
A D D R
C b
R b
R a
C a
B A
A 1 0 / A P
R a
R b
Q a 2
C L = 2
DQ
Q a 0 Q a 1
Q a 3
Q a 2
D b 0 D b 1
D b 2 D b 3
C L = 3
Q a 3
D b 3
D b 0 D b 1 D b 2
Q a 0 Q a 1
W E
D Q M
Row Active
Rea d with
CL= 2
W r i t e w i t h
A u t o P r e c h a r g e
( B - B a n k )
A u t o P r e c h a r g e
S t a r t P o i n t
( B - B a n k )
(
A - Ba n k )
Au to Prech a rge
( A - Ban k )
Au to Prech a rge
Start Poin t
( A - Ba n k)
Row Active
( B - Ban k )
CL= 3
Au to Prech arge
Start Poin t
( A - Ban k )
: D o n ' t C a r e
*Note: 1. CDL Should be controlled to meet minimum RAS before internal precharge start
t
t
(In the case of Burst Length=1 & 2 and BRSW mode)
:
Publication Da te J an. 2000
Elite Semiconductor Memory Technology Inc.
P.19
:
Revis ion 1.3u
M12L16161A
Clock Suspension & DQM Operation Cycle @CAS Latency=2, Burst Length=4
1 6
1 7
1 8
1 1
1 2
1 3
1 4
1 5
1 9
0
1
2
5
9
1 0
3
4
6
7
8
C L O C K
C K E
C S
R A S
C A S
C a
R a
C b
C c
A D D R
B A
A 1 0 / A P
D Q
R a
Q a 0 Q a 1
Q a 3
t S
D c 0
D c 2
Q a 2
Q b 0 Q b 1
t S H
H Z
Z
W E
* N o t e 1
D Q M
C l o c k
W r i t e
D Q M
R o w A c t i v e
R e a d
R e a d
W r i t e
D Q M
S u s p e n s i o n
C l o c k
S u s p e n s i o n
R e a d D Q M
W r i t e
: D o n ' t C a r e
*Note:1.DQM is needed to prevent bus contention.
:
Publication Da te J an. 2000
Elite Semiconductor Memory Technology Inc.
P.20
:
Revis ion 1.3u
M12L16161A
Read Interrupted by Precharge Command & Read Burst Stop Cycle @Burst Length =Full page
0
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
C L O C K
C KE
H I G H
CS
RAS
CAS
A D D R
C Aa
R Aa
C Ab
B A
R Aa
A1 0 / AP
*Note2
Q A a 2 Q A a 3 Q A a 4
1
1
Q A a 1
Q A b 3 Q A b 4 Q A b 5
Q A b 0
Q A b 1 Q A b 2
Q A a 0
C L= 2
D Q
2
2
Q A a 2 Q A a 3 Q A a 4
Q A b 1
Q A b 0
Q A b 5
Q A a 0
Q A b 3
Q A b 4
Q A a 1
Q A b 2
C L= 3
WE
D Q M
R e a d
B u r s t S t o p
R e a d
P r e c h a r g e
(A- B a n k )
R o w Ac t i v e
(A- B a n k )
(A- B a n k )
(A- B a n k )
: D o n ' t C a r e
1.Burst can’t end in full page mode, so auto precharge can’t issue.
*Note:
2.About the valid DQs after burst stop, it is same as the case of RAS interrupt.
Both cases are illustrated above timing diagram. See the label 1,2 on them.
But at burst write, burst stop and RAS interrupt should be compared carefully.
Refer the timing diagram of “Full page write burst stop cycle”.
3.Burst stop is valid at every burst length.
:
Publication Da te J an. 2000
Elite Semiconductor Memory Technology Inc.
P.21
:
Revis ion 1.3u
M12L16161A
Write Interrupted by Precharge Command & Write Burst stop Cycle @ Burst Length =Full page
0
1
9
11
2
3
6
10
12
17
5
7
8
13
15
16
19
4
14
18
C L O C K
H I G H
C K E
C S
R A S
CA S
A D D R
RA a
CA b
CA a
BA
A1 0 /A P
RA a
B D L
tR D L
t
*N o t e 2
DAa 2
DA a4
DAb 0 DAb 1 DAb2 DAb3 DA b4
D Ab5
DA a0
DA a3
D Q
DAa1
W E
D Q M
W r it e
( A - Ba n k )
Bu r s t St o p
W r i t e
( A - Ba n k )
Ro w A c t i ve
( A- B a n k )
Pr e c h a r g e
( A - B an k )
:D o n ' t C a r e
1. Burst can’t end in full page mode, so auto precharge can’t issue.
*Note:
2.Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined
by AC parameter of RDL.
t
DQM at write interrupted by precharge command is needed to prevent invalid write.
Input data after Row precharge cycle will be masked internally.
3.Burst stop is valid at every burst length.
:
Publication Da te J an. 2000
Elite Semiconductor Memory Technology Inc.
P.22
:
Revis ion 1.3u
M12L16161A
Burst Read Single bit Write Cycle @Burst Length=2
1 6
1 7
1 8
0
1
2
5
9
1 0
1 1
1 2
1 3
1 4
1 5
1 9
3
4
6
7
8
C L O C K
* N o t e 1
H IG H
C K E
C S
R A S
C A S
* N o t e 2
R A a
R B b
C A a
R A c
C B c
C A b
C A d
A D D R
B A
R B b
A 1 0 / A P
R A a
R A c
D A a 0
D A a 0
Q A d 0
Q A b 0 Q A b 1
Q A d 1
C L = 2
D B c 0
D B c 0
D Q
C L = 3
Q A b 1
Q A d 0 Q A d 1
Q A b 0
W E
D Q M
R o w A c t i v e
( A - B a n k )
R o w A c t i v e
( A - B a n k )
R e a d
( A - B a n k )
Row Active
(B-Ba n k )
P r e c h a r g e
( A - B a n k )
W r i t e w i t h
Rea d with
W r i t e
( A - B a n k )
A u t o P r e c h a r g e
( B - B a n k )
Au to Prech arge
(A-Ban k )
: D o n ' t C a r e
*Note:1.BRSW modes is enabled by setting A9 “High” at MRS(Mode Register Set).
At the BRSW Mode, the burst length at write is fixed to “1” regardless of programmed burst length.
2.When BRSW write command with auto precharge is executed, keep it in mind that RAS should not be violated.
t
Auto precharge is executed at the next cycle of burst-end, so in the case of BRSW write command, the precharge
command will be issued after two clock cycles.
:
Publication Da te J an. 2000
Elite Semiconductor Memory Technology Inc.
P.23
:
Revis ion 1.3u
M12L16161A
Active/Precharge Power Down Mode @CAS Latency=2, Burst Length=4
1 6
1 7
1 8
1 1
1 2
1 3
1 4
1 5
1 9
0
1
2
5
9
1 0
3
4
6
7
8
C L O C K
* N o t e 2
t S S
t S S
* N o t e 1
t S S
C K E
C S
* N o t e 3
R A S
C A S
R a
C a
A D D R
B A
R a
A 1 0 / A P
t S H Z
Q a 1
Q a 0
Q a 2
D Q
W E
D Q M
Row Active
Read
P r e c h a r g e
P r e c h a r g e
P o w e r - D o w n
E n t r y
Active
Prech a rge
Power-Down
Exit
Active
Power-down
En try
Power-down
Exit
:
D o n ' t c a r e
1.Both banks should be in idle state prior to entering precharge power down mode.
2.CKE should be set high at least 1CLK+tss prior to Row active command.
3.Can not violate minimum refresh specification. (32ms)
*Note :
:
Publication Da te J an. 2000
Elite Semiconductor Memory Technology Inc.
P.24
:
Revis ion 1.3u
M12L16161A
Self Refresh Entry & Exit Cycle
3
6
0
1
2
11
13
4
8
9
10
1 2
1 7
5
7
1 4
15
1 6
18
19
C L O C K
* N o t e 2
* N o t e 4
t R C m i n
* N o t e 6
* N o t e 1
*Note3
C K E
C S
t S S
* N o t e 5
R A S
C A S
* N o t e 7
A D D R
B A
A 1 0 / A P
H i - Z
H i - Z
DQ
W E
D Q M
S e l f R e f r e s h E x i t
S e l f R e f r e s h E n t r y
A u t o R e f r e s h
:
D o n ' t c a r e
*Note: TO ENTER SELF REFRESH MODE
1. CS , RAS & CAS with CKE should be low at the same clock cycle.
2.After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE.
3.The device remains in self refresh mode as long as CKE stays “Low”.
cf.) Once the device enters self refresh mode, minimum RAS is required before exit from self refresh.
t
TO EXIT SELF REFRESH MODE
4.System clock restart and be stable before returning CKE high.
5. CS Starts from high.
6.Minimum tRC is required after CKE going high to complete self refresh exit.
7.2K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst
refresh.
:
Publication Da te J an. 2000
Elite Semiconductor Memory Technology Inc.
P.25
:
Revis ion 1.3u
M12L16161A
Mode Register Set Cycle
Auto Refresh Cycle
1
2
3
4
5
6
0
1
2
3
4
5
6
7
8
9
1 0
0
C L O C K
C K E
H IG H
H IG H
C S
* N o t e 2
t R F C
R A S
* N o t e 1
* N o t e 3
C A S
Key
R a
A D D R
DQ
W E
H i- Z
H i - Z
D Q M
MR S
N e w C o m m a n d
A u t o R e f r e s h
N e w C o m m a n d
: D o n ' t C a r e
*Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
MODE REGISTER SET CYCLE
*Note: 1. CS , RAS , CAS & WE activation at the same clock cycle with address key will set internal mode register.
2.Minimum 2 clock cycles should be met before new RAS activation.
3.Please refer to Mode Register Set table.
:
Publication Da te J an. 2000
Elite Semiconductor Memory Technology Inc.
P.26
:
Revis ion 1.3u
M12L16161A
PACKAGE DIMENSIONS
50-LEAD TSOP(II) SDRAM(400mil)
D
A
2
(4X)
O
2
A
50
26
DETAIL
A
-H-
1
R
1
E
E
2
R
B
O1.5
GAGE
3 (4X)
O
1
A
-C-
O
PLANE
1
25
8.78
-C-
1
O
B
DETAIL
A
L
1
L
b
b
(ZD)
WITH PLATING
BASE METAL
1
c
c
SECTION B-B
-C-
0.10
C
1
e
b
SEATING PLANE
Symbol
Dimension in mm
Dimension in inch
Min
-
Nom
-
0.10
1.00
Max
Min
-
Nom
-
0.004
0.039
Max
0.047
0.006
0.041
0.018
0.016
0.008
0.006
0.830
A
A1
A2
b
b1
c
c1
D
ZD
E
1.20
0.15
1.05
0.45
0.40
0.21
0.16
0.05
0.95
0.30
0.30
0.12
0.10
20.82
0.002
0.037
0.012
0.012
0.005
0.004
0.820
-
-
0.35
0.014
-
0.127
20.95
0.875 REF
11.76
10.16
0.50
0.80 REF
0.80 BSC
-
-
0.005
0.825
0.034 REF
0.463
0.400
0.020
0.031 REF
0.031 BSC
-
21.08
11.56
10.03
0.40
11.96
10.29
0.60
0.455
0.394
0.016
0.471
0.405
0.024
E1
L
L1
R1
R2
0.12
0.12
0
-
0.25
8
0.005
0.005
0
-
-
-
-
0.010
8
0
-
-
0
-
-
10
10
15
15
20
20
10
10
15
15
20
20
:
Publication Da te J an. 2000
Elite Semiconductor Memory Technology Inc.
P.27
:
Revis ion 1.3u
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