F25L04UA-50CG [ESMT]
Flash, 512KX8, PDSO8, 0.150 INCH, LEAD FREE, SOIC-8;
| 型号： | F25L04UA-50CG |
| 厂家： | 
ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. |
| 描述： | Flash, 512KX8, PDSO8, 0.150 INCH, LEAD FREE, SOIC-8 时钟 光电二极管 内存集成电路 |
| 文件： | 总24页 (文件大小：392K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ESMT
F25L04UA
4Mbit (512Kx8)
3V Only Serial Flash Memory
FEATURES
y
y
Single supply voltage 2.7~3.6V
- Sector erase time 0.7s(typical)
Speed
y
y
Auto Address Increment (AAI) Programming
- Decrease total chip programming time over
Byte-Program operations
- Read max frequency : 33MHz
- Fast Read max frequency : 50MHz; 75MHz; 100MHz
y
y
Low power consumption
- typical active current
- 15μ A typical standby current
SPI Serial Interface
- SPI Compatible : Mode 0 and Mode3
y
y
End of program or erase detection
Write Protect ( WP )
Reliability
- 100,000 program/erase cycles typically
- 10 years Data Retention
y
y
Hold Pin (HOLD )
y
y
Program
- Byte program time 8μ s(typical)
Package avalible
- 8-pin SOIC 150-mil
Erase
- Chip erase time 11s(typical)
ORDERING INFORMATION
Part No.
Speed
Package
COMMENTS
Pb-free
F25L04UA -50CG
F25L04UA -75CG
50MHz 8 lead SOIC
75MHz 8 lead SOIC
Pb-free
F25L04UA -100CG 100MHz 8 lead SOIC
Pb-free
GENERAL DESCRIPTION
The F25L04UA is a 4Megabit, 3V only CMOS Serial Flash
memory device organized as 512K bytes of 8 bits. This device is
packaged in 8-lead SOIC 150mil. ESMT’s memory devices
reliably store memory data even after 100,000 program and
erase cycles.
16K bytes, one 32K bytes, and seven 64K bytes. Sectors can be
erased individually without affecting the data in other sectors.
Whole chip erase capabilities provide the flexibility to revise the
data in the device.
The sector protect/unprotect feature disables both program and
erase operations in any combination of the sectors of the
memory.
The F25L04UA features a sector erase architecture. The device
memory array is divided into one 8K bytes, two 4K bytes, one
Elite Semiconductor Memory Technology Inc.
Publication Date: Sep. 2006
Revision: 1.1 1/24
ESMT
F25L04UA
PIN CONFIGURATIONS
8-PIN SOIC
0
1
8
VDD
CE
HOLD
SCK
SO
2
3
7
6
WP
SI
VSS
4
5
PIN Description
Symbol
SCK
Pin Name
Functions
To provide the timming for serial input and
output operations
Serial Clock
To transfer commands, addresses or data
serially into the device.
SI
Serial Data Input
Data is latched on the rising edge of SCK.
To transfer data serially out of the device.
SO
CE
WP
Serial Data Output
Chip Enable
Data is shifted out on the falling edge of
SCK.
To activate the device when CE is low.
The Write Protect ( WP ) pin is used to
enable/disable BPL bit in the status
register.
Write Protect
To temporaiily stop serial communication
with SPI flash memory without resetting
the device.
Hold
HOLD
VDD
VSS
Power Supply
Ground
To provide power.
Elite Semiconductor Memory Technology Inc.
Publication Date: Sep. 2006
Revision: 1.1 2/24
ESMT
F25L04UA
SECTOR STRUCTURE
Table1 : F25L04UA Sector Address Table
Sector Address
A18 A17 A16 A15 A14 A13 A12
Sector Size
Symbol
Address range
(Kbytes)
11
10
9
8KB
4KB
7E000H – 7FFFFH
7D000H – 7DFFFH
7C000H – 7CFFFH
78000H – 7BFFFH
70000H – 77FFFH
60000H – 6FFFFH
50000H – 5FFFFH
40000H – 4FFFFH
30000H – 3FFFFH
20000H – 2FFFFH
10000H – 1FFFFH
00000H – 0FFFFH
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
1
1
1
1
0
X
1
4KB
1
1
0
0
8
16KB
32KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
7
0
X
X
X
X
X
X
X
X
6
X
X
X
X
X
X
X
5
4
3
2
1
0
Table2 : F25L04UA Block Protection Table
Protection Level
BP1
BP0
Protected Memory Area
None
0
0
0
1
1
0
1
0
1
1(1/8 memory array)
2(1/4 memory array)
3(all memory array)
70000H –7FFFFH
60000H –7FFFFH
00000H –7FFFFH
Block Protection (BP1, BP0)
Block Protection Lock-Down (BPL)
The Block-Protection (BP1, BP0) bits define the size of the
memory area, as defined in Table2 to be software protected
against any memory Write (Program or Erase) operations. The
Write-Status-Register (WRSR) instruction is used to program the
WP pin driven low (VIL), enables the Block-Protection
-Lock-Down (BPL) bit. When BPL is set to 1, it prevents any
further alteration of the BPL, BP1, and BP0 bits. When the WP
pin is driven high (VIH), the BPL bit has no effect and its value is
“Don’t Care”. After power-up, the BPL bit is reset to 0.
BP1 and BP0 bits as long as WP is high or the
Block-Protection-Look (BPL) bit is 0. Chip-Erase can only be
executed if Block-Protection bits are both 0. After power-up, BP1
and BP0 are set to1.
Elite Semiconductor Memory Technology Inc.
Publication Date: Sep. 2006
Revision: 1.1 3/24
ESMT
F25L04UA
FUNTIONAL BLOCK DIAGRAM
SuperFlash
Memory
Address
Buffers
and
X-Decoder
Latches
Y-Decoder
I/O Butters
and
Control Logic
Data Latches
Serial Interface
CE SCK
SO
WP
HOLD
SI
Elite Semiconductor Memory Technology Inc.
Publication Date: Sep. 2006
Revision: 1.1 4/24
ESMT
F25L04UA
Hold Operation
coincide with the SCK active low state, then the device exits in
Hold mode when the SCK next reaches the active low state. See
Figure 3 for Hold Condition waveform.
HOLD pin is used to pause a serial sequence underway with the
SPI flash memory without resetting the clocking sequence. To
activate the HOLD mode, CE must be in active low state. The
HOLD mode begins when the SCK active low state coincides
with the falling edge of the HOLD signal. The HOLD mode ends
Once the device enters Hold mode, SO will be in high impedance
state while SI and SCK can be VIL or VIH.
when the HOLD signal’s rising edge coincides with the SCK
active low state.
If CE is driven active high during a Hold condition, it resets the
internal logic of the device. As long as HOLD signal is low, the
memory remains in the Hold condition. To resume
If the falling edge of the HOLD signal does not coincide with the
SCK active low state, then the device enters Hold mode when the
SCK next reaches the active low state.
communication with the device, HOLD must be driven active
high, and CE must be driven active low. See Figure 18 for Hold
timing.
Similarly, if the rising edge of the HOLD signal does not
SCK
HOLD
Hold
Active
Active
Active
Hold
Figure 3 : HOLD CONDITION WAVEFORM
Write Protection
TABLE3: CONDITIONS TO EXECUTE
WRITE-STATUS- REGISTER (WRSR)
INSTRUCTION
F25L04UA provides software Write protection.
The Write Protect pin ( WP ) enables or disables the lockdown
function of the status register. The Block-Protection bits (BP1,
BP0, and BPL) in the status register provide Write protection to
the memory array and the status register. See Table 5 for
Block-Protection description.
BPL
1
Execute WRSR Instruction
Not Allowed
WP
L
L
0
Allowed
Write Protect Pin ( WP )
The Write Protect ( WP ) pin enables the lock-down function of
H
X
Allowed
the BPL bit (bit 7) in the status register. When WP is driven low,
the execution of the Write-Status-Register (WRSR) instruction is
determined by the value of the BPL bit (see Table 3). When WP
is high, the lock-down function of the BPL bit is disabled.
Elite Semiconductor Memory Technology Inc.
Publication Date: Sep. 2006
Revision: 1.1 5/24
ESMT
F25L04UA
Status Register
The software status register provides status on whether the flash
memory array is available for any Read or Write operation,
whether the device is Write enabled, and the state of the memory
Write protection. During an internal Erase or Program operation,
the status register may be read only to determine the completion
of an operation in progress.
Table 4 describes the function of each bit in the software status
register.
TABLE 4: SOFTWARE STATUS REGISTER
Default at
Read/Write
Power-up
Bit
Name
BUSY
WEL
Function
1 = Internal Write operation is in progress
0 = No internal Write operation is in progress
1 = Device is memory Write enabled
0 = Device is not memory Write enabled
Indicate current level of block write protection (See Table 5)
Indicate current level of block write protection (See Table 5)
Reserved for future use
0
0
0
R
R
1
2
3
4:5
BP0
BP1
RES
1
1
0
R/W
R/W
N/A
Auto Address Increment Programming status
1 = AAI programming mode
0 = Byte-Program mode
1 = BP1, BP0 are read-only bits
0 = BP1, BP0 are read/writable
6
7
AAI
0
0
R
BPL
R/W
Note1 : Only BP0,BP1 and BPL are writable
Note2 : All register bits are volatility
Note3 : All area are protected at power-on (BP1=1,BP0=1)
Busy
The Busy bit determines whether there is an internal Erase or
Program operation in progress. A “1” for the Busy bit indicates
the device is busy with an operation in progress. A “0” indicates
the device is ready for the next valid operation.
Write Enable Latch (WEL)
The Write-Enable-Latch bit indicates the status of the internal
memory Write Enable Latch. If the Write-Enable-Latch bit is set to
“1”, it indicates the device is Write enabled. If the bit is set to “0”
(reset), it indicates the device is not Write enabled and does not
accept any memory Write (Program/ Erase) commands. The
Write-Enable-Latch bit is automatically reset under the following
conditions:
• Power-up
• Write-Disable (WRDI) instruction completion
• Byte-Program instruction completion
• Auto Address Increment (AAI) programming reached its
highest memory address
• Sector-Erase instruction completion
• Block-Erase instruction completion
• Chip-Erase instruction completion
Elite Semiconductor Memory Technology Inc.
Publication Date: Sep. 2006
Revision: 1.1 6/24
ESMT
F25L04UA
Instructions
Instructions are used to Read, Write (Erase and Program), and
configure the F25L04UA. The instruction bus cycles are 8 bits
each for commands (Op Code), data, and addresses. Prior to
executing any Byte-Program, Auto Address Increment (AAI)
programming, Sector-Erase, Block-Erase, or Chip-Erase
instructions, the Write-Enable (WREN) instruction must be
executed first. The complete list of the instructions is provided in
Table 5. All instructions are synchronized off a high to low
SCK starting with the most significant bit. CE must be driven
low before an instruction is entered and must be driven high after
the last bit of the instruction has been shifted in (except for Read,
Read-ID and Read-Status-Register instructions). Any low to high
transition on CE , before receiving the last bit of an instruction
bus cycle, will terminate the instruction in progress and return the
device to the standby mode.
Instruction commands (Op Code), addresses, and data are all
input from the most significant bit (MSB) first.
transition of CE . Inputs will be accepted on the rising edge of
TABLE 5: DEVICE OPERATION INSTRUCTIONS
Max
Freq
MHz
Bus Cycle4
Cycle Type/
Operation1,2
1
2
3
4
5
6
SIN
SOUT
SIN
SOUT
SIN
SOUT
SIN
SOUT SIN SOUT SIN
SOUT
Read
33
03H
0BH
20H
60H
02H
Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z
Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z
Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z
X
X
-
DOUT
X
-
High-Speed-Read
X
DOUT
Sector-Erase4,5
Chip-Erase6
Hi-Z
-
-
-
-
-
-
-
-
Byte-Program5
Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z DIN
Hi-Z
Hi-Z
50
and
75
Auto Address Increment
(AAI) Single-Byte Program5,6
Read-Status-Register
(RDSR)
AFH Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z DIN
05H
50H
01H
Hi-Z
Hi-Z
Hi-Z
X
-
DOUT
-
-
-
Note7
-
-
-
Note7
-
-
-
Note7
-
Enable-Write-Status-Register
and
100
(EWSR)8
Write-Status-Register
(WRSR)8
Write-Enable (WREN)
Write-Disable (WRDI)
Jedec-Read-ID (JEDEC-ID)
Data
Hi-Z
-
-
-
-
-
-.
-
-
-
-
-
-
-
06H
04H
9FH
Hi-Z
Hi-Z
Hi-Z
-
-
X
8CH
X
8CH
X
8CH
-
-
1. Operation: SIN = Serial In, SOUT = Serial Out
2. X = Dummy Input Cycles (VIL or VIH); - = Non-Applicable Cycles (Cycles are not necessary)
3. One bus cycle is eight clock periods.
4. Sector addresses: use AMS-A12, remaining addresses can be VIL or VIH
5. Prior to any Byte-Program, AAI-Program, Sector-Erase ,or Chip-Erase operation, the Write-Enable (WREN) instruction must be
executed.
6. To continue programming to the next sequential address location, enter the 8-bit command, AFH, followed by the data to be
programmed.
7. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE .
8. The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction
of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the EWSR instruction to make both
instructions effective.
9. The Jedec-Read-ID is continuous with on going clock cycles until terminated by a low to high transition on CE .
Elite Semiconductor Memory Technology Inc.
Publication Date: Sep. 2006
Revision: 1.1 7/24
ESMT
F25L04UA
Read (33 MHz)
The Read instruction supports up to 33 MHz, it outputs the data
starting from the specified address location. The data output
stream is continuous through all addresses until terminated by a
(wrap-around) of the address space, i.e. for 4 Mbit density, once
the data from address location 7FFFFH had been read, the next
output will be from address location 00000H.
The Read instruction is initiated by executing an 8-bit command,
low to high transition on CE . The internal address pointer will
automatically increment until the highest memory address is
reached. Once the highest memory address is reached, the
address pointer will automatically increment to the beginning
03H, followed by address bits [A23-A0]. CE must remain active
low for the duration of the Read cycle. See Figure 4 for the Read
sequence.
CE
MODE3
1 2 3 4 5 6 7 8
15 16
23 24
31 32
39 40
47 48
55 56
63 64
70
SCK MODE1
ADD.
MSB
03
ADD.
ADD.
SI
MSB
N
N+1
DOUT
N+2
DOUT
N+3
DOUT
N+4
DOU T
HIGH IMPENANCE
SO
DOUT
MSB
Figure 4 : READ SEQUENCE
Elite Semiconductor Memory Technology Inc.
Publication Date: Sep. 2006
Revision: 1.1 8/24
ESMT
F25L04UA
Fast-Read (50 MHz ; 75 MHz; 100 MHz)
The High-Speed-Read instruction supporting up to 100 MHz is
initiated by executing an 8-bit command, 0BH, followed by
through all addresses until terminated by a low to high transition
on CE . The internal address pointer will automatically increment
until the highest memory address is reached. Once the highest
memory address is reached, the address pointer will
automatically increment to the beginning (wrap-around) of the
address space, i.e. for 4 Mbit density, once the data from address
location 07FFFFH has been read, the next output will be from
address location 000000H.
address bits [A23-A0] and a dummy byte. CE must remain
active low for the duration of the High-Speed-Read cycle. See
Figure 5 for the High-Speed-Read sequence.
Following a dummy byte (8 clocks input dummy cycle), the
High-Speed-Read instruction outputs the data starting from the
specified address location. The data output stream is continuous
CE
0
1 2
3
4 5 6 7
8
15 16
23 24
31 32
39 40
47 48
MODE3
MODE0
55 56
63 64
71 72
80
SCK
SI
0B
ADD.
MSB
ADD.
ADD.
X
MSB
N
N+1
DOUT
N+2
DOUT
N+3
DOU T
N+4
DOU T
HIGH IMPENANCE
SO
DOU T
MSB
Note : X = Dummy Byte : 8 Clocks Input Dummy (VIL or VIH)
Figure 5 : HIGH-SPEED-READ SEQUENCE
Elite Semiconductor Memory Technology Inc.
Publication Date: Sep. 2006
Revision: 1.1 9/24
ESMT
F25L04UA
Byte-Program
The Byte-Program instruction programs the bits in the selected
byte to the desired data. The selected byte must be in the erased
state (FFH) when initiating a Program operation. A Byte-Program
instruction applied to a protected memory area will be ignored.
Prior to any Write operation, the Write-Enable (WREN)
instruction is initiated by executing an 8-bit command, 02H,
followed by address bits [A23-A0]. Following the address, the data
is input in order from MSB (bit 7) to LSB (bit 0). CE must be
driven high before the instruction is executed. The user may poll
the Busy bit in the software status register or wait TBP for the
completion of the internal self-timed Byte-Program operation.
See Figure 6 for the Byte-Program sequence.
instruction must be executed. CE must remain active low for
the duration of the Byte-Program instruction. The Byte-Program
CE
0 1 2 3 4 5 6 7 8
1516
2324
3132
MODE3
MODE0
39
SCK
SI
02
ADD.
MSB
ADD.
ADD.
DIN
MSB
MSB LSB
HIGH IMPENANCE
SO
Figure 6 : BYTE-PROGRAM SEQUENCE
Elite Semiconductor Memory Technology Inc.
Publication Date: Sep. 2006
Revision: 1.1 10/24
ESMT
F25L04UA
Auto Address Increment (AAI) Program
The AAI program instruction allows multiple bytes of data to be
programmed without re-issuing the next sequential address
location. This feature decreases total programming time when
the entire memory array is to be programmed. An AAI program
instruction pointing to a protected memory area will be ignored.
The selected address range must be in the erased state (FFH)
when initiating an AAI program instruction.
Prior to any write operation, the Write-Enable (WREN) instruction
must be executed. The AAI program instruction is initiated by
executing an 8-bit command, AFH, followed by address bits
[A23-A0]. Following the addresses, the data is input sequentially
BUSY bit in the software status register or wait TBP for the
completion of each internal self-timed Byte-Program cycle. Once
the device completes programming byte, the next sequential
address may be program, enter the 8-bit command, AFH,
followed by the data to be programmed. When the last desired
byte had been programmed, execute the Write-Disable (WRDI)
instruction, 04H, to terminate AAI. After execution of the WRDI
command, the user must poll the Status register to ensure the
device completes programming. See Figure
programming sequence.
7
for AAI
There is no wrap mode during AAI programming; once the
highest unprotected memory address is reached, the device will
exit AAI operation and reset the Write-Enable-Latch bit (WEL = 0).
from MSB (bit 7) to LSB (bit 0). CE must be driven high before
the AAI program instruction is executed. The user must poll the
TBP
TBP
CE
15 16
31 32 333435 36 373839
MODE3
0
1
2
3
4
5
6
7
8
23 24
0
1
2
3
4
5
6
7
8
9 10 11 1213 14 15
Data Byte 2
0 1
SCK MODE0
AF
A[23,16]
A[15,8]
A[7,0]
Da ta Byte 1
AF
SI
TBP
CE
SCK
SI
0
1
2
3
4
5
6
7
8
9 101112 1314 15
Last Data Byte
0
1
2
3
4
5
6
7
8
9 10 11 1213 14 15
0
1
2
3
4
5 6 7
AF
05
04
Read Status Register(RDSR)
Instruction to verify end of
AAI Operation
Write Disable (WRDI)
Instruction to terminate
AAI Operation
DOUT
SO
Figure 7 : AUTO ADDRESS INCREMENT (AAI) PROGRAM SEQUENCE
Elite Semiconductor Memory Technology Inc.
Publication Date: Sep. 2006
Revision: 1.1 11/24
ESMT
F25L04UA
Sector-Erase
The Sector-Erase instruction clears all bits in the selected sector
to FFH. A Sector-Erase instruction applied to a protected
memory area will be ignored. Prior to any Write operation, the
[AMS-A12] (AMS = Most Significant address) are used to determine
the sector address (SAX), remaining address bits can be VIL or
VIH. CE must be driven high before the instruction is executed.
The user may poll the Busy bit in the software status register or
wait TSE for the completion of the internal self-timed
Sector-Erase cycle. See Figure 8 for the Sector-Erase sequence.
Write-Enable (WREN) instruction must be executed. CE must
remain active low for the duration of the any command sequence.
The Sector-Erase instruction is initiated by executing an 8-bit
command, 20H, followed by address bits [A23-A0]. Address bits
CE
0
1 2
3
4 5 6 7
8
15 16
23 24
31 32
MODE3
MODE0
39
SCK
SI
02
ADD.
MSB
ADD.
ADD.
DIN
MSB
HIGH IMPENANCE
SO
FIGURE 8 : SEQUENCE-ERASE SEQUENCE
Elite Semiconductor Memory Technology Inc.
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Revision: 1.1 12/24
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F25L04UA
Chip-Erase
The Chip-Erase instruction clears all bits in the device to FFH. A
Chip-Erase instruction will be ignored if any of the memory area
is protected. Prior to any Write operation, the Write-Enable
60H. CE must be driven high before the instruction is executed.
The user may poll the Busy bit in the software status register or
wait TCE for the completion of the internal self-timed Chip-Erase
cycle.
(WREN) instruction must be executed. CE must remain active
low for the duration of the Chip-Erase instruction sequence. The
Chip-Erase instruction is initiated by executing an 8-bit command,
See Figure 9 for the Chip-Erase sequence.
CE
0 1 2 3 4 5 6 7
MODE3
SCK
SI
MODE0
60
MSB
HIGH IMPENANCE
SO
FIGURE 9 : CHIP-ERASE SEQUENCE
Read-Status-Register (RDSR)
The Read-Status-Register (RDSR) instruction allows reading of
the status register. The status register may be read at any time
even during a Write (Program/Erase) operation.
When a Write operation is in progress, the Busy bit may be
checked before sending any new commands to assure that the
new commands are properly received by the device.
and remain low until the status data is read.
Read-Status-Register is continuous with ongoing clock cycles
until it is terminated by a low to high transition of the CE
See Figure 10 for the RDSR instruction sequence.
CE must be driven low before the RDSR instruction is entered
CE
MODE3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SCK MODE1
05
SI
MSB
HIGH IMPENANCE
SO
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MSB
Status
Register Out
Figure10 : READ-STATUS-REGISTER (RDSR) SEQUENCE
Elite Semiconductor Memory Technology Inc.
Publication Date: Sep. 2006
Revision: 1.1 13/24
ESMT
F25L04UA
Write-Enable (WREN)
The Write-Enable (WREN) instruction sets the Write-
Enable-Latch bit to 1 allowing Write operations to occur.
The WREN instruction must be executed prior to any Write
(Program/Erase) operation. CE must be driven high before the
WREN instruction is executed.
CE
0 1 2 3 4 5 6 7
MODE3
MODE0
SCK
SI
06
MSB
HIGH IMPENANCE
SO
FIGURE 11 : WRITE ENABLE (WREN) SEQUENCE
Write-Disable (WRDI)
The Write-Disable (WRDI) instruction resets the Write-Enable-Latch
bit and AAI bit to 0 disabling any new Write operations from occurring.
CE must be driven high before the WRDI instruction is executed.
CE
0 1 2 3 4 5 6 7
MODE3
MODE0
SCK
SI
04
MSB
HIGH IMPENANCE
SO
Figure 12 : WRITE DISABLE (WRDI) SEQUENCE
Enable-Write-Status-Register (EWSR)
The Enable-Write-Status-Register (EWSR) instruction arms the
Write-Status-Register (WRSR) instruction and opens the status
register for alteration. The Enable-Write-Status-Register
instruction does not have any effect and will be wasted, if it is not
followed immediately by the Write-Status-Register (WRSR)
instruction. CE must be driven low before the EWSR instruction
is entered and must be driven high before the EWSR instruction
is executed.
Elite Semiconductor Memory Technology Inc.
Publication Date: Sep. 2006
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Write-Status-Register (WRSR)
The Write-Status-Register instruction works in conjunction with
the Enable-Write-Status-Register (EWSR) instruction to write
new values to the BP1, BP0, and BPL bits of the status register.
The Write-Status-Register instruction must be executed
immediately after the execution of the Enable-Write-Status
-Register instruction (very next instruction bus cycle). This
two-step instruction sequence of the EWSR instruction followed
by the WRSR instruction works like SDP (software data
protection) command structure which prevents any accidental
alteration of the status register values. The Write-Status-Register
When WP is high, the lock-down function of the BPL bit is
disabled and the BPL, BP0, and BP1 bits in the status register
can all be changed. As long as BPL bit is set to 0 or WP pin is
driven high (VIH) prior to the low-to-high transition of the CE pin
at the end of the WRSR instruction, the BP0, BP1, and BPL bit in
the status register can all be altered by the WRSR instruction. In
this case, a single WRSR instruction can set the BPL bit to “1” to
lock down the status register as well as altering the BP0 and BP1
bit at the same time. See Table 3 for a summary description of
instruction will be ignored when WP is low and BPL bit is set to
WP and BPL functions. CE must be driven low before the
command sequence of the WRSR instruction is entered and
driven high before the WRSR instruction is executed. See Figure
13 for EWSR and WRSR instruction sequences.
“1”. When the WP is low, the BPL bit can only be set from “0” to
“1” to lockdown the status register, but cannot be reset from “1” to
“0”.
CE
0 1 2 3 4 5 6 7 8 9 1011 12 13 1415
MODE3
0 1 2 3 4 5 6 7
SCK MODE0
STATUS
REGISTER IN
50
7 6 5 4 3 2 1
0
SI
01
MSB
MSB
HIGH IMPENANCE
SO
Figure 13 : ENABLE-WRITE-STATUS-REGISTER (EWSR) AMD WRITE-STATUS-REGISTER (WRSR) SEQUENCE
Elite Semiconductor Memory Technology Inc.
Publication Date: Sep. 2006
Revision: 1.1 15/24
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ELECTRICAL SPECIFICATIONS
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute
Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure
to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . -2.0V to VDD+2.0V
Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C
Output Short Circuit Current1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Output shorted for no more than one second. No more than one output shorted at a time.
AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . . . . . CL = 15 pF for ≧75MHz
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .CL = 30 pF for ≦50MHz
See Figures 20 and 21
TABLE 7: DC OPERATING CHARACTERISTICS VDD = 3.0-3.6V ; TA=0~70oC
Limits
Max
15
Symbol
Parameter
Read Current
Test Conditions
Min
Units
mA
IDDR
IDDW
ISB
CE =0.1 VDD/0.9 VDD@33 MHz, SO=open
CE =VDD
Program and Erase Current
Standby Current
40
25
mA
µA
CE =VDD, VIN=VDD or VSS
ILI
ILO
VIL
VIH
VOL
VOH
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
1
1
µA
µA
V
V
V
VIN=GND to VDD, VDD=VDD Max
VOUT=GND to VDD, VDD=VDD Max
VDD=VDD Min
VDD=VDD Max
IOL=100 µA, VDD=VDD Min
IOH=-100 µA, VDD=VDD Min
0.7 VDD 0.8
VDD-0.2 0.2
V
TABLE 8 : RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol
Parameter
Minimum
Units
µs
1
TPU-READ
VDD Min to Read Operation
VDD Min to Write Operation
10
10
1
TPU-WRITE
µs
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 9: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
VOUT = 0V
Maximum
12 pF
1
COUT
Output Pin Capacitance
Input Capacitance
1
CIN
VIN = 0V
6 pF
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Elite Semiconductor Memory Technology Inc.
Publication Date: Sep. 2006
Revision: 1.1 16/24
ESMT
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Jedec-Read-ID (JEDEC-ID)
The Jedec-Read-ID instruction is for reading the Manufacturer ID of 1-byte and followed by Device ID of 2-byte. The ESMT
Manufacturer ID is 8CH.,the memory type ID is 8CH as the first-byte device ID, the memory capacity ID is 8CH as the second-byte
device ID. The instruction sequence is shown in Fig14. The Jedec-Read-ID instruction is terminated by a low to high transition on CE
at any time during data output.
Figure 14 : Jedec-Read-ID (JEDEC-ID)
CE
MODE3
0 1 2 3 4 5 6 7 8 9 1011 12 13 14 1516 17 18 1920 2122 23 24 2526 27 282930 31 32 33 34
SCK MODE0
9F
SI
HIGH IMPENANCE
SO
8C
8C
8C
MSB
MSB
Jedec-Read-ID DATA
Manufacture’s ID
Device ID
Memory Type
Byte2
Memory Capacity
Byte1
8CH
Byte3
8CH
8CH
Elite Semiconductor Memory Technology Inc.
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TABLE 10: RELIABILITY CHARACTERISTICS
Symbol
Parameter
Typical Specification
Units
Cycles
Years
mA
Test Method
1
NEND
Endurance
100,000
10
JEDEC Standard A117
JEDEC Standard A103
JEDEC Standard 78
1
TDR
Data Retention
Latch Up
1
ILTH
100 + IDD
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 11 : AC OPERATING CHARACTERISTICS TA=0~70oC
Normal 33MHz Fast 50 MHz Fast 75 MHz Fast 100 MHz
VDD=2.7~3.6V VDD=2.7~3.6V VDD=2.7~3.6V VDD=3.2~3.6V
Symbol
FCLK
TSCKH
TSCKL
Parameter
Serial Clock Frequency
Serial Clock High Time
Serial Clock Low Time
Min
Max
Min
Max
Min
Max
Min
Max
Units
MHz
ns
33
50
75
100
13
13
5
9
9
6
6
5
5
ns
1
TCES
5
5
5
ns
CE Active Setup Time
CE Active Hold Time
CE Not Active Setup Time
CE Not Active Hold Time
CE High Time
1
TCEH
5
5
5
5
ns
1
TCHS
5
5
5
5
ns
1
TCHH
5
5
5
5
ns
TCPH
100
100
100
100
ns
TCHZ
9
9
9
9
ns
CE High to High-Z Output
SCK Low to Low-Z Output
Data In Setup Time
TCLZ
0
3
3
5
5
5
5
0
3
3
5
5
5
5
0
3
3
5
5
5
5
0
3
3
5
5
5
5
ns
TDS
ns
TDH
Data In Hold Time
ns
THLS
ns
HOLD Low Setup Time
HOLD High Setup Time
HOLD Low Hold Time
THHS
ns
THLH
ns
THHH
ns
HOLD High Hold Time
THZ
9
9
9
9
9
9
9
9
ns
HOLD Low to High-Z Output
HOLD High to Low-Z Output
Output Hold from SCK Change
Output Valid from SCK
TLZ
ns
TOH
0
0
0
0
ns
TV
12
9
9
7
ns
1. Relative to SCK.
Elite Semiconductor Memory Technology Inc.
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ERASE AND PROGRAMMING PERFORMANCE
Limits
Unit
Parameter
Typ.(2)
Max.(3)
15
Sector Erase Time
0.7
11
sec
sec
Chip Erase Time
50
Byte Programming Time
Chip Programming Time
Erase/Program Cycles(1)
9
300
13.5
-
us
4.5
sec
100,000
Cycles
Notes:
1.Not 100% Tested, Excludes external system level over head.
2.Typical values measured at 25°C, 3V.
3.Maximum values measured at 85°C, 3.0V.
Elite Semiconductor Memory Technology Inc.
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Revision: 1.1 19/24
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FIGURE 15: SERIAL INPUT TIMING DIAGRAM
FIGURE 16: SERIAL OUTPUT TIMING DIAGRAM
Elite Semiconductor Memory Technology Inc.
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Revision: 1.1 20/24
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FIGURE 17: HOLD TIMING DIAGRAM
FIGURE 18: POWER-UP TIMING DIAGRAM
Elite Semiconductor Memory Technology Inc.
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Input timing reference level
Output timing reference level
0.8VCC
0.2VCC
0.7VCC
0.3VCC
AC
Measurement
Level
0.5VCC
Note : Input pulse rise and fall time are <5ns
FIGURE 19: AC INPUT/OUTPUT REFERENCE WAVEFORMS
FIGURE 20: A TEST LOAD EXAMPLE
Elite Semiconductor Memory Technology Inc.
Publication Date: Sep. 2006
Revision: 1.1 22/24
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PACKAGING DIAGRAMS
8-LEAD
SOP ( 150 mil )
8
5
GAUGE PLANE
L
DETAIL "X"
1
4
e
b
D
L1
"X"
SEATING PLANE
Dimension in mm
Dimension in inch
Dimension in mm
Dimension in inch
Symbol
Symbol
Min
1.35
0.10
1.25
0.33
0.19
5.80
Norm
1.60
Max
1.75
0.25
1.55
0.51
0.25
6.20
Min
Norm
0.063
0.006
0.057
0.016
Max
Min
Norm
4.90
Max
Min
Norm
0.193
Max
0.197
0.157
0.050
A
A1
A2
b
0.053
0.004
0.049
0.013
0.069
0.010
0.061
0.020
0.010
0.244
D
E
L
4.80
3.80
0.40
5.00
4.00
1.27
0.189
0.150
0.016
0.15
3.90
0.154
1.45
0.66
0.026
0.406
0.203
6.00
e
1.27 BSC
1.05
0.050 BSC
0.041
c
0.0075 0.008
0.228 0.236
1.00
1.10
0.039
0.043
L1
θ
0°
8°
0°
8°
H
---
---
Controlling dimension : millimenter
Elite Semiconductor Memory Technology Inc.
Publication Date: Sep. 2006
Revision: 1.1 23/24
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Important Notice
All rights reserved.
No part of this document may be reproduced or duplicated in any form or
by any means without the prior permission of ESMT.
The contents contained in this document are believed to be accurate at
the time of publication. ESMT assumes no responsibility for any error in
this document, and reserves the right to change the products or
specification in this document without notice.
The information contained herein is presented only as a guide or
examples for the application of our products. No responsibility is
assumed by ESMT for any infringement of patents, copyrights, or other
intellectual property rights of third parties which may result from its use.
No license, either express , implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of ESMT or
others.
Any semiconductor devices may have inherently a certain rate of failure.
To minimize risks associated with customer's application, adequate
design and operating safeguards against injury, damage, or loss from
such failure, should be provided by the customer when making
application designs.
ESMT 's products are not authorized for use in critical applications such
as, but not limited to, life support devices or system, where failure or
abnormal operation may directly affect human lives or cause physical
injury or property damage. If products described here are to be used for
such kinds of application, purchaser must do its own quality assurance
testing appropriate to such applications.
Elite Semiconductor Memory Technology Inc.
Publication Date: Sep. 2006
Revision: 1.1 24/24
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