F25L01PA-50HG [ESMT]
Flash, 1MX1, PDSO8, 6 X 5 MM, 1.27 MM PITCH, ROHS COMPLIANT, WSON-8;
| 型号： | F25L01PA-50HG |
| 厂家： | 
ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. |
| 描述： | Flash, 1MX1, PDSO8, 6 X 5 MM, 1.27 MM PITCH, ROHS COMPLIANT, WSON-8 光电二极管 |
| 文件： | 总37页 (文件大小：404K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ESMT
F25L01PA
Flash
3V Only 1 Mbit Serial Flash Memory
with Dual Output
FEATURES
y
y
Single supply voltage 2.7~3.6V
Standard, Dual SPI
y
Erase
- Chip erase time 1 sec (typical)
- Block erase time 0.75 sec (typical)
- Sector erase time 90 ms (typical)
y
y
Speed
- Read max frequency: 33MHz
- Fast Read max frequency: 50MHz; 86MHz; 100MHz
- Fast Read Dual max frequency: 50MHz / 86MHz
(100MHz / 172MHz equivalent Dual SPI)
y
y
Page Programming
- 256 byte per programmable page
SPI Serial Interface
- SPI Compatible: Mode 0 and Mode 3
Low power consumption
- Active current: 22 mA
- Standby current: 25μ A
y
y
End of program or erase detection
Write Protect ( WP )
- Deep Power Down current: 10μ A
y
y
Reliability
y
y
Hold Pin (HOLD )
- 100,000 typical program/erase cycles
- 20 years Data Retention
All Pb-free products are RoHS-Compliant
Program
- Page programming time: 1.5 ms (typical)
ORDERING INFORMATION
Product ID
Speed
Package
Comments
F25L01PA –50PG
F25L01PA –86PG
F25L01PA –100PG
F25L01PA –50PAG
F25L01PA –86PAG
F25L01PA –100PAG
F25L01PA –50SG
F25L01PA –86SG
F25L01PA –100SG
F25L01PA –50DG
F25L01PA –86DG
F25L01PA –100DG
F25L01PA –50HG
F25L01PA –86HG
F25L01PA –100HG
F25L01PA –50UG
F25L01PA –86UG
F25L01PA –100UG
50MHz
86MHz
100MHz
50MHz
86MHz
100MHz
50MHz
86MHz
100MHz
50MHz
86MHz
100MHz
50MHz
86MHz
100MHz
50MHz
86MHz
100MHz
8-lead
SOIC
150 mil
200 mil
Pb-free
8-lead
SOIC
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
8-pin
TSSOP
173 mil
(4.4mm)
8-pin
PDIP
300 mil
6x5 mm
2x3 mm
8-contact
WSON
8-contact
USON
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.3 1/37
ESMT
F25L01PA
GENERAL DESCRIPTION
The F25L01PA is a 1Megabit, 3V only CMOS Serial Flash
memory device. The device supports the standard Serial
Peripheral Interface (SPI), and a Dual SPI. ESMT’s memory
devices reliably store memory data even after 100,000
programming and erase cycles.
is divided into 32 uniform sectors with 4K byte each; 2 uniform
blocks with 64K byte each. Sectors can be erased individually
without affecting the data in other sectors. Blocks can be erased
individually without affecting the data in other blocks. Whole chip
erase capabilities provide the flexibility to revise the data in the
device. The device has Sector, Block or Chip Erase but no page
erase.
The memory array can be organized into 512 programmable
pages of 256 byte each. 1 to 256 byte can be programmed at a
time with the Page Program instruction.
The sector protect/unprotect feature disables both program and
erase operations in any combination of the sectors of the
memory.
The device features sector erase architecture. The memory array
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.3
2/37
ESMT
F25L01PA
PIN CONFIGURATIONS
8- Lead SOIC
(SOIC 8L, 150mil Body, 1.27mm Pin Pitch)
(SOIC 8L, 208mil Body, 1.27mm Pin Pitch)
1
8
VDD
CE
HOLD
SCK
SO
2
3
7
6
WP
SI
VSS
4
5
8- Pin PDIP
(PDIP 8P, 300mil Body, 2.54mm Pin Pitch)
1
8
VDD
CE
HOLD
SCK
SO
2
3
7
6
WP
SI
VSS
4
5
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.3 3/37
ESMT
F25L01PA
8- Pin TSSOP
(TSSOP 8P, 173mil (4.4mm) Body, 0.65mm Pin Pitch)
V
DD
CE
SO
WP
8
7
6
1
2
3
HOLD
SCK
SI
4
5
V
SS
8- Contact WSON
(WSON 8C, 6mmX5mm Body, 1.27mm Contact Pitch)
1
VDD
CE
8
HOLD
2
7
SO
3
6
SCK
SI
WP
4
VSS
5
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.3 4/37
ESMT
F25L01PA
8- Contact USON
(USON 8C, 2mmX3mm Body, 0.5mm Contact Pitch)
8
7
1
2
VDD
HOLD
SCK
SI
CE
SO
3
4
6
5
WP
VSS
PIN DESCRIPTION
Symbol
Pin Name
Functions
To provide the timing for serial input and
output operations
SCK
Serial Clock
To transfer commands, addresses or data
serially into the device.
SI
Serial Data Input
Data is latched on the rising edge of SCK.
To transfer data serially out of the device.
SO
CE
WP
Serial Data Output
Chip Enable
Data is shifted out on the falling edge of
SCK.
To activate the device when CE is low.
The Write Protect ( WP ) pin is used to
enable/disable BPL bit in the status
register.
Write Protect
To temporality stop serial communication
with SPI flash memory without resetting
the device.
Hold
HOLD
VDD
VSS
Power Supply
Ground
To provide power.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.3 5/37
ESMT
F25L01PA
FUNCTIONAL BLOCK DIAGRAM
Flash
Address
Buffers
and
X-Decoder
Latches
Y-Decoder
I/O Butters
and
Control Logic
Data Latches
Serial Interface
CE
SCK
SO
WP
HOLD
SI
SECTOR STRUCTURE
Table 1: F25L01PA Sector Address Table
Sector Size
Block
Address
Block
1
Sector
Address range
(Kbytes)
A16
1
31
:
4KB
:
01F000H – 01FFFFH
:
16
15
:
4KB
4KB
:
010000H – 010FFFH
00F000H – 00FFFFH
:
0
0
0
4KB
000000H – 000FFFH
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.3 6/37
ESMT
F25L01PA
STATUS REGISTER
The software status register provides status on whether the flash
memory array is available for any Read or Write operation,
whether the device is Write enabled, and the state of the memory
Write protection. During an internal Erase or Program operation,
the status register may be read only to determine the completion
of an operation in progress. Table 2 describes the function of
each bit in the software status register.
Table 2: Software Status Register
Default at
Power-up
Bit
0
Name
BUSY
WEL
Function
Read/Write
1 = Internal Write operation is in progress
0 = No internal Write operation is in progress
1 = Device is memory Write enabled
0 = Device is not memory Write enabled
0
0
R
R
1
2
3
4
5
6
BP0
BP1
BP2
TB
Indicate current level of block write protection (See Table 3)
Indicate current level of block write protection (See Table 3)
Indicate current level of block write protection (See Table 3)
Top / Bottom write protect
0
0
0
0
0
R/W
R/W
R/W
R/W
N/A
RESERVED Reserved for future use
1 = BP2,BP1,BP0 and TB are read-only bits
0 = BP2,BP1,BP0 and TB are read/writable
7
BPL
0
R/W
Note:
1. Only BP0, BP1, BP2, TB and BPL are writable.
2. BP0, BP1, BP2, TB and BPL are non-volatile.
WRITE ENABLE LATCH (WEL)
BUSY
The Write-Enable-Latch bit indicates the status of the internal
memory Write Enable Latch. If this bit is set to “1”, it indicates the
device is Write enabled. If the bit is set to “0” (reset), it indicates
the device is not Write enabled and does not accept any memory
Write (Program/ Erase) commands. This bit is automatically reset
under the following conditions:
The Busy bit determines whether there is an internal Erase or
Program operation in progress. A “1” for the Busy bit indicates
the device is busy with an operation in progress. A “0” indicates
the device is ready for the next valid operation.
• Power-up
Top/Bottom Block Protect (TB)
• Write Disable (WRDI) instruction completion
• Page Program instruction completion
• Sector Erase instruction completion
• Block Erase instruction completion
• Chip Erase instruction completion
• Write Status Register instructions
The Top/Bottom bit (TB) controls if the Block-Protection (BP2,
BP1, BP0) bits protect from the Top (TB=0) or the Bottom (TB=1)
of the array as show in Table 3, The TB bit can be set with Write
Status Register (WRSR) instruction. The TB bit can not be written
to if the Block- Protection-Look (BPL) bit is 1 or WP is low.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.3
7/37
ESMT
F25L01PA
Table 3: F25L01PA Block Protection Table
Status Register Bit
Protected Memory Area
Protection Level
TB
X
BP2
0
BP1
BP0
0
Block Range
None
Address Range
0
0
0
0
0
1
None
0*
X
1
0
None
None
Upper 1/2
Lower 1/2
All Blocks
0
X
1
Block 1
Block 0
Block 0~1
010000H – 01FFFFH
000000H – 00FFFFH
000000H – 01FFFFH
1
X
1
X
X
X
Note: * The combination of Status Register Bit (X100) can’t use Chip Erase instruction.
Block Protection (BP2, BP1, BP0)
Block Protection Lock-Down (BPL)
The Block-Protection (BP2, BP1, BP0) bits define the size of the
memory area, as defined in Table 3, to be software protected
against any memory Write (Program or Erase) operations. The
Write Status Register (WRSR) instruction is used to program the
WP pin driven low (VIL), enables the Block-Protection-
Lock-Down (BPL) bit. When BPL is set to 1, it prevents any
further alteration of the TB, BPL, BP2, BP1, and BP0 bits. When
the WP pin is driven high (VIH), the BPL bit has no effect and its
value is “Don’t Care”.
BP2, BP1, BP0 bits as long as WP is high or the Block-
Protection-Look (BPL) bit is 0. Chip Erase can only be executed if
Block-Protection bits are all 0. The factory default setting for
Block Protection Bit (BP2 ~ BP0) is 0.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.3
8/37
ESMT
F25L01PA
HOLD OPERATION
Hold mode when the SCK next reaches the active low state. See
Figure 1 for Hold Condition waveform.
HOLD pin is used to pause a serial sequence underway with the
SPI flash memory without resetting the clocking sequence. To
activate the HOLD mode, CE must be in active low state. The
HOLD mode begins when the SCK active low state coincides
with the falling edge of the HOLD signal. The HOLD mode ends
Once the device enters Hold mode, SO will be in high impedance
state while SI and SCK can be VIL or VIH.
If CE is driven active high during a Hold condition, it resets the
when the HOLD signal’s rising edge coincides with the SCK
active low state.
internal logic of the device. As long as HOLD signal is low, the
memory remains in the Hold condition. To resume
communication with the device, HOLD must be driven active
If the falling edge of the HOLD signal does not coincide with the
SCK active low state, then the device enters Hold mode when the
SCK next reaches the active low state.
high, and CE must be driven active low. See Figure 22 for Hold
timing.
Similarly, if the rising edge of the HOLD signal does not
coincide with the SCK active low state, then the device exits in
S C K
HO L D
Hold
A ctive
A ctive
A ctive
H o ld
Figure 1: HOLD Condition Waveform
WRITE PROTECTION
Table 4: Conditions to Execute Write-Status-Register (WRSR)
Instruction
The device provides software Write Protection.
The Write-Protect pin ( WP ) enables or disables the lock-down
function of the status register. The Block-Protection bits (BP2,
BP1, BP0, TB and BPL) in the status register provide Write
protection to the memory array and the status register. See Table
3 for Block-Protection description.
BPL
1
Execute WRSR Instruction
Not Allowed
WP
L
L
0
Allowed
H
X
Allowed
Write Protect Pin ( WP )
The Write-Protect ( WP ) pin enables the lock-down function of
the BPL bit (bit 7) in the status register. When WP is driven low,
the execution of the Write Status Register (WRSR) instruction is
determined by the value of the BPL bit (see Table 4). When WP
is high, the lock-down function of the BPL bit is disabled.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.3
9/37
ESMT
F25L01PA
INSTRUCTIONS
Instructions are used to Read, Write (Erase and Program), and
configure the F25L01PA. The instruction bus cycles are 8 bits
each for commands (Op Code), data, and addresses. Prior to
executing any Page Program, Write Status Register, Sector
Erase, Block Erase, or Chip Erase instructions, the Write Enable
(WREN) instruction must be executed first. The complete list of
the instructions is provided in Table 5. All instructions are
entered and must be driven high after the last bit of the instruction
has been shifted in (except for Read, Read ID, Read Status
Register, Read Electronic Signature instructions). Any low to high
transition on CE , before receiving the last bit of an instruction
bus cycle, will terminate the instruction in progress and return the
device to the standby mode.
synchronized off a high to low transition of CE . Inputs will be
accepted on the rising edge of SCK starting with the most
Instruction commands (Op Code), addresses, and data are all
input from the most significant bit (MSB) first.
significant bit. CE must be driven low before an instruction is
Table 5: Device Operation Instructions
Bus Cycle 1~3
4
Max.
Freq
Operation
1
2
3
5
6
N
SIN
SOUT
SIN
SOUT SIN SOUT SIN SOUT SIN
SOUT
SIN
SOUT
SIN SOUT
Read
33 MHz 03H
50MHz
Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z
X
DOUT0
X
DOUT1
X
cont.
Fast Read13
~
0BH Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z
X
X
X
DOUT0
X
cont.
100MHz
50MHz
~
Fast Read Dual
Output11,12
3BH
A23-A16
A15-A8
A7-A0
X
DOUT0~1
cont.
86MHz
Sector Erase4 (4K Byte)
20H Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z
D8H Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z
60H /
-
-
-
-
-
-
-
-
-
-
-
-
Block Erase4, (64K Byte)
Chip Erase
Hi-Z
-
-
-
-
-
-
-
-
-
-
-
-
C7H
Up to
Page Program (PP)
02H Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z DIN0
Hi-Z
DIN1
Hi-Z
256 Hi-Z
bytes
50MHz
~
Read Status Register
05H Hi-Z
01H Hi-Z
X
DOUT
Hi-Z
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(RDSR) 6
Write Status Register
(WRSR)
DIN
-.
-
-
Write Enable (WREN) 9
Write Disable (WRDI)
Deep Power Down (DP)
Release from Deep
Power Down (RDP)
Read Electronic
06H Hi-Z
04H Hi-Z
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
100MHz
B9h
Hi-Z
ABH Hi-Z
ABH Hi-Z
9FH Hi-Z
90H Hi-Z
-
X
-
X
-
-
-
-
-
X
-
-
10H
-
-
-
-
-
-
-
-
-
-
-
-
-
X
X
X
X
X
X
Signature (RES) 7
Jedec Read ID
X
8CH
30H
11H
(JEDEC-ID) 8
00H Hi-Z
01H Hi-Z
X
X
8CH
10H
X
X
10H
8CH
-
-
-
-
Read ID (RDID) 10
00H
Hi-Z 00H Hi-Z
Note:
1. Operation: SIN = Serial In, SOUT = Serial Out, Bus Cycle 1 = Op Code
2. X = Dummy Input Cycles (VIL or VIH); - = Non-Applicable Cycles (Cycles are not necessary); cont. = continuous
3. One bus cycle is eight clock periods.
4. Sector Earse addresses: use AMS -A12, remaining addresses can be VIL or VIH
Block Earse addresses: use AMS -A16, remaining addresses can be VIL or VIH
5. To continue programming to the next sequential address location, enter the 8-bit command, followed by the data to be
programmed.
6. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE .
7. The Read-Electronic-Signature is continuous with on going clock cycles until terminated by a low to high transition on CE .
8. The Jedec-Read-ID is output first byte 8CH as manufacture ID; second byte 30H as memory type; third byte 11H as
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.3 10/37
ESMT
F25L01PA
memory capacity.
9. The Write-Enable (WREN) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of each
other. The WRSR instruction must be executed immediately (very next bus cycle) after the WREN instruction to make both
instructions effective. WREN can enable WRSR, user just need to execute it. A successful WRSR can reset WREN.
10. The Manufacture ID and Device ID output will repeat continuously until CE terminates the instruction.
11. Dual commands use bidirectional IO pins. DOUT and cont. are serial data out; others are serial data in.
12. Dual output data:
IO
IO
0
= (D
6
, D
4
, D
2
, D
0
), (D
6
, D
4
, D
2
, D
0
)
)
1
= (D
7
, D5
, D3
, D1
), (D
7
, D5
, D3
, D1
DOUT0
DOUT1
13. Max. load capacitance is 15pF.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.3 11/37
ESMT
F25L01PA
Read (33MHz)
The Read instruction supports up to 33 MHz, it outputs the data
starting from the specified address location. The data output
stream is continuous through all addresses until terminated by a
the data from address location 01FFFFH had been read, the next
output will be from address location 000000H.
The Read instruction is initiated by executing an 8-bit command,
low to high transition on CE . The internal address pointer will
automatically increment until the highest memory address is
reached. Once the highest memory address is reached, the
address pointer will automatically increment to the beginning
(wrap-around) of the address space, i.e. for 1Mbit density, once
03H, followed by address bits [A23 -A0]. CE must remain active
low for the duration of the Read cycle. See Figure 2 for the Read
sequence.
Figure 2: Read Sequence
Fast Read (50 MHz ~ 100 MHz)
The Fast Read instruction supporting up to 100 MHz is initiated
by executing an 8-bit command, 0BH, followed by address bits
all addresses until terminated by a low to high transition on CE .
The internal address pointer will automatically increment until the
highest memory address is reached. Once the highest memory
address is reached, the address pointer will automatically
increment to the beginning (wrap-around) of the address space,
i.e. for 1Mbit density, once the data from address location
01FFFFH has been read, the next output will be from address
location 000000H.
[A23 -A0] and a dummy byte. CE must remain active low for the
duration of the Fast Read cycle. See Figure 3 for the Fast Read
sequence.
Following a dummy byte (8 clocks input dummy cycle), the Fast
Read instruction outputs the data starting from the specified
address location. The data output stream is continuous through
CE
0
1 2
3
4 5 6 7
8
15 16
23 24
31 32
39 40
47 48
MODE3
MODE0
55 56
63 64
71 72
80
SCK
SI
0B
ADD.
MSB
ADD.
ADD.
X
MSB
N
N+1
DOUT
N+2
DOUT
N+3
DOU T
N+4
DOU T
HIGH IMPENANCE
SO
DOU T
MSB
Note : X = Dummy Byte : 8 Clocks Input Dummy (VIL or VIH)
Figure 3: Fast Read Sequence
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.3 12/37
ESMT
F25L01PA
Fast Read Dual Output (50 MHz ~ 86 MHz)
The Fast Read Dual Output (3BH) instruction is similar to the
standard Fast Read (0BH) instruction except the data is output
on SI and SO pins. This allows data to be transferred from the
device at twice the rate of standard SPI devices. This instruction
is for quickly downloading code from Flash to RAM upon
power-up or for applications that cache code- segments to RAM
for execution.
The Fast Read Dual Output instruction is initiated by executing
an 8-bit command, 3BH, followed by address bits [A23 -A0] and a
dummy byte. CE must remain active low for the duration of the
Fast Read Dual Output cycle. See Figure 4 for the Fast Read
Dual Output sequence.
Figure 4: Fast Read Dual Output Sequence
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.3
13/37
ESMT
F25L01PA
Page Program (PP)
The Page Program instruction allows many bytes to be
programmed in the memory. The bytes must be in the erased
state (FFH) when initiating a Program operation. A Page
Program instruction applied to a protected memory area will be
ignored.
latched data are discarded and the last 256 bytes Data are
guaranteed to be programmed correctly within the same page. If
less than 256 bytes Data are sent to device, they are correctly
programmed at the requested addresses without having any
effects on the other bytes of the same page.
Prior to any Write operation, the Write Enable (WREN) instruction
CE must be driven high before the instruction is executed. The
user may poll the Busy bit in the software status register or wait
TPP for the completion of the internal self-timed Page Program
operation. While the Page Program cycle is in progress, the Read
Status Register instruction may still be accessed for checking the
status of the Busy bit. The BUSY bit is a 1 during the Page
Program cycle and becomes a 0 when the cycle is finished and
the device is ready to accept other instructions again. After the
Page Program cycle has finished, the Write-Enable-Latch (WEL)
bit in the Status Register is cleared to 0. See Figure 7 for the
Page Program sequence.
must be executed. CE must remain active low for the duration
of the Page Program instruction. The Page Program instruction is
initiated by executing an 8-bit command, 02H, followed by
address bits [A23-A0]. Following the address, at least one byte
Data is input (the maximum of input data can be up to 256 bytes).
If the 8 least significant address bits [A7-A0] are not all zero, all
transmitted data that goes beyond the end of the current page
are programmed from the start address of the same page (from
the address whose 8 least significant bits [A7-A0] are all zero).
If more than 256 bytes Data are sent to the device, previously
Figure 7: Page Program Sequence
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.3
14/37
ESMT
F25L01PA
64K Byte Block Erase
The 64K-byte Block Erase instruction clears all bits in the
selected block to FFH. A Block Erase instruction applied to a
protected memory area will be ignored. Prior to any Write
operation, the Write Enable (WREN) instruction must be
-A0]. Address bits [AMS -A16] (AMS = Most Significant address) are
used to determine the block address (BAX), remaining address
bits can be VIL or VIH. CE must be driven high before the
instruction is executed. The user may poll the Busy bit in the
Software Status Register or wait TBE for the completion of the
internal self-timed Block Erase cycle. See Figure 8 for the Block
Erase sequence.
executed. CE must remain active low for the duration of the any
command sequence. The Block Erase instruction is initiated by
executing an 8-bit command, D8H, followed by address bits [A23
Figure 8: 64K-byte Block Erase Sequence
4K Byte Sector Erase
The Sector Erase instruction clears all bits in the selected sector
to FFH. A Sector Erase instruction applied to a protected memory
area will be ignored. Prior to any Write operation, the Write
[AMS -A12] (AMS = Most Significant address) are used to determine
the sector address (SAX), remaining address bits can be VIL or
VIH. CE must be driven high before the instruction is executed.
The user may poll the Busy bit in the Software Status Register or
wait TSE for the completion of the internal self-timed Sector Erase
cycle. See Figure 9 for the Sector Erase sequence.
Enable (WREN) instruction must be executed. CE must remain
active low for the duration of the any command sequence. The
Sector Erase instruction is initiated by executing an 8-bit
command, 20H, followed by address bits [A23 -A0]. Address bits
CE
15 16
31
23 24
0 1 2 3 4 5 6 7 8
MODE3
MODE0
SCK
SI
20
ADD.
MSB
ADD.
ADD.
MSB
HIGH IMPENANCE
SO
Figure 9: 4K-byte Sector Erase Sequence
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.3 15/37
ESMT
F25L01PA
Chip Erase
The Chip Erase instruction clears all bits in the device to FFH. A
Chip Erase instruction will be ignored if any of the memory area is
protected. Prior to any Write operation, the Write Enable (WREN)
Erase instruction is initiated by executing an 8-bit command, 60H
or C7H. CE must be driven high before the instruction is
executed. The user may poll the Busy bit in the Software Status
Register or wait TCE for the completion of the internal self-timed
Chip Erase cycle. See Figure 10 for the Chip Erase sequence.
instruction must be executed. CE must remain active low for
the duration of the Chip-Erase instruction sequence. The Chip
CE
0 1 2 3 4 5 6 7
MODE3
SCK
SI
MODE0
60 or C7
MSB
HIGH IMPENANCE
SO
Figure 10: Chip Erase Sequence
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows reading of
the status register. The status register may be read at any time
even during a Write (Program/Erase) operation.
When a Write operation is in progress, the Busy bit may be
checked before sending any new commands to assure that the
new commands are properly received by the device.
CE must be driven low before the RDSR instruction is entered
and remain low until the status data is read. Read Status
Register is continuous with ongoing clock cycles until it is
terminated by a low to high transition of the CE . See Figure 11
for the RDSR instruction sequence.
Figure 11: Read Status Register (RDSR) Sequence
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.3
16/37
ESMT
F25L01PA
Write Enable (WREN)
The Write Enable (WREN) instruction sets the Write-Enable-
Latch bit in the Software Status Register to 1 allowing Write
operations to occur.
(Program/Erase) operation. CE must be driven high before the
WREN instruction is executed.
The WREN instruction must be executed prior to any Write
CE
0 1 2 3 4 5 6 7
MODE3
MODE0
SCK
SI
06
MSB
HIGH IMPENANCE
SO
Figure 12: Write Enable (WREN) Sequence
Write Disable (WRDI)
The Write Disable (WRDI) instruction resets the Write-Enable-
Latch bit to 0 disabling any new Write operations from occurring.
CE must be driven high before the WRDI instruction is
executed.
CE
0 1 2 3 4 5 6 7
MODE3
SCK
SI
MODE0
04
MSB
HIGH IMPENANCE
SO
Figure 13: Write Disable (WRDI) Sequence
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.3 17/37
ESMT
F25L01PA
Write-Status-Register (WRSR)
The Write Status Register instruction writes new values to the
When WP is high, the lock-down function of the BPL bit is
disabled and the BPL, TB, BP0, BP1,and BP2 bits in the status
BP2, BP1, BP0, TB and BPL bits of the status register. CE
must be driven low before the command sequence of the WRSR
instruction is entered and driven high before the WRSR
instruction is executed. See Figure 14 for WREN and WRSR
instruction sequences.
register can all be changed. As long as BPL bit is set to 0 or WP
pin is driven high (VIH) prior to the low-to-high transition of the
CE pin at the end of the WRSR instruction, the bits in the status
register can all be altered by the WRSR instruction. In this case,
a single WRSR instruction can set the BPL bit to “1” to lock down
the status register as well as altering the TB, BP0; BP1 and BP2
bits at the same time. See Table 4 for a summary description of
Executing the Write Status Register instruction will be ignored
when WP is low and BPL bit is set to “1”. When the WP is
low, the BPL bit can only be set from “0” to “1” to lock down the
status register, but cannot be reset from “1” to “0”.
WP and BPL functions.
CE
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
MODE3
MODE0
SCK
Stauts Register
Data In
06
01
7
6
4
3
2
0
1
SI
5
MSB
MSB
HIGH IMPENANCE
SO
Figure 14: Write-Enable (WREN) and Write-Status-Register (WRSR)
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.3 18/37
ESMT
F25L01PA
Deep Power Down (DP)
The Deep Power Down instruction is for minimizing power
consumption (the standby current is reduced from ISB1 to ISB2.).
Once the device is in deep power down status, all instructions will
be ignored except the Release from Deep Power Down
instruction (RDP) and Read Electronic Signature instruction
(RES). The device always power-up in the normal operation with
the standby current (ISB1). See Figure 15 for the Deep Power
Down instruction.
This instruction is initiated by executing an 8-bit command, B9H,
and then CE must be driven high. After CE is driven high, the
device will enter to deep power down within the duration of TDP
.
CE
MODE3
0
1
2
3
4
5
6
7
TDP
SCK MODE0
B9
SI
MSB
Standard Current
Deep Power Down Current
(ISB2)
Figure 15: Deep Power Down Instruction
Release from Deep Power Down (RDP) and Read-Electronic-Signature (RES)
The Release form Deep Power Down and Read-Electronic-
Signature instruction is a multi-purpose instruction.
CE low and executing an 8-bit command, ABH, followed by 3
dummy bytes. The Electronic-Signature byte is then output from
the device. The Electronic-Signature can be read continuously
The instruction can be used to release the device from the deep
power down status. This instruction is initiated by driving CE
until CE go high. See Figure 17 for RES sequence. After
driving CE high, it must remain high during for the duration of
low and executing an 8-bit command, ABH, and then drive CE
high. See Figure 16 for RDP instruction. Release from the deep
power down will take the duration of TRES1 before the device will
resume normal operation and other instructions are accepted.
T
RES2, and then the device will resume normal operation and
other instructions are accepted.
The instruction is executed while an Erase, Program or WRSR
cycle is in progress is ignored and has no effect on the cycle in
progress.
CE must remain high during TRES1
.
The instruction also can be used to read the 8-bit Electronic-
Signature of the device on the SO pin. It is initiated by driving
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.3
19/37
ESMT
F25L01PA
CE
MODE3
0
1
2
3
4
5
6
7
TRES1
SCK MODE0
AB
SI
MSB
HIGH IMPEDANCE
SO
Standby Current
Deep Power Down Current
(ISB2)
Figure 16: Release from Deep Power Down (RDP) Instruction
CE
30 31 32 33 34 35 36 37 38
0
1
2
3
4
5
6
7
8
9
MODE3
TRES2
SCK MODE0
SS
3 Dummy Bytes
SS
AB
SI
MSB
HIGH IMPEDANCE
SS
Electronic-Signature Data Out
SO
MSB
Standby
Current
Deep Power Down Current
(ISB2)
Figure 17: Read Electronic -Signature (RES) Sequence
Table 6: Electronic Signature Data
Command
RES
Electronic Signature Data
10H
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.3 20/37
ESMT
F25L01PA
JEDEC Read-ID
The JEDEC Read-ID instruction identifies the device as
F25L01PA and the manufacturer as ESMT. The device
information can be read from executing the 8-bit command, 9FH.
Following the JEDEC Read-ID instruction, the 8-bit
manufacturer’s ID, 8CH, is output from the device. After that, a
16-bit device ID is shifted out on the SO pin. Byte1, 8CH,
identifies the manufacturer as ESMT. Byte2, 30H, identifies the
memory type as SPI Flash. Byte3, 11H, identifies the device as
F25L01PA. The instruction sequence is shown in Figure 18.
The JEDEC Read ID instruction is terminated by a low to high
transition on CE at any time during data output. If no other
command is issued after executing the JEDEC Read-ID
instruction, issue a 00H (NOP) command before going into
Standby Mode ( CE =VIH).
CE
0
1
2
3
4 5 6 7 8 9 10 11 12 13 1415 1617 1819 2021 22 23 24 25 2627 2829 3031
MODE3
MODE0
SCK
9F
SI
MSB
HIGH IMPENANCE
SO
8C
30
11
MSB
MSB
MSB
Figure 18: JEDEC Read-ID Sequence
Table 7: JEDEC READ-ID Data
Device ID
Manufacturer’s ID
(Byte 1)
Memory Type
(Byte 2)
Memory Capacity
(Byte 3)
8CH
30H
11H
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.3 21/37
ESMT
F25L01PA
Read-ID (RDID)
The Read-ID instruction (RDID) identifies the devices as
F25L01PA and manufacturer as ESMT. This command is
backward compatible to all ESMT SPI devices and should be
used as default device identification when multiple versions of
ESMT SPI devices are used in one design. The device
information can be read from executing an 8-bit command, 90H,
followed by address bits [A23 -A0]. Following the Read-ID
instruction, the manufacturer’s ID is located in address 000000H
and the device ID is located in address 000001H.
Once the device is in Read-ID mode, the manufacturer’s and
device ID output data toggles between address 000000H and
000001H until terminated by a low to high transition on CE .
CE
15 16
31 32
0
1
2
3
4
5
6
7
8
23 24
MSB
39 40
47 48
55 56
63
MODE3
SCK MODE0
SI
90
00
00
ADD1
MSB
HIGH
IMPENANCE
HIGH IMPENANCE
SO
8C
10
8C
10
MSB
Note: The Manufacture’s and Device ID output stream is continuous until terminated by a low to high transition on CE.
1. 00H will output the Manufacture’s ID first and 01H will output Device ID first before toggling between the two. .
Figure 19: Read-ID Sequence
Table 8: Product ID Data
Address
Byte1
Byte2
8CH
10H
000000H
Device ID
Manufacturer’s ID
ESMT F25L01PA
10H
8CH
000001H
Device ID
Manufacturer’s ID
ESMT F25L01PA
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.3 22/37
ESMT
F25L01PA
ELECTRICAL SPECIFICATIONS
Absolute Maximum Stress Ratings
(Applied conditions are greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the
operational sections of this datasheet is not implied. Exposure to absolute maximum stress rating conditions may affect device
reliability.)
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V
Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Output Short Circuit Current (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
( Note 1: Output shorted for no more than one second. No more than one output shorted at a time. )
AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . . . . . CL = 15 pF for ≧75MHz
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .CL = 30 pF for ≦50MHz
See Figures 25 and 26
OPERATING RANGE
Parameter
Symbol
VDD
Value
Unit
Operating Supply Voltage
Ambient Operating Temperature
2.7 ~ 3.6
-40 ~ +85
V
℃
TA
Table 9: DC OPERATING CHARACTERISTICS
Limits
Max
Symbol
Parameter
Read Current
Test Condition
Min
Unit
Standard
Dual
10
15
15
20
17
22
IDDR1
IDDR2
IDDR3
IDDR4
mA
mA
mA
mA
CE =0.1 VDD/0.9 VDD, SO=open
CE =0.1 VDD/0.9 VDD, SO=open
CE =0.1 VDD/0.9 VDD, SO=open
CE =0.1 VDD/0.9 VDD, SO=open
@33 MHz
Read Current
@ 50MHz
Standard
Dual
Read Current
@ 86MHz
Standard
Dual
Read Current
@ 100MHz
Standard
22
IDDW
ISB1
ISB2
Program and Erase Current
Standby Current
20
25
10
mA
µA
µA
CE =VDD
CE =VDD, VIN =VDD or VSS
Deep Power Down Current
CE =VDD, VIN =VDD or VSS
±2
±2
ILI
ILO
VIL
VIH
VOL
VOH
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
µA VIN=GND to VDD, VDD=VDD Max
µA VOUT=GND to VDD, VDD=VDD Max
V
V
V
V
VDD=VDD Min
VDD=VDD Max
IOL= 1.6 mA, VDD=VDD Min
IOH=-100 µA, VDD=VDD Min
-0.5
0.7 x VDD
0.3 x VDD
VDD +0.4
0.4
VDD-0.2
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.3 23/37
ESMT
F25L01PA
Table 10: CAPACITANCE (TA = 25°C, f=1 MHz, other pins open)
Parameter
Description
Test Condition
VOUT = 0V
Maximum
8 pF
1
COUT
Output Pin Capacitance
Input Capacitance
1
CIN
VIN = 0V
6 pF
Note 1: This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Table 11: AC OPERATING CHARACTERISTICS
Normal 33MHz Fast 50 MHz
Fast 86 MHz Fast 100 MHz
Symbol
Parameter
Unit
Min
Max
Min
Max
Min
Max
Min
Max
FCLK
Serial Clock Frequency
33
50
86
100
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
TSCKH
Serial Clock High Time
Serial Clock Low Time
13
13
5
9
9
5
5
4
4
2
TSCKL
1
TCES
5
5
5
CE Active Setup Time
CE Active Hold Time
CE Not Active Setup Time
CE Not Active Hold Time
CE High Time
1
TCEH
5
5
5
5
1
TCHS
5
5
5
5
1
TCHH
5
5
5
5
TCPH
TCHZ
TCLZ
TDS
100
100
100
100
6
6
6
6
CE High to High-Z Output
SCK Low to Low-Z Output
Data In Setup Time
0
3
3
5
5
0
3
3
5
5
0
3
3
5
5
0
3
3
5
5
TDH
Data In Hold Time
THLS
THHS
HOLD Low Setup Time
HOLD High Setup Time
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.3 24/37
ESMT
F25L01PA
Table 11: AC OPERATING CHARACTERISTICS - Continued
Normal 33MHz Fast 50 MHz
Fast 86 MHz Fast 100 MHz
Symbol
Parameter
Unit
Min
Max
Min
Max
Min
Max
Min
Max
THLH
THHH
ns
ns
ns
ns
5
5
5
5
HOLD Low Hold Time
5
5
5
5
HOLD High Hold Time
3
THZ
6
6
6
6
6
6
6
6
HOLD Low to High-Z Output
3
TLZ
HOLD High to Low-Z Output
Output Hold from SCK Change
Output Valid from SCK
TOH
TV
TWHSL
0
0
0
0
ns
ns
ns
12
20
8
7
7
4
20
20
20
Write Protect Setup Time before CE Low
Write Protect Hold Time after CE High
CE High to Deep Power Down Mode
CE High to Standby Mode ( for DP)
CE High to Standby Mode (for RES)
4
TSHWL
ns
us
us
us
100
3
100
3
100
3
100
3
3
TDP
3
TRES1
3
3
3
3
3
TRES2
1.8
1.8
1.8
1.8
Note:
1. Relative to SCK.
2. SCKH + TSCKL must be less than or equal to 1/ FCLK
3. Value guaranteed by characterization, not 100% tested in production.
T
.
4. Only applicable as a constraint for a Write status Register instruction when Block- Protection-Look (BPL) bit is set at 1.
ERASE AND PROGRAMMING PERFORMANCE
Limit
Parameter
Symbol
Unit
Typ2
90
Max3
Sector Erase Time
TSE
TBE
TCE
TW
250
1.5
2
ms
s
Block Erase Time
0.75
1
Chip Erase Time
s
Write Status Register Time
Page Programming Time
Erase/Program Cycles1
Data Retention
5
15
5
ms
TPP
1.5
ms
100,000
20
-
Cycles
Years
-
Notes:
1. Not 100% Tested, Excludes external system level over head.
2. Typical values measured at 25°C, 3V.
3. Maximum values measured at 85°C, 2.7V.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.3 25/37
ESMT
F25L01PA
Figure 20: Serial Input Timing Diagram
Figure 21: Serial Output Timing Diagram
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.3 26/37
ESMT
F25L01PA
Figure 22: HOLD Timing Diagram
WP
CE
TSHWL
TWHSL
SCK
SI
HIGH IMPENANCE
SO
Figure 23: Write Protect setup and hold timing during WRSR when BPL = 1
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.3 27/37
ESMT
F25L01PA
VCC
VCC (max)
Program, Erase and Write command is ignored
CE must track VCC
VCC (min)
Read command
is allowed
T
VSL
Device is fully
accessible
Reset
State
VWI
T
PUW
Time
Figure 24: Power-Up Timing Diagram
Table 12: Power-Up Timing and VWI Threshold
Unit
Parameter
Symbol
Min.
10
1
Max.
TVSL
TPUW
VWI
us
ms
V
VCC(min) to CE low
Time Delay before Write instruction
10
2
Write Inhibit Threshold Voltage
1
Note: These parameters are characterized only.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.3 28/37
ESMT
F25L01PA
Input timing reference level
Output timing reference level
0.8VCC
0.2VCC
0.7VCC
0.3VCC
AC
Measurement
Level
0.5VCC
Note : Input pulse rise and fall time are <5ns
Figure 25: AC Input/Output Reference Waveforms
Figure 26: A Teat Load Example
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.3
29/37
ESMT
F25L01PA
PACKING DIMENSIONS
8-LEAD
SOIC ( 150 mil )
8
5
GAUGE PLANE
L
DETAIL "X"
1
4
e
b
D
L1
"X"
SEATING PLANE
Dimension in mm
Dimension in inch
Dimension in mm
Dimension in inch
Symbol
Symbol
Min
1.35
0.10
1.25
0.33
0.19
5.80
Norm
1.60
Max
1.75
0.25
1.55
0.51
Min
Norm
0.063
0.006
0.057
0.016
Max
Min
Norm
4.90
Max
Min
Norm
0.193
Max
A
A1
A2
b
0.053
0.004
0.049
0.013
0.069
0.010
0.061
0.020
0.010
0.244
D
E
L
4.80
3.80
0.40
5.00
4.00
0.86
0.189
0.150
0.016
0.197
0.157
0.034
0.15
3.90
0.154
1.45
0.66
0.026
0.406
0.203
6.00
e
1.27 BSC
1.05
0.050 BSC
0.041
c
0.25 0.0075 0.008
6.20 0.228 0.236
1.00
1.10
0.039
0.043
L1
θ
0°
8°
0°
8°
H
---
---
Controlling dimension : millimenter
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.3 30/37
ESMT
F25L01PA
PACKING DIMENSIONS
8-LEAD SOIC 200 mil ( official name – 208 mil )
θ
5
8
4
1
b
e
D
L
L1
SEATING PLANE
DETAIL "X"
Dimension in mm
Dimension in inch
Dimension in mm
Dimension in inch
Symbol
Symbol
Min
---
Norm
---
Max
2.16
0.25
1.91
0.51
0.25
5.33
Min
Norm
---
Max
Min
Norm
7.90
Max
Min
Norm
0.311
Max
0.319
0.212
0.032
A
A1
A2
b
---
0.085
0.010
0.075
0.020
0.010
0.210
E
E1
L
7.70
5.18
0.50
8.10
5.38
0.80
0.303
0.204
0.020
0.05
1.70
0.36
0.19
5.13
0.15
1.80
0.41
0.20
5.23
0.002
0.067
0.014
0.007
0.202
0.006
0.071
0.016
0.008
0.206
5.28
0.208
0.65
0.026
e
1.27 BSC
1.37
0.050 BSC
0.054
c
1.27
1.47
0.050
0.058
L1
θ
0°
8°
0°
8°
D
---
---
Controlling dimension : millimenter
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.3 31/37
ESMT
F25L01PA
PACKING DIMENSIONS
8-LEAD TSSOP SPI Flash (4.4mm)
D
D
A
A2
1
A1
e
1
8
Y
4
5
b
b1
c
with Plating
Base Material
c1
B
B
Gage Plane
Section B-B
°
L
L1
Dimension in mm
Dimension in inch
Symbol
Min
-
Norm
Max
1.20
0.15
1.05
0.30
0.25
0.20
0.16
Min
-
Norm
Max
-
-
0.004
0.039
-
0.009
-
A
A1
A2
b
b1
c
c1
D
D1
E
L
L1
e
Y
Θ
0.047
0.006
0.041
0.012
0.010
0.008
0.006
0.05
0.80
0.19
0.19
0.09
0.09
0.10
1.00
-
0.22
-
0.002
0.031
0.008
0.008
0.004
0.004
0.127
6.40 BSC
4.40
3.00
0.60
1.00 REF
0.65 BSC
-
0.005
0.252 BSC
0.173
0.118
0.024
0.039 REF
0.026 BSC
-
4.30
2.90
0.45
4.50
3.10
0.75
0.169
0.114
0.018
0.177
0.122
0.030
-
-
0.10
8°
0.004
8°
0°
0°
-
-
Controlling dimension : Millimeter
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.3 32/37
ESMT
F25L01PA
PACKING
DIMENSIONS
8-PIN P-DIP ( 300 mil )
D
8
5
0
1
4
S e a tin g P la n e
1
b
b
e
Dimension in mm
Dimension in inch
Symbol
Min
Norm
---
Max
Min
---
Norm
Max
0.21
---
---
---
---
A
A1
A2
D
5.00
---
---
0.38
3.18
9.02
0.015
0.125
0.355
3.30
3.43
10.16
0.130
0.135
0.400
9.27
0.365
E
7.62 BSC.
6.35
0.300 BSC.
0.250
E1
L
6.22
9.02
6.48
0.245
0.115
0.255
0.150
9.27
10.16
0.130
e
2.54 TYP.
9.02
0.100 TYP.
0.355
eB
b
8.51
9.53
15O
0.335
0O
0.375
15O
0.46 TYP.
1.52 TYP.
7O
0.018 TYP.
0.060 TYP.
7O
b1
θO
0O
Controlling dimension : Inch.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.3 33/37
ESMT
F25L01PA
PACKING DIMENSIONS
8-CONTACT
WSON ( 6x5 mm )
D
PIN# 1
L
DETAIL : "B"
"A"
D2
DETAIL : "A"
"B"
PIN# 1
Symbol
Dimension in mm
Dimension in inch
Min
0.70
0.00
0.35
5.90
3.30
4.90
3.90
Norm
0.75
0.02
0.40
6.00
3.40
5.00
4.00
Max
0.80
0.05
0.45
6.10
3.50
5.10
4.10
Min
Norm
0.030
0.001
0.016
0.236
0.134
0.197
0.157
Max
A
A1
b
D
D2
E
E2
e
L
0.028
0.000
0.014
0.232
0.130
0.193
0.154
0.031
0.002
0.018
0.240
0.138
0.201
0.161
1.27 BSC
0.60
0.050 BSC
0.024
0.55
0.65
0.022
0.026
Controlling dimension : millimeter
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.3 34/37
ESMT
F25L01PA
PACKING
DIMENSIONS
8-CONTACT
USON ( 2x3 mm )
Symbol
Dimension in mm
Dimension in inch
Min
0.50
0.00
0.20
2.90
0.10
1.90
1.50
Min
0.55
Min
0.60
0.05
0.30
3.10
0.30
2.10
1.70
Min
Norm
0.022
Max
0.020
0.000
0.008
0.114
0.004
0.075
0.059
0.024
0.002
0.012
0.122
0.012
0.083
0.067
A
A1
b
0.02
0.001
0.25
0.010
3.00
0.118
D
0.20
0.008
D1
E
2.00
0.079
1.60
0.063
E1
e
0.50 BSC
0.45
0.020 BSC
0.018
0.40
0.30
0.50
0.40
0.016
0.012
0.020
0.016
L
0.35
0.014
L1
Controlling dimension : millimeter
(Revision date : Mar 25 2013)
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.3 35/37
ESMT
F25L01PA
Revision History
Revision
Date
Description
0.1
2010.03.09
Original
1. Modify surface mount lead soldering temperature
2. Add package description into pin configurations
3. Delete TPU-READ & TPU-WRITE
0.2
2010.04.02
0.3
1.0
2010.05.14
2010.08.06
Modify WSON packing dimension
1. Delete Preliminary
2. Modify the specification of Tw(typ)
1. Modify voltage
2. Modify the specification of IDDR1~4,IDDW,ISB1~2
TDS,TDH,TV,TSE and TCE(max)
3. Delete TCLCH, TCHCL, byte programming time, chip
programming time and 100MHz for Dual Output
,
1.1
1.2
1.3
2012.10.22
2012.11.06
2013.04.03
Add TSSOP package
1. Add USON package
2. Correct the description of Block Protection, Block
Protection Lock-Down
3. Modify Ambient Operating Temperature
4. Correct protection level (0) of block protection table
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.3 36/37
ESMT
F25L01PA
Important Notice
All rights reserved.
No part of this document may be reproduced or duplicated in any form or
by any means without the prior permission of ESMT.
The contents contained in this document are believed to be accurate at
the time of publication. ESMT assumes no responsibility for any error in
this document, and reserves the right to change the products or
specification in this document without notice.
The information contained herein is presented only as a guide or
examples for the application of our products. No responsibility is
assumed by ESMT for any infringement of patents, copyrights, or other
intellectual property rights of third parties which may result from its use.
No license, either express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of ESMT or
others.
Any semiconductor devices may have inherently a certain rate of failure.
To minimize risks associated with customer's application, adequate
design and operating safeguards against injury, damage, or loss from
such failure, should be provided by the customer when making
application designs.
ESMT's products are not authorized for use in critical applications such
as, but not limited to, life support devices or system, where failure or
abnormal operation may directly affect human lives or cause physical
injury or property damage. If products described here are to be used for
such kinds of application, purchaser must do its own quality assurance
testing appropriate to such applications.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.3 37/37
相关型号：
©2020 ICPDF网 联系我们和版权申明