PBL38650/2SOT [ERICSSON]
SLIC, Bipolar, PDSO24, SOIC-24;型号: | PBL38650/2SOT |
厂家: | ERICSSON |
描述: | SLIC, Bipolar, PDSO24, SOIC-24 电信 光电二极管 电信集成电路 |
文件: | 总16页 (文件大小:138K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
June 1999
PBL 386 50/2
Subscriber Line
Interface Circuit
Description
Key Features
The PBL 386 50/2 Subscriber Line Interface Circuit (SLIC) is a 90 V bipolar integrated • 24-pin SSOP package
circuit for use in Central Office Metering applications and other telecommunications
equipment. The PBL 386 50/2 has been optimized for low total line interface cost and
headroom for 2.2 Vrms metering
a high degree of flexibility in different applications.
• Programmable two-wire signal
• High and low battery with automatic
The PBL 386 50/2 emulates resistive loop feed, programmable between 2x50 Ω
switching
and 2x900 Ω, with short loop current limiting adjustable to max 45 mA. In the current
• Only +5 V feed in addition to battery
limited region the loop feed is nearly constant current with a slight slope
corresponding to 2x30kΩ.
• Selectable transmit gain (0.5x or 0.25x)
A second, lower battery voltage may be connected to the device to reduce short
loop power dissipation. The SLIC automatically switches between the two battery
supply voltages without need for external components or external control.
The SLIC incorporates loop current, ground key and ring trip detection functions.
The PBL 386 50/2 is compatible with both loop and ground start signaling.
Two- to four-wire and four- to two-wire voice frequency (VF) signal conversion is
accomplished by the SLIC in conjunction with either a conventional CODEC/filter or
with a programmable CODEC/filter, e.g. SLAC, SiCoFi, Combo II. The programmable
two-wire impedance, complex or real, is set by a simple external network.
Longitudinal voltages are suppressed by a feedback loop in the SLIC and the
longitudinal balance specifications meet Bellcore TR909 requirements.
The PBL 386 50/2 package options are 24-pin SSOP, 24-pin SOIC or 28-pin PLCC.
• 70 mW on-hook power dissipation in
active state
• On-hook transmission
• Long loop battery feed tracks Vbat for
maximum line voltage
• No power-up sequence
• 43V open loop voltage @
-48V battery feed
• Constant loop voltage for line leakage
<5 mA (RLeak ~ >10 kΩ @ -48V)
• Full longitudinal current capability
during on-hook state
• Analog over temperature protection
permits transmission while the
protection circuit is active
• Line voltage measurement
• Polarity reversal
Ring Relay
RRLY
Driver
• Ground key detector
DT
C1
Ring Trip
Comparator
• Tip open state with ring ground
detector
DR
TIPX
RINGX
HP
C2
Input
Decoder
and
C3
Ground Key
Detector
Control
DET
POV
PSG
PLC
Line Feed
Controller
and
Longitudinal
Signal
VCC
Two-wire
Interface
PBL 386 50/2
PBL
Suppression
LP
386 50/2
VBAT2
VBAT
PLD
REF
Off-hook
Detector
PBL 386 50/2
AGND
BGND
VTX
RSN
VF Signal
Transmission
24-pin SOIC, 24-pin SSOP, 28-pin PLCC
PTG
Figure 1. Block diagram.
1
PBL 386 50/2
Maximum Ratings
Parameter
Symbol
Min
Max
Unit
Temperature, Humidity
Storage temperature range
Operating temperature range
Operating junction temperature range, Note 1
TStg
TAmb
TJ
-55
-40
-40
+150
+110
+140
°C
°C
°C
Power supply, 0°C ≤ TAmb ≤ -70°C
V
V
V
V
CC with respect to A/BGND
Bat2 with respect to A/BGND
Bat with respect to A/BGND, continuous
Bat with respect to A/BGND, 10 ms
VCC
VBat2
VBat
VBat
-0.4
VBat
-75
-80
6.5
0.4
0.4
0.4
V
V
V
V
Power dissipation
Continuous power dissipation at TAmb ≤ +70 °C
PD
VG
1.5
0,3
W
V
Ground
Voltage between AGND and BGND
Relay Driver
-0,3
Ring relay supply voltage
BGND+14 V
Ring trip comparator
Input voltage
Input current
VDT, VDR
IDT, IDR
VBat
-5
AGND
5
V
mA
Digital inputs, outputs (C1, C2, C3, DET)
Input voltage
VID
-0.4
-0.4
VCC
VCC
V
V
Output voltage
VOD
TIPX and RINGX terminals, 0°C < TAmb < +70°C, VBat = -50V
Maximum supplied TIPX or RINGX current
ITIPX, IRINGX -100
+100
2
mA
V
TIPX or RINGX voltage, continuous (referenced to AGND), Note 2
TIPX or RINGX, pulse < 10 ms, tRep > 10 s, Note 2
TIPX or RINGX, pulse < 1 µs, tRep > 10 s, Note 2
VTA, VRA
VTA, VRA
VTA, VRA
VTA, VRA
-80
VBat -10
VBat -25
VBat -35
5
V
10
15
V
TIPX or RINGX, pulse < 250 ns, tRep > 10 s, Notes 2 & 3
V
Recommended Operating Condition
Parameter
Symbol
Min
Max
Unit
Ambient temperature
TAmb
VCC
VBat
VG
0
+70
5.25
-8
°C
V
V
V
V
CC with respect to AGND
Bat with respect to AGND
4.75
-65
-100
AGND with respect to BGND
100
mV
Notes
1. The circuit includes thermal protection. Operation at or above 140°C junction temperature may degrade device reliability.
2. With the diodes DVB and DVB2 included, see figure 12.
3.
RF1 and RF2 ≥ 20 Ω is also required. Pulse is applied to TIP and RING outside RF1 and RF2.
2
PBL 386 50/2
Electrical Characteristics
0 °C ≤ TAmb ≤ +70 °C, PTG = Open (see pin description), ROV = ∞, VCC= +5V ±5 %, VBat= -58V to -40V, VBat2 = -32V, RLC=32.4 kΩ, IL
= 27 mA. RL = 600 Ω, RF1= RF2= RP1= RP2=0, RRef = 49.9 kΩ, CHP = 47 nF, CLP=0.15 µF, RT = 60 kΩ, RSG = 0 kΩ, RRX = 60 kΩ, RR =
11 kΩ unless otherwise specified. Current definition: current is positive if flowing into a pin.
Ref
Parameter
fig
Conditions
Min
Typ
Max
Unit
Two-wire port
Overhead voltage, VTRO ,ILdc > 18mA
2
Active state, ROV = ∞
0.2 kHz < f < 3.4 kHz
1% THD, Note 1
f≤16kHz, ZLAC =200Ω, Adj. by ROV
Note 2
0 < f < 100 Hz
active state
Normal polarity:
0.2 kHz < f < 1.0 kHz
1.0 kHz < f < 3.4 kHz
Reverse polarity:
0.2 kHz < f < 3.4 kHz
2.7
1.1
VPeak
On-Hook, ILdc < 5mA
Over load level, metering
Input impedance, ZTR
Longitudinal impedance, ZLOT, ZLOR
Longitudinal current limit, ILOT, ILOR
Longitudinal to metallic balance, BLM
(IEEE standard 455-1985, ZTRX=736Ω)
Longitudinal to metallic balance, BLME
ELo
VPeak
VPeak
5.0
35
ZT/200
20
Ω/wire
mArms /wire
18
55
55
dB
dB
3
3
BLME = 20 · Log
55
dB
VTR
Longitudinal to four-wire balance, BLFE
Normal polarity:
0.2 kHz < f < 1.0 kHz
1.0 kHz < f < 3.4 kHz
Reverse polarity:
61
61
75
70
dB
dB
ELo
BLFE = 20 · Log
VTX
0.2 kHz < f < 3.4 kHz
0.2 kHz < f < 3.4 kHz
61
40
68
50
dB
dB
Metallic to longitudinal balance, BMLE
VTR
4
BMLE = 20 · Log
; ERX = 0
VLo
C
TIPX
VTX
Figure 2. Overhead voltage, VTRO, two-
wire port
RL
VTRO
ILDC
RT
PBL 386 50/2
ERX
RINGX
RSN
1
<< RL, RL= 600 Ω
ωC
RRX
RT = 60 kΩ, RRX = 60 kΩ
VTX
TIPX
ELo
RLT
C
Figure 3. Longitudinal to metallic (BLME
)
RT
VTR
PBL 386 50/2
VTX
and Longitudinal to four-wire (BLFE
)
balance
RLR
1
RINGX
RSN
<< 150 Ω, RLR =RLT =RL /2=300Ω
ωC
RRX
RT = 60 kΩ, RRX = 60 kΩ
3
PBL 386 50/2
Ref
fig
Parameter
Conditions
Min
Typ
Max
Unit
Four-wire to longitudinal balance, BFLE
4
0.2 kHz < f < 3.4 kHz
40
50
dB
ERX
BFLE = 20 · Log
VLo
Two-wire return loss, r
|ZTR + ZL|
r = 20 · Log
|ZTR - ZL|
0.2 kHz < f < 1.0 kHz
1.0 kHz < f < 3.4 kHz, Note 3
active, IL <5 mA
27
20
35
22
- 1.3
dB
dB
V
TIPX idle voltage, VTi
RINGX idle voltage, VRi
active, IL <5 mA
tip open, IL <5 mA
active, IL<5 mA
VBat +3.0
VBat +3.0
VBat +4.3
V
V
V
VTR
Four-wire transmit port (VTX)
Overhead voltage, VTXO, IL > 18mA
5
Load impedance > 20 kΩ,
1.35
VPeak
1% THD, Note 4
On-hook, IL < 5mA
Output offset voltage, ∆VTX
Output impedance, zTX
0.55
-100
VPeak
mV
Ω
0
15
100
50
0.2 kHz < f < 3.4 kHz
Four-wire receive port (RSN)
Receive summing node (RSN) DC voltage
Receive summing node (RSN) impedance
Receive summing node (RSN)
current (IRSN) to metallic loop current (IL)
gain,αRSN
I
RSN = -155 µA
1.15
1.25
8
1.35
20
V
Ω
0.2 kHz < f < 3.4 kHz
0.3 kHz < f < 3.4 kHz
200
ratio
Frequency response
Two-wire to four-wire, g2-4
6
relative to 0 dBm, 1.0 kHz. ERX = 0 V
0.3 kHz < f < 3.4 kHz
-0.20
-1.0
0.10
0.1
dB
dB
f = 8.0 kHz, 12 kHz, 16 kHz
TIPX
VTX
RLT
Figure 4. Metallic to longitudinal and four-
wire to longitudinal balance
C
VTR
RT
PBL 386 50/2
ERX
VLo
RLR
1
RINGX
RSN
<< 150 Ω, RLT =RLR =RL /2 =300Ω
ωC
RRX
RT = 60 kΩ, RRX = 60 kΩ
C
TIPX
VTX
Figure 5. Overhead voltage, VTXO, four-
wire transmit port
RL
ILDC
RT
VTXO
PBL 386 50/2
1
EL
<< RL, RL = 600 Ω
ωC
RINGX
RSN
RRX
RT = 60 kΩ, RRX = 60 kΩ
4
PBL 386 50/2
Ref
fig
Parameter
Conditions
Min
Typ
Max
Unit
Four-wire to two-wire, g4-2
6
relative to 0 dBm, 1.0 kHz. EL=0 V
0.3 kHz < f < 3.4 kHz
f = 8 kHz, 12 kHz,
-0.2
-1.0
-2.0
0.1
0
0
dB
dB
dB
16 kHz
Four-wire to four-wire, g4-4
6
6
relative to 0 dBm, 1.0 kHz, EL=0 V
0.3 kHz < f < 3.4 kHz
-0.2
0.1
dB
Insertion loss
Two-wire to four-wire, G2-4
0 dBm, 1.0 kHz, Note 5
VTX
G2-4 = 20 · Log
; ERX = 0
-6.22
-6.02
-5.82
dB
dB
VTR
PTG = AGND
-12.24
-12.04
-11.84
Four-wire to two-wire, G4-2
6
0 dBm, 1.0 kHz, Note 6
VTR
G4-2 = 20 · Log
; EL = 0
-0.2
0.2
dB
ERX
Gain tracking
Two-wire to four-wire
6
6
Ref. -10 dBm, 1.0 kHz, Note 7
-40 dBm to +3 dBm
-55 dBm to -40 dBm
Ref. -10 dBm, 1.0 kHz,
-40 dBm to +3 dBm
-0.1
-0.2
0.1
0.2
dB
dB
Four-wire to two-wire
-0.1
-0.2
0.1
0.2
dB
dB
-55 dBm to -40 dBm
Noise
Idle channel noise at two-wire
(TIPX-RINGX) or four-wire (VTX) output
C-message weighting, 2 wire
Psophometrical weighting, 2 wire
C-message weighting, 4 wire
Psophometrical weighting, 4 wire
Note 8
12
-78
6
dBrnC
dBmp
dBrnC
dBmp
-84
Harmonic distortion
Two-wire to four-wire
Four-wire to two-wire
6
0 dBm
0.3 kHz < f < 3.4 kHz
-67
-67
-50
-50
dB
dB
Battery feed characteristics
Loop current, IL , in the current
limited region, reference A, B & C
13
7
18mA ≤ IL ≤ 45 mA
0.92 IL
IL
1.08 IL
-150
mA
Tip open state TIPX current, ILeak
Tip open state RINGX current, ILRTo
S = closed; R = 7 kΩ, Note 10
RLRTo = 0Ω, VBat = -48V
RLRTo = 2.5 kΩ, VBat = -48V
ILRTo < 23 mA
µA
mA
mA
V
IL
17
Tip open state RINGX voltage, VRTo
VBat +6
C
Figure 6.
TIPX
VTX
Frequency response, insertion loss,
gain tracking.
RL
EL
VTR
ILDC
RT
PBL 386 50/2
VTX
ERX
1
<< RL, RL = 600 Ω
ωC
RINGX
RSN
RRX
RT = 60 kΩ, RRX = 60 kΩ
5
PBL 386 50/2
Ref
fig
Parameter
Conditions
Min
Typ
Max
Unit
Tip voltage (ground start)
7
Active state, Tip lead open (S open), -4
-2.2
V
Ring lead to ground through 150 Ω
Tip voltage (ground start)
Active state, tip lead to -48 V
through 7 kΩ (S closed), Ring
lead to ground through 150 Ω
RL = 0Ω
-6
-2.4
0
V
Open circuit state loop current, ILOC
-100
100
µA
Loop current detector
Programmable threshold, ILTh
active, active reverse
500
RLD
,
ILTh
=
0.85·ILTh ILTh
0.85·ILTh ILTh
1.15·ILTh mA
1.15·ILTh mA
RLD in kΩ, ILTh ≥ 7 mA
Tip open state
500
=
ILTh
RLD
Ground key detector
Ground key detector threshold
(ILTIPX and ILRINGX difference to trigger ground key det.)
10
16
22
mA
Line voltage measurement
Pulse width, tLVM
Note 9
5.5
µs/V
Ring trip comparator
Offset voltage, ∆VDTDR
Input bias current, IB
Input common mode range, VDT, VDR
Ring relay driver
Source resistance, RS = 0 Ω
IB = (IDT + IDR)/2
-20
-200
VBat+1
0
-20
20
200
-1
mV
nA
V
Saturation voltage, VOL
Off state leakage current, ILk
Digital inputs (C1, C2, C3)
Input low voltage, VIL
Input high voltage, VIH
Input low current, IIL
Input high current, IIH
Detector output (DET)
Output low voltage
IOL = 50 mA
VOH = 12 V
0.2
0.5
10
V
µA
0
2.5
0.5
VCC
-50
50
V
V
µA
µA
VIL = 0.5
VIH = 2.5 V
I
OL = 0.5 mA
0.7
V
Internal pull-up resistor
Power dissipation (VBat = -48V, VBat2 = -32V)
P1
15
10
kΩ
Open circuit state, C1, C2, C3 = 0, 0, 0
Active state, C1, C2, C3 = 0, 1, 0
15
85
mW
P2
P3
P4
Longitudinal current = 0 mA, I L=0 mA (on-hook) 70
mW
mW
mW
RL = 300 Ω (off-hook)
RL = 800 Ω (off-hook)
730
360
Power supply currents (VBat = -48V)
VCC current, ICC
VBat current, IBat
VCC current, ICC
VBat current, IBat
Open circuit state
1.2
-0.05
2.8
2.0
4.0
mA
mA
mA
mA
-0.1
-1.5
Active state
On-hook, Long Current = 0 mA
-1.1
Power supply rejection ratios
VCC to 2- or 4-wire port
VBat to 2- or 4-wire port
VBat2 to 2- or 4-wire port
Active State
f = 1 kHz Vn = 100mV
30
36
40
42
45
60
dB
dB
dB
Temperature guard
Junction threshold temperature, TJG
Thermal resistance
145
°C
28-pin PLCC, θJP28plcc
24-pin SOIC, θJP24soic
24-pin SSOP, θJP24ssop
39
43
55
°C/W
°C/W
°C/W
6
PBL 386 50/2
R
S
TIPX
VBExt
PBL 386 50/2
RLRTo
RINGX
Figure 7. Tipx voltage.
Notes
1. The overhead voltage can be adjusted with the ROV resistor
for higher levels e.g. min 3.1 VPeak and is specified at the
two-wire port with the signal source at the four-wire
receive port.
5. Pin PTG = Open sets transmit gain to nom. -6.02dB
Pin PTG = AGND sets transmit gain to nom. -12.04 dB
Secondary protection resistors RF and resistors RP impact
the insertion loss as explained in the text, section
Transmission. The specified insertion loss is for RF = RP = 0.
6. The specified insertion loss tolerance does not include
errors caused by external components.
2. The two-wire impedance is programmable by selection of
external component values according to:
ZTRX = ZT/|G2-4S α RSN| where:
7. The level is specified at the two-wire port.
8. The two-wire idle noise is specified with the port
terminated in 600 Ω (RL) and with the four-wire receive
port grounded (ERX = 0; see figure 6).
ZTRX = impedance between the TIPX and RINGX
terminals
ZT = programming network between the VTX and RSN
terminals
The four-wire idle noise at VTX is specified with the two-
wire port terminated in 600 Ω (RL). The noise specification
is referenced to a 600 Ω programmed two-wire impedance
level at VTX. The four-wire receive port is grounded
(ERX = 0).
G2-4S = transmit gain, nominally = 0.5 (or 0.25 see pin
PTG)
α
RSN = receive current gain, nominally = 200 (current
defined as positive flowing into the receivesumm-
ing node, RSN, and when flowing from ring to tip).
9. Previous state must be active - loop or ground key
detector.
10. If |VBExt| ≥ |VBat + 2 V|, where VBat is the voltage at VBAT pin,
the current ILeak is limited to ≈ 5mA.
3. Higher return loss values can be achieved by adding a
reactive component to RT, the two-wire terminating
impedance programming resistance, e.g. by dividing RT
into two equal halves and connecting a capacitor from the
common point to ground.
4. The overhead voltage can be adjusted with the ROV
resistor for higher levels e.g. min 1.6 VPeak and is specified
at the four-wire transmit port, VTX, with the signal source
at the two-wire port. Note that the gain from the two-wire
port to the four-wire transmit port is G2-4S = 0.5 (or 0.25 see
pin PTG). The overhead voltage is dependent on G2-4S and
POV setting.
7
PBL 386 50/2
1
2
24 VTX
PTG
RRLY
HP
23 AGND
3
22
21
20
RSN
REF
PLC
POV
5
6
25
24
23
22
21
20
19
RINGX
BGND
TIPX
NC
RINGX
BGND
TIPX
4
REF
PLC
POV
PLD
VCC
NC
5
24-pin SOIC
and
7
28-pin PLCC
6
24-pin SSOP 19
8
VBAT
VBAT2
PSG
VBAT
VBAT2
PSG
7
18 PLD
17 VCC
16 DET
9
8
10
11
9
NC
10
15
C1
LP
DT
DR
11
12
14 C2
13
C3
Figure 8. Pin configuration, 24-pin SSOP, 24-pin SOIC and 28 pin PLCC package, top view.
Pin Description
Refer to figure 8.
PLCC Symbol Description
1
2
3
PTG
RRLY
HP
Progr.Transmit Gain. Left open transmit gain = -6.02 dB, connected to AGND transmit gain = -12.04 dB.
Ring Relay driver output. The relay coil may be connected to maximum +14V.
Connection for High Pass filter capacitor, CHP. Other end of CHP connects to TIPX.
4
5
NC
RINGX
No internal Connection
The TIPX and RINGX pins connect to the tip and ring leads of the two-wire interface via overvoltage
protection components and ring relay (and optional test relay).
6
7
BGND
TIPX
Battery Ground, should be tied together with AGND.
The TIPX and RINGX pins connect to the tip and ring leads of the two-wire interface via overvoltage
protection components and ring relay (and optional test relay).
8
VBAT
VBAT2
PSG
Battery supply Voltage. Negative with respect to AGND.
An optional second (2) Battery Voltage connects to this pin.
9
10
Programmable Saturation Guard. The resistive part of the DC feed characteristic is programmed by a
resistor connected from this pin to VBAT.
11
12
13
NC
LP
DT
No internal Connection
Connection for Low Pass filter capacitor, CLP. Other end of CLP connects to VBAT.
Input to the ring trip comparator. With DR more positive than DT the detector output, DET, is at logic level
low, indicating off-hook condition. The external ring trip network connects to this input.
14
DR
Input to the ring trip comparator. With DR more positive than DT the detector output, DET, is at logic
level low, indicating off-hook condition. The external ring trip network connects to this input.
8
PBL 386 50/2
15
16
17
C3
C2
C1
C1, C2 and C3 are digital inputs (internal pull-up) controlling the SLIC operating states.
Refer to section "Operating states" for details.
}
18
DET
Detector output. Active low when indicating loop detection and ring trip, active high when indicating
ground key detection.
19
20
21
NC
No internal Connection
VCC
PLD
+5 V power supply.
Programmable Loop Detector threshold. The loop detection threshold is programmed by a resistor
connected from this pin to AGND.
22
23
POV
PLC
Programmable Overhead Voltage. If pin is left open: The overhead voltage is internally set to min 2.7 V in
off-hook and min 1.1 V in On-hook. If a resistor is connected between this pin and AGND: the overhead
voltage can be set to higher values.
Prog. Line Current, the current limit,reference C in figure 13, is programmed by a resistor connected from
this pin to AGND.
24
25
26
REF
NC
A Reference, 49.9 kΩ, resistor should be connected from this pin to AGND.
No internal Connection
RSN
Receive Summing Node. 200 times the AC-current flowing into this pin equals the metallic (transversal)
AC-current flowing from RINGX to TIPX. Programming networks for two-wire impedance and receive gain
connect to the receive summing node. A resistor should be connected from this pin to AGND.
27
28
AGND
VTX
Analog Ground, should be tied together with BGND.
Transmit vf output. The AC voltage difference between TIPX and RINGX, the AC metallic voltage, is
reproduced as an unbalanced GND referenced signal at VTX with a gain of 0.5 (or 0.25, see pin PTG).
The two-wire impedance programming network connects between VTX and RSN.
SLIC Operating States
State
C3
C2
C1
SLIC operating state
Active detector
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Open circuit
Ringing state
Active state
Active state
Tip open state
Active state
-
Ring trip detector (active low)
Loop detector (active low)
Line voltage measurement (note 9)
Loop detector (active low)
Ground key detector (active high)
Loop detector (active low)
Ground key detector (active high)
Active reverse
Active reverse
Table 1. SLIC operating states.
9
PBL 386 50/2
Four-Wire to Two-Wire Gain
From (1), (2) and (3) with EL = 0:
VTR
TIPX
G4−2
=
=
TIP
I
+
L
VRX
R
R
P
F
F
Z
ZT
−
ZL
L
Z
+
TR
VTX
V
ZT
αRSN
TR
ZRX
RHP
G
+
2-4S
+ G2− 4S (ZL + 2RF + 2RP)
-
+
E
-
L
V
TX
R
R
P
-
I
L
RING
-
RINGX
Z
T
For applications where
ZT/(αRSN·G2-4S) + 2RF + 2RP is chosen to
be equal to ZL the expression for G4-2
simplifies to:
Z
RX
ZT
1
RSN
+
V
G4−2 = −
ZRX 2G2− 4S
RX
I /αRSN
L
-
Four-Wire to Four-Wire Gain
From (1), (2) and (3) with EL = 0:
VTX
PBL 386 50/2
G4−4
=
=
Figure 9. Simplified ac transmission circuit.
VRX
ZT
−
G2− 4S (ZL + 2RF + 2RP)
+ G2−4S (ZL + 2RF + 2RP )
Functional Description
and Applications
Information
ZT
αRSN
ZRX
ZT determines the SLIC TIPX to
RINGX impedance at voice
frequencies.
ZRX controls four- to two-wire gain.
VRX is the analog ground referenced
receive signal.
Hybrid Function
The hybrid function can easily be
Transmission
implemented utilizing the uncommitted
amplifier in conventional CODEC/filter
combinations. Please, refer to figure 10.
Via impedance ZB a current proportional
to VRX is injected into the summing node
of the combination CODEC/filter ampli-
fier. As can be seen from the expression
for the four-wire to four-wire gain a
voltage proportional to VRX is returned to
VTX. This voltage is converted by RTX to a
current flowing into the same summing
node. These currents can be made to
αRSN is the receive summing node current
to metallic loop current gain = 200.
General
A simplified ac model of the transmis-
sion circuits is shown in figure 9. Circuit
analysis yields:
Note that the SLICs two-wire to four-
wire gain, G2-4S, is user programmable
between two fix values. Refer to the
VTX
VTR
=
+ IL (2RF + 2RP )
(1)
(2)
datasheets for values on G2-4S.
G2− 4S
VTX VRX
Two-Wire Impedance
IL
+
=
To calculate ZTR, the impedance
presented to the two-wire line by the
SLIC including the fuse and protection
resistors RF and RP, let VRX = 0.
From (1) and (2):
ZT
ZRX
αRSN
cancel by letting:
VTX VRX
VTR = EL - IL · ZL
where:
(3)
+
= 0(EL = 0)
RTX
ZB
The four-wire to four-wire gain, G4-4
includes the required phase shift and
thus the balance network ZB can be
calculated from:
,
ZT
VTX is a ground referenced version of
the ac metallic voltage between the
TIPX and RINGX terminals.
ZTR
=
+ 2RF + 2RP
αRSN G2− 4S
Thus with ZTR, αRSN, G2-4S, RP and RF
known:
G2-4S is the programmable SLIC two-wire
V
RX
to four-wire gain (transmit
direction). See note below.
VTR is the ac metallic voltage between
tip and ring.
EL is the line open circuit ac metallic
voltage.
Z
= −R
=
B
TX
V
TX
ZT = αRSN G2− 4S (ZTR − 2RF − 2RP )
Z
T
+ G
(Z + 2R + 2R )
L F P
2−4S
Z
α
RX
RSN
G
Two-Wire to Four-Wire Gain
R
TX
Z
(Z + 2R + 2R )
L F P
T
2−4S
From (1) and (2) with VRX = 0:
IL
is the ac metallic current.
VTX
VTR
ZT / αRSN
G2− 4
=
=
When choosing RTX, make sure the
output load of the VTX terminal is >20kΩ.
RF is a fuse resistor.
RP is part of the SLIC protection
ZL is the line impedance.
ZT
αRSN G2− 4S
+ 2RF + 2RP
10
PBL 386 50/2
If calculation of the ZB formula above
yields a balance network containing an
inductor, an alternate method is recom-
mended. Contact Ericsson Microelectron-
ics for assistance.
R
FB
R
The PBL 386 50/2 SLIC may also be
used together with programmable
CODEC/filters. The programmable
CODEC/filter allows for system controller
adjustment of hybrid balance to accom-
modate different line impedances without
change of hardware. In addition, the
transmit and receive gain may be
adjusted. Please, refer to the program-
mable CODEC/filter data sheets for
design information.
TX
VTX
V
T
PBL
386 50/2
Z
Z
Combination
CODEC/Filter
V
T
B
Z
RX
RX
RSN
Figure 10. Hybrid function.
Longitudinal Impedance
A feed back loop counteracts longitudi-
nal voltages at the two-wire port by
injecting longitudinal currents in opposing
phase.
AC - DC Separation Capacitor, CHP
ance) forms the total two wire output
impedance of the SLIC. The choise of
these programmable components have
an influence on the power supply
The high pass filter capacitor con-
nected between terminals HP and TIPX
provides the separation of the ac signal
from the dc part. CHP positions the low
end frequency response break point of
the ac loop in the SLIC. Refer to table 1
for recommended values of CHP.
Example: A CHP value of 150 nF will
position the low end frequency response
3dB break point of the ac loop at 1.8 Hz
(f3dB) according to f3dB = 1/(2·π·RHP·CHP)
where RHP = 600 kΩ.
Thus longitudinal disturbances will
appear as longitudinal currents and the
TIPX and RINGX terminals will experi-
ence very small longitudinal voltage
excursions, leaving metallic voltages well
within the SLIC common mode range.
The SLIC longitudinal impedance per
wire, ZLoT and ZLoR, appears as typically
20Ω to longitudinal disturbances. It
should be noted that longitudinal currents
may exceed the dc loop current without
disturbing the vf transmission.
rejection ratio (PSRR) from VBAT to the
two wire side at sub-audio frequencies.
At these frequencies capacitor CLP also
influences the transversal to longitudinal
balance in the SLIC. Table 1 suggests
suitable values on CLP for different
feeding characteristics. Typical values of
the transversal to longitudinal balance
(T-L bal.) at 200Hz is given in table 1 for
the chosen values on CLP.
High-Pass Transmit Filter
The capacitor CTX in figure 12 con-
nected between the VTX output and the
CODEC/filter forms, together with RTX
and/or the input impedance of a pro-
grammable CODEC/filter, a high-pass
RC filter. It is recommended to position
the 3 dB break point of this filter between
30 and 80 Hz to get a faster response for
the dc steps that may occur at DTMF
signalling.
RFeed
RSG
CLP
T-L bal. CHP
@200Hz
Capacitors CTC and CRC
The capacitors designated CTC and CRC
in figure 12, connected between TIPX
and ground as well as between RINGX
and ground, can be used for RFI filtering.
The recommended value for CTC and
CRC is 2200 pF. Higher capacitance
values may be used, but care must be
taken to prevent degradation of either
longitudinal balance or return loss. CTC
and CRC contribute to a metallic imped-
ance of 1/(π·f·CTC) = 1/(π·f·CRC), a TIPX to
ground impedance of 1/(2·π·f·CTC) and a
RINGX to ground impedance of
[Ω]
2·50
2·200 60.4
2·400 147
2·800 301
[kΩ]
0
[nF] [dB]
[nF]
47
150
100
47
-46
-46
-43
-36
150
150
150
22
Table 1. RSG , CLP and CHP values for
different feeding characteristics.
Capacitor CLP
The capacitor CLP, which connects
between the terminals CLP and VBAT,
positions together with the resistive loop
feed resistor RSG (see section Battery
Feed), the high end frequency break
point of the low pass filter in the dc loop
in the SLIC. CLP together with RSG, CHP
and ZT (see section Two-Wire Imped-
1/(2·π·f·CRC).
11
PBL 386 50/2
The current limit (reference C in figure
13) is adjusted by connecting a resistor,
RLC, between terminal PLC and ground
according to the equation:
receive output via the resistor RRX, is dc
biased with +1.25V. This makes it
possible to compensate for currents
floating due to dc voltage differences
between RSN and the CODEC output
without using any capacitors. This is
done by connecting a resistor RR be-
tween the RSN terminal and ground.
With current directions defined as in
figure 14, current summation gives:
Battery Feed
The PBL 386 50/2 SLIC emulate
resistive loop feed, programmable
between 2·50Ω and 2·900 Ω, with
adjustable current limitation. In the
current limited region the loop current
has a slight slope corresponding to
2·30 kΩ, see figure 13 reference B.
The open loop voltage measured
between the TIPX and RINGX terminals
is tracking the battery voltage VBat. The
signalling headroom, or overhead voltage
1000
LProg + 4
RLC
=
I
where RLC is in kΩ for ILProg in mA.
A second, lower battery voltage may be
connected to the device at terminal
VBAT2 to reduce short loop power
dissipation. The SLIC automatically
switches between the two battery supply
voltages without need for external
control. The silent battery switching
occurs when the line voltage passes the
value |VB2| - 40·IL - (VOHVirt -1.3),
if IL > 6 mA.
For correct functionality it is important
to connect the terminal VBAT2 to the
second power supply via the diode DVB2
in figure 12.
An optional diode DBB connected
between terminal VB and the VB2 power
supply, see figure 12, will make sure that
the SLIC continues to work on the
second battery even if the first battery
voltage disappears.
−IRSN = IRT + IRRX + IRR
=
1,25 1,25 − VCODEC
1,25
RR
VTRO, is programmable with a resistor ROV
+
+
RT
RRX
connected between terminal POV on the
SLIC and ground. Please refer to section
“Programmable overhead voltage(POV)”.
The battery voltage overhead, VOH
depends on the programmed signal
overhead voltage VTRO. VOH defines the
TIP to RING voltage at open loop
conditions according to VTR(at IL = 0 mA)
where VCODEC is the reference voltage of
the CODEC at the receive output.
From this equation the resistor RR can be
calculated as
,
1,25
RR
=
= |VBat| - VOH
.
1,25 − VCODEC
1,25
RT
−IRSN
−
−
Refer to table 2 for typical values on
VOH and VOHVirt. The overhead voltage is
changed when the line current is ap-
proaching open loop conditions. To
ensure maximum open loop voltage,
even with a leaking telephone line, this
occurs at a line current of approximately
6 mA. When the overhead voltage has
changed, the line voltage is kept nearly
constant with a steep slope correspond-
ing to 2·25 Ω(reference G in figure 13).
The virtual battery overhead, VOHVirt, is
defined as the difference between the
battery voltage and the crossing point of
all possible resistive feeding slopes, see
figure 13 reference J. The virtual battery
overhead is a theoretical constant
RRX
For values on IRSN, see table 3.
The resistor RR has no influence on the
ac transmission.
If a second battery voltage is not used,
VBAT2 is connected to VBAT on the
SLIC and CVB2, DBB and DVB2 are removed.
SLIC
IRSN [µA]
PBL 386 50/2
-155
Metering applications
For designs with metering applications
please contact Ericsson Microelectronics
for assistance.
Table 3. The SLIC internal bias current
with the direction of the current defined
as positive when floating into the terminal
RSN.
CODEC Receive Interface
Programmable overhead voltage(POV)
The PBL 386 50/2 SLIC have got a
completely new receive interface at the
four wire side which makes it possible to
reduce the number of capacitors in the
applications and to fit both single and
dual battery feed CODECs. The RSN
terminal, connecting to the CODEC
needed to be able to calculate the
feeding characteristics.
With the POV function the overhead
voltage can be increased.
If the POV pin is left open the overhead
voltage is internally set to 3.2 VPeak in off-
SLIC
VOH(typ)
[V]
VOHVirt(typ)
[V]
PBL 386 50/2 3.0 +VTRO 4.9 +VTRO
12
11
10
9
Table 2. Battery overhead.
8
off-hook
on-hook
7
6
5
4
3
2
The resistive loop feed (reference D in
figure 13) is programmed by connecting
a resistor, RSG, between terminals PSG
and VBAT according to the equation:
1
0
RSG + 2·104
RFeed
=
+ 2RF
0
10
20
30
40
50
60
200
R
ov
(KΩ)
where RFeed is in Ω for RSG and RF in Ω.
Figure 11. Programmable overhead voltage (POV). RL = 600 Ω or ∞.
12
PBL 386 50/2
hook and 1.3 VPeak on-hook. If a resistor
ROV is connected between the POV pin
and AGND, the overhead voltage can be
set to higher values, typical values can
be seen in figure 11. The ROV and
corresponding VTRO (signal headroom)
are typical values for THD <1% and the
signal frequency 1000Hz.
Observe that the 4-wire output terminal
VTX can not handle more than 3.2 VPeak. So
if the gain 2-wire to 4-wire is -6.02dB,
6.4 VPeak is maximum also for the 2-wire
side. Signal levels between 6.4 and
12.8 VPeak on the 2-wire side can be han-
dled with the PTG shorted so that the gain
G2-4S become -12.04dB. Please note that
the 2-wire impedance, RR and the 4-wire to
4-wire gain has to be recalculated if the
PTG is shorted.
Please note that the maximum signal
current at the 2-wire side can not be
greater than 29 mA.
Analog Temperature Guard
The widely varying environmental
conditions in which SLICs operate may
lead to the chip temperature limitations
being exceeded. The PBL 386 50/2 SLIC
reduce the dc line current when the chip
temperature reaches approximately
145°C and increases it again automati-
cally when the temperature drops.
Accordingly transmission is not lost
under high ambient temperature condi-
tions.
How to use POV:
1. Decide what overhead voltage(VTRO) is
needed. The POV function is only
needediftheoverheadvoltageexceeds
3.2 VPeak
2. In figure 11 the corresponding ROV for
the decided VTRO can be found.
3. If the overhead voltage exceeds
6.4 VPeak , the G2-4S gain has to be
changed to -12.04dB by connecting
the PTG pin to AGND. Please note
that the two-wire impedance, RR and
the 4-wire to 4-wire gain has to be
recalculated.
The detector output, DET, is forced to a
logic low level when the temperature
guard is active.
RFB
PBL 386 50/2
CTX
RTX
KR
-
PTG
VTX
-
0
+
+
RT
RRLY
HP
AGND
RSN
NC
RB
+12 V /+5V
RRX
0
CGG
DHP
CHP
NC
CODEC/
Filter
RF2
RR
RP2
RING
TIP
RINGX
BGND
TIPX
VBAT
VBAT2
PSG
NC
REF
PLC
POV
PLD
VCC
NC
RREF
RLC
ROV
RLD
CRC
CTC
VB
OVP
RF1
RP1
PBL 386 50/2
DVB2
VB2
VB
VCC
VCC
DBB
RSG
CVB2
DVB
CVCC
DET
C1
CLP
ERG
CVB
R1
LP
RRT
DT
C2
R2
DR
C3
C1
C2
SYSTEM CONTROL
INTERFACE
R3
R4
SLIC No. 2 etc.
RESISTORS: (Values according to IEC E96 series)
CAPACITORS: (Values according to IEC E96 series)
OVP:
RSG
RLD
ROV
RLC
RREF
RR
= 0 Ω
1% 1/10 W
1% 1/10 W
CVB
CVB2
CVCC
CTC
CRC
CHP
CLP
CTX
CGG
C1
= 100 nF
= 150 nF
= 100 nF
= 2.2 nF
= 2.2 nF
= 47 nF
100 V 10%
100 V 10%
10 V 10%
100 V 10%
100 V 10%
100 V 10%
100 V 10%
10 V 10%
100 V 10%
63 V 10%
63 V 10%
Secondary protection ( e.g. Power
Innovations TISPPBL2). The ground
terminals of the secondary protection should
be connected to the common ground on the
Printed Board Assembly with a track as
short and wide as possible, preferable a
groundplane.
= 49.9 kΩ
= User programmable
= 32.4 kΩ
= 49.9 kΩ
= 11.5 kΩ
= 52.3 kΩ
= 32.4 kΩ
= 57.6 kΩ
= 52.3 kΩ
1% 1/10 W
1% 1/10 W
1% 1/10 W
1% 1/10 W
1% 1/10 W
1% 1/10 W
1% 1/10 W
RT
= 150 nF
= 68 nF
NOTES:
RTX
RB
1. RP1 and RP2 may be omitted if DVB is in
place.
= 220 nF
= 330 nF
= 330 nF
RRX
RFB
R1
2. It is required to connect DHP between
terminal HP and ground if CHP >47nF.
Depending on CODEC / filter
C2
= 604 kΩ
= 604 kΩ
= 249 kΩ
= 280 kΩ
= 330 Ω
≥ 10 Ω
1% 1/10 W
1% 1/10 W
1% 1/10 W
1% 1/10 W
5% 2 W
DIODES:
DVB
R2
= 1N4448
= 1N4448
= 1N4448
R3
DVB2
R4
DBB
RRT
RP1, RP2
RF1, RF2
DHP
= 1N4448 (Note 2)
1% 1/10 W (Note 1)
= Line resistor, 40 Ω 1% match
Figure 12. Single-channel subscriber line interface with PBL 386 50/2 and combination CODEC/filter.
13
PBL 386 50/2
DC characteristics
A
A
B
C
B
C
D
D
E
G
F
F
H
J
VTR [V]
|VBat| - VOHVirt - RFeed · (ILProg + 4·10-3)
E:
F:
G:
H:
J:
IL ≈ 6 mA
Apparent battery VBat(@ IL = 0) =|VBat| - VOHVirt - (RFeed · 4·10-3)
feedG = 2 · 25 Ω
A:
IL (@ VTR = 0V) = ILProg +
60 · 103
B:
C:
RfeedB = 2 · 30 kΩ
R
103
ILConst(typ) = ILProg
=
- 4·10-3
RLC
VTROpen = |VBat| - VOH
VTR = |VBat| - VOHVirt - RFeed · (ILProg + 4·10-3)
Virtual battery VBatVirt (@ IL = 4 mA) = |VBat| - VOHVirt
RSG + 2 · 104
D:
RFeed =
200
Figure 13. Battery feed characteristics (without the protection resistors on the line).
Loop Monitoring Functions
and is calculated according to
Ring Trip Detector
500
Ring trip detection is accomplished by
connecting an external network to a
comparator in the SLIC with inputs DT
and DR. The ringing source can be
balanced or unbalanced superimposed
on VB or GND. The unbalanced ringing
source may be applied to either the ring
lead or the tip lead with return via the
other wire. A ring relay driven by the
SLIC ring relay driver connects the
ringing source to tip and ring.
The ring trip function is based on a
polarity change at the comparator input
when the line goes off-hook. In the on-
hook state no dc current flows through
the loop and the voltage at comparator
input DT is more positive than the
voltage at input DR. When the line goes
off-hook, while the ring relay is ener-
The loop current, ground key and ring
trip detectors report their status through a
common output, DET. The detector to be
connected to DET is selected via the
three bit wide control interface C1, C2
and C3. Please refer to section Control
Inputs for a description of the control
interface.
RLD
=
ILTh
The current detector is internally filtered
and is not influenced by the ac signal at
the two wire side.
Ground Key Detector
The ground key detector is indicating
when the ground key is pressed (active)
by putting the output pin DET to a logical
high level when selected. The ground
key detector circuit senses the difference
in TIPX and RINGX currents. When the
current at the RINGX side exceeds the
current at the TIPX side with the thresh-
old value the detector is triggered. For
threshold current values, please refer to
the datasheet.
Loop Current Detector
The loop current detector is indicating
that the telephone is off hook and that
current is flowing in the loop by putting
the output DET to a logical low level
when selected. The loop current thresh-
old value, ILTh, at which the loop current
detector changes state is programmable
by selecting the value of resistor RLD. RLD
connects between pin PLD and ground
14
PBL 386 50/2
gized, dc current flows and the compara-
tor input voltage reverses polarity.
Figure 12 gives an example of a ring
trip detection network. This network is
applicable, when the ring voltage is
superimposed on VB and is injected on
the ring lead of the two-wire port. The dc
voltage across sense resistor RRT is
monitored by the ring trip comparator
input DT and DR via the network R1, R2,
R3, R4, C1 and C2. With the line on-hook
(no dc current) DT is more positive than
DR and the DET output will report logic
level high, i.e. the detector is not tripped.
When the line goes off-hook, while
ringing, a dc current will flow through the
loop including sense resistor RRT and will
cause input DT to become more negative
than input DR. This changes output DET
to logic level low, i.e. tripped detector
condition. The system controller (or line
card processor) responds by de-energiz-
ing the ring relay, i.e. ring trip.
VTX
PBL386 50/2
CODEC
DC-GND
RT
I
IRT
IRSN
IRRX
RRX
_
RSN
+
IRR
+1.25 V
UREFcodec
RR
Figure 14. CODEC receive interface.
and the programmed dc characteristic,
with the longitudinal current compensa-
tion (see section Longitudinal Imped-
ance) not active, to the line on the
RINGX pin.
Ringing State
The ring relay driver and the ring trip
detector are activated and the ring trip
detector is indicating off hook with a logic
low level at the detector output.
Complete filtering of the 20 Hz ac
component at terminal DT and DR is not
necessary. A toggling DET output can be
examined by a software routine to
determine the duty cycle. When the DET
output is at logic level low for more than
half the time, off-hook condition is
The loop current detector is active.
The SLIC is in the active normal state.
Active Polarity Reversal State
Active States
TIPX and RINGX polarity is reversed
from the Active State: RINGX is the
terminal closest to ground and sources
loop current while TIPX is the more
negative terminal and sinks current. Vf
signal transmission is normal. The loop
current or the ground key detector is
activated. The loop current detector is
indicating off hook with a logic low level
and the ground key detector is indicating
active ground key with a logic high level
present at the detector output.
TIPX is the terminal closest to ground
and sources loop current while RINGX is
the more negative terminal and sinks
loop current. Vf signal transmission is
normal. The loop current or the ground
key detector is activated. The loop
current detector is indicating off hook
with a logic low level and the ground key
detector is indicating active ground key
with a logic high level present at the
detector output.
In PBL 386 50/2 a line voltage meas-
urement feature is available in the active
state, which may be used for line length
estimations or for line test purposes. The
line voltage is presented on the detector
output as a pulse at logic high level with
a pulsewidth of 5.5 µs/V. To start the line
voltage measurement this mode has to
be entered from the Active State with the
loop or ground key detector active. The
pulse presented at the DET output
proportional to the line voltage starts
when entering the line voltage measuring
mode.
indicated.
Relay driver
The PBL 386 50/2 SLIC incorporates a
ring relay driver designed as open
collector (npn) with a current sinking
capability of 50mA. The drive transistor
emitter is connected to BGND. The relay
driver has an internal zener diode clamp
for inductive kickback voltages. Care
must be taken when using the relay
driver together with relays that have high
impedance.
Overvoltage Protection
The PBL 386 50/2 SLIC must be
protected against overvoltages on the
telephone line caused by lightning, ac
power contact and induction. Refer to
Maximum Ratings, TIPX and RINGX
terminals, for maximum allowable
continuous and transient currents that
may be applied to the SLIC.
Control Inputs
The PBL 386 50/2 SLIC have three
digital control inputs, C1, C2 and C3.
A decoder in the SLIC interprets the
control input condition and sets up the
commanded operating state.
C1 to C3 are internal pull-up inputs.
Open Circuit State
Secondary Protection
In the Open Circuit State the TIPX and
RINGX line drive amplifiers as well as
other circuit blocks are powered down.
This causes the SLIC to present a high
impedance to the line. Power dissipation
is at a minimum and no detectors are
active.
The circuit shown in figure 12 utilizes
series resistors together with a
programmable overvoltage protector
(e.g. PowerInnovations TISPPBL2),
serving as a secondary protection.
Tip Open State
Tip Open State is used for ground start
signalling.
In this state the SLICs present a high
impedance to the line on the TIPX pin
15
PBL 386 50/2
needed to carry enough charge to supply
a high enough current to quickly turn on
the thyristor in the protector. CGG shall be
placed close to the overvoltage
protection device. Without the capacitor
even the low inductance in the track to
the VBat supply will limit the current and
delay the activation of the thyristor
clamp.
The fuse resistors RF serve the dual
purposes of being non- destructive
energy dissipators, when transients are
clamped and of being fuses, when the
line is exposed to a power cross.
If a PTC is choosen for RF, note that it
is important to always use PTC´s in
series with resistors not sensitive to
temperature, as the PTC will act as a
capacitance for fast transients and
therefore will not protect the SLIC.
The TISPPBL2 is a dual forward-
conducting buffered p-gate overvoltage
protector. The protector gate references
the protection (clamping) voltage to
negative supply voltage (i e the battery
voltage, VB ). As the protection voltage
will track the negative supply voltage the
overvoltage stress on the SLIC is
minimized.
Power-up Sequence
No special power-up sequence is
necessary except that ground has to be
present before all power supply voltages.
Printed Circuit Board Layout
Care in PCB layout is essential for
proper function. The components
connecting to the RSN input should be
placed in close proximity to that pin, so
that no interference is injected into the
RSN pin. Ground plane surrounding the
RSN pin is advisable.
Analog ground (AGND) should be
connected to battery ground (BGND) on
the PCB in one point.
Positive overvoltages are clamped to
ground by a diode. Negative
overvoltages are initially clamped close
to the SLIC negative supply rail voltage
and the protector will crowbar into a low
voltage on-state condition, by firing an
internal thyristor.
A gate decoupling capacitor, CGG, is
The capacitors for the battery should
be connected with short wide leads of the
same length.
Ordering Information
Package
Temp. Range
Part No.
24 pin SSOP Tape & Reel 0° - +70° C PBL 386 50/2SHT
24 pin SOIC Tube 0° - +70° C PBL 386 50/2SOS
24 pin SOIC Tape & Reel 0° - +70° C PBL 386 50/2SOT
28 pin PLCC Tube 0° - +70° C PBL 386 50/2QNS
28 pin PLCC Tape & Reel 0° - +70° C PBL 386 50/2QNT
Information given in this data sheet is believed to be
accurate and reliable. However no responsibility is
assumed for the consequences of its use nor for any
infringement of patents or other rights of third parties
which may result from its use. No license is granted
by implication or otherwise under any patent or
patent rights of Ericsson Microelectronics. These
products are sold only according to Ericsson
Microelectronics' general conditions of sale, unless
otherwise confirmed in writing.
Specifications subject to change without
notice.
1522-PBL 386 50/2 Uen Rev. A
© Ericsson Microelectronics AB 1999
This product is an original Ericsson
product protected by US, European and
other patents.
Ericsson Microelectronics AB
SE-164 81 Kista-Stockholm, Sweden
Telephone: +46 8 757 50 00
16
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