EM421M3284LBA-75FE [EOREX]
512Mb (4M】4Bank】32) Double DATA RATE SDRAM; 512MB （ 4M 】 4Bank 】 32 ），双倍数据速率SDRAM
| 型号： | EM421M3284LBA-75FE |
| 厂家： | 
EOREX CORPORATION |
| 描述： | 512Mb (4M】4Bank】32) Double DATA RATE SDRAM |
| 文件： | 总20页 (文件大小：1000K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
eorex
EM42AM3284LBA
512Mb (4M×4Bank×32)
Double DATA RATE SDRAM
Features
Description
• Internal Double-Date-Rate architecture with 2
Accesses per clock cycle.
• 1.8V ±0.1V VDD/VDDQ
• 1.8V LV-COMS compatible I/O
• Burst Length (B/L) of 2, 4, 8, 16
The EM42AM3284LBA is high speed Synchronous
graphic RAM fabricated with ultra high performance
CMOS process containing 536,870,912 bits which
organized as 4Meg words x 4 banks by 32 bits.
The 512Mb DDR SDRAM uses a double data rate
architecture to accomplish high-speed operation.
The data path internally prefetches multiple bits and
It transfers the datafor both rising and falling edges
of the system clock.It means the doubled data
bandwidth can be achieved at the I/O pins.
• 3 Clock read latency
• Bi-directional,intermittent data strobe(DQS)
• All inputs except data and DM are sampled
at the positive edge of the system clock.
• Data Mask (DM) for write data
• Sequential & Interleaved Burst type available
• Auto Precharge option for each burst accesses
• DQS edge-aligned with data for Read cycles
• DQS center-aligned with data for Write cycles
• No DLL;CK to DQS is not synchronized
• Deep power down mode
Available packages:TFBGA-90B(13mmx11mm).
• Partial Array Self-Refresh(PASR)
• Auto Temperature Compensated Self-Refresh
(TCSR) by built-in temperature sensor
• Auto Refresh and Self Refresh
• 8,192 Refresh Cycles / 64ms
Ordering Information
Part No
Organization
Max. Freq
Package
Grade
Pb
EM42AM3284LBA-75F
16M X 32
133MHz/DDR266 @CL3 TFBGA-90B Commercial Free
* EOREX reserves the right to change products or specification without notice.
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EM42AM3284LBA
Pin Assignment
1
2
3
7
8
9
VSS
DQ31
DQ29
DQ27
DQ25
DQS3
DM3
VSSQ
A
B
C
D
E
F
VDDQ
DQ16
DQ18
DQ20
DQ22
DQS2
DM2
/CAS
BA0
VDD
VDDQ
VSSQ
VDDQ
VSSQ
VDD
DQ30
DQ28
DQ26
DQ24
NC
DQ17
DQ19
DQ21
DQ23
NC
VSSQ
VDDQ
VSSQ
VDDQ
VSS
CKE
CLK
/CLK
A12
G
H
J
/WE
/RAS
BA1
A9
A11
/CS
A6
A7
A8
A10
A0
A1
A4
DM1
A5
K
L
A2
DM0
DQS0
DQ6
A3
VSSQ
VDDQ
VSSQ
VDDQ
VSS
DQS1
DQ9
DQ8
DQ10
DQ12
DQ14
VSSQ
DQ7
DQ5
DQ3
DQ1
VDDQ
VDDQ
VSSQ
VDDQ
VSSQ
VDD
M
N
P
R
DQ11
DQ13
DQ15
DQ4
DQ2
DQ0
90ball TFBGA / (13mm x 11mm x 1.2mm)
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EM42AM3284LBA
Pin Description (Simplified)
Pin
Name
Function
(System Clock)
Clock input active on the Positive rising edge except for DQ and
DM are active on both edge of the DQS.
CLK and /CLK are differential clock inputs.
(Chip Select)
G2,G3
CLK,/CLK
/CS enables the command decoder when ”L” and disable the
command decoder when “H”.The new command are over-
Looked when the command decoder is disabled but previous
operation will still continue.
H7
G1
/CS
(Clock Enable)
Activates the CLK when “H” and deactivates when “L”.
When deactivate the clock,CKE low signifies the power down or
self refresh mode.
CKE
(Address)
J8,J9,K7,K9,K1,
K3,J1~J3,H1~H3,
Row address (A0 to A12) and Calumn address (CA0 to CA8) are
multiplexed on the same pin.
A0~12
CA10 defines auto precharge at Calumn address.
(Bank Address)
Selects which bank is to be active.
H8,H9
G9
BA0, BA1
/RAS
(Row Address Strobe)
Latches Row Addresses on the positive rising edge of the CLK with
/RAS “L”. Enables row access & pre-charge.
(Column Address Strobe)
G8
/CAS
Latches Column Addresses on the positive rising edge of the CLK
with /CAS low. Enables column access.
(Write Enable)
G7
/WE
Latches Column Addresses on the positive rising edge of the CLK
with /CAS low. Enables column access.
(Data Input/Output)
Data Inputs and Outputs are synchronized with both edge of DQS.
(Data Input/Output Mask)
L8,L2,E8,E2
K8,K2,F8,F2
DQS0~3
DM0~3
DM controls data inputs.DM0 corresponds to the data on
DQ0~DQ7.DM1 corresponds to the data on DQ8~DQ15……..
R8,P7,P8,N7,N8,M7,
M8,L7,L3,M2,M3,N2,
N3,P2,P3,R2,A8,B7,
B8,C7,C8,D7,D8,E7,
E3,D2,D3,C2,C3,B2,
B3,A2
(Data Input/Output)
Data inputs and outputs are multiplexed on the same pin.
DQ0~31
VDD/VSS
A9,F1,R9/
A1,F9,R1
(Power Supply/Ground)
VDD and VSS are power supply pins for internal circuits.
A7,B1,C9,D1,E9,L9,
M1,N9,P1,R7/A3,B9,
C1,D9,E1,L1,M9,N1,
P9,R3
(Power Supply/Ground)
VDDQ and VSSQ are power supply pins for the output buffers.
VDDQ/VSSQ
(No Connection/Reserved for Future Use)
This pin is recommended to be left No Connection on the device.
F3,F7
NC/RFU
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EM42AM3284LBA
Absolute Maximum Rating
Symbol
Item
Input, Output Voltage
Rating
Units
V
VIN, VOUT
VDD, VDDQ
-0.5 ~ +2.3
-0.5 ~ +2.3
Power Supply Voltage
V
Commercial
Extended
0 ~ +70
-25 ~ +85
TOP
Operating Temperature Range
°C
TSTG
PD
Storage Temperature Range
Power Dissipation
-55 ~ +125
°C
W
1
IOS
Short Circuit Current
50
mA
Note: Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could
cause permanent damage. The device is not meant to be operated under conditions outside the
limits described in the operational section of this specification. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability.
Capacitance (VCC=1.8V ± 0.1V, f=1MHz, TA=25°C)
Symbol
CCLK
Parameter
Clock Capacitance
Min.
2.0
Typ.
Max.
4.5
Units
pF
Input Capacitance for CLK, CKE, Address,
/CS, /RAS, /CAS, /WE, DQML, DQMU
CI
2.0
3.5
4.5
6.0
pF
pF
CO
Input/Output Capacitance
Recommended DC Operating Conditions (TA=0°C ~70°C)
Symbol
VDD
Parameter
Power Supply Voltage
Min.
1.7
Typ.
1.8
Max.
1.9
Units
V
VDDQ
VIH
Power Supply Voltage (for I/O Buffer)
Input Logic High Voltage
1.7
1.8
1.9
V
0.8* VDDQ
-0.3
VDDQ+0.3
0.2*VDDQ
V
VIL
Input Logic Low Voltage
V
Note: * All voltages referred to VSS.
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EM42AM3284LBA
Recommended DC Operating Conditions
(VDD=1.8V±0.1V, TA=0°C ~ 70°C)
Max.
Symbol
IDD1
Parameter
Test Conditions
Units
mA
-75
Burst length=2,
tRC≥tRC(min.), IOL=0mA,
One bank active
Operating Current (Note 1)
80
Precharge Standby Current in
Power Down Mode
IDD2P
1
4
mA
CKE≤VIL(max.), tCK=min
CKE≥VIL(min.), tCK=min,
/CS≥VIH(min.)
Input signals are changed one time
during 2 clks
Precharge Standby Current in
Non-power Down Mode
IDD2N
IDD3P
IDD3N
IDD4
mA
mA
mA
mA
Active Standby Current in
Power Down Mode
3
CKE≤VIL(max.), tCK=min
CKE≥VIH(min.), tCK=min,
/CS≥VIH(min.)
Input signals are changed one time
during 2 clks
Active Standby Current in
Non-power Down Mode
10
Operating Current (Burst
Mode) (Note 2)
tCK ≥ tCK(min.), IOL=0mA,
All banks active
120
Refresh Current (Note 3)
IDD5
IDD6
90
mA
mA
tRC≥ tRFC (min.), All banks active
CKE≤0.2V
Self Refresh Current
0.8
*All voltages referenced to VSS.
Note 1: IDD1 depends on output loading and cycle rates.
Specified values are obtained with the output open.
Input signals are changed only one time during tCK (min.)
Note 2: IDD4 depends on output loading and cycle rates.
Specified values are obtained with the output open.
Input signals are changed only one time during tCK (min.)
Note 3: Min. of tRFC (Auto refresh Row Cycle Times) is shown at AC Characteristics.
Recommended DC Operating Conditions (Continued)
Symbol
IIL
Parameter
Test Conditions
Min.
-2
Typ.
Max.
+2
Units
0≤VI≤VDDQ, VDDQ=VDD
All other pins not under
test=0V
Input Leakage Current
Output Leakage Current
uA
IOL
VOH
VOL
-1.5
+1.5
uA
V
0≤VO≤VDDQ, DOUT is disabled
High Level Output Voltage IO=-0.1mA
Low Level Output Voltage IO=+0.1mA
0.9*VDDQ
0.1*VDDQ
V
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EM42AM3284LBA
Block Diagram
Auto/Self
Refresh Counter
A0
A1
DM
A2
A3
A4
Memory
Array
A5
Write DQM
Control
A6
A7
A8
Data In
A9
DOi
S/ A &I/ O Gating
Col. Decoder
A10
A11
A12
BA0
BA1
Data Out
Col. Add. Buffer
Mode Register Set
Col Add. Counter
Burst Counter
Timing Register
CLK
CKE
/CS
/RAS
/CAS
/WE
/CLK
DM
DQS
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EM42AM3284LBA
AC Operating Test Conditions
(VDD=1.8V ± 0.1V, TA=0°C ~70°C)
Item
Conditions
0.9V/0.9V
Output Reference Level
Output Load
See diagram as below
1.6V/0.2V
Input Signal Level
Transition Time of Input Signals
Input Reference Level
0.5ns
0.9V
AC Operating Test Characteristics
(VDD=1.8V±0.1V, TA=0°C ~70°C)
-7.5
7.5
Symbol
Parameter
Units
Min.
2
Max.
tDQCK
tDQSCK
tCL,tCH
DQ output access from CLK,/CLK
DQS output access from CLK,/CLK
CL low/high level width
6
6
ns
ns
tCK
2
0.45
0.55
tCK
Clock Cycle Time
ns
tDH,tDS
tDIPW
DQ and DM hold/setup time
0.8
ns
ns
DQ and DM input pulse width for
each input
1.75
Data out high/low impedance time
from CLK,/CLK
DQS-DQ skew for associated DQ
signal
Write command to first latching DQS
transition
tHZ,tLZ
tDQSQ
1
6
ns
ns
0.6
1.25
tDQSS
tDSL,tDSH
tMRD
0.75
0.2
2
tCK
tCK
tCK
DQS input valid window
Mode Register Set command cycle
time
tWPRES
tWPST
tIH,tIS
tRPRE
Write Preamble setup time
Write Preamble
0
ns
0.4
0.9
0.6
1.1
tCK
Address/control input hold/setup
time
1.3
ns
Read Preamble
tCK
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EM42AM3284LBA
AC Operating Test Characteristics (Continued)
(VDD=1.8V±0.1V, TA=0°C ~70°C)
-75
Units
Symbol
Parameter
Read Postamble
Min.
0.4
Max.
0.6
tRPST
tRAS
tCK
ns
Active to Precharge command period
45
120k
tRC
tRFC
tRCD
tRP
Active to Active command period
Auto Refresh Row Cycle Time
Active to Read or Write delay
Precharge command period
75
108
30
ns
ns
ns
ns
22.5
tRRD
tCCD
Active bank A to B command period
15
ns
Column address to column address
delay
1
tCK
tHZP
tCDLW
tDPL
Pre-charge command to high-Z
Last data in to Write command
Last data in to Precharge command
3
1
3
tCK
tCK
tCK
tSREX
tWTR
Exit self refresh to non-col. command
Internal Write to Read command delay
16
1
tCK
tCK
tCKE
tWPD
tRPD
CKE minimum pulse width
2
tCK
tCK
tCK
tCK
tCK
tCK
us
Write to pre-charge delay(same bank) 3+BL/2
Read to pre-charge delay(same bank)
Write to Read command delay
Burst stop to write delay
BL/2
tWRD
tBSTW
tWRD
tREFI
2+BL/2
3
2
Write recovery
Average periodic refresh interval
7.8
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EM42AM3284LBA
Simplified State Diagram
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EM42AM3284LBA
1. Command Truth Table
CKE
n-1
BA0,
BA1
Command
Symbol
/CS /RAS /CAS /WE
A10 A12~A0
n
X
X
X
X
X
X
X
X
X
X
X
Ignore Command
No Operation
Burst Stop
DESL
NOP
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
X
H
H
H
H
H
L
X
H
H
L
X
H
L
X
X
X
X
L
X
X
X
V
V
V
V
V
X
X
V
X
BSTH
READ
X
Read
H
H
L
V
Read with Auto Pre-charge READA
Write WRIT
Write with Auto Pre-charge WRITA
L
V
H
L
L
V
H
H
H
H
L
H
H
L
V
H
V
L
Bank Activate
ACT
PRE
PALL
MRS
L
V
Pre-charge Select Bank
Pre-charge All Banks
Mode Register Set
L
V
L
L
X
H
L
L
L
L
H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input
2. CKE Truth Table
CKE
Item
Command
Symbol
/CS /RAS /CAS /WE Addr.
n-1
H
n
H
L
Idle
Idle
CBR Refresh Command
Self Refresh Entry
REF
L
L
L
L
L
L
H
H
H
X
X
X
X
X
X
X
X
X
SELF
H
L
H
H
L
L
H
X
X
X
H
X
X
X
Self Refresh
Self Refresh Exit
L
H
L
H
X
X
Idle
Power Down Entry
Power Down Exit
Power Down
H
Remark H = High level, L = Low level, X = High or Low level (Don't care)
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EM42AM3284LBA
3. Operative Command Table
Current
State
/CS /R /C /W
Addr.
Command
Action
H
L
L
L
X
H
H
H
X
H
H
L
X
H
L
X
X
X
DESL
NOP
NOP
NOP
NOP
TERM
ILLEGAL (Note 1)
Bank active,Latch RA
NOP(Note 3)
X
BA/CA/A10 READ/WRIT/BW
Idle
L
L
L
L
L
L
H
H
L
H
L
BA/RA
BA, A10
X
ACT
PRE/PREA
REFA
Auto refresh(Note 4)
H
Op-Code,
Mode-Add
L
L
L
L
MRS
Mode register
H
L
X
H
X
H
X
H
X
X
DESL
NOP
NOP
NOP
Begin read,Latch CA,
Determine auto-precharge
Begin write,Latch CA,
L
L
H
H
H
L
L
L
BA/CA/A10
BA/CA/A10
READ/READA
WRIT/WRITA
Row
Determine auto-precharge
Active
ILLEGAL (Note 1)
Precharge/Precharge all
ILLEGAL
L
L
L
L
L
L
H
H
L
H
L
BA/RA
BA/A10
X
ACT
PRE/PREA
REFA
H
Op-Code,
Mode-Add
L
L
L
L
MRS
ILLEGAL
H
L
L
X
H
H
X
H
H
X
H
L
X
X
X
DESL
NOP
TERM
NOP(Continue burst to end)
NOP(Continue burst to end)
Terminal burst
Terminate burst,Latch CA,
Begin new read,
L
H
L
H
H
BA/CA/A10
READ/READA
Read
Determine Auto-precharge
ILLEGAL (Note 1)
L
L
H
BA/RA
ACT
L
L
L
L
H
L
L
BA, A10
PRE/PREA
REFA
Terminate burst, PrecharE
ILLEGAL
H
X
Op-Code,
Mode-Add
L
L
L
L
MRS
ILLEGAL
H
L
L
X
H
H
X
H
H
X
H
L
X
X
X
DESL
NOP
TERM
NOP(Continue burst to end)
NOP(Continue burst to end)
ILLEGAL
Terminate burst with DM=”H”,Latch
CA,Begin read,Determine
auto-precharge (Note 2)
L
L
H
H
L
L
H
L
BA/CA/A10
BA/CA/A10
READ/READA
WRIT/WRITA
Terminate burst,Latch CA,Begin
new write, Determine
auto-precharge (Note 2)
ILLEGAL (Note 1)
Write
L
L
L
L
H
H
H
L
BA/RA
ACT
Terminate burst with DM=”H”,
BA, A10
PRE/PREA
Precharge
ILLEGAL
ILLEGAL
L
L
L
L
L
L
H
L
X
REFA
MRS
Op-Code,
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EM42AM3284LBA
3. Operative Command Table (Continued)
Current
State
/CS /R /C /W
Addr.
Command
Action
H
L
L
X
H
H
X
H
H
X
H
L
X
X
DESL
NOP
TERM
NOP(Continue burst to end)
NOP(Continue burst to end)
ILLEGAL
BA/CA/A10
ILLEGAL (Note 1)
ILLEGAL (Note 1)
L
L
H
L
L
X
H
BA/RA
BA/A10
X
READ/WRITE
ACT
Read with
AP
H
ILLEGAL (Note 1)
ILLEGAL
L
L
L
L
H
L
L
PRE/PREA
REFA
H
X
Op-Code,
Mode-Add
L
L
L
L
MRS
ILLEGAL
H
L
L
X
H
H
X
H
H
X
H
L
X
X
X
DESL
NOP
TERM
NOP(Continue burst to end)
NOP(Continue burst to end)
ILLEGAL
ILLEGAL (Note 1)
ILLEGAL (Note 1)
L
L
H
L
L
X
H
BA/CA/A10 READ/WRITE
Write with AP
H
BA/RA
ACT
ILLEGAL (Note 1)
ILLEGAL
L
L
L
L
H
L
L
BA/A10
PRE/PREA
REFA
H
X
Op-Code,
Mode-Add
L
L
L
L
MRS
ILLEGAL
H
L
L
X
H
H
X
H
H
X
H
L
X
X
X
DESL
NOP
TERM
NOP(idle after tRP)
NOP(idle after tRP)
NOP
ILLEGAL (Note 1)
ILLEGAL (Note 1)
L
L
H
L
L
X
H
BA/CA/A10 READ/WRITE
Pre-charging
H
BA/RA
ACT
NOP(idle after tRP) (Note 3)
ILLEGAL
L
L
L
L
H
L
L
BA/A10
PRE/PREA
REFA
H
X
Op-Code,
Mode-Add
L
L
L
L
MRS
ILLEGAL
H
L
L
X
H
H
X
H
H
X
H
L
X
X
X
DESL
NOP
TERM
NOP(Row active after tRCD
NOP(Row active after tRCD
NOP
ILLEGAL (Note 1)
ILLEGAL (Note 1)
)
)
L
L
H
L
L
X
H
BA/CA/A10 READ/WRITE
Row
H
BA/RA
ACT
Activating
ILLEGAL (Note 1)
ILLEGAL
L
L
L
L
H
L
L
BA/A10
PRE/PREA
REFA
H
X
Op-Code,
Mode-Add
L
L
L
L
MRS
ILLEGAL
Remark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Pre-charge
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EM42AM3284LBA
3. Operative Command Table (Continued)
Current State /CS /R /C /W
Addr.
Command
Action
H
L
L
L
X
H
H
H
X
H
H
L
X
H
L
X
X
X
DESL
NOP
TERM
READ
NOP
NOP
NOP
ILLEGAL(Note 1)
H
BA/CA/A10
L
L
H
L
L
L
BA/CA/A10 WRIT/WRITA New write, Determine AP
Write
Recovering
ILLEGAL (Note 1)
H
H
BA/RA
ACT
ILLEGAL (Note 1)
ILLEGAL
L
L
L
L
H
L
L
BA/A10
PRE/PREA
REFA
H
X
Op-Code,
Mode-Add
L
L
L
L
MRS
ILLEGAL
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
H
H
L
X
H
L
X
H
L
X
X
X
DESL
NOP
TERM
NOP(idle after tRP)
NOP(idle after tRP)
NOP
BA/CA/A10 READ/WRIT ILLEGAL
Refreshing
BA/RA
BA/A10
X
ACT
PRE/PREA
REFA
ILLEGAL
NOP(idle after tRP)
ILLEGAL
L
L
H
Op-Code,
Mode-Add
L
L
L
L
MRS
ILLEGAL
Remark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Pre-charge
Note 1: ILLEGAL to bank in specified states;
Function may be legal in the bank indicated by Bank Address (BA), depending on the state of
that bank.
Note 2: Must satisfy bus contention, bus turn around, and/or write recovery requirements.
Note 3: NOP to bank precharging or in idle state.May precharge bank indicated by BA.
Note 4: ILLEGAL of any bank is not idle.
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4. Command Truth Table for CKE
CKE
n-1
Current State
/CS /R /C /W
Addr.
Action
n
X
H
H
H
H
H
L
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
X
H
L
L
L
X
X
H
H
H
L
X
X
X
H
H
H
L
X
X
H
H
L
X
X
X
X
H
H
L
X
X
H
L
X
X
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
INVALID
Exist Self-Refresh
Exist Self-Refresh
ILLEGAL
Self Refresh
ILLEGAL
ILLEGAL
L
X
X
H
L
L
L
NOP(Maintain self refresh)
INVALID
Exist Power down
Exist Power down
ILLEGAL
X
H
H
H
H
H
L
Both bank
precharge
power down
ILLEGAL
ILLEGAL
L
X
X
X
X
X
X
H
X
X
X
NOP(Maintain Power down)
Refer to function true table
H
Enter power down mode(Note 3)
H
L
L
Enter power down mode(Note 3)
ILLEGAL
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
L
H
H
L
H
L
H
L
X
H
H
L
X
X
X
RA
X
L
L
L
L
ILLEGAL
All Banks
Idle
Row active/Bank active
Enter self-refresh(Note 3)
L
L
L
L
L
Op-Code Mode register access
H
L
L
L
L
L
Op-Code Special mode register access
X
H
X
X
X
X
X
X
Refer to current state
Any State Other
than Listed above
H
X
X
X
X
Refer to command truth table
Remark: H = High level, L = Low level, X = High or Low level (Don't care)
Notes 1: After CKE’s low to high transition to exist self refresh mode.And a time of tRC(min) has to be
Elapse after CKE’s low to high transition to issue a new command.
Notes 2:CKE low to high transition is asynchronous as if restarts internal clock.
Notes 3:Power down and self refresh can be entered only from the idle state of all banks.
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Mode Register Definition
Mode Register Set
The mode register stores the data for controlling the various operating modes of DDR SDRAM which
contains addressing mode, burst length, /CAS latency, test mode, DLL reset and various vendor＇s specific
opinions. The defaults values of the register is not defined, so the mode register must be written after EMRS
setting for proper DDR SDRAM operation. The mode register is written by asserting low on /CS, /RAS, /CAS,
/WE and BA0 ( The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into
the mode register. ) The state of the address pins A0-A12 in the same cycle as /CS, /RAS, /CAS, /WE and
BA0 going low is written in the mode register. Two clock cycles are requested to complete the write operation
in the mode register. The mode register contents can be changed using the same command and clock cycle
requirements during operating as long as all banks are in the idle state. The mode register is divided into
various fields depending on functionality. The burst length uses A0-A2, addressing mode uses A3, /CAS
latency ( read latency from column address ) uses A4-A6. A7 is used for test mode. A8 is used for DDR reset.
A7 must be set to low for normal MRS operation.
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Address input for Mode Register Set
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Burst Type (A3)
Burst Length
A3 A2 A1 A0
Sequential Addressing
Interleave Addressing
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
X
X
X
X
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0 1
0 1
2
1 0
1 0
0 1 2 3
0 1 2 3
1 2 3 0
1 0 3 2
4
8
2 3 0 1
2 3 0 1
3 0 1 2
3 2 1 0
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
1 2 3 4 5 6 7 0
1 0 3 2 5 4 7 6
2 3 4 5 6 7 0 1
2 3 0 1 6 7 4 5
3 4 5 6 7 0 1 2
3 2 1 0 7 6 5 4
4 5 6 7 0 1 2 3
4 5 6 7 0 1 2 3
5 6 7 0 1 2 3 4
5 4 7 6 1 0 3 2
6 7 0 1 2 3 4 5
6 7 4 5 2 3 0 1
7 0 1 2 3 4 5 6
7 6 5 4 3 2 1 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1
3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2
4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3
5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4
6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5
7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6
8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8
10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9
11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10
12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11
13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12
14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13
15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1 0 3 2 5 4 7 6 9 8 11 10 13 12 15 14
2 3 0 1 6 7 4 5 10 11 8 9 14 15 12 13
3 2 1 0 7 6 5 4 11 10 9 8 15 14 13 12
4 5 6 7 0 1 2 3 12 13 14 15 8 9 10 11
5 4 7 6 1 0 3 2 13 12 15 14 9 8 11 10
6 7 4 5 2 3 0 1 14 15 12 13 10 11 8 9
7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8
8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
9 8 11 10 13 12 15 14 1 0 3 2 5 4 7 6
10 11 8 9 14 15 12 13 2 3 0 1 6 7 4 5
11 10 9 8 15 14 13 12 3 2 1 0 7 6 5 4
12 13 14 15 8 9 10 11 4 5 6 7 0 1 2 3
13 12 15 14 9 8 11 10 5 4 7 6 1 0 3 2
14 15 12 13 10 11 8 9 6 7 4 5 2 3 0 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
16
* Page length is a function of I/O organization and column addressing
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EM42AM3284LBA
Extended Mode Register Set ( EMRS )
The Extended mode register is written by asserting low on /CS, /RAS, /CAS, /WE and high on BA1 ( The
DDR SDRAM should be in all bank precharge with CKE already prior to writing into the extended mode
register. ) The state of address pins A0-A10 and BA1 in the same cycle as /CS, /RAS, /CAS, and /WE going
low is written in the extended mode register. The mode register contents can be changed using the same
command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used
for DLL enable or disable. High on BA0 is used for EMRS. All the other address pins except A0 and BA0
must be set to low for proper EMRS operation.
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Output Drive Strength
The normal drive strength got all outputs is specified to be LV-CMOS. By setting EMRS specific parameter
on A6 and A5, driving capability of data output drivers is selected.
Temperature Compensated Self-Refresh
TCSR controlled by programming in the extended mode register (EMRS). The memory automatically
changes the self-refresh cycle by temperature fluctuations.
Partial Array Self Refresh
In EMRS setting ,memory array size to be refreshed during self-refresh operation is programmable in order
to reduce power. Data outside the defined area will not be retained during self-refresh.
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Package Description
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