EN29LV400AT45RBCP [EON]
4 Megabit (512K x 8-bit / 256K x 16-bit) Flash Memory Boot Sector Flash Memory, CMOS 3.0 Volt-only; 4兆位（ 512K ×8位/ 256K ×16位）闪存引导扇区快闪记忆体， CMOS 3.0伏只
| 型号： | EN29LV400AT45RBCP |
| 厂家： | 
EON SILICON SOLUTION INC. |
| 描述： | 4 Megabit (512K x 8-bit / 256K x 16-bit) Flash Memory Boot Sector Flash Memory, CMOS 3.0 Volt-only |
| 文件： | 总43页 (文件大小：423K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EN29LV400A
Purpose
Eon Silicon Solution Inc. (hereinafter called “Eon”) is going to provide its products’ top marking on
ICs with < cFeon > from January 1st, 2009, and without any change of the part number and the
compositions of the ICs. Eon is still keeping the promise of quality for all the products with the
same as that of Eon delivered before. Please be advised with the change and appreciate your
kindly cooperation and fully support Eon’s product family.
Eon products’ New Top Marking
cFeon Top Marking Example:
cFeon
Part Number: XXXX-XXX
Lot Number: XXXXX
Date Code: XXXXX
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as an Eon product. Any
changes that have been made are the result of normal data sheet improvement and are noted in
the document revision summary, where supported. Future routine revisions will occur when
appropriate, and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
Eon continues to support existing part numbers beginning with “Eon” and “cFeon” top marking. To
order these products, during the transition please specify “Eon top marking” or “cFeon top marking”
on your purchasing orders.
For More Information
Please contact your local sales office for additional information about Eon memory solutions.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2005 Eon Silicon Solution, Inc.,
www.eonssi.com
1
Rev. H, Issue Date: 2011/10/27
EN29LV400A
EN29LV400A
4 Megabit (512K x 8-bit / 256K x 16-bit) Flash Memory
Boot Sector Flash Memory, CMOS 3.0 Volt-only
FEATURES
• 3V, single power supply operation
• High performance program/erase speed
- Byte/Word program time: 8µs typical
- Sector erase time: 500ms typical
- Full voltage range: 2.7-3.6 volt read and write
operations for battery-powered applications.
- Regulated voltage range: 3.0-3.6 volt read
and write operations for compatibility with
high performance 3.3 volt microprocessors.
• JEDEC Standard Embedded Erase and
Program Algorithms
• JEDEC standard DATA# polling and toggle
bits feature
• High performance
- Access times as fast as 45 ns
• Single Sector and Chip Erase
• Sector Unprotect Mode
• Low power consumption (typical values at 5
MHz)
- 7 mA typical active read current
- 15 mA typical program/erase current
- 1 μA typical standby current (standard access
time to active mode)
• Erase Suspend / Resume modes:
Read or program another Sector during
Erase Suspend Mode
• triple-metal double-poly triple-well CMOS
Flash Technology
• Flexible Sector Architecture:
- One 16 K-byte, two 8 K-byte, one 32 K-byte,
and seven 64 K-byte sectors (byte mode)
- One 8 K-word, two 4 K-word, one 16 K-word
and seven 32 K-word sectors (word mode)
• Low Vcc write inhibit < 2.5V
• minimum 100K program/erase endurance
cycle
• Sector protection:
• Package Options
- Hardware locking of sectors to prevent
program or erase operations within individual
sectors
- Additionally, temporary Sector Unprotect
allows code changes in previously locked
sectors.
- 48-pin TSOP (Type 1)
- 48-ball 6mm x 8mm TFBGA
- 48-ball 4mm x 6mm WFBGA
• Commercial and Industrial Temperature
Range
GENERAL DESCRIPTION
The EN29LV400A is a 4-Megabit, electrically erasable, read/write non-volatile flash memory, organized
as 524,288 bytes or 256,144 words. Any byte can be programmed typically in 8µs. The EN29LV400A
features 3.0V voltage read and write operation, with access times as fast as 45ns to eliminate the need
for WAIT states in high-performance microprocessor systems.
The EN29LV400A has separate Output Enable (OE#), Chip Enable (CE#), and Write Enable (WE#)
controls, which eliminate bus contention issues. This device is designed to allow either single Sector
or full chip erase operation, where each Sector can be individually protected against program/erase
operations or temporarily unprotected to erase or program. The device can sustain a minimum of 100K
program/erase cycles on each Sector.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2005 Eon Silicon Solution, Inc.,
www.eonssi.com
2
Rev. H, Issue Date: 2011/10/27
EN29LV400A
CONNECTION DIAGRAMS
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
1
2
3
4
5
6
7
8
48
A16
BYTE#
Vss
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
Vcc
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Standard
TSOP 48
WE#
RESET#
NC
NC
RY/BY#
NC
A17
A7
A6
A5
A4
A3
A2
A1
Vss
CE#
A0
48-Ball TFBGA
Top View, Balls Facing Down
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2005 Eon Silicon Solution, Inc.,
www.eonssi.com
3
Rev. H, Issue Date: 2011/10/27
EN29LV400A
48-Ball WFBGA
Top View, Balls Facing Down
F6
NC
G6
H6
B6
A4
B5
A3
B4
A5
B3
C6
A6
C5
A7
C4
NC
C3
D6
E6
NC
K6
A6
A2
J6
A9
J5
A10
J4
A8
WE# Reset#
A17
D5
A11
H5
K5
A13
K4
A12
L5
A14
L4
A15
L3
A16
L2
DQ7
L1
VSS
A5
A1
A4
A0
A3
NC
NC
K3
J3
DQ8
B2
DQ10
C2
DQ11
K2
CE#
A2
DQ4
J2
H2
D2
Byte#
D1
NC
OE#
B1
DQ9
C1
DQ6
K1
VSS
DQ5
J1
F1
VCC
G1
H1
E1
DQ12 DQ13
DQ0
DQ1
DQ2
DQ3
DQ15/
DQ14
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2005 Eon Silicon Solution, Inc.,
www.eonssi.com
4
Rev. H, Issue Date: 2011/10/27
EN29LV400A
TABLE 1. PIN DESCRIPTION
FIGURE 1. LOGIC DIAGRAM
Pin Name
A0-A17
DQ0-DQ14
DQ15 / A-1
CE#
Function
EN29LV400A
Addresses
DQ0 –DQ15
(A-1)
15 Data Inputs/Outputs
A0 - A17
DQ15 (data input/output, word mode),
A-1 (LSB address input, byte mode)
Reset#
Chip Enable
CE#
OE#
OE#
Output Enable
RY/BY#
WE#
RESET#
RY/BY#
WE#
Hardware Reset Pin
Ready/Busy Output
Write Enable
Byte#
Vcc
Supply Voltage
Ground
Vss
NC
Not Connected to anything
Byte/Word Mode
BYTE#
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2005 Eon Silicon Solution, Inc.,
www.eonssi.com
5
Rev. H, Issue Date: 2011/10/27
EN29LV400A
TABLE 2A. TOP BOOT BLOCK SECTOR ARCHITECTURE
SECTOR
SIZE
(Kbytes /
ADDRESS RANGE
A17 A16 A15 A14
A13
A12
Sector
(X16)
(X8)
Kwords)
16/8
10
9
8
7
6
5
4
3
2
1
0
3E000h-3FFFFh
3D000h-3DFFFh
3C000h-3CFFFh
38000h-3BFFFh
30000h-37FFFh
28000h-2FFFFh
20000h-27FFFh
18000h-1FFFFh
10000h-17FFFh
08000h-0FFFFh
00000h-07FFFh
7C000h-7FFFFh
7A000h-7BFFFh
78000h-79FFFh
70000h – 77FFFh
60000h - 6FFFFh
50000h – 5FFFFh
40000h – 4FFFFh
30000h – 3FFFFh
20000h - 2FFFFh
10000h - 1FFFFh
00000h - 0FFFFh
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
0
1
0
1
0
1
0
1
1
1
0
X
1
8/4
8/4
1
0
0
32/16
64/32
64/32
64/32
64/32
64/32
64/32
64/32
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2005 Eon Silicon Solution, Inc.,
www.eonssi.com
6
Rev. H, Issue Date: 2011/10/27
EN29LV400A
TABLE 2B. BOTTOM BOOT BLOCK SECTOR ARCHITECTURE
SECTOR
SIZE
(Kbytes/
ADDRESS RANGE
A17 A16 A15 A14 A13 A12
Sector
(X16)
(X8)
Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
32/16
8/4
10
9
8
7
6
5
4
3
2
1
0
38000h-3FFFFh
30000h-37FFFh
28000h-2FFFFh
20000h-27FFFh
18000h-1FFFFh
10000h-17FFFh
08000h-0FFFFh
04000h-07FFFh
03000h-03FFFh
02000h-02FFFh
00000h-01FFFh
70000h –7FFFFh
60000h – 6FFFFh
50000h – 5FFFFh
40000h – 4FFFFh
30000h – 3FFFFh
20000h – 2FFFFh
10000h – 1FFFFh
08000h – 0FFFFh
06000h – 07FFFh
04000h – 05FFFh
00000h – 03FFFh
1
1
1
1
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
1
0
1
0
1
0
1
0
0
0
0
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
1
0
8/4
0
1
0
16/8
0
0
X
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2005 Eon Silicon Solution, Inc.,
www.eonssi.com
7
Rev. H, Issue Date: 2011/10/27
EN29LV400A
PRODUCT SELECTOR GUIDE
Product Number
EN29LV400A
Regulated Voltage Range: Vcc=3.0-3.6 V
Full Voltage Range: Vcc=2.7 – 3.6 V
-45R
-55R
Speed Option
-70
Max Access Time, ns (tacc
Max CE# Access, ns (tce)
Max OE# Access, ns (toe)
)
45
45
25
55
55
30
70
70
30
BLOCK DIAGRAM
RY/BY#
Vcc
Vss
DQ0-DQ15 (A-1)
Block Protect Switches
Erase Voltage Generator
Input/Output Buffers
State
Control
WE#
Program Voltage
Generator
Command
Register
STB
Chip Enable
Output Enable
Logic
Data Latch
CE#
OE#
Y-Decoder
Y-Gating
STB
Vcc Detector
A0-A17
Timer
X-Decoder
Cell Matrix
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2005 Eon Silicon Solution, Inc.,
www.eonssi.com
8
Rev. H, Issue Date: 2011/10/27
EN29LV400A
TABLE 3. OPERATING MODES
4M FLASH USER MODE TABLE
DQ8-DQ15
Operation
Read
CE#
OE# WE#
Reset#
A0-A17 DQ0-DQ7
Byte#
= VIH
DOUT
DIN
High-Z High-Z
High-Z High-Z
High-Z High-Z
Byte#
= VIL
High-Z
High-Z
L
L
L
H
X
H
X
H
L
X
H
X
H
H
AIN
AIN
X
DOUT
DIN
High-Z
High-Z
High-Z
Write
CMOS Standby
Output Disable
Hardware Reset
Temporary
Vcc ± 0.3V
Vcc ± 0.3V
L
X
H
L
X
X
Sector
X
X
X
VID
AIN
DIN
DIN
X
Unprotect
Notes:
L=logic low= VIL, H=Logic High= VIH, VID =11 ± 0.5V, X=Don’t Care (either L or H, but not floating!),
DIN=Data In, DOUT=Data Out, AIN=Address In
TABLE 4. DEVICE IDENTIFICTION (Autoselect Codes)
4M FLASH MANUFACTURER/DEVICE ID TABLE
A17 A11
to to
A12 A10
A5
DQ8
to
DQ15
DQ7
to
DQ0
1Ch
7Fh
B9h
Description
Mode
CE# OE# WE#
A92 A8 A7 A6 to A1 A0
A2
Manufacturer ID:
Eon
H1
L
L
H
X
X
VID
X
L
X
L
L
X
L
Device ID
(top boot
block)
Device ID
(bottom boot
block)
Word
Byte
L
L
L
L
L
L
L
L
H
H
H
H
22h
X
X
X
VID
X
X
L
X
L
H
B9h
BAh
BAh
01h
Word
Byte
22h
X
X
X
X
VID
VID
X
X
X
X
L
L
X
X
L
H
L
X
X
Sector Protection
Verification
(Protected)
00h
(Unprotected)
L
L
H
SA
H
Note:
1. A8 = H is recommended for Manufacturing ID check. If a manufacturing ID is read with A8=L, the chip will output a
configuration code 7Fh.
2. A9 = VID is for HV A9 Autoselect mode only. A9 must be ≤ Vcc (CMOS logic level) for Command Autoselect Mode.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2005 Eon Silicon Solution, Inc.,
www.eonssi.com
9
Rev. H, Issue Date: 2011/10/27
EN29LV400A
USER MODE DEFINITIONS
Word / Byte Configuration
The signal set on the BYTE# Pin controls whether the device data I/O pins DQ15-DQ0 operate in the
byte or word configuration. When the Byte# Pin is set at logic ‘1’, then the device is in word
configuration, DQ15-DQ0 are active and are controlled by CE# and OE#.
On the other hand, if the Byte# Pin is set at logic ‘0’, then the device is in byte configuration, and only
data I/O pins DQ0-DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8-DQ14 are
tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.
Standby Mode
The EN29LV400A has a CMOS-compatible standby mode, which reduces the current to < 1µA (typical).
It is placed in CMOS-compatible standby when the CE# pin is at VCC ± 0.5. RESET# and BYTE# pin
must also be at CMOS input levels. The device also has a TTL-compatible standby mode, which
reduces the maximum VCC current to < 1mA. It is placed in TTL-compatible standby when the CE# pin
is at VIH. When in standby modes, the outputs are in a high-impedance state independent of the OE#
input.
Read Mode
The device is automatically set to reading array data after device power-up. No commands are required
to retrieve data. The device is also ready to read array data after completing an Embedded Program or
Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode.
The system can read array data using the standard read timings, except that if it reads at an address
within erase-suspended sectors, the device outputs status data. After completing a programming
operation in the Erase Suspend mode, the system may once again read array data with the same
exception. See “Erase Suspend/Erase Resume Commands” for more additional information.
The system must issue the reset command to re-enable the device for reading array data if DQ5 goes
high, or while in the autoselect mode. See the “Reset Command” additional details.
Output Disable Mode
When the OE# pin is at a logic high level (VIH), the output from the EN29LV400A is disabled. The
output pins are placed in a high impedance state.
Auto Select Identification Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification,
through identifier codes output on DQ15–DQ0. This mode is primarily intended for programming
equipment to automatically match a device to be programmed with its corresponding programming
algorithm. However, the autoselect codes can also be accessed in-system through the command
register.
When using programming equipment, the autoselect mode requires VID (10.5V to 11.5 V) on address
pin A9. Address pins A8, A6, A1, and A0 must be as shown in Autoselect Codes table. In addition,
when verifying sector protection, the sector address must appear on the appropriate highest order
address bits. Refer to the corresponding Sector Address Tables. The Command Definitions table
shows the remaining address bits that are don’t-care. When all necessary bits have been set as
required, the programming equipment may then read the corresponding identifier code on DQ15–DQ0.
To access the autoselect codes in-system; the host system can issue the autoselect command via the
command register, as shown in the Command Definitions table. This method does not require VID. See
“Command Definitions” for details on using the autoselect mode.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2005 Eon Silicon Solution, Inc.,
www.eonssi.com
10
Rev. H, Issue Date: 2011/10/27
EN29LV400A
Write Mode
Write operations, including programming data and erasing sectors of memory, require the host system
to write a command or command sequence to the device. Write cycles are initiated by placing the byte
or word address on the device’s address inputs while the data to be written is input on DQ[7:0] in Byte
Mode (BYTE# = L) or on DQ[15:0] in Word Mode (BYTE# = H). The host system must drive the CE#
and WE# pins Low and the OE# pin high for a valid write operation to take place. All addresses are
latched on the falling edge of WE# and CE#, whichever happens later. All data is latched on the rising
edge of WE# or CE#, whichever happens first. The system is not required to provide further controls or
timings. The device automatically provides internally generated program / erase pulses and verifies the
programmed /erased cells’ margin. The host system can detect completion of a program or erase
operation by observing the RY/BY# pin, or by reading the DQ[7] (Data# Polling) and DQ[6] (Toggle)
status bits.
The ‘Command Definitions’ section of this document provides details on the specific device commands
implemented in the EN29LV400A.
Sector Protection/Unprotection
The hardware sector protection feature disables both program and erase operations in any sector. The
hardware sector unprotection feature re-enables both program and erase operations in previously protected
sectors.
There are two methods to enabling this hardware protection circuitry. The first one requires only that
the RESET# pin be at VID and then standard microprocessor timings can be used to enable or disable
this feature. See Flowchart 7a and 7b for the algorithm and Figure 12 for the timings.
When doing Sector Unprotect, all the other sectors should be protected first.
The second method is meant for programming equipment. This method requires VID be applied to both
OE# and A9 pin and non-standard microprocessor timings are used. This method is described in a
separate document called EN29LV400A Supplement, which can be obtained by contacting a
representative of Eon Silicon Devices, Inc.
Temporary Sector Unprotect
Start
This feature allows temporary unprotection of previously protected
sector groups to change data while in-system. The Sector
Unprotect mode is activated by setting the RESET# pin to VID.
During this mode, formerly protected sectors can be programmed
or erased by simply selecting the sector addresses. Once is
removed from the RESET# pin, all the previously protected sectors
Reset#=VID (note 1)
Perform Erase or Program
Operations
are protected again.
diagrams for more details.
See accompanying figure and timing
Reset#=VIH
Notes:
Temporary Sector
Unprotect Completed (note 2)
1. All protected sectors unprotected.
2. Previously protected sectors protected
again.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically
enables this mode when addresses remain stable for tacc + 30ns. The automatic sleep mode is
independent of the CE#, WE# and OE# control signals. Standard address access timings provide new
data when addresses are changed. While in sleep mode, output is latched and always available to the
system. ICC4 in the DC Characteristics table represents the automatic sleep more current specification.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2005 Eon Silicon Solution, Inc.,
www.eonssi.com
11
Rev. H, Issue Date: 2011/10/27
EN29LV400A
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data
protection against inadvertent writes as seen in the Command Definitions table. Additionally, the
following hardware data protection measures prevent accidental erasure or programming, which might
otherwise be caused by false system level signals during Vcc power up and power down transitions, or
from system noise.
Low VCC Write Inhibit
When Vcc is less than VLKO, the device does not accept any write cycles. This protects data during Vcc
power up and power down. The command register and all internal program/erase circuits are disabled,
and the device resets. Subsequent writes are ignored until Vcc is greater than VLKO. The system must
provide the proper signals to the control pins to prevent unintentional writes when Vcc is greater than
VLKO
.
Write Pulse “Glitch” protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH, or WE# = VIH. To initiate a write
cycle, CE# and WE# must be a logical zero while OE# is a logical one. If CE#, WE#, and OE# are all
logical zero (not recommended usage), it will be considered a read.
Power-up Write Inhibit
During power-up, the device automatically resets to READ mode and locks out write cycles. Even with
CE# = VIL, WE# = VIL and OE# = VIH, the device will not accept commands on the rising edge of WE#.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2005 Eon Silicon Solution, Inc.,
www.eonssi.com
12
Rev. H, Issue Date: 2011/10/27
EN29LV400A
COMMAND DEFINITIONS
The operations of the EN29LV400A are selected by one or more commands written into the
command register to perform Read/Reset Memory, Read ID, Read Sector Protection, Program,
Sector Erase, Chip Erase, Erase Suspend and Erase Resume. Commands are made up of data
sequences written at specific addresses via the command register. The sequences for the specified
operation are defined in the Command Definitions table (Table 5). Incorrect addresses, incorrect data
values or improper sequences will reset the device to Read Mode.
Table 5. EN29LV400A Command Definitions
Bus Cycles
1st
Cycle
2nd
Cycle
3rd
Cycle
4th
Cycle
5th
Cycle
6th
Cycle
Command
Sequence
Addr Data Addr Data
Addr
Data
Addr Data
Addr Data Addr Data
Read
Reset
1
1
RA
xxx
RD
F0
000
100
000
200
7F
1C
7F
1C
Word
Byte
555
2AA
555
555
Manufacturer
ID
4
AA
55
90
AAA
AAA
Device ID
Top Boot
Word
Byte
555
AAA
555
2AA
555
2AA
555
2AA
555
AAA
555
X01 22B9
X02 B9
4
4
AA
AA
55
55
90
90
Device ID
Bottom Boot
Word
Byte
X01 22BA
X02 BA
(SA) XX00
AAA
AAA
Word
Byte
555
555
X02
Sector Protect
Verify
XX01
4
AA
55
90
(SA) 00
AAA
555
AAA
X04
PA
01
Word
Byte
Word
Byte
Word
Byte
555
AAA
555
AAA
555
AAA
xxx
2AA
555
2AA
555
2AA
555
555
AAA
555
AAA
555
Program
4
6
6
AA
AA
AA
55
55
55
A0
80
80
PD
555
AAA
555
2AA
555
2AA
555
555
AAA
Chip Erase
AA
AA
55
55
10
30
Sector Erase
SA
AAA
AAA
Erase Suspend
Erase Resume
1
1
B0
30
xxx
Address and Data values indicated in hex
RA = Read Address: address of the memory location to be read. This is a read cycle.
RD = Read Data: data read from location RA during Read operation. This is a read cycle.
PA = Program Address: address of the memory location to be programmed. X = Don’t-Care
PD = Program Data: data to be programmed at location PA
SA = Sector Address: address of the Sector to be erased or verified. Address bits A17-A12 uniquely select any Sector.
Reading Array Data
The device is automatically set to reading array data after power up. No commands are required to
retrieve data. The device is also ready to read array data after completing an Embedded Program or
Embedded Erase algorithm.
Following an Erase Suspend command, Erase Suspend mode is entered. The system can read array
data using the standard read timings, with the only difference in that if it reads at an address within
erase suspended sectors, the device outputs status data. After completing a programming operation in
the Erase Suspend mode, the system may once again read array data with the same exception.
The Reset command must be issued to re-enable the device for reading array data if DQ5 goes high, or
while in the autoselect mode. See next section for details on Reset.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2005 Eon Silicon Solution, Inc.,
www.eonssi.com
13
Rev. H, Issue Date: 2011/10/27
EN29LV400A
Reset Command
Writing the reset command to the device resets the device to reading array data. Address bits are don’t-
care for this command.
The reset command may be written between the sequence cycles in an erase command sequence
before erasing begins. This resets the device to reading array data. Once erasure begins, however, the
device ignores reset commands until the operation is complete. The reset command may be written
between the sequence cycles in a program command sequence before programming begins. This
resets the device to reading array data (also applies to programming in Erase Suspend mode). Once
programming begins, however, the device ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must be written to return to reading array data (also
applies to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation, writing the reset command returns the device to
reading array data (also applies during Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manufacturer and devices
codes, and determine whether or not a sector is protected. The Command Definitions table shows the
address and data requirements. This is an alternative to the method that requires VID on address bit A9
and is intended for PROM programmers.
Two unlock cycles followed by the autoselect command initiate the autoselect command sequence.
Autoselect mode is then entered and the system may read at addresses shown in Table 4 any number
of times, without needing another command sequence.
The system must write the reset command to exit the autoselect mode and return to reading array data.
Word / Byte Programming Command
The device may be programmed by byte or by word, depending on the state of the Byte# Pin.
Programming the EN29LV400A is performed by using a four bus-cycle operation (two unlock write
cycles followed by the Program Setup command and Program Data Write cycle). When the program
command is executed, no additional CPU controls or timings are necessary. An internal timer
terminates the program operation automatically. Address is latched on the falling edge of CE# or WE#,
whichever is last; data is latched on the rising edge of CE# or WE#, whichever is first.
Programming status may be checked by sampling data on DQ7 (DATA# polling) or on DQ6 (toggle bit).
When the program operation is successfully completed, the device returns to read mode and the user
can read the data programmed to the device at that address. Note that data can not be programmed
from a 0 to a 1. Only an erase operation can change a data from 0 to 1. When programming time limit
is exceeded, DQ5 will produce a logical “1” and a Reset command can return the device to Read mode.
Chip Erase Command
Chip erase is a six-bus-cycle operation. The chip erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by
the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not
require the system to preprogram prior to erase. The Embedded Erase algorithm automatically
preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or timings during these operations. The Command
Definitions table shows the address and data requirements for the chip erase command sequence.
Any commands written to the chip during the Embedded Chip Erase algorithm are ignored.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2005 Eon Silicon Solution, Inc.,
www.eonssi.com
14
Rev. H, Issue Date: 2011/10/27
EN29LV400A
The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. See “Write
Operation Status” for information on these status bits. When the Embedded Erase algorithm is
complete, the device returns to reading array data and addresses are no longer latched.
Flowchart 4 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables
in “AC Characteristics” for parameters, and to the Chip/Sector Erase Operation Timings for timing
waveforms.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing
two un-lock cycles, followed by a set-up command. Two additional unlock write cycles are then followed
by the address of the sector to be erased, and the sector erase command. The Command Definitions
table shows the address and data requirements for the sector erase command sequence.
Once the sector erase operation has begun, only the Erase Suspend command is valid. All other
commands are ignored.
When the Embedded Erase algorithm is complete, the device returns to reading array data and
addresses are no longer latched. The system can determine the status of the erase operation by using
DQ7, DQ6, or DQ2. Refer to “Write Operation Status” for information on these status bits. Flowchart 4
illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the
“AC Characteristics” section for parameters, and to the Sector Erase Operations Timing diagram for
timing waveforms.
Erase Suspend / Resume Command
The Erase Suspend command allows the system to interrupt a sector erase operation and then read
data from, or program data to, any sector not selected for erasure. This command is valid only during
the sector erase operation. The Erase Suspend command is ignored if written during the chip erase
operation or Embedded Program algorithm. Addresses are don’t-cares when writing the Erase
Suspend command.
When the Erase Suspend command is written during a sector erase operation, the device requires a
maximum of 20 µs to suspend the erase operation.
After the erase operation has been suspended, the system can read array data from or program data to
any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.)
Normal read and write timings and command definitions apply. Reading at any address within erase-
suspended sectors produces status data on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2
together, to determine if a sector is actively erasing or is erase-suspended. See “Write Operation
Status” for information on these status bits.
After an erase-suspended program operation is complete, the system can once again read array data
within non-suspended sectors. The system can determine the status of the program operation using the
DQ7 or DQ6 status bits, just as in the standard program operation. See “Write Operation Status” for
more information. The Autoselect command is not supported during Erase Suspend Mode.
The system must write the Erase Resume command (address bits are don’t-care) to exit the erase
suspend mode and continue the sector erase operation. Further writes of the Resume command are
ignored. Another Erase Suspend command can be written after the device has resumed erasing.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2005 Eon Silicon Solution, Inc.,
www.eonssi.com
15
Rev. H, Issue Date: 2011/10/27
EN29LV400A
WRITE OPERATION STATUS
DQ7: DATA# Polling
The EN29LV400A provides DATA# polling on DQ7 to indicate the status of the embedded operations.
The DATA# polling feature is active during the embedded Programming, Sector Erase, Chip Erase, and
Erase Suspend. (See Table 6)
When the embedded Programming is in progress, an attempt to read the device will produce the
complement of the data written to DQ7. Upon the completion of the embedded Programming, an
attempt to read the device will produce the true data written to DQ7. For the embedded Programming,
DATA# polling is valid after the rising edge of the fourth WE# or CE# pulse in the four-cycle sequence.
When the embedded Erase is in progress, an attempt to read the device will produce a “0” at the DQ7
output. Upon the completion of the embedded Erase, the device will produce the “1” at the DQ7 output
during the read cycles. For Chip Erase, the DATA# polling is valid after the rising edge of the sixth WE#
or CE# pulse in the six-cycle sequence. DATA# polling is valid after the last rising edge of WE# or CE#
pulse for chip erase or sector erase.
DATA# Polling must be performed at any address within a sector that is being programmed or erased
and not a protected sector. Otherwise, DATA# polling may give an inaccurate result if the address used
is in a protected sector.
Just prior to the completion of the embedded operations, DQ7 may change asynchronously when the
output enable (OE#) is low. This means that the device is driving status information on DQ7 at one
instant of time and valid data at the next instant of time. Depending on when the system samples the
DQ7 output, it may read the status of valid data. Even if the device has completed the embedded
operations and DQ7 has a valid data, the data output on DQ0-DQ6 may be still invalid. The valid data
on DQ0-DQ7 will be read on the subsequent read attempts.
The flowchart for DATA# polling (DQ7) is shown on Flowchart 5. The DATA# polling (DQ7) timing
diagram is shown in Figure 8.
RY/BY#: Ready/Busy Status output
The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in
progress or completed. The RY/BY# status is valid after the rising edge of the final WE# pulse in the
command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together
in parallel with a pull-up resistor to Vcc.
In the output-low period, signifying Busy, the device is actively erasing or programming. This includes
programming in the Erase Suspend mode. If the output is high, signifying the Ready, the device is
ready to read array data (including during the Erase Suspend mode), or is in the standby mode.
DQ6: Toggle Bit I
The EN29LV400A provides a “Toggle Bit” on DQ6 to indicate the status of the embedded programming
and erase operations. (See Table 6)
During an embedded Program or Erase operation, successive attempts to read data from the device at
any address (by active OE# and CE#) will result in DQ6 toggling between “zero” and “one”. Once the
embedded Program or Erase operation is completed, DQ6 will stop toggling and valid data will be read
on the next successive attempts. During embedded Programming, the Toggle Bit is valid after the rising
edge of the fourth WE# pulse in the four-cycle sequence. During Erase operation, the Toggle Bit is valid
after the rising edge of the sixth WE# pulses for sector erase or chip erase.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2005 Eon Silicon Solution, Inc.,
www.eonssi.com
16
Rev. H, Issue Date: 2011/10/27
EN29LV400A
In embedded Programming, if the sector being written to is protected, DQ6 will toggles for about 2 μs,
then stop toggling without the data in the sector having changed. In Sector Erase or Chip Erase, if all
selected sectors are protected, DQ6 will toggle for about 100 μs. The chip will then return to the read
mode without changing data in all protected sectors.
The flowchart for the Toggle Bit (DQ6) is shown in Flowchart 6. The Toggle Bit timing diagram is shown
in Figure 9.
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit.
Under these conditions DQ5 produces a “1.” This is a failure condition that indicates the program or
erase cycle was not successfully completed. Since it is possible that DQ5 can become a 1 when the
device has successfully completed its operation and has returned to read mode, the user must check
again to see if the DQ6 is toggling after detecting a “1” on DQ5.
The DQ5 failure condition may appear if the system tries to program a “1” to a location that is previously
programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition,
the device halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a
“1.” Under both these conditions, the system must issue the reset command to return the device to
reading array data.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the output on DQ3 can be used to determine whether
or not an erase operation has begun. (The sector erase timer does not apply to the chip erase
command.) When sector erase starts, DQ3 switches from “0” to “1.” This device does not support
multiple sector erase command sequences so it is not very meaningful since it immediately shows as a
“1” after the first 30h command. Future devices may support this feature.
DQ2: Erase Toggle Bit II
The “Toggle Bit” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended.
Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2
toggles when the system reads at addresses within those sectors that have been selected for erasure.
(The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether
the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected
for erasure. Thus, both status bits are required for sector and mode information. Refer to the following
table to compare outputs for DQ2 and DQ6.
Flowchart 6 shows the toggle bit algorithm, and the section “DQ2: Toggle Bit” explains the algorithm.
See also the “DQ6: Toggle Bit I” subsection. Refer to the Toggle Bit Timings figure for the toggle bit
timing diagram. The DQ2 vs. DQ6 figure shows the differences between DQ2 and DQ6 in graphical
form.
Reading Toggle Bits DQ6/DQ2
Refer to Flowchart 6 for the following discussion. Whenever the system initially begins reading toggle
bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling.
Typically, a system would note and store the value of the toggle bit after the first read. After the second
read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not
toggling, the device has completed the program or erase operation. The system can read array data on
DQ7–DQ0 on the following read cycle.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2005 Eon Silicon Solution, Inc.,
www.eonssi.com
17
Rev. H, Issue Date: 2011/10/27
EN29LV400A
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped
toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully
completed the program or erase operation. If it is still toggling, the device did not complete the
operation successfully, and the system must write the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5
has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive
read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose
to perform other system tasks. In this case, the system must start at the beginning of the algorithm
when it returns to determine the status of the operation (top of Flowchart 6).
Write Operation Status
Operation
DQ7
DQ6
DQ5
DQ3
DQ2
RY/BY#
Embedded Program
Algorithm
No
toggle
DQ7#
Toggle
Toggle
0
0
0
N/A
1
0
0
1
Standard
Mode
Embedded Erase Algorithm
0
1
Toggle
Reading within Erase
Suspended Sector
Reading within Non-Erase
Suspended Sector
No
Toggle
N/A
Toggle
Erase
Suspend
Mode
Data
Data
Data
0
Data
N/A
Data
N/A
1
0
Erase-Suspend Program
DQ7#
Toggle
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2005 Eon Silicon Solution, Inc.,
www.eonssi.com
18
Rev. H, Issue Date: 2011/10/27
EN29LV400A
Table 6. Status Register Bits
DQ
Name
Logic Level
Definition
‘1’
‘0’
Erase Complete or erase Sector in Erase suspend
Erase On-Going
DATA#
POLLING
7
Program Complete or
data of non-erase Sector during Erase Suspend
DQ7
DQ7#
‘-1-0-1-0-1-0-1-’
DQ6
Program On-Going
Erase or Program On-going
Read during Erase Suspend
6
TOGGLE BIT
‘-1-1-1-1-1-1-1-‘ Erase Complete
‘1’
‘0’
‘1’
‘0’
Program or Erase Error
5
3
TIME OUT BIT
Program or Erase On-going
Erase operation start
ERASE TIME
OUT BIT
Erase timeout period on-going
Chip Erase, Erase or Erase suspend on currently
addressed
‘-1-0-1-0-1-0-1-’ Sector. (When DQ5=1, Erase Error due to currently
addressed Sector. Program during Erase Suspend
on-going at current address
2
TOGGLE BIT
Erase Suspend read on
non Erase Suspend Sector
DQ2
Notes:
DQ7 DATA# Polling: indicates the P/E C status check during Program or Erase, and on completion before checking bits DQ5 for
Program or Erase Success.
DQ6 Toggle Bit: remains at constant level when P/E operations are complete or erase suspend is acknowledged. Successive
reads output complementary data on DQ6 while programming or Erase operation are on-going.
DQ5 Tim Out Bit: set to “1” if failure in programming or erase
DQ3 Sector Erase Command Timeout Bit: Operation has started. Only possible command is Erase suspend (ES).
DQ2 Toggle Bit: indicates the Erase status and allows identification of the erased Sector.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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19
Rev. H, Issue Date: 2011/10/27
EN29LV400A
EMBEDDED ALGORITHMS
Flowchart 1. Embedded Program
START
Write Program
Command Sequence
(shown below)
Data# Poll Device
No
Verify Data?
Yes
No
Last
Increment
Address
Address?
Yes
Programming Done
Flowchart 2. Embedded Program Command Sequence
See the Command Definitions section for more information on WORD mode.
555H / AAH
2AAH / 55H
555H / A0H
PROGRAM ADDRESS / PROGRAM DATA
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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20
Rev. H, Issue Date: 2011/10/27
EN29LV400A
Flowchart 3. Embedded Erase
START
Write Erase
Command Sequence
Data Poll from
System or Toggle Bit
successfully
completed
Data =FFh?
No
Yes
Erase Done
Flowchart 4. Embedded Erase Command Sequence
See the Command Definitions section for more information on WORD mode.
Chip Erase
555H/AAH
Sector Erase
555H/AAH
2AAH/55H
555H/80H
2AAH/55H
555H/80H
555H/AAH
2AAH/55H
555H/10H
555H/AAH
2AAH/55H
Sector Address/30H
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2005 Eon Silicon Solution, Inc.,
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21
Rev. H, Issue Date: 2011/10/27
EN29LV400A
Flowchart 5. DATA# Polling
Algorithm
Start
Read Data
Yes
DQ7 = Data?
No
No
DQ5 = 1?
Yes
Read Data (1)
Notes:
Yes
(1) This second read is necessary in case the
first read was done at the exact instant when
the status data was in transition.
DQ7 = Data?
No
Fail
Pass
Start
Flowchart 6. Toggle Bit Algorithm
Read Data twice
No
DQ6 = Toggle?
Yes
No
DQ5 = 1?
Yes
Read Data twice (2)
Notes:
No
(2) This second set of reads is necessary in case
the first set of reads was done at the exact
instant when the status data was in transition.
DQ6 = Toggle?
Yes
Fail
Pass
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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22
Rev. H, Issue Date: 2011/10/27
EN29LV400A
Flowchart 7a. In-System Sector Protect Flowchart
START
PLSCNT = 1
RESET# = VID
Wait 1 μs
No
First Write
Cycle =
60h?
Temporary Sector
Unprotect Mode
Yes
Set up sector
address
Sector Protect: Write 60h
to sector addr with
A6 = 0, A1 = 1, A0 = 0
Wait 150 μs
Verify Sector Protect:
Write 40h to sector
address with
A6 = 0, A1 = 1, A0 = 0
Increment
PLSCNT
Reset
PLSCNT = 1
Wait 0.4 μs
Read from sector
address with
A6 = 0, A1 = 1, A0 = 0
No
No
Data = 01h?
Yes
PLSCNT = 25?
Yes
Device failed
Yes
Protect another
sector?
No
Remove VID
from RESET#
Write reset
command
Sector Protect
Algorithm
Sector Protect
complete
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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23
Rev. H, Issue Date: 2011/10/27
EN29LV400A
Flowchart 7b. In-System Sector Unprotect Flowchart
START
PLSCNT = 1
Protect all sectors:
The indicated portion
of the sector protect
RESET# = VID
algorithm must be
performed for all
Wait 1 μS
unprotected sectors
prior to issuing the
first sector unprotect
No
address (see
Diagram 7a.)
Temporary Sector
Unprotect Mode
First Write
Cycle = 60h?
Yes
No
All sectors
protected?
Yes
Set up first sector
address
Sector Unprotect: Write 60H to
sector address with A6 = 1,
A1 = 1, A0 = 0
Wait 15 ms
Verify Sector Unprotect:
Write 40h to sector address
with A6 = 1, A1 = 1, A0 =0
Increment
PLSCNT
Wait 0.4 μS
Read from sector address with
A6 = 1, A1 = 1, A0 = 0
No
No
PLSCCNT =
1000?
Set up next sector
Data = 00h?
address
Yes
Yes
Sector
Unprotect
Algorithm
No
Last sector
verified?
Device failed
Yes
Remove VID from
RESET#
Write reset
command
Sector Unprotect
complete
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2005 Eon Silicon Solution, Inc.,
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24
Rev. H, Issue Date: 2011/10/27
EN29LV400A
Table 7. DC Characteristics
(Ta = 0°C to 70°C or - 40°C to 85°C; VCC = 2.7-3.6V)
Symbol
Parameter
Test Conditions
0V≤ V ≤ Vcc
Min
Typ
Max
±1
Unit
µA
Input Leakage Current
Output Leakage Current
Supply Current (read) CMOS Byte
(read) CMOS Word
I
LI
IN
±1
µA
I
0V≤ V ≤ Vcc
OUT
LO
6
7
12
mA
mA
CE# = V ; OE# = V
IL
;
IH
I
I
CC1
f = 5MHz
12
CE# = BYTE# =
RESET# = Vcc ± 0.3V
(Note 1)
Supply Current (Standby - CMOS)
Supply Current (Program or Erase)
1
5.0
30
µA
CC2
Byte program, Sector or
Chip Erase in progress
15
1
mA
µA
I
I
CC3
CC4
V
= Vcc ± 0.3 V
= Vss ± 0.3 V
IH
5.0
0.8
Automatic Sleep Mode
Input Low Voltage
V
IL
-0.5
V
V
V
V
V
IL
0.7 x
Vcc
Vcc +
0.3
Input High Voltage
V
IH
Output Low Voltage
0.45
V
I
= 4.0 mA
OL
OL
OH
Vcc -
0.4V
Output High Voltage CMOS
V
I
= -100 μA,
OH
A9 Voltage (Electronic Signature)
A9 Current (Electronic Signature)
10.5
11.5
100
V
V
ID
A9 = VID
µA
I
ID
Supply voltage (Erase and
Program lock-out)
V
LKO
2.3
2.5
V
Notes
1. BYTE# pin can also be GND ± 0.3V. BYTE# and RESET# pin input buffers are always enabled so that they
draw power if not at full CMOS supply voltages.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2005 Eon Silicon Solution, Inc.,
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25
Rev. H, Issue Date: 2011/10/27
EN29LV400A
Test Conditions
Device Under Test
CL
Test Specifications
Test Conditions
Output Load Capacitance, CL
Input Rise and Fall times
Input Pulse Levels
-45R
30
-55R
30
-70
30
Unit
pF
ns
5
5
5
0.0-3.0
0.0-3.0
0.0-3.0
V
Input timing measurement
reference levels
Output timing measurement
reference levels
1.5
1.5
1.5
1.5
1.5
V
V
1.5
This Data Sheet may be revised by subsequent versions
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26
Rev. H, Issue Date: 2011/10/27
EN29LV400A
AC CHARACTERISTICS
Hardware Reset (Reset#)
Parameter
Std
Speed
-45R -55R -70
Unit
Test
Setup
Description
RESET# Pulse Width (During Embedded
Algorithms)
RESET# Pulse Width (NOT During Embedded
Algorithms)
tRP1
tRP2
Min
Min
10
us
ns
500
Reset# High Time Before Read
tRH
tRB1
tRB2
Min
Min
Min
50
0
50
ns
ns
ns
RY/BY# Recovery Time ( to CE#, OE# go low)
RY/BY# Recovery Time ( to WE# go low)
Reset# Pin Low (During Embedded Algorithms)
to Read or Write
Reset# Pin Low (NOT During Embedded
Algorithms) to Read or Write
tREADY1
tREADY2
Max
Max
20
us
ns
500
Figure 1. AC Waveforms for RESET#
Reset# Timings
This Data Sheet may be revised by subsequent versions
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Rev. H, Issue Date: 2011/10/27
EN29LV400A
AC CHARACTERISTICS
Word / Byte Configuration (Byte#)
Speed
Unit
Std
Parameter
Description
-45R
0
-55R
0
-70
0
tBCS
tCBH
tRBH
Byte# to CE# switching setup time
CE# to Byte# switching hold time
RY/BY# to Byte# switching hold time
Min
Min
Min
ns
ns
ns
0
0
0
0
0
0
Figure 2. AC Waveforms for BYTE#
CE#
OE#
Byte#
tCBH
tBCS
Byte# timings for Read Operations
CE#
WE#
Byte#
tRBH
tBCS
RY/BY#
Byte #timings for Write Operations
Note: Switching BYTE# pin not allowed during embedded operations
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2005 Eon Silicon Solution, Inc.,
www.eonssi.com
28
Rev. H, Issue Date: 2011/10/27
EN29LV400A
Table 8. AC CHARACTERISTICS
Read-only Operations Characteristics
Parameter
Symbols
Speed Options
Test
Description
Setup
JEDEC
Standard
-45R -55R
-70
Unit
Min
45
45
45
25
10
10
55
55
55
30
15
15
70
ns
tAVAV
tRC
Read Cycle Time
CE# = VIL
OE#= VIL
Max
Max
Max
Max
Max
70
70
30
20
20
ns
ns
ns
ns
ns
tAVQV
tELQV
tGLQV
tEHQZ
tGHQZ
tACC
tCE
tOE
tDF
Address to Output Delay
Chip Enable To Output Delay
Output Enable to Output Delay
Chip Enable to Output High Z
Output Enable to Output High Z
OE#= VIL
tDF
Output Hold Time from
Addresses, CE# or OE#,
whichever occurs first
Min
0
0
0
ns
tAXQX
tOH
Read
Min
Min
0
0
0
ns
ns
Output Enable
Hold Time
tOEH
Toggle and
Data# Polling
10
10
10
Notes:
1. High Z is Not 100% tested.
2. For -45R,-55R,70 Vcc = 3.0V ± 5%
Output Load : 30pF
Input Rise and Fall Times: 5ns Input Rise Levels: 0.0 V to Vcc
Timing Measurement Reference Level, Input and Output: 1.5 V
Figure 3. AC Waveforms for READ Operations
tRC
Addresses
Addresses Stable
tACC
CE#
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0V
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2005 Eon Silicon Solution, Inc.,
www.eonssi.com
29
Rev. H, Issue Date: 2011/10/27
EN29LV400A
Table 9. AC CHARACTERISTICS
Write (Erase/Program) Operations
Parameter
Symbols
Speed Options
JEDEC
Standard Description
-45R
-55R
-70
Unit
Min
Min
Min
Min
Min
45
0
55
70
ns
tAVAV
tWC
tAS
Write Cycle Time (Note 1)
0
45
25
0
0
45
30
0
ns
ns
ns
ns
tAVWL
tWLAX
tDVWH
tWHDX
Address Setup Time
Address Hold Time
Data Setup Time
35
20
0
tAH
tDS
tDH
tOES
Data Hold Time
Min
MIn
Min
0
0
0
0
0
0
ns
ns
ns
Output Enable Setup Time
Read
Toggle and
Data# Polling
Output Enable
Hold Time
tOEH
10
10
10
Read Recovery Time before
Write (OE# High to WE# Low)
Min
0
0
0
ns
tGHWL
tELWL
tWHEH
tWLWH
tWHDL
tGHWL
tCS
CE# SetupTime
CE# Hold Time
Min
Min
Min
Min
Typ
Max
0
0
0
0
0
0
ns
ns
ns
ns
µs
µs
tCH
25
20
8
30
20
8
35
20
8
tWP
Write Pulse Width
tWPH
Write Pulse Width High
Programming Operation
(Word AND Byte Mode)
(Note 2)
tWHWH1 tWHWH1
tWHWH2 tWHWH2
300
300
300
Sector Erase Operation
(Note 2)
Typ
0.5
0.5
0.5
s
Min
Min
50
50
50
µs
ns
tVCS
tVIDR
tRB
Vcc Setup Time
500
500
500
Rise Time to V
ID
Min
0
0
0
ns
ns
Recovery Time from RY/BY#
WE# High to RY/BY# Low
Max
45
55
70
tBUSY
B
Notes:
1. Not 100% tested.
2. See Erase and Programming Performance for more information.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2005 Eon Silicon Solution, Inc.,
www.eonssi.com
30
Rev. H, Issue Date: 2011/10/27
EN29LV400A
Table 10. AC CHARACTERISTICS
Write (Erase/Program) Operations
Alternate CE# Controlled Writes
Parameter
Symbols
Speed Options
Description
JEDEC
tAVAV
tAVEL
tELAX
tDVEH
tEHDX
Standard
-45R
-55R
-70
Unit
Min
Min
Min
Min
Min
45
0
55
70
ns
tWC
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
0
45
25
0
0
45
30
0
ns
ns
ns
ns
tAS
35
20
0
tAH
tDS
tDH
Data Hold Time
Min
Min
Min
0
0
0
0
0
0
ns
ns
ns
tOES
Output Enable Setup Time
Read
Output Enable
Toggle and
Hold Time
tOEH
10
10
10
Data# Polling
Read Recovery Time before
Min
0
0
0
ns
tGHEL
tGHEL
Write (
High to
Low)
CE
OE
Min
Min
Min
Min
Typ
Max
0
0
0
0
0
0
ns
ns
ns
ns
µs
µs
tWLEL
tEHWH
tELEH
tEHEL
tWS
tWH
tCP
WE# SetupTime
WE# Hold Time
Write Pulse Width
25
20
8
30
20
8
35
20
8
tCPH
Write Pulse Width High
Programming Operation
(byte AND word mode)
tWHWH1 tWHWH1
tWHWH2 tWHWH2
300
300
300
(Note 2)
Sector Erase Operation
(Note 2)
Typ
0.5
0.5
0.5
s
Min
Min
Min
50
500
0
50
500
0
50
500
0
µs
ns
ns
tVCS
tVIDR
tRB
Vcc Setup Time
Rise Time to V
ID
Recovery Time from RY/BY#
Notes:
1. Not 100% tested.
2. See Erase and Programming Performance for more information.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2005 Eon Silicon Solution, Inc.,
www.eonssi.com
31
Rev. H, Issue Date: 2011/10/27
EN29LV400A
Table 11. ERASE AND PROGRAMMING PERFORMANCE
Limits
Max
Parameter
Comments
Typ
Unit
Sector Erase Time
Chip Erase Time
0.5
10
sec
Excludes 00H programming prior
to erasure
5
8
8
100
300
300
sec
µs
Byte Programming Time
Word Programming Time
µs
Excludes system level overhead
Minimum 100K cycles
Byte
Word
4.2
2.1
12.6
6.3
Chip Programming
Time
sec
Erase/Program Endurance
100K
cycles
Table 12. 48-PIN TSOP AND BGA PACKAGE CAPACITANCE
Parameter Symbol
Parameter Description
Test Setup
= 0
Package
TSOP
BGA
Typ
6
Max
7.5
1.2
12
Unit
C
IN
V
IN
Input Capacitance
pF
1.2
8.5
1.1
7.5
1.0
TSOP
BGA
C
OUT
V
OUT
= 0
Output Capacitance
pF
pF
1.2
9
TSOP
BGA
C
IN2
V
IN
= 0
Control Pin Capacitance
1.3
Note: Test conditions are Temperature = 25°C and f = 1.0 MHz.
Table 13. DATA RETENTION
Parameter Description
Test Conditions
Min
Unit
150°C
125°C
10
20
Years
Years
Data Retention Time
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2005 Eon Silicon Solution, Inc.,
www.eonssi.com
32
Rev. H, Issue Date: 2011/10/27
EN29LV400A
AC CHARACTERISTICS
Figure 4. AC Waveforms for Chip/Sector Erase Operations Timings
Erase Command Sequence (last 2 cycles)
Read Status Data (last two cycles)
tAS
SA
tAH
tWC
Addresses
CE#
0x2AA
VA
VA
0x555 for chip
erase
tGHW
L
tCH
OE#
WE#
tWP
tWPH
tCS
tWHWH 2
Data
0x55
tDS
0x30
Status
DOUT
tRB
10 for chip
erase
tDH
tBUSY
RY/BY#
VCC
tVCS
Notes:
1. SA=Sector Address (for sector erase), VA=Valid Address for reading status, Dout=true data at read address.
2. Vcc shown only to illustrate tvcs measurement references. It cannot occur as shown during a valid command
sequence.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2005 Eon Silicon Solution, Inc.,
www.eonssi.com
33
Rev. H, Issue Date: 2011/10/27
EN29LV400A
Figure 5. Program Operation Timings
Program Command Sequence (last 2 cycles)
Program Command Sequence (last 2 cycles)
tAS
PA
tAH
tWC
Addresses
CE#
0x555
PA
PA
tGHWL
tCH
OE#
WE#
tWP
tWPH
tWHWH1
tCS
Data
DOUT
tRB
OxA0
Status
PD
tDS
tDH
tBUSY
RY/BY#
VCC
tVCS
Notes:
1. PA=Program Address, PD=Program Data, DOUT is the true data at the program address.
2. VCC shown in order to illustrate tVCS measurement references. It cannot occur as shown during a valid command
sequence.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2005 Eon Silicon Solution, Inc.,
www.eonssi.com
34
Rev. H, Issue Date: 2011/10/27
EN29LV400A
Figure 6. AC Waveforms for DATA# Polling During Embedded Algorithm
Operations
tRC
Addresses
CE#
VA
VA
VA
tACC
tCE
tOE
tCH
OE#
WE#
tOEH
tDF
tOH
Comple
-ment
Valid Data
Valid Data
Complement
Status Data
True
DQ[7]
Status
Data
True
DQ[6:0]
tBUSY
RY/BY#
Notes:
1. VA=Valid Address for reading Data# Polling status data
2. This diagram shows the first status cycle after the command sequence, the last status read cycle and the array data read cycle.
Figure 7. AC Waveforms for Toggle Bit During Embedded Algorithm Operations
tRC
Addresses
CE#
VA
VA
VA
VA
tCH
tACC
tCE
tOE
OE#
WE#
tOEH
tDF
tOH
Valid Data
Valid Status
(first read)
Valid Status
Valid Status
DQ6, DQ2
RY/BY#
tBUSY
(second read)
(stops toggling)
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2005 Eon Silicon Solution, Inc.,
www.eonssi.com
35
Rev. H, Issue Date: 2011/10/27
EN29LV400A
Figure 8. Alternate CE# Controlled Write Operation Timings
PA for Program
SA for Sector Erase
0x555 for Program
0x2AA for Erase
0x555 for Chip Erase
Addresses
WE#
VA
tWC
tAS
tAH
tWH
tGHEL
OE#
CE#
Data
tCP
tCPH
tWHWH1 / tWHWH2
tWS
tBUSY
tDH
tDS
Status
DOUT
PD for Program
0x30 for Sector Erase
0x10 for Chip Erase
0xA0 for
Program
0x55 for Erase
RY/BY
tRH
Reset#
Notes:
PA = address of the memory location to be programmed.
PD = data to be programmed at byte address.
VA = Valid Address for reading program or erase status
Dout = array data read at VA
Shown above are the last two cycles of the program or erase command sequence and the last status read cycle
Reset# shown to illustrate tRH measurement references. It cannot occur as shown during a valid command
sequence.
Figure 9. DQ2 vs. DQ6
Enter
Embedded
Erase
Enter Erase
Suspend
Program
Erase
Suspend
Erase
Resume
WE#
Erase
Enter
Suspend
Read
Enter
Suspend
Program
Erase
Suspend
Read
Erase
Complete
Erase
DQ6
DQ2
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2005 Eon Silicon Solution, Inc.,
www.eonssi.com
36
Rev. H, Issue Date: 2011/10/27
EN29LV400A
Figure 10. Sector Protect/Unprotect Timing Diagram
VID
Vcc
RESET#
0V
0V
tVIDR
tVIDR
SA,
A6,A1,A0
Valid
Valid
Valid
Data
60h
60h
40h
Status
Sector Protect/Unprotect
Verify
CE#
>0.4μS
WE#
>1μS
Sector Protect: 150 uS
Sector Unprotect: 15 mS
OE#
Notes:
Use standard microprocessor timings for this device for read and write cycles.
For Sector Protect, use A6=0, A1=1, A0=0. For Sector Unprotect, use A6=1, A1=1, A0=0.
Temporary Sector Unprotect
Speed Option
-45R -55R -70
Unit
Parameter
Std
Description
tVIDR
tRSP
VID Rise and Fall Time
Min
Min
500
4
ns
µs
RESET# Setup Time for Temporary
Sector Unprotect
Figure 11. Temporary Sector Unprotect Timing Diagram
VID
RESET#
0 or 3 V
0 or 3 V
tVIDR
tVIDR
CE#
WE#
tRSP
RY/BY#
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2005 Eon Silicon Solution, Inc.,
www.eonssi.com
37
Rev. H, Issue Date: 2011/10/27
EN29LV400A
FIGURE 12. 48L TSOP 12mm x 20mm package outline
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2005 Eon Silicon Solution, Inc.,
www.eonssi.com
38
Rev. H, Issue Date: 2011/10/27
EN29LV400A
FIGURE 13. 48L TFBGA 6mm x 8mm package outline
DIMENSION IN MM
NOR
SYMBOL
MIN.
- - -
MAX
1.30
- - -
A
A1
A2
D
- - -
0.29
0.91
8.00
6.00
5.60
4.00
0.80
0.40
0.23
0.84
7.90
5.90
- - -
- - -
8.10
6.10
- - -
E
D1
E1
e
- - -
- - -
- - -
- - -
b
0.35
0.45
Note : 1. Coplanarity: 0.1 mm
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2005 Eon Silicon Solution, Inc.,
www.eonssi.com
39
Rev. H, Issue Date: 2011/10/27
EN29LV400A
Figure 14. 48L WFBGA 4mm x 6mm package outline
Note : Controlling dimensions are in millimeters (mm).
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2005 Eon Silicon Solution, Inc.,
www.eonssi.com
40
Rev. H, Issue Date: 2011/10/27
EN29LV400A
ABSOLUTE MAXIMUM RATINGS
Parameter
Value
Unit
Storage Temperature
-65 to +150
°C
Plastic Packages
-65 to +125
-55 to +125
°C
°C
Ambient Temperature
With Power Applied
Output Short Circuit Current1
200
mA
V
A9, OE#, Reset# 2
-0.5 to +11.5
Voltage with
Respect to Ground
All other pins 3
Vcc
-0.5 to Vcc+0.5
-0.5 to +4.0
V
V
Notes:
1.
2.
No more than one output shorted at a time. Duration of the short circuit should not be greater than one second.
Minimum DC input voltage on A9, OE#, RESET# pins is –0.5V. During voltage transitions, A9, OE#, RESET# pins may
undershoot Vss to –1.0V for periods of up to 50ns and to –2.0V for periods of up to 20ns. See figure below. Maximum DC input
voltage on A9, OE#, and RESET# is 10.5V which may overshoot to 11.5V for periods up to 20ns.
3.
4.
Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, inputs may undershoot Vss to –1.0V for periods of
up to 50ns and to –2.0 V for periods of up to 20ns. See figure below. Maximum DC voltage on output and I/O pins is Vcc + 0.5 V.
During voltage transitions, outputs may overshoot to Vcc + 1.5 V for periods up to 20ns. See figure below.
Stresses above the values so mentioned above may cause permanent damage to the device. These values are for a stress
rating only and do not imply that the device should be operated at conditions up to or above these values. Exposure of the
device to the maximum rating values for extended periods of time may adversely affect the device reliability.
RECOMMENDED OPERATING RANGES1
Parameter
Value
Unit
Ambient Operating Temperature
Commercial Devices
0 to 70
-40 to 85
°C
Industrial Devices
Regulated Voltage
Range: 3.0-3.6
Operating Supply Voltage
Vcc
V
Standard Voltage Range:
2.7 to 3.6
1.
Recommended Operating Ranges define those limits between which the functionality of the device is guaranteed.
Vcc
+1.5V
Maximum Negative Overshoot
Waveform
Maximum Positive Overshoot
Waveform
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2005 Eon Silicon Solution, Inc.,
www.eonssi.com
41
Rev. H, Issue Date: 2011/10/27
EN29LV400A
ORDERING INFORMATION
EN29LV400A
T
─
70
T
C
P
PACKAGING CONTENT
P = RoHS compliant
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I = Industrial (-40°C to +85°C)
PACKAGE
T = 48-pin TSOP
B = 48-ball Thin Fine Pitch Ball Grid Array (TFBGA)
0.80mm pitch, 6mm x 8mm package
N = 48-Ball Very-Very-Thin-Profile Fine Pitch
Ball Grid Array (WFBGA)
0.5mm pitch, 4mm x 6mm package
SPEED
45R = 45ns Regulated range 3.0V~3.6V
55R = 55ns Regulated range 3.0V~3.6V
70 = 70ns
BOOT CODE SECTOR ARCHITECTURE
T = Top Sector
B = Bottom Sector
BASE PART NUMBER
EN = Eon Silicon Solution Inc.
29LV = FLASH, 3V Read Program Erase
400 = 4 Megabit (512K x 8 / 256K x 16)
A = Version Identifier
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2005 Eon Silicon Solution, Inc.,
www.eonssi.com
42
Rev. H, Issue Date: 2011/10/27
EN29LV400A
Revisions List
Revision No Description
Date
A
B
Initial Release
2004/01/07
1. Correct the typo of program/erase Endurance cycle to 100K at
FEATURES page 1
2. Change the FBGA package dimension to enhance the BGA
substrate and ball strength, the difference is
Package Thickness A : 1.10 mm to 1.31 mm
Ball size b : 0.3 mm to 0.4 mm
2005/11/8
1. Remove ,Unlock Bypass, Unlock Bypass Program, and Unlock
Bypass Reset, commands from Table 9.
C
2006/02/21
2. Remove description of Unlock Bypass
1. Add the tBUSY description in Table 9. Write (Erase/Program)
Operations in page 28
2. Correct the Figure 7. Program Operation Timings in page 32
3. Update 48 pin TSOP-I package outline in page 36
4. Change the FBGA 48 Ball package thickness from 1.31mm to
1.30mm in page 37
Add Eon products’ New top marking “cFeon“ information in page 1.
1. Add 48-ball 4mm x 6mm WFBGA package option.
D
E
2008/04/25
2009/01/09
2. Modify Table 6 Status Register Bits DQ5 from ERROE BIT to TIME
OUT BIT on page 19.
3. Modify Test Conditions illustration on page 26.
4. Update Hardware Reset (RESET#) table and Figure 1. AC
Waveforms for RESET# on page 27.
F
2009/09/24
5. Modify Storage Temperature from "-65 to + 125" to "-65 to +150" on
page 41.
6. Modify P = Pb free to P = RoHS compliant on page 42.
7. Remove the Latch up Characteristics Table.
1. Add the chip will output a configuration code 7Fh, if a manufacturing
ID is read with A8=L (000h).
2. Remove the speed option of 90ns.
1. Correct the typo of VIH (max.) = Vcc + 0.3V on page 25.
2. Add BGA PACKAGE CAPACITANCE on page 32.
G
H
2011/01/04
2011/10/27
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2005 Eon Silicon Solution, Inc.,
www.eonssi.com
43
Rev. H, Issue Date: 2011/10/27
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