EM8502_技术文档

EM MICROELECTRONIC - MARIN SA

EM8502

POWER MANAGEMENT CONTROLLER

WITH MULTI-CELL SOLAR HARVESTING

Description

The EM8502 is an integrated power management solution for low

power applications. It is designed to simplify the design of application

using multiple solar cells in series that can be directly connected to

the application and storage elements.

Features

. Flexible operation with different energy banks

. Secondary cell battery

. Capacitors (gold-cap, super-cap)

. Fast start-up on any energy storage

. Dual energy storage elements

. Start-up on solar cell or on battery

. Power management control

. Multiple independent supply outputs

. Sleep mode and wake-up functions

. User programmable under-voltage and over-voltage levels

. Configurable application voltage

. Battery voltage

The device is designed to speed-up system start-up time when the

main energy storage element (aka Long Term Storage – LTS) is

completely discharged or insufficiently charged to supply the

application, by using a secondary energy storage element (Short

Term Storage - STS).

When solar energy is high enough the device connects the solar cell

to STS or LTS to maintain the supply of the application, while

charging the rechargeable element.

. LDO

. Limited external components

. Device configurations are stored in on-chip E²PROM

. Dynamic configuration through a SPI or I²C interface

. Extended power management status

. Battery on protection mode

The EM8502 is capable of working with a variety of energy elements

as secondary storage, namely re-chargeable batteries, super-

capacitors or conventional capacitors. In all cases the EM8502

maintains its fast start-up capability that depends only on the

harvester conditions and the STS capacitor value.

. LTS/STS connection status

. Minimum/Maximum voltage warning

. USB connected

A USB connection to an external power source is available on the

EM8502 for fast charge of the long term storage element.

The EM8502 integrates voltage supervisory functions. Minimum and

maximum voltages are controlled on the LTS element to prevent

damage to the energy storage element. Harvester minimum voltage

monitoring allows disconnecting the solar cell from the storage

elements to avoid leakages. Output voltages are kept in a safe range

for the application.

Applications

. Multi-Solar cell platforms

. Wearable systems

. Beacons and wireless sensor networks

. Industrial and environmental monitoring

. Battery operated platforms

To perform granular power management of the application, the

EM8502 integrates four independent supply outputs and a sleep

mode offering the capability to switch off part or all the supplies.

The EM8502 is available in QFN24 package.

24

23

22

21

20

19

1

2

3

4

5

6

18

17

16

15

14

13

VDD_STS

WAKE_UP

VDD_USB

MOSI_SDA

MISO

BAT_LOW

HRV_LOW

VSUP

EM8502

N.C.

VAUX[2]

VAUX[1]

SCL

7

8

9

10

11

12

Figure 1 EM8502 QFN24 pins location

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EM8502

TABLE OF CONTENTS

1. Ordering Information .................................................................................................................. 3

2. Product description ..................................................................................................................... 3

2.1. Operating modes................................................................................................................................3

2.2. voltage naming conventions ...............................................................................................................4

2.3. Block diagram ....................................................................................................................................5

3. Handling Procedures ................................................................................................................... 6

4. Pin description ............................................................................................................................ 6

5. Electrical specifications ............................................................................................................... 7

5.1. Absolute Maximum Ratings................................................................................................................7

5.2. Operating Conditions..........................................................................................................................7

5.3. Electrical Characteristics .....................................................................................................................7

5.4. Timing diagrams.................................................................................................................................9

5.4.1.

5.4.2.

SPI interface .............................................................................................................................................................9

I2C Interface.............................................................................................................................................................9

6. Product configuration ............................................................................................................... 10

6.1. Status information ...........................................................................................................................10

6.2. Supervising and harvester controller behaviour ................................................................................11

6.2.1.

6.2.2.

6.2.3.

Storage element.....................................................................................................................................................11

Harvester power supervisory functions.................................................................................................................11

Timing configuration..............................................................................................................................................12

6.3. Power management functions ..........................................................................................................13

6.4. Sleep mode and Wake-up functions..................................................................................................15

6.5. Lux-meter ........................................................................................................................................16

6.6. USB charging ....................................................................................................................................17

6.7. Miscellaneous functions ...................................................................................................................18

6.7.1.

6.7.2.

6.7.3.

Soft reset function .................................................................................................................................................18

Register protection ................................................................................................................................................18

LTS protection DISABLE..........................................................................................................................................18

7. Serial interface.......................................................................................................................... 19

7.1. I2C interface.....................................................................................................................................19

7.2. SPI interface.....................................................................................................................................20

7.2.1.

Interface selection .................................................................................................................................................21

7.3. E2PROM...........................................................................................................................................21

7.3.1.

Accessing the E2PROM ..........................................................................................................................................21

8. Register map............................................................................................................................. 24

9. Typical Application.................................................................................................................... 27

10. packaging Information.............................................................................................................. 28

10.1.

QFN24 4x4 package .......................................................................................................................28

10.1.1. Package marking ....................................................................................................................................................28

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EM8502

1.

ORDERING INFORMATION

Part Nb

Package form

Delivery form

Quantity

2500 p/reel

EM8502-A005-LF24B+

QFN24 4x4 mm

Tape & Reel

Table 1 Ordering Information

For other delivery format please contact EM Microelectronics representative.

2.

PRODUCT DESCRIPTION

The EM8502 is a power management IC with battery charger function. It manages different energy source elements: a multi-cell solar harvester

element through VDD_SOL, external supply through VDD_USB, a battery or a Long Term Storage (LTS) through VDD_LTS. It generates a local

supply on a Short Term Storage (STS), visible through VDD_STS. The EM8502 provides the supply to the application from the energy sources.

Surplus energy is stored in a LTS element.

Features and benefits include:



Power management controller, extending application battery life: the EM8502 supplies the external application through the pins

VSUP and VAUX[i]. The voltage is delivered directly from VDD_STS or through a regulator. On the VSUP pin a wake-up function allows

to automatically re-enable the supply after a given time. For external devices using an I²C serial interface, it is possible to disconnect

their ground through the use of the auxiliary ground pins (VAUX_GND). This solution avoids supplying the devices connected to a

switched-off output supply through the pull-up of I²C bus. Overall power consumption is reduced by turning off peripheral ICs through

the EM8502.



Battery charger from solar source: EM8502 manages energy harvesting from a multiple solar cell in series by connecting to LTS

and/or STS to maintain the application supply. With its dual storage architecture, application start-up is fast and independent of the

battery (LTS) voltage.



Battery charger from USB source: Fast charging is supported through a USB compatible supply input on the EM8502 (system start-

up and battery charging to maximum voltage with configurable speed).

Voltage and current supervisor: The EM8502 includes supervisory functions to detect harvester energy levels detecting (visible

through the HRV_LOW pin) – and to monitor low battery voltage levels (visible through the BAT_LOW pin).

The EM8502 protects the battery against over voltage conditions and automatically stops charging when a configurable threshold

level is reached.



Configuration with E²PROM, no additional external components: The mode and functional configuration of the EM8502 is

controlled by the host MCU through a SPI or an I²C interface. Voltage supervision thresholds are set by registers. Configuration

parameters are held in on-chip non-volatile memory (E²PROM). The EM8502 default configuration parameter values can be modified

by the user.

2.1. OPERATING MODES

The EM8502 operates in three main modes:

1) Normal mode (STS and LTS Connected)

-

V_LTSis inside battery operating range.

LTS is connected to STS.

The system can be configured to disconnect VAUX or/and VAUX_GND pins.

2) LTS protection mode (STS and LTS disconnected)

-

EM8502 enters this mode when V_LTSdrops below minimum battery operation (v_bat_min_lo).

BAT_LOW pin is set to '1'.

LTS and STS are disconnected to protect LTS against under voltage condition.

VSUP and VAUX are maintained by the multiple solar cells connected on VDD_SOL or by VDD_USB through a LDO.

3) Sleep mode

-

VSUP is not supplied – no communication on SPI/I²C interface.

VSUP can be re-activated by WAKE_UP pin or internal timer.

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2.2. VOLTAGE NAMING CONVENTIONS

To describe the operation of this product, the following set of voltage naming conventions is adopted throughout this document, Table 2:

NAME

DESCRIPTION

v_bat_max_hi

Maximum battery voltage. High level of hysteresis.

v_bat_min_hi_dis

v_bat_min_hi_con

v_bat_min_hi

Minimum STS maintenance voltage – acts as v_bat_min_hi when STS and LTS are disconnected

Minimum battery maintenance voltage – acts as v_bat_min_hi when STS and LTS are connected

Minimum battery voltage. High level of hysteresis

Equal to v_bat_min_hi_dis or v_bat_min_hi_con according to the connection state in between STS and LTS.

The term “v_bat_min_hi” is used here whenever there is no specific usage of the connected and disconnected

values

v_bat_min_lo

v_apl_max_hi

v_apl_max_lo

V_{cs_hi}

Minimum battery voltage. Low level of hysteresis

Maximum application voltage. High level of hysteresis

Maximum application voltage. Low level of hysteresis

Cold start voltage level

v_ulp_ldo

Regulated voltage on VSUP pin

Table 2 Voltage Naming Conventions

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2.3. BLOCK DIAGRAM

n o i t a c i l p p A

s t s _ s t l _ w s

Figure 2-1 EM8502 Block Diagram

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3.

HANDLING PROCEDURES

This device has built-in protection against high static voltages or electric fields; however, anti-static precautions must be taken as for any other

CMOS component. Unless otherwise specified, proper operation can only occur when all terminal voltages are kept within the voltage range.

Unused inputs must always be tied to a defined logic voltage level.

4.

PIN DESCRIPTION

NAME

I/O TYPE

DESCRIPTION

NO.

DIRECTION

SUPPLY

1

2

3

4

5

6

7

8

9

VDD_STS

WAKE_UP

VDD_USB

MOSI_SDA

MISO

SCL

CS

VAUX_GND[2]

VAUX_GND[1]

N.C.

I/O

Input

Output

Input

Output

–

up to 3.6V

–

VSUP

–

Connection for the Short Term energy Storage element (STS)

Wake-up pin

USB power supply connection

SPI MOSI or I2C SDA connection

SPI MISO connection

SPI or I2C clock

SPI chip select and SPI/I2C selection mode(when at ‘1’)

Auxiliary 2 ground connection

Auxiliary 1 ground connection

–

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

VAUX_GND[0]

VAUX[0]

VAUX[1]

VAUX[2]

N.C.

Output

–

Auxiliary 0 ground connection

Auxiliary 0 supply output connection

Auxiliary 1 supply output connection

Auxiliary 2 supply output connection

VSUP

Output

Supply

Input

–

Main supply output

HRV_LOW

BAT_LOW

VREG

VSS1

VSS2

VDD_SOL

N.C.

VDD_LTS

VSUP

–

Energy harvester cell low indicator (when at ‘1’)

Battery low indicator (when at ‘1’)

Regulated voltage connection

Device ground connection

Direct connection from the solar cell

I/O

–

Connection for the Long Term energy Storage element (LTS)

Table 3 Pin-out description

The digital pads are all supplied by VSUP, with the exception of the WAKE_UP pad whose trigger levels are independent of the supply voltages.

When VSUP is disabled these pads are floating therefore the communication interface is off. All digital pads are active HIGH.

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5.

ELECTRICAL SPECIFICATIONS

5.1. ABSOLUTE MAXIMUM RATINGS

VALUE

UNIT

PARAMETER

MIN

MAX

Power supply VDD_STS, VDD_LTS, VDD_SOL

Power supply VDD_USB

-0.2

4.2

8.0

V

Input voltage

Input voltage (pin WAKE_UP)

VSS-0.2

-0.2

V_SUP+0.2

3.8

V

Storage Temperature Range (T_STG

Electrostatic discharge to ANSI/ESDA/JEDEC JS-001-2014 for HBM

)

-65

-2000

150

2000

°C

V

Table 4 Absolute maximum ratings

Stresses at or above these listed under Absolute Maximum Ratings may cause permanent damages to the device. Exposure beyond specified

operating conditions may affect device reliability or cause malfunction.

Warning: The device is not functional when exposed to light. When a non-packaged version is used, it is mandatory to protect the device from

light (e.g. glob-top, non-transparent package, metal shield on the PCB …)

5.2. OPERATING CONDITIONS

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Solar input

V_SOL

V_LTS

V_STS

V_USB

C_LTS

C_STS

C_REG

C_HRV

C_SUP

C_AUX

L₁

3.8

3.6

5.5

V

F

µF

nF

µF

µH

Long Term energy Storage bank voltage

Short Term energy Storage bank voltage

VDD_USB voltage

3.0

5

Long term capacitor⁽¹⁾

0.001

47

470

Short term capacitor⁽²⁾

Regulated voltage capacitor

Harvester capacitor (nominal value)

VSUP capacitor

VAUX capacitor

Input inductance

1

37.6

0.1*C_STS

56.4

47

(1) When using a super-capacitor

(2) C_STSshall be greater than 10 times C_HRVto avoid drops on STS when switching back and forth in between connection to LTS and STS

Table 5 Operating Conditions

5.3. ELECTRICAL CHARACTERISTICS

Unless otherwise specified: T_A=-40 to +85°C for min max specifications and T_A= 25°C for typical specifications.

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNIT

CURRENT CONSUMPTIONS ON LTS

IDD in “LTS protection mode” and “HRV low

mode”

I_{LTS_prot1}

Battery supervisory at 4Hz; VSUP and VAUX LDOs disabled

65

nA

IDD in “LTS protection mode”

IDD in “HRV low mode” STS and LTS connected

I_{LTS_prot2}

I_{HRV_lo2}

I_{HRV_lo3}

Battery supervisory at 4Hz; VSUP and VAUX LDOs disabled

Battery supervisory at 4Hz; ULP LDO enabled and VAUX LDO

disabled

15

145

170

nA

IDD in “HRV low mode” STS and LTS connected

IDD in “normal mode” STS and LTS

I_{HRV_lo4}

I_{HRV_lo5}

I_{HRV_lo6}

I_NORM

Battery supervisory at 4Hz; VSUP and VAUX[0] LDO enabled

Battery supervisory at 4Hz; VSUP and VAUX[1] LDO enabled

Battery supervisory at 4Hz; VSUP and VAUX[2] LDO enabled

Battery supervisory at 4Hz; VSUP and all VAUX LDO enabled

Battery supervisory at 4Hz; VSUP and VAUX LDOs disabled

(VDD_STS < VDD_LTS)

285

265

250

380

45

nA

disconnected

QUIESCENT CURRENT AND LEAKAGE ON STS (WHEN LTS IS NOT CONNECTED TO STS)

IDD in “HRV low mode”

I_{STS_hrvlo}

Battery supervisory at 4Hz; VSUP and VAUX LDOs disabled

65

nA

VSUP AND VAUX LDO VOLTAGE LEVEL

ULP/VAUX LDO level 0

ULP/VAUX LDO level 1

ULP/VAUX LDO level 2

ULP/VAUX LDO level 3

ULP/VAUX LDO level 4

ULP/VAUX LDO level 5

ULP/VAUX LDO level 6

ULP/VAUX LDO level 7

V_STS– V_SUP> 0.3V

1.08

1.39

1.48

1.62

1.8

1.98

2.16

2.34

1.2

1.55

1.65

1.8

2

2.2

2.4

2.6

1.32

1.71

1.82

1.98

2.2

2.42

2.64

2.86

V

MAXIMUM CURRENT ON THE ULP AND VAUX LDO

Maximum current on ULP LDO

Maximum current on VAUX[0] LDO

Maximum current on VAUX[1] LDO

Maximum current on VAUX[2] LDO

SWITCH RESISTOR

Drop from open voltage is 100 mV, LDO level at 1.8V

10

20

10

5

mA

VDD_LTS to VDD_STS

VDD_STS to VSUP

R_{sw_LTS_STS}

R_{sw_VSUP}

VDD_STS at 3V

3.1

7.4

4.4

5.8

6.4

Ω

VDD_STS to VAUX[0]

VDD_STS to VAUX[1]

VDD_STS to VAUX[2]

VAUX_GND[0] to VSS

VAUX_GND[1,2] to VSS

SUPERVISORY LEVELS ON STS, LTS AND HRV⁽¹⁾

Maximum voltage

R_{sw_VAUX0}

R_{sw_VAUX1}

R_{sw_VAUX2}

R_{sw_GND0}

R_{sw_GND1,2}

4.74

5.62

3.6

V

Level step from lvl0 to lvl15

Level step from lvl16 to lvl30 (1.24V to 2.26V)

V_{lvl_15}

V_{lvl_30}

73

mV

67.9

78.1

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PARAMETER

Level step from lvl31 to lvl54 (2.34V to 4.2V)

Differential non linearity

SYMBOL

V_{lvl_54}

CONDITIONS

MIN

69.4

TYP

73

±0.5

MAX

76.7

UNIT

mV

LSB

Number of levels

50

HARVESTER CURRENT LEVEL DETECTOR – LUX METER

Harvester current level step

Luxmeter current detection level

“lvl” = level used for the measurement [0..15]

Short circuit voltage

I_{hrv_check_lvl}

I_{lux_lvl}

1

µA

2^lvl

V_{hrv_scv}

70

mV

USB POWER

Minimum voltage for USB charging detection

Regulated voltage on VDD_STS

Current source level 0 on LTS

Current source level 1 on LTS

Current source level 2 on LTS

Current source level 3 on LTS

E2PROM PARAMETERS

E²PROM write time

V_{usb_min}

V_{USB_REG}

I_{USB_lvl0}

I_{USB_lvl1}

I_{USB_lvl2}

I_{USB_lvl3}

3.5

2.1

0

6.9

12.7

20.6

V

mA

T_{ee_wr}

T_{ee_rd}

N_{ee_cyc}

T_{hd_rd}

8

0.9

ms

E²PROM read time

E2PROM maximum write cycle

E2PROM read hold time

INTERFACE PARAMETERS

Input WAKE_UP - low level

Input WAKE_UP - high level

Wake-up rising edge reaction time

Wake-up falling edge reaction time

Input - low level

1000

0.9

10

µs

V_{il_wk}

V_{ih_wk}

T_{r_wk}

T_{f_wk}

V_{il_si}

V_LTS=1.2V to 3.6V

Debouncer disabled

V_SUP=1.2V to 3.6V

0.3

V

µs

V

4.5

120

0.2*

V_SUP

Input - high level

V_{ih_si}

V_SUP=1.2V to 3.6V

0.8*

V_SUP

3

1

V

Output – low level for I2C

Output – low level

I_{ol_sda}

I_{ol_sda_1.2}

I_ol

V_SUP=1.8V, Vol=0.2* V_SUP

V_SUP=1.20V, Vol=0.23*Vsup

V_SUP=1.8V, Vol=0.2*Vsup

mA

(MISO, MOSI_SDA, BAT_LOW, HRV_LOW)

V_SUP=1.20V, Vol=0.23*Vsup

(MISO, MOSI_SDA, BAT_LOW, HRV_LOW)

V_SUP=1.8V, Voh=0.8*Vsup

(MISO, MOSI_SDA, BAT_LOW, HRV_LOW)

V_SUP=1.2V, Voh=0.8*Vsup

(MISO, MOSI_SDA, BAT_LOW, HRV_LOW)

On MOSI_SDA and SCL

Output – low level

Output – high level

I_{ol_1.2}

I_oh

I_{oh_1.2}

C_b

1

mA

pF

-1

I²C bus load capacitor

SPI TIMINGS

400

SPI clock input frequency

SCL low pulse

SCL high pulse

MOSI_SDA setup time

MOSI_SDA hold time

MISO output delay

CS setup time

F_spi

T_{low_scl}

T_{high_scl}

T_{setup_mosi}

T_{hold_mosi}

T_{delay_miso}

T_{setup_cs}

T_{hold_cs}

5

MHz

ns

20

25pF load, V_SUP=1.6V min

25pF load, V_SUP=1.2V min

30

40

50

20

CS hold time

I²C TIMINGS⁽²⁾

MOSI_SDA setup time

t_sudat

t_hddat

Standard & Fast Modes

High Speed Mode

160

30

80

90

18

ns

MOSI_SDA hold time

Standard & Fast Modes with C_b=100pF Max.

Standard & Fast Modes with C_b=400pF Max

High Speed Mode with C_b=100pF Max.

High Speed Mode with C_b=400pF Max.

High Speed Mode with C_b=100pF Max.

V_SUP=1.62V

115

150

24

160

SCL low pulse

t_low

High Speed Mode with C_b=100pF Max. V_SUP=1.2V

210

ns

(1) The v_bat_min, v_bat_max, v_apl_min with their hysteresis can be set according to the supervising levels. E.g. for v_bat_max, both v_bat_max_lo and

v_bat_max_hi will have to be set accordingly.

(2) Refers to I²C specification 2.1 (January 2000)

Table 6 Electrical Specifications

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5.4. TIMING DIAGRAMS

5.4.1. SPI INTERFACE

CS

T_{hold_cs}

T_{setup_cs}

SCL

T_{low_scl}

T_{high_scl}

MOSI_SDA

MISO

T_{setup_mosi}

T_{hold_mosi}

T_{delay_miso}

Figure 5-1 4-wire SPI Timing Diagram

5.4.2. I2C INTERFACE

MOSI_SDA

t_buf

t_f

t_low

SCL

t_high

t_hdsta

t_r

t_hddat

t_sudat

MOSI_SDA

t_susta

t_susto

Figure 5-2 I²C Timing Diagram

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6.

PRODUCT CONFIGURATION

The EM8502 is an autonomous power management system able to manage power domains, power sources and storage elements.

At start-up the device enters a boot sequence. It controls the state of both energy storage elements, and sets the default configuration parameters

of the device by retrieving the corresponding values from the on-chip E²PROM.

Upon completion of the boot sequence the system enters the supervising and harvester controller state (“normal mode”). It is now possible to

modify configuration parameters through the serial interface to change the behavior of the device. When updating the device configuration through

the serial interface it is recommended to write the complete set of EM8502 configuration parameters in a single transaction (see §7).

EM8502 is able to operate autonomously by using default configuration values from the on-chip E²PROM.

6.1. STATUS INFORMATION

EM8502 provides status feed-back as follows.



To allow fast system response the pins HRV_LOW and BAT_LOW directly indicate the status of the harvester cell and the battery to

the host MCU.

Additional status information is provided through register reg_status. During an SPI transaction the reg_status value sent as the first

byte (along with the indication from the MCU of the address to be accessed). In case of an I2C transaction the reg_status register has

to be polled explicitly.

Register Name: reg_status

Bit name

Address: 0x22

Description

Bits

Type Reset



'1' EEPROM being written. Wait for new configuration

'0' EEPROM ready to be written. New configuration can be written

7

eeprom_data_busy

RO

0



'1' lux-meter or HRV current supervisory is running

‘0’ no current measurement on the harvester on-going.

6

5

hrv_lux_busy

hrv_low



'1' HRV energy level too low for harvesting

'0' HRV has enough energy to be harvested



'1' LTS voltage lower than v_bat_min_hi in normal mode, lower than

v_bat_min_lo in primary cell mode

‘0’ LTS voltage higher than v_bat_min_hi in normal mode, higher than

v_bat_min_lo in primary cell mode

4

bat_low

RO

0



'1' Solar cell connected to LTS

‘0’ Solar cell connected to STS

3

2

1

0

sw_solar_lts_nsts

sw_lts_sts

RO

0



'1' LTS and STS are connected

‘0’ STS is disconnected from LTS



'1' USB power has been detected

‘0’ No USB power found

usb_on



'1' LTS protection mode activated (V_LTS< v_bat_min_lo)

‘0’ LTS protection mode inactive (V_LTS> v_bat_min_lo)

lts_protect

Table 7 Status Register (0x22)

EM8502 offers great flexibility in being configured for different system applications and use cases. The following chapters provide detailed

descriptions of all configuration parameters and registers available to the user.

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6.2. SUPERVISING AND HARVESTER CONTROLLER BEHAVIOUR

6.2.1. STORAGE ELEMENT

Storage element voltage and state are available through the reg_vld_status register.

Reguster name: reg_vld_status

Address: 0x23

Description

Bits

Bit name

lts_bat_min_hi

Type Reset



'1' V_LTS> v_bat_min_hi

'0' V_LTS<= v_bat_min_hi

7

RO

0



'1' V_LTS> v_bat_min_lo

'0' V_LTS<= v_bat_min_lo

6

5

4

3

2

1

0

lts_bat_min_lo

sts_bat_max_hi

sts_bat_max_lo

sts_apl_max_hi

sts_apl_max_lo

sts_bat_min_hi

sts_bat_min_lo



'1' V_STS> v_bat_max_hi

'0' V_STS<= v_bat_max_hi



'1' V_STS> v_bat_max_lo

'0' V_STS<= v_bat_max_lo



'1' V_STS> v_apl_max_hi

'0' V_STS<= v_apl_max_hi



'1' V_STS> v_apl_max_lo

'0' V_STS<= v_apl_max_lo



'1' V_STS> v_bat_min_hi

'0' V_STS<= v_bat_min_hi



'1' V_STS> v_bat_min_lo

'0' V_STS<= v_bat_min_lo

Table 8 Voltage Status Register (0x23)

Operation of the two energy banks (LTS and STS) is performed through three key voltage threshold levels.



Minimum battery level voltage

Maximum battery level voltage

Maximum application level voltage

v_bat_min (reg_v_bat_min_hi_con or reg_v_bat_min_hi_dis and reg_v_bat_min_lo)

v_bat_max (reg_v_bat_max_hi and reg_v_bat_max_lo)

v_apl_max (reg_ v_apl_max_hi and reg_v_apl_max_lo)

The three levels include a hysteresis to avoid instability of the controller. The hysteresis values have to be carefully chosen according to the

application and have to fulfill the following conditions:



v_bat_min_hi_dis > v_bat_min_hi_con > v_bat_min_lo

v_apl_max_hi > v_apl_max_lo

v_bat_max_hi > v_bat_max_lo

If v_apl_max ≥ v_bat_max the application maximum level is considered to be the maximum battery level.

Supervising of the minimum battery level is performed through two registers for its highest control level (v_bat_min_hi). When the two battery

banks are not connected v_bat_min_hi_dis is used to inform the system when it has to charge STS again (see phase 4 to 5 in Error! Reference

ource not found. on page Error! Bookmark not defined.). When LTS and STS are connected together v_bat_min_hi_con is used as

supervising level.

The minimum value allowed for the v_bat_min_hi_dis register is 0x15 corresponding to typically 1.47 V. For any value lower than this minimum

the system may shut-down without notification through the BAT_LOW pin.

All voltage levels with prefix “v_” are configured by register according to the following equation:

v_<voltage name> = V_lvl* (reg_<voltage name>+1)

Supervisory status of the battery is also visible through the pin BAT_LOW. When the V_LTSis below v_bat_min_hi for two consecutive

measurements, BAT_LOW is asserted (set to VSUP level). When two measurements show that V_LTSis above v_bat_min_hi, BAT_LOW is de-

asserted (set to VSS). The only exception is during the boot phase where the BAT_LOW signal is asserted after the first measurement of V_LTS

.

The EM8502 protects the battery when its voltage is too low. This corresponding threshold level can be set through the v_bat_min_lo register.

When V_LTSis falling below this value the EM8502 operates only on the harvester.

6.2.2. HARVESTER POWER SUPERVISORY FUNCTIONS

The EM8502 monitors harvester power to prevent reverse current from the energy storage (LTS). The detection is done regularly

through a current sensor. The device is sensing the current at the voltage V_{hrv_scv}delivered by the solar cell. The current threshold of

detection is set through the reg_hrv_check_lvl.hrv_check_lvl register to disconnect the solar cell from the energy banks. To return to

the running state, the EM8502 detection is done with a different principle. The current measurement is done by connecting a resistance

on VDD_SOL and sense voltage on this pin using v_hrv_min voltage level.

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Resistances and currents are defined in reg_hrv_check_lvl.hrv_check_lvl:

reg_hrv_check_lvl.hrv_check_lvl 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F

Current (µA)

1

2

3

4

5

6

7

8

9

7

10

11

12

13

5

14

15

16

Resistance (kΩ)

35 23.3 17.5 14 11.7 10 8.75 7.8

6.36 5.38 5.4

4.7

4.4

Table 9 HRV Current Detection Levels

Configuration example:



reg_hrv_check_lvl =0x00; reg_v_hrv_cfg = 0x00

The system indicates HRV_LOW =’1’ from 1µA at V_{hrv_scv}(70mV) and remains off until V_lvlis reached with 35 kΩ load on VDD_SOL

(2 µA at V_lvl). A hysteresis of 1 µA is applied.

Register name: reg_v_hrv_cfg

Address: 0x04

Default value mapped in E²PROM

Description

Bits

7

Bit name

Type

–

Reserved

6

RW To be written always to ‘0’

Minimum HRV open voltage required to generate energy.

V_{hrv_min}= V_lvl* (reg_v_hrv_min(5:0)+1)

5:0

v_hrv_min

RW

if V_HRV< V_{hrv_min}and reg_v_hrv_cfg.hrv_check_vld = '1' then reg_status.hrv_low = '1'

Table 10 Minimum HRV voltage (0x04)

Register name: reg_hrv_check_lvl

Address: 0x05

Default value mapped in E²PROM

Description

Bits

Bit name

Type

7:4

–

Reserved

Minimum HRV short-cut current level to generate energy.

I_{hrv_check}= (hrv_check_lvl+1) * 1µA

3:0

hrv_check_lvl

RW

if I_HRV< I_{hrv_check}and reg_v_hrv_cfg.hrv_check_vld = '0' then reg_status.hrv_low = '1'

Table 11 Minimum HRV short-cut current (0x05)

6.2.3. TIMING CONFIGURATION

In addition to voltage level supervision, the user can select independent values for the frequency of supervision on LTS, STS and the harvester.

The frequency influences the overall EM8502 power consumption and therefore its efficiency.

The STS and LTS measurement periods are set through the registers reg_t_sts_period and reg_t_lts_period. The monitoring of the harvester

however requires disconnecting the solar cell and the storages in order to measure the short-cut current. The duration of the disconnect time is

configured through the reg_t_hrv_meas register, whereas the measurement period is configured through the reg_t_hrv_period register.

Register value

t_hrv_meas

t_hrv_period

t_sts_period

t_lts_period

t_hrv_low_period

t_lts_hrv_low_period

0x00

0x01

16 ms

32 ms

256 ms

512 ms

1 ms

2 ms

1 ms

4 ms

256 ms

512 ms

2 ms

8 ms

32 ms

128 ms

512 ms

2 s

0x02

0x03

0x04

0x05

0x06

0x07

64 ms

128 ms

256 ms

512 ms

1 s

2 s

8 ms

16 ms

32 ms

64 ms

128 ms

256 ms

16 ms

64 ms

256 ms

1 s

2 s

4 s

8 s

16 s

32 s

4 s

16 s

32 s

8 s

2 s

16 s

32 s

Table 12 Timing Configuration

When entering in “HRV low mode” the monitoring on LTS and the harvester remains active, however the monitoring frequency can be adapted to

this situation where the system cannot take energy anymore from the harvester source. The measurement period is then set in parameter

t_hrv_low_period. In this mode STS is not fed by the harvester anymore. If STS and LTS are not connected internally, STS will collapse. No

monitoring is performed on STS.

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6.3. POWER MANAGEMENT FUNCTIONS

The EM8502 controls four independent power supply outputs.

The VSUP power supply output is connected to STS when STS level is within the application voltage range ([v_bat_min:v_apl_max]) or to an

LDO (when above v_apl_max) to regulate the output to a given value.

The three auxiliary supply outputs VAUX [0:2], are user configurable between STS and the internal LDO. It is possible to force the use of the LDO

even though the STS voltage level is compatible with the application supply requirements.

During the boot phase – which corresponds to the set-up of the device – all the power supply outputs are floating. Once the set-up of the registers

is completed the supply output values are determined by configuration registers reg_ldo_cfg.vsup_tied_low and reg_vaux_cfg.vaux[x]_cfg.

The main application power supply (VSUP) is intended to be connected to the application controller. When connected to the LDO its maximum

power is limited as LDO is optimized for low consumption. The VSUP supply output is controlled by the reg_ldo_cfg register.

The value of the LDO is configurable through reg_ldo_cfg.v_ulp_ldo. The LDO enable can be forced with reg_ldo_cfg.frc_ulp_ldo. In “sleep state”,

VSUP can be grounded (reg_ldo_cfg.vsup_tied_low = ‘1’) or floating (reg_ldo_cfg.vsup_tied_low = ‘1’) (see §6.4).

The individual configurability of the three auxiliary supply outputs allows the creation of different power domains for the external application. The

auxiliary outputs are split into the supply and ground pins where all six outputs can be switched on/off independently.

The behavior of the VAUX pins is controlled through the reg_vaux_cfg register. reg_vaux_cfg.v_aux_ldo controls the level of the single LDO

connected to the three auxiliary supplies.

When switched on (reg_pwr_mgt.vaux[i]_en = ‘1’) the auxiliary supply output is controlled by reg_vaux_cfg.vaux[i]_cfg.

Four possible settings are available to the user:

1) Force the connection to STS

2) Force the connection to the LDO

3) Use the automatic configuration permitting the auxiliary output to float when STS drops below v_bat_min

4) Use the automatic configuration grounding the auxiliary output when STS drops below v_bat_min

The automatic configuration of the auxiliary supplies is ensures that the auxiliary output voltage is kept within the application voltage range by

auto-connecting the supply output to the LDO when STS voltage is exceeding the v_apl_max value.

When the power supply output is switched off (reg_pwr_mgt.vaux[i]_en = ‘0’), its configuration is also controlled by the reg_pwr_mgt.vaux[i]_cfg

register. The output is grounded if reg_pwr_mgt.vaux[i]_cfg is set to 3 (b11), otherwise it is kept floating.

When the LDO is used on VSUP or VAUX pins, changing the LDO settings does not generate over or under shoots on the output power supply

terminals.

EM8502 offers the possibility to control the ground pin as part of the application, by connecting it to the ground of the EM8502 or letting it float. It

is of particular interest when involving applications that are using I²C communication through the pulls of the I²C lines. The configuration of the

VAUX_GND pins is controlled through the reg_pwr_mgt.vaux_gnd[i] en register.

Register name: reg_ldo_cfg

Bit name

Address: 0x0E

Default value mapped in E²PROM

Description

Bits

Type

RW When set to '1', connects VSUP pin to ground when VSUP is disabled, otherwise VSUP

remains floating.

7

vsup_tied_low

RW VAUX LDO regulated voltage selection



"000" (0)

"001" (1)

"010" (2)

"011" (3)

"100" (4)

"101" (5)

"110" (6)

"111" (7)

1.2 V

1.55 V

1.65 V

1.8 V

2.0 V

2.2 V

2.4 V

2.6 V

6:4

v_vaux_ldo

frc_ulp_ldo

v_ulp_ldo

3

RW Force ULP LDO on as soon as V_STS> v_bat_min_hi

RW ULP LDO regulated voltage selection



"000" (0)

"001" (1)

"010" (2)

"011" (3)

"100" (4)

"101" (5)

"110" (6)

"111" (7)

1.2 V

1.55 V

1.65 V

1.8 V

2.0 V

2.2 V

2.4 V

2.6 V

2:0

Table 13 VSUP output supply and LDOs configuration register (0x0E)

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Register name: reg_pwr_cfg

Bit name

Address: 0x0F

Default value mapped in E²PROM

Description

Bits

Type



'1' Disable USB LDO after boot sequence even if usb_crt_src_sel is > 0x0

‘0’ Keep the default behavior on USB LDO

7

usb_ldo_frc_dis

RW



'1' open the VAUX_GND[2] (pin is floating) in "HRV low" mode.

'0' Keep the same behavior as in normal mode

6

dis_vaux_gnd2_hrv_low

RW

5

4

dis_vaux_gnd1_hrv_low

dis_vaux_gnd0_hrv_low

RW "HRV low" mode VAUX_GND[1] behavior. same as for pin VAUX_GND[2]

RW "HRV low" mode VAUX_GND[0] behavior. same as for pin VAUX_GND[2]



'1' Disable vaux[2] in "HRV low" mode. It is configured by reg_vaux_cfg.vaux2_cfg

'0' Keeps its normal mode configuration.

3

dis_vaux2_hrv_low

RW

2

1

dis_vaux1_hrv_low

dis_vaux0_hrv_low

RW "HRV low" mode VAUX[1] behavior. same as for pin VAUX[2]

RW "HRV low" mode VAUX[0] behavior. same as for pin VAUX[2]



'1' Disable VSUP in "HRV low" mode. Its behavior is defined by

reg_ldo_cfg.vsup_tied_low

'0' Keeps its normal mode configuration

0

dis_vsup_hrv_low

RW

Table 14 "HRV low" mode power switch configuration register (0x0F)

Register name: reg_vaux_cfg

Address: 0x10

Default value mapped in E²PROM

Description

Bits

Bit name

Type

7:6

–

Reserved

vaux2_cfg

RW Configuration of VAUX[2] pin



"00" (0) Constantly connected to STS

"01" (1) Constantly connected to the LDO

"10" (2) Automatic configuration – floating when below V_STS< v_bat_min

"11" (3) Automatic configuration – grounded when below V_STS< v_bat_min

5:4

If VAUX[2] is disconnected – VAUX[2] is connected to ground if the value is "11", otherwise

it is floating

3:2

1:0

vaux1_cfg

vaux0_cfg

RW Configuration of VAUX[1] pin – same as for VAUX[2] pin

RW Configuration of VAUX[0] pin – same as for VAUX[2] pin

Table 15 Auxiliary supply configuration register (0x10)

Register name: reg_vaux_gnd_cfg

Address: 0x11

Default value mapped in E²PROM

Description

Bits

7:3

2

Bit name

Type

–

Reserved

vaux_gnd2_cfg

RW



'1' Auto disconnect when V_STSnot within [v_bat_min.. v_apl_max]

'0' Fully manual connection

1

0

vaux_gnd1_cfg

vaux_gnd0_cfg

RW Configuration of VAUX_GND[1] pin – same as for VAUX_GND [2] pin

RW Configuration of VAUX_GND[0] pin – same as for VAUX_GND[2] pin

Table 16 Auxiliary ground pins configuration register (0x11)

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Register name: reg_pwr_mgt

Address: 0x19

Value at start-up mapped in E²PROM

Bits

7

Bit name

Type

Description

–

To be written always to ‘0’

6

vaux_gnd2_en

RW Enable the VAUX_GND[2] connection (see reg_vaux_gnd_cfg.vaux_gnd2_cfg) when V_STS

v_bat_min_hi

>

5

4

vaux_gnd1_en

vaux_gnd0_en

RW Enable the VAUX_GND[1] connection (see reg_vaux_gnd_cfg.vaux_gnd0_cfg) when V_STS

v_bat_min_hi

RW Enable the VAUX_GND[0] connection (see reg_vaux_gnd_cfg.vaux_gnd0_cfg) when V_STS

v_bat_min_hi

3

2

1

0

vaux2_en

vaux1_en

vaux0_en

sleep_vsup

RW Enable the VAUX[2] connection (see reg_vauxcfg.vaux2_cfg) when V_STS> v_bat_min_hi

RW Enable the VAUX[1] connection (see reg_vauxcfg.vaux1_cfg) when V_STS> v_bat_min_hi

RW Enable the VAUX[0] connection (see reg_vauxcfg.vaux0_cfg) when V_STS> v_bat_min_hi

RW Enable the VSUP "sleep state" – disconnects VSUP for t_sleep_vsup interval

Table 17 Power switch enable register (0x19)

6.4. SLEEP MODE AND WAKE-UP FUNCTIONS

In addition to the direct control of the power supply outputs the EM8502 supports stopping supplying the application (switching off VSUP) for a

given time interval to allow very low consumption modes. When enabled, the auxiliary supplies are kept in the same state as before entering in

the “sleep state”. The “sleep state” is not a functional mode of the power management unit, as the device is still working according to the

configuration parameters set and is only acting on the state of the VSUP supply output.

The “sleep state” can also be interrupted (VSUP is connected again on STS or on the LDO according to the settings of the VSUP power switch

see Table 13) by setting the WAKE_UP pin to a level above V_{ih_wk}

.

During “sleep state” the serial interface is disabled.

To avoid false wake-up detection, a debouncing logic is connected to the WAKE_UP pin. The debouncer function is enabled by default (factory

default value on E²PROM), and can be disabled by setting the reg_ext_cfg. wake_up_deb_en to ‘0’. The wake-up is sensitive to the edge

configured in reg_ext_cfg.wake_up_edge_cfg. It is not permitted to set reg_ext_cfg.wake_up_edge_cfg = “00”.

Register name: reg_ext_cfg

Bit name

Address: 0x13

Default value mapped in E²PROM

Description

Bits

Type

RW MOSI_SDA pad slope control

7

sda_slopectrl



‘0’ for standard and fast I2C mode, and high speed mode if VSUP < 1.8V

‘1’ for high speed mode if VSUP > 1.8V

6

wake_up_deb_en

RW When at '1' the wake-up debouncer is enabled

5:4

wake_up_edge_cfg

RW “00” (0x0): Forbidden

“01” (0x1): wake-up on falling edge

“10” (0x2): wake-up on rising edge

“11” (0x3): wake-up on both edge

3

2

usb_frc_hrv_low_hiz

usb_frc_bat_low_hiz

usb_crt_src_sel

RW

See Table 24 USB Configuration Register (0x13)

1:0

Table 18 Wake-up terminal configuration register (0x13)

The “sleep state” duration is controlled through a 24-bit counter (reg_t_sleep_vsup[23:0]). VSUP supply can be interrupted for up to 4 hours,

with a granularity of 1 ms.

t_sleep_vsup = reg_t_sleep_vsup[23:0]/1000 seconds

When VSUP is in “sleep state” it is possible to ground VSUP to create a known voltage level on the main controller supply, by setting

reg_ldo_cfg.vsup_tied_low to ‘1’ (see above in page 13).

The VSUP “sleep state” is enabled by setting reg_pwr_mgt.sleep_vsup to ‘1’ (see Table 17 bit 0).

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Register name: reg_t_sleep_vsup_lo

Bits Bit name Type

7:0 t_sleep_vsup_lo RW Sleep counter duration – least significant byte

Address: 0x14

Default value mapped in E²PROM

Description

Table 19 VSUP "sleep state" counter time-out Least significant byte (0x14)

Register name: reg_t_sleep_vsup_mid

Bits Bit name Type

7:0 t_sleep_vsup_mid

Address: 0x15

Default value mapped in E²PROM

Description

RW Sleep counter duration – byte 2

Table 20 VSUP "sleep state" counter time-out middle significant byte (0x15)

Register name: reg_t_sleep_vsup_hi

Bits Bit name Type

7:0 t_sleep_vsup_hi RW Sleep counter duration – most significant byte

Address: 0x16

Default value mapped in E²PROM

Description

Table 21 VSUP "sleep state" counter time-out Most significant byte (0x16)

6.5. LUX-METER

The device contains a specific element to determine ranges of current supplied by the solar cell.

The lux-meter is able to run in three modes:



Fully automatic mode

Automatic range selection

Fully manual mode

In fully automatic mode (selected by writing ‘1’ in reg_lux_meter_cfg.lux_meter_auto_meas) the device determines the value range for the current

flowing in from the solar cell. The result is available in the reg_lux_meter_result.lux_meter_result register field. The

reg_lux_meter_result.lux_meter_busy bit indicates that the measurement is still ongoing and that the result is not available yet.

In automatic range selection mode (selected by writing ‘1’ in reg_lux_meter_cfg.lux_meter_auto_rng) the EM8502 automatically determines the

optimal range, and measures the voltage at VDD_SOL for maximum precision. The reg_lux_meter_result.lux_meter_busy bit indicates that the

range search is complete. In this mode lux-meter continues to operate until user disabled by writing ‘0’ into the

reg_lux_meter_cfg.lux_meter_auto_rng.

The full manual mode allows the user to select the range. The mode is selected by writing on the bit reg_lux_meter_cfg.lux_meter_manu – ‘1’ to

activate the mode, and ‘0’ to deactivate it. The selection of the range is done through the reg_lux_meter_cfg.lux_meter_rng field.

In case a lux-meter action is requested with LTS and STS disconnected, V_LTS< v_bat_min_lo the action is disregarded and the result – in

automatic mode – is invalid.

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Register name: reg_lux_meter_cfg

Bit name Type Reset

Address: 0x1C

Description

Bits

7

–

0

Reserved

Start the automatic lux-meter measurement. The lux-meter is disabled

automatically when the measure is finished

6

lux_auto_meas

OS

5

4

lux_auto_rng

lux_manu

RW

0

Enable the lux-meter, and search for the best range. It remains enabled

Enable the lux-meter in manual mode (range forced by reg_lux_meter_cfg.lux_lvl)

Target current level to be detected



"0000" (0x0)

"0001" (0x1)

"0010" (0x2)

"0011" (0x3)

"0100" (0x4)

"0101" (0x5)

"0110" (0x6)

"0111" (0x7)

"1000" (0x8)

"1001" (0x9)

"1010" (0xA)

"1011" (0xB)

"1100" (0xC)

"1101" (0xD)

"1110" (0xE)

"1111" (0xF)

1 µA

2 µA

4 µA

8 µA

15 µA

30 µA

60 µA

120 µA

0.25 mA

0.5 mA

1 mA

1.8 mA

3.2 mA

6 mA

3:0

lux_lvl

RW

0x0

11 mA

17 mA

Table 22 Lux Meter Configuration Register (0x1C)

Register name: reg_lux_meter_result

Bit name Type Reset

Address: 0x1D

Description

Bits

7:5

4

–

'000' Reserved

lux_meter_busy

RO

0

Indicates that the lux-meter is still searching for best range

Lux-meter range status (result in automatic measurement mode)



"0000" (0x0)

"0001" (0x1)

"0010" (0x2)

"0011" (0x3)

"0100" (0x4)

"0101" (0x5)

"0110" (0x6)

"0111" (0x7)

"1000" (0x8)

"1001" (0x9)

"1010" (0xA)

"1011" (0xB)

"1100" (0xC)

"1101" (0xD)

"1110" (0xE)

"1111" (0xF)

below 2 µA

from 2 µA to 4 µA

from 4 µA to 8 µA

from 8 µA to 15 µA

from 15 µA to 30 µA

from 30 µA to 60 µA

from 60 µA to 120 µA

from 120 µA to 0.25 mA

from 0.25 mA to 0.5 mA

from 0.5 mA to 1 mA

from 1 mA to 1.8 mA

from 1.8 mA to 3.2 mA

from 3.2 mA to 6 mA

from 6 mA to 11 mA

from 11 mA to 17 mA

above 17 mA

3:0

lux_meter_result

RO

0x0

Table 23 Lux-meter Result Register (0x1D)

6.6. USB CHARGING

The EM8502 is equipped with a USB power line input to supply the device and to charge has the energy bank elements.

When a voltage above V_{usb_min}is detected, a regulator between VDD_USB and VDD_STS is enabled. The regulated voltage is V_{USB_REG}. In addition

to the regulator, a current source is activated between VDD_USB and VDD_LTS. This function is controlled by the reg_ext_cfg register. Four user

selected level of charge current delivered to LTS are available (reg_ext_cfg.usb_crt_src_sel).

When VDD_USB is connected, pins HRV_LOW and BAT_LOW can be brought into HiZ state.

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Register name: reg_ext_cfg

Bit name

Address: 0x13

Default value mapped in E²PROM

Description

Bits

7

Type

RW

sda_slopectrl

6

wake_up_deb_en

wake_up_edge_cfg

usb_frc_hrv_low_hiz

5:4

3



‘1’ force HRV_LOW in Hi-Z state if usb_on = '1'

‘0’ HRV_LOW pin standard configuration

2

usb_frc_bat_low_hiz

usb_crt_src_sel

RW



‘1’ force BAT_LOW in Hi-Z state if usb_on = '1'

‘0’ BAT_LOW pin standard configuration

1:0

RW USB power current source selection



"00" (0x0)

"01" (0x1)

"10" (0x2)

"11" (0x3)

0 mA

5 mA

10 mA

20 mA

(do not charge)

Table 24 USB Configuration Register (0x13)

Warning: When VDD_LTS is to be disconnected from its load, the USB current injected into LTS must be set to 0 mA, otherwise the device

could be damaged.

6.7. MISCELLANEOUS FUNCTIONS

This chapter describes additional control functions related to the regulation loop.

6.7.1. SOFT RESET FUNCTION

The soft reset function restarts the EM8502 from its boot sequence. The behavior of the EM8502 is the same as in a normal boot sequence. A

soft reset is generated by setting the register reg_soft_res_word to 0xAB. This register is enabled only if reg_protect_key is set to 0xE2. If the

value of the reg_protect_key is different from 0xE2, the register reg_soft_res_word is set to 0x00.

The reg_protect_key register is reset by the soft reset. Creating a new soft sequence requires preloading the reg_protect_key again.

Register name: reg_soft_res_word

Bit name Type Reset

soft_res_word

Address: 0x1A

Description

Bits

7:0

RW

0x00 Force reset when set at 0xAB

Table 25 Soft reset register (0x1A)

Register name: reg_protect_key

Bit name Type Reset

Address: 0x1B

Description

Bits

Allow writing on reg_soft_res_word register when set at 0xE2

0x00 Allow writing on protected registers when set at 0x4B

Allow writing on E2PROM when set at 0xA5

7:0

protect_key

RW

Table 26 Protected registers key (0x1B)

6.7.2. REGISTER PROTECTION

The EM8502 functionality is determined by the content of the configuration registers (like the supervising levels or periods). The registers are

always accessible in read mode. Some registers are write protected against unwanted write operations.

The registers ranging is address space from 0x00 to 0x18 are write protected. Writing into these registers is enabled after setting reg_protect_key

to 0x4B.

Note: The reg_protect_key is reset at the end of the communication transaction (see §7 on page 19). It is necessary to set it on the same

communication transaction – on SPI keeping CS to ‘1’ or on I²C before putting an I²C stop.

Write access to the on-chip E²PROM is controlled by the same mechanism. Prior to a write operation into the E²PROM reg_protect_key must be

set to 0xA5.

6.7.3. LTS PROTECTION DISABLE

By default the EM8502’s monitors voltage levels, namely lower voltage limit, to prevent damage to the LTS energy storage element.

This protection can be disabled by setting register reg_lts_cfg.no_bat_protect leaving the system connected to LTS even when the voltage level

drops below v_bat_min. Disabling protection might be suitable for systems using super-caps or solid-state battery storage elements.

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When LTS protection is active the EM8502 tries to start-up from LTS only once, if after booting it still detects that V_LTS< v_bat_min it enables the

protection and never try to restart from LTS. The system will then re-start as from a standard cold-start.

Register name: reg_lts_cfg

Address: 0x06

Default value mapped in E²PROM

Description

Bits

7:3

2

Bit name

Type

–

Reserved

–

Shall be written to ‘0’

1

–

Shall be written to ‘0’

0

no_bat_protect

RW



'1' disables the battery protection feature. (reg.status.lts_protect = ‘0’)

‘0’ enables the battery protection feature.

Table 27 Wake-up terminal configuration register (0x13)

7.

SERIAL INTERFACE

The EM8502 offers SPI and I²C serial interfaces selected by the CS pin (see §7.2.1).

The configuration/function of the EM8502 is updated only after the end of a communication transaction. An SPI transaction is defined by all the

bytes sent and received when the pad CS is kept to ‘1’. An I²C transaction is defined by all the data sent or received between a start and a stop

or repeated start I²C patterns.

Data synchronization between the communication interface and the internal part of the device is done at the end of a supervising loop. New

information is active two milliseconds after the end of the transaction. All write transactions sent before the end of this synchronization interval are

ignored. It is recommended to perform the device configuration in one transaction. Read transactions are allowed at any time.

7.1. I2C INTERFACE

The I²C slave interface is compatible with Philips I²C Specification version 2.1 (see specific timings on electrical specifications chapter). All modes

(standard, fast, high speed) are supported. MOSI_SDA and SCL pins are not strictly open-drain (they represent diodes to VSUP).

The 7-bit device address is defined in the E²PROM (at address 0x58). This address is copied at boot into the reg_spi_i2c_cfg.ic2_addr register

field.

The I²C bus uses the 2 wires SCL (Serial Clock) and MOSI_SDA. CS has to be connected to VSS. MOSI_SDA is bi-directional with open drain to

VSS: it must be externally connected to VSUP via a pull up resistor.

The I2C interface supports single and multiple read and write transactions.

In the following figures, “S” indicates the I²C transaction start, “P” indicates the I²C transaction stop.

The multi-read and multi write transactions are described in the following figures.

ACKS

MOSI_SDA

SCL

Address/data couple to be

written

i²c address

Register address (n)

Register value to be written @ n

P

S

Write

Figure 7-1: I2C write (multiple transactions)

To access registers in read mode, first address should first be send in write mode. Then a stop and a start conditions must be generated and

data bytes are transferred with automatic address increment:

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ACKS

MOSI_SDA

SCL

i²c address

Register address (n)

Write

ACKS

ACKM

NOACKM

MOSI_SDA

SCL

i²c address

P

Register read @ n+1, n+2, ...

Register read @ n

Figure 7-2: I2C read (multiple transactions)

S

Read

In the case of a read transaction, it is possible to avoid stopping and starting again a new transaction by following the register address with a

repeated start.

7.2. SPI INTERFACE

The SPI interface is a standard Serial to Peripheral Interface. It is compatible with two of the four standard transmission modes. The automatic

selection between the two modes ([CPOL=’0’ and CPHA=’0’] and [CPOL=’1’ and CPHA=’1’]) is determined by the value of SCL after the CS rising

edge.

The SPI interface can be used in 4-wire or 3-wire. The 3-wire is selected by setting the register reg_spi_i2c_cfg.spi_3w_en to '1’. The pin MOSI

is used as a data pin in 3-wire mode.

The SPI interface is a byte-oriented transmission interface. The first byte sent is contains the address of the register and access type of the

transmission – on the first transmitted bit (reads register – ‘1’ – or writes register – ‘0’). The following bytes contain register values. On read access

the address read is incremented for each additional byte until the address 0x7F. When reaching this address, the devices internal address counter

wraps to 0x00 and starts to read again from this address.

In case of a write transaction the protocol is based on an interleaved scheme of address and data. The first byte contains a 7-bit address and the

write command (First sent bit of the first byte equal to ‘0’). The second byte contains data to be written to this address.

It is important to note that it is possible to send a set of write commands, followed by a multi read transaction within the same SPI transaction.

Once in read mode, write accesses are not possible anymore in the same SPI transaction.

The following example shows a write of some registers followed by a check of the data.

0x00

0x05

0x01

0x03

0x06

0x02

0x80

0x00

Set hrv_period to 1/8 Hz

Set hrv_meas to 128ms

Set the system in primary cell mode

Read registers 0x00 to 0x03

CS

SCL

MOSI_SDA

MISO

R_Wn

ST7

AD6

ST6

AD5

ST5

AD4

ST4

AD3

ST3

AD2

ST2

AD1

ST1

AD0

ST0

DI7

DI6

DI5

DI4

DI3

DO3

DI2

DO2

DI1

DI0

DO7

DO6

DO5

DO4

DO1

DO0

Figure 7-3 SPI transaction scheme CPOL=1, CPHA=1

CS

SCL

MOSI_SDA

MISO

R_Wn

ST7

AD6

ST6

AD5

ST5

AD4

ST4

AD3

ST3

AD2

ST2

AD1

ST1

AD0

ST0

DI7

DI6

DI5

DI4

DI3

DO3

DI2

DO2

DI1

DO1

DI0

DO0

DO7

DO6

DO5

DO4

Figure 7-4 SPI transaction scheme CPOL=0, CPHA=0

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CS

SCL

address

status

address

data to be written

MOSI_SDA

MISO

data to be written in 'x',

output at '0'

address "x", access type (write)

and status byte

Next address/data couple

other address/data couple

MOSI_SDA

MISO

address "n"

status

data @ n

data @ n+1

data @ n+2

data @ x

address "x", access type (read)

and status byte

Figure 7-5 Multi register access transaction

Along with the address information the SPI interface sends the status register (reg_status – address 0x22) as the first response byte. In the case

of the 3-wire mode the protocol is identical to the I²C interface, and doesn’t allow having the status byte when sending the address to the device.

Interface signals are the following:



CS

SCL

MOSI_SDA

MISO

chip select, active high

clock

data input; data input/output in 3-wire mode

data output; Hi-Z level in 3-wire mode

7.2.1. INTERFACE SELECTION

The interface selection process is done through the use of the CS pin.

At reset (at the end of the boot sequence) the default interface selection is I²C. The SPI selection is done by asserting the CS pin. After CS

assertion the SPI interface is selected until the device is shut-down (V_STSbelow V_{cs_lo}).

If the CS pin is continuously asserted (through a hard connection to VSUP) the SPI interface is permanently selected. I²C is not available in this

case.

Register name: reg_spi_i2c_cfg

Address: 0x18

Default value mapped in E²PROM

Description

Bits

7

Bit name

spi_3w_en

Type

RW Set the SPI in its 3 wire mode (shared MOSI/MISO)

RW i2c address

6:0

i2c_addr

Table 28 SPI/I2C configuration register (0x18)

7.3. E2PROM

7.3.1. ACCESSING THE E2PROM

The on-chip E²PROM contains the default working parameters of the device. The E²PROM address space is mapped into the EM8502 register

map from address 0x40 (E²PROM address 0) to 0x7F ((E²PROM address 63). Some addresses are reserved (0x76 to 0x7F) and are accessible

in read-only mode by the user; some contains the defaults values – as described on §8. All other addresses can be freely used.

The user can write on the E²PROM at any time. Note that no protection is built in to prevent incomplete write transaction caused by a lack of

energy (STS too low). The user must ensure that the EM8502 is able to properly finish a write transaction.

Read and write accesses are performed through the serial interface. In difference to standard registers (addresses 0x00 to 0x3F), an E²PROM

access requires a dead time. A read access needs a dead time between read address and the data. A write access requires a dead time after

having sent the write data.

CS

SCL

MOSI_SDA

MISO

T_{ee_rd}

Figure 7-6 SPI transaction for reading the E²PROM (CPOL=1)

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CS

SCL

MOSI_SDA

MISO

T_{ee_rd}

Figure 7-7 SPI transaction for reading the E²PROM (CPOL=0)

CS

SCL

MOSI_SDA

MISO

address "n"

status

address "m"

data @ n

status

data @ m

T_{ee_rd}

T_{hd_rd}

Table 29 SPI multiple E²PROM read transactions

CS

SCL

0x1B

0xA5

E²PROM address

data

0x1B

0xA5

E²PROM address

data

MOSI_SDA

MISO

status

T_{ee_wr}

Figure 7-8 Two consecutive single E²PROM write SPI transactions

CS

SCL

MOSI_SDA

MISO

0x1B

0xA5

E²PROM address

data

E²PROM address

data

status

T_{ee_wr}

Figure 7-9 SPI multi-byte transaction for writing the E²PROM

When the I²C serial interface is used only single action per transaction is allowed when accessing the E²PROM. As for an SPI transaction a

dead time are necessary. Prior to a write transaction into the E²PROM it is necessary to set the reg_protection_key register to 0xA5.

For a write transaction, no other I²C transaction into the E²PROM address area is allowed for T_{wr_ee}after the end of the write transaction. A

transaction inside this time window is ignored by the device.

In the following diagram responses from EM8502 are shown in red, data from the I²C master in black.

The following abbreviations are used:



W

R

S

P

A

N

Write transaction request

Read transaction request

Start an I²C transaction

Stop an I²C transaction

I²C Acknowledge

I²C Non Acknowledge

S

I²C address

W

0x1B

0xA5

reg address

reg data

P

S

I²C address

W

0x1B

0xA5

reg address

A

reg data

P

A

MOSI_SDA

SCL

T_{ee_wr}

Figure 7-10 I²C transaction for writing on the E²PROM

For a read transaction a dead-time (T_{rd_ee}) has to be inserted in between the address setting transaction and the read action itself.

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S

I²C address

W

A

Register address

A

P

S

I²C address

R

A

Read data

N P

MOSI_SDA

SCL

T_{ee_rd}

Figure 7-11 I²C transaction for reading the E²PROM

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8.

REGISTER MAP

Table 30 Register summary with default value defined in E²PROM

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Table 31 Register summary – No E²PROM default values

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Table 32 E²PROM default values memory mapping

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9.

TYPICAL APPLICATION

V_SOL

VDD_SOL

EM8502

VDD_STS

C_HRV

C_STS

VSS2

VDD_USB

Cold-start Booster

WAKE_UP

VDD_LTS

VREG

VSUP

C_REG

C_LTS

MPPT

Boost

Controller

controller

MOSI_SDA

MISO

Battery

(typically secondary cell)

VAUX[2]

SCL

C_SUP

HOST

MCU

CS

VAUX[1]

VAUX[0]

BAT_LOW

HRV_LOW

Peripheral

(sensor, RF

transmitter, …)

Charge control and

supervisory

VAUX_GND[2]

VAUX_GND[1]

VAUX_GND[0]

C_AUX0

Other

peripherals

VSS1

I²C interface

SPI interface

Figure 9-1 Example of Application with a Solar Cell Harvester

Symbol

Component

Value

Harvester capacitor

STS capacitor

Regulator capacitor

Main supply output capacitor

Auxiliary (2) supply output capacitor

C_HRV

C_STS

C_REG

C_SUP

C_AUX2

4.7µF

200µF

470 nF

1 µF

Table 33 Component list for solar cell application

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10. PACKAGING INFORMATION

10.1. QFN24 4X4 PACKAGE

QFN24 4x4mm

D

MIN

NOM

MAX

e

L

0.5

0.45

0.18

2.5

0.5

0.55

0.3

b

0.25

2.6

D2

E2

A

2.7

E

2.5

2.6

2.7

0.85

0.02

0.20

0.20min

4.0

0.9

A1

A3

K

0.05

TOP VIEW

D

A

E

4.0

A3

A1

SIDE VIEW

L1

0.15max

ALL DIMENSIONS ARE IN MILLIMETERS

D2

K

D2/2

SEE DETAIL "A"

L

E2/2

5 * e

E2

K

TERMINAL/SIDE

2

1

L

L1

b

e

PIN #1 ID

e

SEE DETAIL "A"

e/2

DETAIL "A"

TERMINAL TIP

5 * e

BOTTOM VIEW

Figure 10-1 QFN24 Mechanical Information

10.1.1. PACKAGE MARKING

This section reports the package marking for EM8502. Additional marking letters and numbers are used for lot traceability.

8

0

5

0

2

0

A

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EM Microelectronic-Marin SA (“EM”) makes no warranties for the use of EM products, other than those expressly contained in EM's applicable

General Terms of Sale, located at http://www.emmicroelectronic.com. EM assumes no responsibility for any errors which may have crept into

this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any

commitment to update the information contained herein.

No licenses to patents or other intellectual property rights of EM are granted in connection with the sale of EM products, neither expressly nor

implicitly.

In respect of the intended use of EM products by customer, customer is solely responsible for observing existing patents and other intellectual

property rights of third parties and for obtaining, as the case may be, the necessary licenses.

Important note: The use of EM products as components in medical devices and/or medical applications, including but not limited to,

safety and life supporting systems, where malfunction of such EM products might result in damage to and/or injury or death of

persons is expressly prohibited, as EM products are neither destined nor qualified for use as components in such medical devices

and/or medical applications. The prohibited use of EM products in such medical devices and/or medical applications is exclusively at

the risk of the customer.

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8502-DS, Version 1.1, 8-Mar-17

420005-A01, 2.0


型号：	EM8502
厂家：	EM MICROELECTRONIC - MARIN SA
描述：	POWER MANAGEMENT CONTROLLER WITH MULTI-CELL SOLAR HARVESTING
文件：	总29页 (文件大小：1419K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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