EM7645FV8EU-85L [EMLSI]
256K x16 bit Low Power and Low Voltage Full CMOS Static RAM; 256K X16位低功耗和低电压全CMOS静态RAM
| 型号： | EM7645FV8EU-85L |
| 厂家： | 
Emerging Memory & Logic Solutions Inc |
| 描述： | 256K x16 bit Low Power and Low Voltage Full CMOS Static RAM |
| 文件： | 总11页 (文件大小：82K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EM640FV16FW Series
Low Power, 256Kx16 SRAM
Document Title
256K x16 bit Low Power and Low Voltage Full CMOS Static RAM
Revision History
RevisionNo. History
Draft Date
Remark
0.0
Initial Draft
August 13 , 2003
Emerging Memory & Logic Solutions Inc.
4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Zip Code : 690-719
Tel : +82-64-740-1712 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com
The attached data sheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your
questions about device. If you have any questions, please contact the EMLSI office.
1
EM640FV16FW Series
Low Power, 256Kx16 SRAM
256K x16 Bit Low Power and Low Voltage CMOS Static RAM
FEATURES
- Process Technology : 0.18µm Full CMOS
- Organization :256K x16
- Power Supply Voltage
=> EM640FV16FW : 2.7~3.6V
- Three state output and TTL Compatible
- Packaged product designed for 55/70ns
GENERAL PHYSICAL SPECIFICATIONS
- Backside die surface of polished bare silicon
- Typical Die Thickness = 725um
- Typical top-level metalization :
=> Metal ( Ti/TiN/Al-Cu 0.5% ) : 5.7K Angstroms thickness
- Topside Passivation :
=> 7K Angstroms PE-SiN
- Typical Pad Size : 90.0um x 80.0um
- Wafer diameter : 8 inch
OPTIONS
- C1/W1 : DC Probed Die/Wafer @ Hot Temp
- C2/W2 : DC/AC Probed Die/Wafer @ Hot Temp
PAD DESCRIPTIONS
Name
CS1, CS2
OE
Function
Name
Vcc
Vss
Function
Chip select inputs
Output Enable input
Write Enable input
Power Supply
Ground
Upper Byte (I/O9~16
)
WE
UB
Lower Byte (I/O1~8
No Connection
)
A0~A17
Address Inputs
LB
I/O1~I/O16 Data Inputs/Outpus
*NC
2
EM640FV16FW Series
Low Power, 256Kx16 SRAM
FUNCTIONAL SPECIFICATIONS
There are 3 classifications for EMLSI die and wafers products, which are C1 and C2 for die and W1 and W2 for wafer, respectively.
Each die and wafer support dedicated charateristics and probe the eletrical parameters within their specifications. Followings are
brief information for die and wafer classifications. Please refer to packaged specifications for more information but these parameters
are not guaranteed at bare die and wafer.
− C1 LEVEL DIE OR W1 LEVEL WAFER
The DC parameters are measured by specification for C1 level die or W1 level wafer. The DC parameters measured at 70°C tem-
perature, which called ‘Hot DC Sorting’ Other parameters are not guaranteed and warranted including device reliability. Please refer
to qualification report for device reliability and package level datasheets for electrical parameters.
− C2 LEVEL DIE OR W2 LEVEL WAFER
The DC parameters and selected AC parameters are measured with for C2 level die or W2 level wafer. The DC characteristics of C2
die and W2 wafer is tested based on DC specifications of C1 level die and W1 level wafer. The DC and specified AC parameters are
tested at 70°C temperature, which called ‘Hot DC & Selective AC Sorting’. Other parameters are not guaranteed and warranted
including device reliability. Please refer to qualification report for device reliability and package level datasheets for electrical param-
eters.
C2 level die and W2 level wafer probe following AC parameter.
− tRC, tAA, tCO
− tWC, tCW
PACKAGING
Individual device will be packed in anti-static trays.
− Chip Trays : A 2-inch square waffle style carrier for die with separate compartments for each die. Commonly referred to as a waffle
pack, each tray has a cavity size selected for the device that allows for easy loading and unloading and prevents
rotation. The tray itself is made of conductive material to reduce the danger of damage to the die from electrostatic
discharge. The chip carriers will be labeled with the following information :
− EMLSI wafer lot number
− EMLSI part number
− Quantity
− Jar Packing : Jar packing is made by EMLSI and used by many customers that we deliver the requested die as wafer. The pack is
consisted of clean paper to wrap the wafer, high cushioned sponge between wafers and hardly fragile plastic box with sponge. Each
pack has typically 25 wafers and then several packs are put into larger box depending on amounts of wafers.
Bond Pad #1 at Top
Die orientation in chip carriers
STORAGE AND HANDLING
EMLSI recommends the die stored in a controlled environment with filtered nitrogen. The carrier must be opened at ESD safe
environment when inspection and assembly.
3
EM640FV16FW Series
Low Power, 256Kx16 SRAM
ABSOLUTE MAXIMUM RATINGS *
Parameter
Voltage on Any Pin Relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Symbol
Ratings
Unit
V
V , V
-0.2 to Vcc+0.3(Max.4.0V)
IN
OUT
V
V
-0.2 to 4.0V
1.0
CC
P
W
D
o
Operating Temperature
T
-40 to 85
C
A
* Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
FUNCTIONAL DESCRIPTION
CS
CS
OE
WE
LB
UB
I/O
I/O
9-16
Mode
Power
1
2
1-8
H
X
X
L
L
L
L
L
L
L
L
X
L
X
X
X
H
H
L
X
X
X
H
H
H
H
H
L
X
X
H
L
X
X
H
X
L
High-Z
High-Z
High-Z
High-Z
High-Z
Data Out
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Deselected
Deselected
Stand by
Stand by
Stand by
Active
X
H
H
H
H
H
H
H
H
Deselected
Output Disabled
Output Disabled
Lower Byte Read
X
L
Active
H
L
Active
L
H
L
Data Out Upper Byte Read
Active
L
L
Data Out Data Out
Word Read
Lower Byte Write
Upper Byte Write
Word Write
Active
X
X
X
L
H
L
Data In
High-Z
Data In
High-Z
Data In
Data In
Active
L
H
L
Active
L
L
Active
Note: X means don’t care. (Must be low or high state)
4
EM640FV16FW Series
Low Power, 256Kx16 SRAM
1)
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Supply voltage
Symbol
Min
2.7
0
Typ
3.3
0
Max
3.6
0
Unit
V
V
CC
Ground
V
V
V
SS
2)
Input high voltage
V
2.2
-
-
IH
V
+ 0.2
CC
3)
Input low voltage
V
0.6
V
IL
-0.2
1. TA= -40 to 85oC, otherwise specified
2. Overshoot: VCC +2.0 V in case of pulse width < 20ns
3. Undershoot: -2.0 V in case of pulse width < 20ns
4. Overshoot and undershoot are sampled, not 100% tested.
1)
o
CAPACITANCE (f =1MHz, T =25 C)
A
Item
Input capacitance
Symbol
Test Condition
V =0V
Min
Max
Unit
C
-
-
8
pF
pF
IN
IO
IN
Input/Ouput capacitance
C
V =0V
10
IO
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Parameter
Symbol
Test Conditions
Min
Typ Max
Unit
ILI
VIN=VSS to VCC
Input leakage current
-1
-1
-
-
-
-
1
1
3
uA
uA
CS1=VIH or CS2=VIL or OE=VIH or WE=VIL or LB=UB=VIH
VIO=VSS to VCC
ILO
ICC
Output leakage current
Operating power supply
IIO=0mA, CS1=VIL, CS2=WE=VIH, VIN=VIH or VIL
mA
Cycle time=1µs, 100% duty, IIO=0mA,
CS1<0.2V, LB<0.2V or/and UB<0.2V, CS2>VCC-0.2V,
VIN<0.2V or VIN>VCC-0.2V
ICC1
-
-
3
mA
Average operating current
Cycle time = Min, IIO=0mA, 100% duty,
CS1=VIL, CS2=VIH, LB=VIL or/and UB=VIL ,
VIN=VIL or VIH
55ns
70ns
-
-
-
-
30
25
mA
mA
ICC2
Output low voltage
Output high voltage
Standby Current (TTL)
VOL
VOH
ISB
IOL = 2.1mA
-
2.4
-
-
-
-
0.4
-
V
V
IOH = -1.0mA
CS1=VIH, CS2=VIL, Other inputs=VIH or VIL
0.3
mA
CS1>VCC-0.2V, CS2>VCC-0.2V (CS1 controlled)
or 0V<CS2<0.2V (CS2 controlled),
Other inputs = 0~VCC
11)
ISB1
Standby Current (CMOS)
LL
-
12
uA
o
(Typ. condition : VCC=3.3V @ 25 C)
o
(Max. condition : VCC=3.6V @ 85 C)
NOTES
1. Typical values are measured at Vcc=3.3V, T =25oC and not 100% tested.
A
5
EM640FV16FW Series
Low Power, 256Kx16 SRAM
3)
VTM
AC OPERATING CONDITIONS
Test Conditions (Test Load and Test Input/Output Reference)
2)
R1
Input Pulse Level : 0.4 to 2.2V
Input Rise and Fall Time : 5ns
Input and Output reference Voltage : 1.5V
Output Load (See right) : CL = 100pF+ 1 TTL
2)
R2
1)
1)
CL
CL = 30pF + 1 TTL
1. Including scope and Jig capacitance
2. R =3070 ohm,
R =3150 ohm
2
1
3. V =2.8V
TM
o
o
READ CYCLE (V =2.7 to 3.6V, Gnd = 0V, T = -40 C to +85 C)
cc
A
55ns
70ns
Symbol
Parameter
Unit
Min
Max
Min
Max
Read cycle time
tRC
tAA
co1, tco2
tOE
55
-
70
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
-
-
-
55
55
30
55
-
70
70
35
70
-
Chip select to output
t
-
Output enable to valid output
UB, LB acess time
-
tBA
Chip select to low-Z output
UB, LB enable to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
UB, LB disable to high-Z output
Output disable to high-Z output
Output hold from address change
tLZ1, LZ2
tBLZ
tOLZ
tHZ1, HZ2
t
10
10
5
10
10
5
-
-
-
-
t
0
20
20
20
-
0
25
25
25
-
tBHZ
tOHZ
tOH
0
0
0
0
10
10
o
o
WRITE CYCLE (V =2.7 to 3.6V, Gnd = 0V, T = -40 C to +85 C)
cc
A
55ns
70ns
Unit
Symbol
Parameter
Write cycle time
Min
Max
Min
Max
tWC
tCW1, tCW2
tAs
55
-
70
60
0
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip select to end of write
Address setup time
45
0
-
-
-
Address valid to end of write
UB, LB valid to end of write
Write pulse width
tAW
45
45
40
0
-
60
55
50
0
-
tBW
-
-
tWP
-
-
Write recovery time
tWR
-
-
Write to ouput high-Z
tWHZ
tDW
0
20
0
25
Data to write time overlap
Data hold from write time
End write to output low-Z
30
0
30
0
tDH
-
-
-
-
tOW
5
5
6
EM640FV16FW Series
Low Power, 256Kx16 SRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1). (Address Controlled, CS1=OE=V , CS2=WE=V UB or/and LB V )
IL
IH,
= IL
t
RC
Address
Data Out
t
AA
t
OH
Previous Data Valid
Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE = V )
IH
t
RC
Address
t
AA
t
OH
t
CO
CS1
CS2
t
HZ
t
t
BA
UB,LB
t
t
BHZ
OHZ
OE
OE
t
OLZ
High-Z
Data Out
Data Valid
t
t
BLZ
WHZ
t
LZ
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the outputs achieve the open circuit conditions and are not referanced to output voltage levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
7
EM640FV16FW Series
Low Power, 256Kx16 SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE CONTROLLED)
t
WC
Address
t
(2)
t
(4)
CW
WR
CS1
CS2
t
AW
t
BW
UB,LB
WE
t
(1)
WP
t
DH
t
(3)
t
AS
DW
High-Z
High-Z
Data in
Data Valid
t
WHZ
t
OW
Data out
Data Undefined
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 CONTROLLED)
t
WC
Address
tAS(3)
t
(2)
t
(4)
CW
WR
CS1
CS2
t
AW
t
BW
UB,LB
t
(1)
WP
WE
t
DH
t
DW
Data in
Data Valid
High-Z
High-Z
Data out
8
EM640FV16FW Series
Low Power, 256Kx16 SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB CONTROLLED)
t
WC
Address
t
(2)
t
(4)
CW
WR
CS1
CS2
t
AW
t
BW
UB,LB
WE
t
(1)
t
(3)
WP
AS
t
DH
t
DW
Data in
Data Valid
High-Z
High-Z
Data out
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS1 and low WE. A write begins when CS1 goes low and WE
goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double
byte operation. A write ends at the earliest transition when CS1 goes high and WE goes high. The tWP is
measured from the beginning of write to the end of write.
2. tCW is measured from the CS1 going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS1
or WE going high.
9
EM640FV16FW Series
Low Power, 256Kx16 SRAM
DATA RETENTION CHARACTERISTICS
Parameter
VCC for Data Retention
Symbol
VDR
Test Condition
Min
Typ
Max
Unit
ISB1 Test Condition
(Chip Disabled) 1)
1.5
-
3.6
V
VCC=1.5V, ISB1 Test Condition
(Chip Disabled) 1)
IDR
Data Retention Current
-
0.5
-
uA
ns
Chip Deselect to Data Retention Time
Operation Recovery Time
tSDR
tRDR
0
-
-
-
-
See data retention wave form
tRC
NOTES
1. See the I
measurement condition of datasheet page 5.
SB1
DATA RETENTION WAVE FORM
t
t
RDR
Data Retention Mode
SDR
V
cc
2.7V
2.2V
V
DR
CS1 > Vcc-0.2V
CS
1
GND
Data Retention Mode
V
cc
2.7V
CS
2
t
t
RDR
SDR
V
DR
0.4V
CS2 < 0.2V
GND
10
EM640FV16FW Series
Low Power, 256Kx16 SRAM
MEMORY FUNCTION GUIDE
EM X XX X X X XX X X - XX XX
1. EMLSI Memory
2. Device Type
3. Density
11. Power
10. Speed
4. Option
9. Packages
8. Version
5. Technology
6. Operating Voltage
7. Orgainzation
1. Memory Component
7. Orginzation
8 ---------------------- x8 bit
16 ---------------------- x16 bit
32 ---------------------- x32 bit
2. Device Type
6 ------------------------ Low Power SRAM
7 ------------------------ STRAM
8. Version
3. Density
Blank ----------------- Mother Die
A ----------------------- First revision
B ----------------------- Second revision
C ----------------------- Third revision
D ----------------------- Fourth revision
E ----------------------- Fifth revision
F ----------------------- Sixth revision
1 ------------------------- 1M
2 ------------------------- 2M
4 ------------------------- 4M
8 ------------------------- 8M
16 ----------------------- 16M
32 ----------------------- 32M
64 ----------------------- 64M
9. Package
4. Mode Option
Blank ---------------------- FPBGA
S ---------------------------- 32 sTSOP1
T ---------------------------- 32 TSOP1
U ---------------------------- 44 TSOP2
W ---------------------------- Wafer
0 -------- Dual CS
1 -------- Single CS
2 -------- Multiplexed Address
3 -------- Single CS with LB,UB (tBA=tOE)
4 -------- Single CS with LB,UB (tBA=tCO)
5 -------- Dual CS with LB,UB (tBA=tOE)
6 -------- Dual CS with LB,UB (tBA=tCO)
10. Speed
45 ---------------------- 45ns
55 ---------------------- 55ns
70 ---------------------- 70ns
85 ---------------------- 85ns
10 --------------------- 100ns
12 --------------------- 120ns
5. Technology
Blank ------------------ CMOS
F ------------------------ Full CMOS
6. Operating Voltage
Blank ------------------- 5V
V ------------------------- 2.7V~3.6V
U ------------------------- 3.0V
S ------------------------- 2.5V
R ------------------------- 2.0V
P ------------------------- 1.8V
11. Power
LL ---------------------- Low Low Power
L ---------------------- Low Power
S ---------------------- Standard Power
11
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