EM7323SU16H-55LL [EMLSI]
2M x 16Bit Asynchronous / Page Mode StRAM; 2米x 16Bit的异步/页模式STRAM
| 型号： | EM7323SU16H-55LL |
| 厂家： | 
Emerging Memory & Logic Solutions Inc |
| 描述： | 2M x 16Bit Asynchronous / Page Mode StRAM |
| 文件： | 总11页 (文件大小：130K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
EM7323SU16H
2Mx16 Async. / Page StRAM
Document Title
2M x 16Bit Asynchronous / Page Mode StRAM
Revision History
Revision No.
History
Draft Date
Remark
0.0
Initial Draft
Oct. 23 , 2007
Preliminary
Emerging Memory & Logic Solutions Inc.
4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Zip Code : 690-717
Tel : +82-64-740-1700 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com
The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to
your questions about device. If you have any questions, please contact the EMLSI office.
1
Rev. 0.0
Preliminary
EM7323SU16H
2Mx16 Async. / Page StRAM
2M x16 Bit Async./Page StRAM
GENERAL DISCRIPTION
FEATURES
The EM7323SU16H is a 32M-bit StRAM organized as 2M
words by 16 bits. It provides high density, high speed and
low power. The device operates single power supply. The
device also features SRAM-like W/R timing whereby the
device is controlled by CE1, OE and WE on asynchro-
nous. The device has the page access operation. Page
size is 8 words. The device also supports deep power-
down mode, realizing low-power standby.
- Single power supply voltage of 2.6 to 3.3V
- Direct TTL compativility for all inputs and outputs.
- Deep power-down mode : Memory cell data invalid.
- Supplied in KGD(Known Good Die) form.
- Page operation mode
Page read operation by 8 words.
- Logic compatible with SRAM R/W pin.
- Standby Current
Standby 120 uA
Deep power-down standby (10) uA
- Access Time
Access Time
CE1 Access Time
OE Access Time
Page Access Time
65ns
65ns
25ns
20NS
PAD DESCRIPTION
SYMBOL
A0~A20
A0~A2
CE1
DESCRIPTION
Address input
Page Address input
Chip Enable Input1, Low : Enable
Chip Enable Input2, High:Enable, Low:Enter Power Down mode
Write Enable input, Low :Enable
Output Enable input, Low :Enable
Lower byte write control
CE2
WE
OE
LB
UB
Upper byte write control
DQ0~DQ15
VDD
Data inputs/outputs
Device Power supply
VSS
VDDQ
VSSQ
NC
VSS must be connected ground
I/O Power supply
VSS must be connected ground
Not Connection
2
Rev. 0.0
Preliminary
EM7323SU16H
2Mx16 Async. / Page StRAM
FUNCTION BLOCK DIAGRAM
CE
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
VDD
GND
MEMORY CELL ARRAY
A19
A20
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Sense AMP
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
COLUMN ADDRESS
DECODER
COLUMN ADDRESS
BUFFER
REFRESH
ADDRESS
COUNTER
REFRESH
CONTROL
A0 A1 A2 A3 A4 A5 A6A7
CONTROL SIGNAL
GENERATOR
CE
WE
OE
UB
LB
CE1
CE2
CE
3
Rev. 0.0
Preliminary
EM7323SU16H
2Mx16 Async. / Page StRAM
OPERATION MODE
DQ to DQ DQ to DQ
CE1 CE2 OE WE
LB
L
UB Add
Mode
Read(Word)
Power
IDD0
0
7
8
15
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
L
L
L
H
H
H
L
L
H
L
X
X
X
X
X
X
X
X
X
Data Out
Data Out
High-Z
Data In
Data In
Invalid
High-Z
High-Z
High-Z
Data Out
High-Z
Data Out
Data In
Invalid
Data In
High-Z
High-Z
High-Z
L
Read(Lower Byte)
Read(Upper Byte)
Write(Word)
IDD0
IDD0
IDD0
IDD0
IDD0
IDD0
IDDS
IDDSD
L
H
L
X
X
X
H
X
X
L
L
L
H
L
Write(Lower Byte)
Write(Upper Byte)
Outputs Disabled
Standby
L
H
X
X
X
H
X
X
X
X
X
Deep Power-down
Standby
Note: X means don’t care. (Must be low or high state)
ABSOLUTE MAXIMUM RATINGS (SEE NOTE1)
SYMBOL
RATING
Device Power Supply Voltage
Input Voltage
VALUE
-1.0 to 3.6
-1.0 to 3.6
-1.0 to 3.6
-25 to 85
-55 to 150
0.6
UNIT
VDD
VIN
V
V
V
VOUT
Topr.
Tstrg.
PD
Output Voltage
Operating Temperature
Stroage Temperature
Power Dissipation
℃
℃
W
IOUT
Short Circuit Output Current
50
mA
DC RECOMMENDED OPERATING CONDITIONS(Ta = -25℃ to 85 ℃)
SYMBOL
VDD
PARAMETER
Device Power Supply Voltage
Input High Voltage
MIN
2.6
TYP
Max
3.3
Unit
2.75
VIH
VIL
0.8*VDD
-0.3
-
-
VDD + 0.3
0.15*VDD
V
Input Low Voltage
VIH(Max) VDD+1.0V with 10ns pulse width
VIL(Min)-1.0V with 10ns pulse width
4
Rev. 0.0
Preliminary
EM7323SU16H
2Mx16 Async. / Page StRAM
DC CHARACTERISTICS(Ta = -25℃ to 85 ℃, VDD=2.6 to 3.3V) (SEE NOTE 3 to 4)
Parameter
Input leakage current
Output leakage current
Operating current
Symbol
Test Conditions
Min
-1
-1
-
Typ
Max
1
Unit
uA
ILI
VIN=0 to VDD
-
-
-
ILO
Output disable, VOUT= 0V to VDD
tRC= Min, CE1=VIL , CE2=VIH , IOUT=0mA
1
uA
IDDO1
25
mA
Page Access Operating
current
tPC = Min, CE1=VIL, CE2=VIH , IOUT=0mA,
Page add. cycling.
IDDO2
-
-
15
mA
0.8*VDD
-
Output high voltage
Output low voltage
VOH
VOL
IDDS
-
-
-
V
V
IOH = -0.5mA
0.15*VCCQ
IOL = 1.0mA, VCC=VCCmin
CE1>VDD-0.2V, CE2=VDD -0.2V
Standby Current (CMOS)
-
-
-
-
120
10
uA
uA
Deep Power-down
Standby Curret
VDDSD
(*1, *2)
CE2 = 0.2V
Note
*1. Max VIL of signals(i.e. A0~A20, DQ1~DQ16, CE1#, CE2, WE#, OE#, LB#, UB#) can be 0.2V to 0.616V.
*2. For deep power-down, CE2<=0.2V is essential. If max VIL of CE2 is from 0.2V to 0.616V, the (10)uA deep-power
current will not be guaranteed, and the deep-power current might go high as (15)uA.
o
CAPACITANCE (f =1MHz, T =25 C)
A
Item
Input capacitance
Symbol
Test Condition
V =VSS
Min
Max
Unit
C
-
10
pF
pF
IN
IN
Ouput capacitance
C
V
=VSS
OUT
-
10
OUT
Note : This parameter is sampled periodically and is not 100% tested
5
Rev. 0.0
Preliminary
EM7323SU16H
2Mx16 Async. / Page StRAM
AC TEST CONDITIONS
PARAMETER
Output load
CONDITION
50 ohm+0.5 * VDD
VDD-0.2V, 0.2V
VDD * 0.5
Input pulse level
Timing measurements
Reference level
tR, tF
VDD * 0.5
5 ns
o
o
AC CHARACTERISTICS (V = 2.6 to 3.3V, Gnd = 0V, T = -25 C to +85 C) (SEE NOTE 5-11)
cc
A
Speed
Parameter List
Symbol
Unit
Min
Max
tRC
tACC
tCO
Read Cycle Time
Address Access Time
65
10000
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ms
ns
us
-
-
65
Chip Enable(CE1) Access Time
Output Enable Access Time
Data Byte Control Access Time
Chip Enable Low to Output Active
Output Enable Low to Output Active
Data Byte Control Low to Output Active
Chip Enable High to Ouput High-Z
Output Enable High to Output High-Z
Data Byte Control High to Output High-Z
Output Data Hold Time
65
tOE
-
25
tBA
-
25
tCOE
tOEE
tBE
10
0
-
-
0
-
tOD
-
20
tODO
tBD
-
20
-
20
tOH
5
-
tPM
Page Mode Time
65
20
-
10000
tPC
Page Mode Cycle Time
-
tAA
Page Mode Address Access Time
Page Mode Output Data Hold Time
Write Cycle Time
20
tAOH
tWC
tWP
tCW
tBW
tAW
tAS
5
-
65
50
65
60
60
0
10000
Write Pulse Width
-
-
Chip Enable to End of Write
Data Byte Control to End of Write
Address Valid to End of Write
Address Set-up Time
-
-
-
tWR
tCEH
tWEH
tODW
tOEW
tDS
Write Recovery Time
0
-
Chip Enable High Pulse Width
Write Enable High Pulse Width
WE Low to Output High-Z
WE High to Output Active
Data Set-up Time
10
6
-
-
-
20
-
0
30
0
-
tDH
Data Hold Time
-
tCS
CE2 Set-up Time
0
-
tCH
CE2 Hold Time
300
10
0
-
tDPD
tCHC
tCHP
CE2 Pulse Width
-
CE2 Hold from CE1
-
CE2 Hold from Power On
30
-
6
Rev. 0.0
Preliminary
EM7323SU16H
2Mx16 Async. / Page StRAM
TIMING WAVEFORM OF READ CYCLE
tRC
Address
A0 to A20
tOH
tACC
tCO
CE1
CE2
OE
tOD
tODO
WE
UB, LB
tBE
tBD
tOEE
Dout
DQ0 ~ DQ15
Valid Data
High-Z
High-Z
tCOE
TIMING WAVEFORM OF PAGE READ CYCLE (8 words access)
tPM
Address
A0 to A2
tRC
tPC
tPC
Address
A3 to A20
CE1
CE2
OE
tOE
WE
tBA
UB, LB
tAOH
tAOH
tAOH
tOD
tOEE
tBE
tBD
Dout
DQ0 ~ DQ15
High-Z
High-Z
Dout
tAA
Dout
Dout
tAA
Dout
tCOE
tACC
tACC
tOH
tODO
7
Rev. 0.0
Preliminary
EM7323SU16H
2Mx16 Async. / Page StRAM
TIMING WAVEFORM OF WRITE CYCLE1 (WE CONTROLLED) (SEE NOTE 8)
tWC
Address
A0 to A20
tAW
tWEH
tWP
WE
tAS
tCW
tWR
CE1
CE2
tCH
tBW
tWR
UB, LB
tODW
tOEW
Dout
DQ0 ~ DQ15
High - Z
tDS
(See Note 10)
(See Note11)
(See Note 9)
tDH
Din
DQ0 ~ DQ15
(See Note 9)
Valid Data
TIMING WAVEFORM OF WRITE CYCLE 2 (CE CONTROLLED) (SEE NOTE 8)
tWC
Address
A0 to A20
tAW
tWR
tWP
WE
tCW
tWR
tCEH
CE1
tAS
tCH
CE2
tBW
tWR
UB, LB
tODW
Dout
DQ0 ~ DQ15
High - Z
High - Z
tBE
tDS
tDH
tCOE
(See Note9)
Din
DQ0 ~ DQ15
Valid Data
8
Rev. 0.0
Preliminary
EM7323SU16H
2Mx16 Async. / Page StRAM
DEEP POWER-DOWN TIMING
CE1
CE2
tDPD
tCS
tCH
POWER_ON TIMING
VDD min
V
DD
CE1
CE2
tCHC
tCHP
tCH
PROVISIONS OF ADDRESS SKEW
Read
In case, multiple invalid address cycles shorter than tRC_min sustain over 10us in a active status, as least one valid address cycle over
tRC_min must be needed during 10us.
over 10 us
CE1
WE
Address
tRCmin
Write
In case, multiple invalid address cycles shorter than tWC_min sustain over 10us in a active status, as least one valid address cycle over
tRC_min with tWP_min must be needed during 10us.
over 10 us
CE1
tWPmin
WE
Address
tWCmin
9
Rev. 0.0
Preliminary
EM7323SU16H
2Mx16 Async. / Page StRAM
Notes :
1. Stresses greater than listed under “Absolute Maximum Ratings” may cause permanet damage to the device.
2. All voltages are reference to VSS.
3. IDD0 depends on the cycle time.
4. IDD0 depends on output loading. Specified values are defined with the output open condition.
5. AC measurement are assumed tR, tF = 5ns.
6. Parameters tOD, tODO, tBD and tODW define the time at which the output goes the open condition and are not
output voltage reference levels
7. Data cannot be retained at deep power-down stand-by mode.
8. If OE is high during the write cycle, the outputs will remain at high impedence.
9. During the output state of DQ signals, input signals of reverse polarity must not be applied.
10. If CE1 or LB / UB goes LOW coincident with or after WE goes LOW, the outputs will remain at high impedence.
11. If CE1 or LB./UB goes HIGH coincident with or before WE goes HIGH, the outputs will remain at high impedence.
10
Rev. 0.0
Preliminary
EM7323SU16H
2Mx16 Async. / Page StRAM
MEMORY FUNCTION GUIDE
EM X XX X X X XX X X X - XX XX
1. EMLSI Memory
2. Device Type
3. Density
12. Power
11. Speed
10. PKG
4. Function
9. Option
8. Version
5. Technology
6. Operating Voltage
1. Memory Component
7. Organization
8. Version
Blank ----------------- Mother die
A ----------------------- 2’nd generation
B ----------------------- 3’rd generation
C ----------------------- 4’th generation
D ----------------------- 5’th generation
2. Device Type
6 ---------------------- Low Power SRAM
7 ---------------------- STRAM
C ---------------------- CellularRAM
9. Option
3. Density
Blank ---- No optional mode
4 ----------------------- 4M
8 ----------------------- 8M
16 --------------------- 16M
32 --------------------- 32M
64 --------------------- 64M
28 --------------------- 128M
H ----------- Demultiplexed with DPD
J ------------ Demultiplexed with DPD & RBC
K ------------ Multiplexed with RBC
L ------------ Multiplexed with DPD & RBC
10. Package
Blank ---------------------- Wafer
4. Function
S
T
U
P
Z
Y
V
---------------------- 32 sTSOP1
---------------------- 32 TSOP1
---------------------- 44 TSOP2
---------------------- 48 FPBGA
---------------------- 52 FPBGA
---------------------- 54 FPBGA
---------------------- 90 FPBGA
2 ----Multiplexed async.
3-----Demultiplexed async. with page mode
4-----Demultiplexed async. with direct DPD
5-----Multiplexed sync.
6-----Optional mux/demuxed sync.
5. Technology
S ----------------------- Single Transistor & Trench Cell
11. Speed (@async.)
45 ---------------------- 45ns
55 ---------------------- 55ns
70 ---------------------- 70ns
85 ---------------------- 85ns
90 ---------------------- 90ns
10 --------------------- 100ns
12 --------------------- 120ns
6. Operating Voltage
V ----------------------- 3.3V
U ----------------------- 3.0V
S ----------------------- 2.5V
R ----------------------- 2.0V
P ----------------------- 1.8V
L ----------------------- 1.5V
7. Organization
12. Power
8 ---------------------- x8 bit
16 ---------------------- x16 bit
32 ---------------------- x32 bit
LL ---------------------- Low Low Power
LF ---------------------- Low Low Power
(Pb-Free&Green)
L ---------------------- Low Power
11
Rev. 0.0
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