EM682FR16EU-45LF [EMLSI]

128K x16 bit Low Power and Low Voltage Full CMOS Static RAM; 128K X16位低功耗和低电压全CMOS静态RAM
EM682FR16EU-45LF
型号: EM682FR16EU-45LF
厂家: Emerging Memory & Logic Solutions Inc    Emerging Memory & Logic Solutions Inc
描述:

128K x16 bit Low Power and Low Voltage Full CMOS Static RAM
128K X16位低功耗和低电压全CMOS静态RAM

文件: 总11页 (文件大小:380K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
EM621FV16BU Series  
Low Power, 128Kx16 SRAM  
Document Title  
128K x16 bit Low Power and Low Voltage Full CMOS Static RAM  
Revision History  
Revision No.  
History  
Initial Draft  
0.1 Revision  
Draft Date  
June 28, 2007  
July 2, 2007  
Remark  
0.0  
0.1  
Revised VOH(2.2v to 2.4v),tOH(15ns to 10ns),  
tOE-55(30ns to 25ns), tWP-55(45ns to 40ns),  
tWP-70(55ns to 50ns), tWHZ-70(25ns to 20ns),  
ICC(2mA to 3mA), ICC1(2mA to 3mA)  
0.2  
0.2 Revision  
Fix typo error  
Nov. 13, 2007  
Emerging Memory & Logic Solutions Inc.  
4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Zip Code : 690-719  
Tel : +82-64-740-1712 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com  
The attached data sheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your  
questions about device. If you have any questions, please contact the EMLSI office.  
1
EM621FV16BU Series  
Low Power, 128Kx16 SRAM  
128K x16 Bit Low Power and Low Voltage CMOS Static RAM  
GENERAL DESCRIPTION  
FEATURES  
The EM621FV16BU series are fabricated by EMLSI’s  
advanced full CMOS process technology. The families  
support industrial temperature range and Chip Scale Pack-  
age for user flexibility of system design. The families also  
supports low data retention voltage for battery back-up  
operation with low data retention current.  
- Process Technology : 0.15mm Full CMOS  
- Organization : 128K x16  
- Power Supply Voltage  
=> EM621FV16BU Series : 2.7V~3.6V  
- Low Data Retention Voltage : 1.5V (MIN)  
- Three state output and TTL Compatible  
- Packaged product designed for 45/55/70ns  
- Package Type: 44-TSOP2  
The EM621FV16BU series are available in KGD, JEDEC  
standard 44 pin 400 mil TSOP2 package.  
PRODUCT FAMILY  
Power Dissipation  
Product  
Family  
Operating  
Temperature  
Vcc Range  
Speed  
PKG Type  
Standby  
(ISB1, Typ.)  
Operating  
(ICC1.Max)  
Industrial (-40 ~ 85oC)  
Industrial (-40 ~ 85oC)  
Industrial (-40 ~ 85oC)  
EM621FV16BU-45LF  
EM621FV16BU-55LF  
EM621FV16BU-70LF  
2.7V~3.6V  
2.7V~3.6V  
2.7V~3.6V  
45ns  
55ns  
70ns  
1 µA  
1 µA  
1 µA  
3mA  
3mA  
3mA  
44-TSOP2  
44-TSOP2  
44-TSOP2  
FUNCTIONAL BLOCK DIAGRAM  
PIN DESCRIPTION  
44  
A5  
A6  
A7  
OE  
UB  
A4  
A3  
A2  
A1  
A0  
1
2
3
4
5
6
7
8
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
Pre-charge Circuit  
CS  
LB  
I/O 15  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
A9  
VCC  
VSS  
I/O 0  
I/O 1  
I/O 2  
I/O 14  
I/O 13  
I/O 12  
VSS  
VCC  
I/O 11  
I/O 10  
I/O 9  
I/O 8  
NC  
Memory Array  
1024 x 2048  
9
10  
11  
I/O 3  
VCC  
VSS  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
12  
13  
14  
15  
16  
17  
18  
19  
20  
Data  
I/O0 ~ I/O7  
I/O8 ~ I/O15  
Cont  
I/O Circuit  
Data  
Cont  
Column Select  
WE  
A16  
A15  
A14  
A13  
A12  
A8  
A9  
A10  
A11  
A14  
A15  
A16  
A11  
A13  
A10  
A12  
21  
22  
NC  
WE  
OE  
UB  
LB  
Name  
CS  
Function  
Name  
Function  
Control Logic  
Chip select inputs  
Vcc  
Power Supply  
Ground  
CS  
OE  
Output Enable input Vss  
Upper Byte (I/O8~15  
)
WE  
Write Enable input  
Address Inputs  
UB  
LB  
Lower Byte (I/O0~7  
No Connection  
)
A0~A16  
I/O0~I/O15 Data Inputs/Outputs NC  
2
EM621FV16BU Series  
Low Power, 128Kx16 SRAM  
ABSOLUTE MAXIMUM RATINGS *  
Parameter  
Voltage on Any Pin Relative to Vss  
Voltage on Vcc supply relative to Vss  
Power Dissipation  
Symbol  
Minimum  
-0.2 to 4.0V  
-0.2 to 4.0V  
1.0  
Unit  
V
V , V  
IN  
OUT  
V
V
CC  
P
W
D
o
Operating Temperature  
T
-40 to 85  
A
C
* Stresses greater than those listed above “Absolute Maximum Ratings” may cause permanent damage to the device. Functional oper-  
ation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods  
may affect reliability.  
FUNCTIONAL DESCRIPTION  
CS  
OE  
WE  
LB  
UB  
I/O  
I/O  
Mode  
Power  
0-7  
8-15  
H
X
L
L
L
L
L
L
L
L
X
X
H
H
L
X
X
H
H
H
H
H
L
X
H
L
X
H
X
L
High-Z  
High-Z  
High-Z  
High-Z  
Data Out  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
Deselected  
Deselected  
Stand by  
Stand by  
Active  
Active  
Active  
Active  
Active  
Active  
Active  
Active  
Output Disabled  
Output Disabled  
Lower Byte Read  
X
L
H
L
L
H
L
Data Out Upper Byte Read  
L
L
Data Out Data Out  
Word Read  
Lower Byte Write  
Upper Byte Write  
Word Write  
X
X
X
L
H
L
Data In  
High-Z  
Data In  
High-Z  
Data In  
Data In  
L
H
L
L
L
Note: X means don’t care. (Must be low or high state)  
3
EM621FV16BU Series  
Low Power, 128Kx16 SRAM  
1)  
RECOMMENDED DC OPERATING CONDITIONS  
Parameter  
Supply voltage  
Symbol  
Min  
2.7  
0
Typ  
3.3  
0
Max  
3.6  
0
Unit  
V
V
CC  
Ground  
V
V
V
SS  
2)  
Input high voltage  
V
2.2  
-
-
IH  
V
+ 0.2  
CC  
3)  
Input low voltage  
V
0.6  
V
IL  
-0.2  
1. TA= -40 to 85oC, otherwise specified  
2. Overshoot: VCC +2.0 V in case of pulse width < 20ns  
3. Undershoot: -2.0 V in case of pulse width < 20ns  
4. Overshoot and undershoot are sampled, not 100% tested.  
1)  
o
CAPACITANCE (f =1MHz, T =25 C)  
A
Item  
Input capacitance  
Symbol  
Test Condition  
V =0V  
Min  
Max  
Unit  
C
-
8
pF  
IN  
IO  
IN  
Input/Ouput capacitance  
C
V =0V  
-
10  
pF  
IO  
1. Capacitance is sampled, not 100% tested.  
DC AND OPERATING CHARACTERISTICS  
Parameter  
Symbol  
Test Conditions  
Min  
Typ Max  
Unit  
ILI  
VIN=VSS to VCC  
Input leakage current  
-1  
-1  
-
-
-
-
1
1
3
uA  
CS=VIH or OE=VIH or WE=VIL or LB=UB=VIH  
VIO=VSS to VCC  
ILO  
ICC  
Output leakage current  
Operating power supply  
uA  
IIO=0mA, CS=VIL, VIN=VIH or VIL  
mA  
Cycle time=1µs, 100% duty, IIO=0mA,  
ICC1  
CS<0.2V, LB<0.2V or/and UB<0.2V,  
-
-
3
mA  
mA  
V
IN<0.2V or VIN>VCC-0.2V  
45ns  
55ns  
70ns  
-
-
-
-
-
-
-
-
35  
30  
25  
0.4  
Average operating current  
Cycle time = Min, IIO=0mA, 100% duty,  
CS=VIL, LB=VIL or/and UB=VIL ,  
VIN=VIL or VIH  
ICC2  
VOL  
VOH  
ISB  
IOL = 2.1mA  
Output low voltage  
Output high voltage  
Standby Current (TTL)  
V
V
IOH = -1.0mA  
2.4  
-
-
-
-
CS=VIH, Other inputs=VIH or VIL  
0.3  
mA  
CS>VCC-0.2V  
Other inputs = 0~VCC  
11)  
ISB1  
Standby Current (CMOS)  
LF  
-
10  
uA  
o
(Typ. condition : VCC=3.3V @ 25 C)  
o
(Max. condition : VCC=3.6V @ 85 C)  
NOTES  
1. Typical values are measured at Vcc=3.3V, T =25oC and not 100% tested.  
A
4
EM621FV16BU Series  
Low Power, 128Kx16 SRAM  
AC OPERATING CONDITIONS  
Test Conditions (Test Load and Test Input/Output Reference)  
3)  
VTM  
2)  
R1  
Input Pulse Level : 0.4V to 2.2V  
Input Rise and Fall Time : 5ns  
Input and Output reference Voltage : 1.5V  
1)  
Output Load (See right) : CL = 100pF + 1 TTL (70ns)  
1)  
2)  
CL = 30pF + 1 TTL (45ns/55ns)  
R2  
1)  
CL  
1. Including scope and Jig capacitance  
2. R =3070 ohm,  
R =3150 ohm  
2
1
3. V =2.8V  
TM  
4. CL = 5pF + 1 TTL (measurement with t  
, t  
, t  
, t  
, t  
)
LZ1,2 HZ1,2 OLZ OHZ WHZ  
o
o
READ CYCLE (V =2.7V to 3.6V, Gnd = 0V, T = -40 C to +85 C)  
cc  
A
45ns  
Max  
55ns  
Max  
70ns  
Min Max  
Symbol  
Parameter  
Unit  
Min  
Min  
Read cycle time  
tRC  
tAA  
45  
-
-
55  
-
70  
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address access time  
45  
45  
25  
45  
-
-
-
-
55  
55  
25  
55  
-
70  
70  
35  
70  
-
Chip select to output  
tCO  
tOE  
tBA  
-
-
Output enable to valid output  
UB, LB access time  
-
-
Chip select to low-Z output  
UB, LB enable to low-Z output  
Output enable to low-Z output  
Chip disable to high-Z output  
UB, LB disable to high-Z output  
Output disable to high-Z output  
Output hold from address change  
tLZ  
10  
5
10  
5
10  
5
tBLZ  
tOLZ  
tHZ  
-
-
-
5
-
5
-
5
-
0
20  
15  
15  
-
0
20  
20  
20  
-
0
25  
25  
25  
-
tBHZ  
tOHZ  
tOH  
0
0
0
0
0
0
10  
10  
10  
o
o
WRITE CYCLE (V =2.7V to 3.6V, Gnd = 0V, T = -40 C to +85 C)  
cc  
Parameter  
Write cycle time  
A
45ns  
Max  
55ns  
Max  
70ns  
Unit  
Symbol  
Min  
Min  
Min  
Max  
tWC  
tCW  
tAS  
45  
-
-
55  
-
-
70  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Chip select to end of write  
Address setup time  
45  
0
45  
0
60  
0
-
-
-
-
Address valid to end of write  
UB, LB valid to end of write  
Write pulse width  
tAW  
tBW  
tWP  
tWR  
tWHZ  
tDW  
tDH  
45  
45  
35  
0
-
45  
45  
40  
0
-
60  
60  
50  
0
-
-
-
-
-
-
-
Write recovery time  
-
-
-
Write to ouput high-Z  
0
15  
0
20  
0
20  
Data to write time overlap  
Data hold from write time  
End write to output low-Z  
25  
0
25  
0
30  
0
-
-
-
-
-
-
tOW  
5
5
5
5
EM621FV16BU Series  
Low Power, 128Kx16 SRAM  
TIMING DIAGRAMS  
TIMING WAVEFORM OF READ CYCLE(1). (Address Controlled, CS=OE=V , UB or/and LB=V  
)
IL  
IL  
t
RC  
Address  
Data Out  
t
AA  
t
OH  
Previous Data Valid  
Data Valid  
TIMING WAVEFORM OF READ CYCLE(2) (WE = V )  
IH  
t
RC  
Address  
CS  
t
AA  
t
OH  
t
CO  
t
HZ  
t
t
BA  
OE  
UB,LB  
t
t
BHZ  
OHZ  
OE  
t
OLZ  
High-Z  
Data Out  
Data Valid  
t
t
BLZ  
WHZ  
t
LZ  
NOTES (READ CYCLE)  
1. tHZ and tOHZ are defined as the outputs achieve the open circuit conditions and are not referenced to output voltage levels.  
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device  
interconnection.  
6
EM621FV16BU Series  
Low Power, 128Kx16 SRAM  
TIMING WAVEFORM OF WRITE CYCLE(1) (WE CONTROLLED)  
t
WC  
Address  
CS  
t
(2)  
t
(4)  
CW  
WR  
t
AW  
t
BW  
UB,LB  
WE  
t
(1)  
WP  
t
DH  
t
(3)  
t
AS  
DW  
High-Z  
High-Z  
Data in  
Data Valid  
t
WHZ  
t
OW  
Data out  
Data Undefined  
TIMING WAVEFORM OF WRITE CYCLE(2) (CS CONTROLLED)  
t
WC  
Address  
CS  
tAS(3)  
t
(2)  
t
(4)  
CW  
WR  
t
AW  
t
BW  
UB,LB  
t
(1)  
WP  
WE  
t
DH  
t
DW  
Data in  
Data Valid  
High-Z  
High-Z  
Data out  
7
EM621FV16BU Series  
Low Power, 128Kx16 SRAM  
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB CONTROLLED)  
t
WC  
Address  
CS  
t
(2)  
t
(4)  
CW  
WR  
t
AW  
t
BW  
UB,LB  
WE  
t
(1)  
t
(3)  
WP  
AS  
t
DH  
t
DW  
Data in  
Data Valid  
High-Z  
High-Z  
Data out  
NOTES (WRITE CYCLE)  
1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE  
goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double  
byte operation. A write ends at the earliest transition when CS goes high and WE goes high. The tWP is  
measured from the beginning of write to the end of write.  
2. tCW is measured from the CS going low to end of write.  
3. tAS is measured from the address valid to the beginning of write.  
4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS  
or WE going high.  
8
EM621FV16BU Series  
Low Power, 128Kx16 SRAM  
DATA RETENTION CHARACTERISTICS  
2)  
Parameter  
VCC for Data Retention  
Symbol  
VDR  
Test Condition  
Min  
Typ  
Max  
Unit  
ISB1 Test Condition  
(Chip Disabled) 1)  
1.5  
-
3.6  
V
VCC=1.5V, ISB1 Test Condition  
(Chip Disabled) 1)  
IDR  
Data Retention Current  
-
0.5  
5.0  
µA  
Chip Deselect to Data Retention Time  
Operation Recovery Time  
tSDR  
tRDR  
0
-
-
-
-
See data retention wave form  
ns  
tRC  
NOTES  
1. See the I  
measurement condition of data sheet page 4.  
SB1  
o
2. Typical value is measured at T =25 C and not 100% tested.  
A
DATA RETENTION WAVE FORM  
t
t
RDR  
Data Retention Mode  
SDR  
V
cc  
3.0V  
2.2V  
V
DR  
CS > Vcc-0.2V  
CS  
GND  
9
EM621FV16BU Series  
Low Power, 128Kx16 SRAM  
PACKAGE DIMENSIONS  
44Pin - TSOP Type2  
Unit : millimeters/Inches  
10  
EM621FV16BU Series  
Low Power, 128Kx16 SRAM  
SRAM PART CODING SYSTEM  
EM X XX X X X XX X X - XX XX  
1. EMLSI Memory  
2. Product Type  
3. Density  
11. Power  
10. Speed  
4. Function  
9. Package  
8. Generation  
7. Organization  
5. Technology  
6. Operating Voltage  
1. Memory Component  
7. Organization  
EM --------------------- Memory  
8 ---------------------- x8 bit  
16 ---------------------- x16 bit  
2. Product Type  
6 ------------------------ SRAM  
8. Generation  
Blank ----------------- 1st generation  
A ----------------------- 2nd generation  
B ----------------------- 3rd generation  
C ----------------------- 4th generation  
D ----------------------- 5th generation  
E ----------------------- 6th generation  
F ----------------------- 7th generation  
G ---------------------- 8th generation  
3. Density  
1 ------------------------- 1M  
2 ------------------------- 2M  
4 ------------------------- 4M  
8 ------------------------- 8M  
4. Function  
0 ----------------------- Dual CS  
1 ----------------------- Single CS  
9. Package  
2 ----------------------- Multiplexed  
Blank ---------------- KGD, 48&36FpBGA  
S ---------------------- 32 sTSOP1  
T ---------------------- 32 TSOP1  
U ---------------------- 44 TSOP2  
V ---------------------- 32 SOP  
3 ------------- Single CS / LBB, UBB(tBA=tOE)  
4 ------------- Single CS / LBB, UBB(tBA=tCO)  
5 ------------- Dual CS / LBB, UBB(tBA=tOE)  
6 ------------- Dual CS / LBB, UBB(tBA=tCO)  
5. Technology  
10. Speed  
F ------------------------- Full CMOS  
45 ---------------------- 45ns  
55 ---------------------- 55ns  
70 ---------------------- 70ns  
85 ---------------------- 85ns  
10 ---------------------- 100ns  
12 ---------------------- 120ns  
6. Operating Voltage  
T ------------------------- 5.0V  
V ------------------------- 3.3V  
U ------------------------- 3.0V  
S ------------------------- 2.5V  
R ------------------------- 2.0V  
P ------------------------- 1.8V  
11. Power  
LL ---------------------- Low Low Power  
LF ---------------------- Low Low Power(Pb-Free & Green)  
L ---------------------- Low Power  
S ---------------------- Standard Power  
11  

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