EM632AFU8AW-55LF [EMLSI]
256K x16 bit Low Power and Low Voltage Full CMOS Static RAM; 256K X16位低功耗和低电压全CMOS静态RAM
| 型号： | EM632AFU8AW-55LF |
| 厂家： | 
Emerging Memory & Logic Solutions Inc |
| 描述： | 256K x16 bit Low Power and Low Voltage Full CMOS Static RAM |
| 文件： | 总11页 (文件大小：112K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EM640FP16 Series
Low Power, 256Kx16 SRAM
Document Title
256K x16 bit Low Power and Low Voltage Full CMOS Static RAM
Revision History
Revision No.
History
Draft Date
Remark
0.0
Initial Draft
October 24 , 2002
November 11 , 2002
December 23 , 2002
Preliminary
0.1
0.2
2’nd Draft
3’rd Draft
Changed Icc, Icc1 value
Changed I
test conditions,
SB1
Changed VDR & IDR
measurement condition
0.3
0.4
4’th Draft
5’th Draft
Add Pb-free part number
February 13 , 2004
April 11 , 2006
EM640FP16:
Changed Icc2 value
Changed Package Dimension
Emerging Memory & Logic Solutions Inc.
IT Venture Tower Eastside 11F, 78, Karac-Dong, Songpa-Ku, Seoul, Rep.of Korea Zip Code : 138-160
Tel : +82-2-2142-1759~1766 Fax : +82-2-2142-1769 / Homepage : www.emlsi.com
The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your
questions about device. If you have any questions, please contact the EMLSI office.
1
EM640FP16 Series
Low Power, 256Kx16 SRAM
FEATURES
GENERAL DESCRIPTION
• Process Technology : 0.18 m Full CMOS
• Organization : 256K x 16 bit
• Power Supply Voltage : 1.65V ~ 2.2V
• Low Data Retention Voltage : 1.0V(Min.)
• Three state outputs
The EM640FP16 families are fabricated by EMLSI’s
advanced full CMOS process technology. The families
support industrial temperature range and Chip Scale
Package for user flexibility of system design. The fami-
lies also supports low data retention voltage for battery
back-up operation with low data retention current.
µ
• Package Type : 48-FPBGA 6.0x7.0
PRODUCT FAMILY
Power Dissipation
Product
Family
Operating
Temperature
Vcc
Range
PKG
Type
Speed
Standby
(I , Typ.)
Operating
(I .Max)
SB1
CC1
48-FPBGA
(6.0x7.0)
o
1)
EM640FP16
1.65~2.2V
1 µA
2 mA
Industrial (-40 ~ 85 C)
70ns
1. The parameter is measured with 30pF test load.
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
1
2
3
4
5
6
Pre-charge Circuit
A
B
C
D
E
LB
I/O
OE
UB
A
A
A
A
A
A
A
A
CS
I/O
I/O
0
3
5
1
4
6
7
2
2
1
3
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
VCC
VSS
CS
9
1
Memory Array
I/O
I/O
I/O
I/O
I/O
I/O
10
11
12
13
14
2
4
5
6
2048 x 2048
V
V
I/O
I/O
I/O
A
V
CC
SS
17
DNU
A
A
A
A
V
SS
Data
Cont
CC
16
15
13
10
I/O1 ~ I/O8
I/O Circuit
Data
Cont
I/O9 ~ I/O16
Column Select
F
I/O
A
I/O
15
16
14
7
8
G
H
I/O
DNU
A
WE I/O
12
A11 A12 A13 A14 A15 A16
A17
DNU
A
A
A
11
DNU
8
9
48-FPBGA : Top view (ball down)
WE
OE
UB
Control Logic
LB
CS1
CS2
Name
Function
Name
Function
CS1,CS2 Chip select inputs
Vcc Power Supply
OE
Output Enable input
Write Enable input
Vss Ground
WE
UB Upper Byte (I/O9~16)
A0~A17 Address Inputs
LB
Lower Byte (I/O1~8)
I/O1~I/O16 Data Inputs/outputs
DNU Do Not Use
2
EM640FP16 Series
Low Power, 256Kx16 SRAM
ABSOLUTE MAXIMUM RATINGS *
Parameter
Voltage on Any Pin Relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Symbol
Minimum
Unit
V
V , V
-0.5 to 2.5V
-0.3 to 2.5V
1.0
IN
OUT
V
V
CC
P
W
D
A
o
Operating Temperature
T
-40 to 85
C
*
Stresses greater than those listed above “Absolute Maximum Ratings” may cause permanent damage to the device. Functional oper-
ation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
FUNCTIONAL DESCRIPTION
CS
CS
OE
WE
LB
UB
I/O
I/O
9-16
Mode
Power
1
2
1-8
H
X
X
L
L
L
L
L
L
L
L
X
L
X
X
X
H
H
L
X
X
X
H
H
H
H
H
L
X
X
H
L
X
X
H
X
L
High-Z
High-Z
High-Z
High-Z
High-Z
Data Out
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Deselected
Deselected
Stand by
Stand by
Stand by
Active
X
H
H
H
H
H
H
H
H
Deselected
Output Disabled
Output Disabled
Lower Byte Read
X
L
Active
H
L
Active
L
H
L
Data Out Upper Byte Read
Active
L
L
Data Out Data Out
Word Read
Lower Byte Write
Upper Byte Write
Word Write
Active
X
X
X
L
H
L
Data In
High-Z
Data In
High-Z
Data In
Data In
Active
L
H
L
Active
L
L
Active
Note: X means don’t care. (Must be low or high state)
3
EM640FP16 Series
Low Power, 256Kx16 SRAM
1)
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Supply voltage
Symbol
Min
1.65
0
Typ
1.8
0
Max
2.2
0
Unit
V
V
CC
V
Ground
V
SS
2)
V
Input high voltage
Input low voltage
1.4
-
-
V
V
V
+ 0.3
IH
CC
3)
V
0.4
-0.3
IL
o
1. TA= -40 to 85 C, otherwise specified
2. Overshoot: VCC +1.0 V in case of pulse width < 20ns
3. Undershoot: -1.0 V in case of pulse width < 20ns
4. Overshoot and undershoot are sampled, not 100% tested
.
1)
o
CAPACITANCE
(f =1MHz, T =25 C)
A
Item
Input capacitance
Symbol
Test Condition
Min
Max
8
Unit
C
V =0V
-
-
pF
pF
IN
IO
IN
C
V =0V
Input/Ouput capacitance
10
IO
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Parameter
Symbol
Test Conditions
Min
Typ Max
Unit
I
VIN=VSS to VCC
Input leakage current
-1
-1
-
-
-
-
1
1
2
uA
uA
LI
CS1=VIH, CS2=VIL or OE=VIH or WE=VIL or LB=UB=VIH
VIO=VSS to VCC
I
Output leakage current
Operating power supply
LO
I
IIO=0mA, CS1=VIL, CS2=WE=VIH, VIN=VIH or VIL
mA
CC
Cycle time=1 s, 100% duty, ILO=0mA,
µ
I
CS1<0.2V, LB<0.2V or/and UB<0.2V, CS2>VCC-0.2V
VIN<0.2V or VIN>VCC-0.2V
-
-
-
-
2
mA
mA
CC1
Average operating current
Cycle time = Min, IIO=0mA, 100% duty,
CS1=VIL, CS2=VIH , LB=VIL or/and UB=VIL
VIN=VIL or VIH
I
15
CC2
V
IOL = 0.1mA
IOH = -0.1mA
Output low voltage
Output high voltage
-
-
-
0.2
-
V
V
OL
V
1.4
OH
CS1>VCC-0.2V, CS2>VCC-0.2V (CS1 controlled)
or 0V<CS2<0.2V (CS2 controlled),
LL
LF
Other inputs = 0 ~ VCC
I
Standby Current (CMOS)
-
1
5
uA
SB1
o
(Typ. condition : VCC=1.8V @ 25 C)
o
(Max. condition : VCC=2.2V @ 85 C)
4
EM640FP16 Series
Low Power, 256Kx16 SRAM
3)
V
TM
AC OPERATING CONDITIONS
Test Load and Test Input/Output Reference)
Test Conditions (
2)
2)
R
R
1
2
Input Pulse Level : 0.2 to VCC-0.2V
Input Rise and Fall Time : 5ns
Input and Output reference Voltage : 0.9V
Output Load (See right) : CL = 100pF+ 1 TTL
1)
1)
CL
CL = 30pF + 1 TTL
1. Including scope and Jig capacitance
2. R =3070 ohm
R =3150 ohm
2
,
1
3. V =1.8V
TM
o
o
READ CYCLE (V =1.65 to 2.2V, Gnd = 0V, T = -40 C to +85 C)
cc
A
70ns
Symbol
Parameter
Unit
Min
Max
Read Cycle Time
t
70
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Address Access Time
t
-
-
-
70
70
35
70
-
AA
Chip Select to output
t
t
co1, co2
Output Enable to valid output
UB, LB Acess time
t
OE
t
BA
Chip select to low-Z output
UB, LB enable to low-Z output
Output Enable to Low-Z output
Chip disable to high-Z output
UB, LB disable to high-Z output
Output disable to high-Z output
Output hold from address change
t
t
10
10
5
LZ1, LZ2
t
-
BLZ
OLZ
t
-
t
t
0
25
25
25
-
HZ1, HZ2
t
0
BHZ
OHZ
t
0
t
OH
10
o
o
(V =1.65 to 2.2V, Gnd = 0V, T = -40 C to +85 C)
WRITE CYCLE
cc
A
70ns
Unit
Symbol
Parameter
Min
Max
Write Cycle Time
t
70
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
Chip Select to end of write
Address Setup time
t
t
60
0
-
-
CW1, CW2
t
As
Address valid to end of write
UB, LB valid to end of write
Write pulse width
t
t
t
t
60
60
55
0
-
AW
BW
WP
WR
-
-
Write recovery time
-
Write to ouput high-Z
t
0
25
WHZ
Data to write time overlap
Data hold from write time
End write to output low-Z
t
30
0
DW
t
-
-
DH
t
5
OW
5
EM640FP16 Series
Low Power, 256Kx16 SRAM
TIMING DIAGRAMS
(Address Controlled, CS1=OE=VIL, CS2=WE=VIH, UB or/and LB=VIL
)
TIMING WAVEFORM OF READ CYCLE(1).
t
RC
Address
t
AA
t
OH
Previous Data Valid
Data Valid
Data Out
(WE = V )
TIMING WAVEFORM OF READ CYCLE(2)
IH
t
RC
Address
t
AA
t
OH
t
CO
CS1
CS2
t
HZ
t
t
BA
OE
UB,LB
t
t
BHZ
OHZ
OE
t
OLZ
High-Z
Data Out
Data Valid
t
t
BLZ
WHZ
t
LZ
NOTES (READ CYCLE)
1. t and t
are defined as the outputs achieve the open circuit conditions and are not referanced to output voltage levels.
HZ
OHZ
2. At any given temperature and voltage condition, t (Max.) is less than t (Min.) both for a given device and from device to device
HZ
LZ
interconnection.
6
EM640FP16 Series
Low Power, 256Kx16 SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE CONTROLLED)
t
WC
Address
t
(2)
t
(4)
CW
WR
CS1
CS2
t
AW
t
BW
UB,LB
WE
t
(1)
WP
t
DH
t
(3)
t
AS
DW
High-Z
High-Z
Data in
Data Valid
t
WHZ
t
OW
Data out
Data Undefined
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 CONTROLLED)
t
WC
Address
t
AS(3)
t
(2)
t
(4)
CW
WR
CS1
CS2
t
AW
t
BW
UB,LB
t
(1)
WP
WE
t
DH
t
DW
Data in
Data Valid
High-Z
High-Z
Data out
7
EM640FP16 Series
Low Power, 256Kx16 SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB CONTROLLED)
t
WC
Address
t
(2)
t
(4)
CW
WR
CS1
CS2
t
AW
t
BW
UB,LB
WE
t
(1)
t
(3)
WP
AS
t
DH
t
DW
Data in
Data Valid
High-Z
High-Z
Data out
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(t ) of low CS and low WE. A write begins when CS1 goes low and WE
WP
1
goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double
byte operation. A write ends at the earliest transition when CS goes high and WE goes high. The t
is
1
WP
measured from the beginning of write to the end of write.
2. t
is measured from the CS going low to end of write.
1
CW
3. t is measured from the address valid to the beginning of write.
AS
4. t
is measured from the end or write to the address change. t
applied in case a write ends as CS
WR 1
WR
or WE going high.
8
EM640FP16 Series
Low Power, 256Kx16 SRAM
DATA RETENTION CHARACTERISTICS
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
I
Test Condition
SB1
V
for Data Retention
V
1.0
-
2.2
V
CC
DR
1)
(Chip Disabled)
V
=1.2V, I
Test Condition
CC
SB1
I
Data Retention Current
-
0.5
2
uA
ns
DR
1)
(Chip Disabled)
Chip Deselect to Data Retention Time
Operation Recovery Time
t
t
0
-
-
-
-
SDR
RDR
See data retention wave form
t
RC
NOTES
1. See the I
measurement condition of datasheet page 4.
SB1
DATA RETENTION WAVE FORM
t
t
RDR
Data Retention Mode
SDR
V
cc
1.65V
1.4V
V
DR
CS1 > Vcc-0.2V
CS
1
GND
Data Retention Mode
V
cc
1.65V
CS
2
t
t
RDR
SDR
V
DR
0.4V
CS2 < 0.2V
GND
9
EM640FP16 Series
Low Power, 256Kx16 SRAM
Unit: millimeters
PACKAGE DIMENSION
48 Ball Fine Pitch BGA (0.75mm ball pitch)
Bottom View
Top View
A1 index Mark
B
B
B1
0.4
6
5
4
3
2
1
A
B
C
D
E
F
#A1
G
H
B/2
Side View
D
Detail A
A
Y
C
Min
Typ
0.75
6.00
3.75
7.00
5.25
0.35
0.85
0.58
0.27
-
Max
A
B
-
-
6.05
-
5.95
NOTES.
B1
C
-
1. Bump counts : 48(8row x 6column)
2. Bump pitch : (x,y)=(0.75x0.75) (typ.)
3. All tolerence are +/-0.050 unless
otherwise specified.
6.95
7.05
-
C1
D
-
0.30
0.40
0.90
-
4. Typ : Typical
5. Y is coplanarity : 0.08(Max)
E
-
-
-
-
E1
E2
Y
-
0.08
10
EM640FP16 Series
Low Power, 256Kx16 SRAM
MEMORY FUNCTION GUIDE
EM X XX X X X XX X X - XX XX
1. EMLSI Memory
2. Device Type
3. Density
11. Power
10. Speed
4. Option
9. Packages
8. Version
5. Technology
6. Operating Voltage
7. Orgainzation
1. Memory Component
8. Version
Blank ----------------- Mother die
2. Device Type
A ----------------------- First version
B ----------------------- Second version
C ----------------------- Third version
D ----------------------- Fourth version
E ----------------------- Fifth version
6 ------------------------ Low Power SRAM
7 ------------------------ Pseudo SRAM
3. Density
1 ------------------------- 1M
2 ------------------------- 2M
4 ------------------------- 4M
8 ------------------------- 8M
16 ----------------------- 16M
32 ----------------------- 32M
64 ----------------------- 64M
9. Package
Blank ---------------------- Package
W --------------------- Wafer
10. Speed
45 ---------------------- 45ns
55 ---------------------- 55ns
70 ---------------------- 70ns
85 ---------------------- 85ns
10 --------------------- 100ns
12 --------------------- 120ns
4. Option
0 ----------------------- Dual CS
1 ----------------------- Single CS
5. Technology
Blank ------------------ CMOS
F ------------------------ Full CMOS
11. Power
LL ------------ Low Low Power
LF ------------ Low Low Power(Pb-Free & Green)
L ------------- Low Power
6. Operating Voltage
Blank ------------------- 5V
V ------------------------- 3.3V
U ------------------------- 3.0V
S ------------------------- 2.5V
R ------------------------- 2.0V
P ------------------------- 1.8V
S ------------- Standard Power
7. Orginzation
8 ---------------------- x8 bit
16 ---------------------- x16 bit
32 ---------------------- x32 bit
11
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