EM78P468NBL64 [ELAN]
8-Bit Microcontroller;
| 型号： | EM78P468NBL64 |
| 厂家： | 
ELAN MICROELECTRONICS CORP |
| 描述： | 8-Bit Microcontroller 微控制器 |
| 文件： | 总80页 (文件大小：1512K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EM78P468NB/P470N
8-Bit
Microcontroller
Product
Specification
DOC. VERSION 1.2
ELAN MICROELECTRONICS CORP.
November 2012
Trademark Acknowledgments:
IBM is a registered trademark and PS/2 is a trademark of IBM.
Windows is a trademark of Microsoft Corporation.
ELAN and ELAN logo
are trademarks of ELAN Microelectronics Corporation.
Copyright © 2010~2012 by ELAN Microelectronics Corporation
All Rights Reserved
Printed in Taiwan, ROC
The contents of in this specification are subject to change without notice. ELAN Microelectronics assumes no
responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics
makes no commitment to update, or to keep current the information and material contained in this specification.
Such information and material may change to conform to each confirmed order.
In no event shall ELAN Microelectronics be made responsible to any claims attributed to errors, omissions, or
other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not
be liable for direct, indirect, special incidental, or consequential damages arising out of the use of such information
or material.
The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and
may be used or copied only in accordance with the terms of such agreement.
ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of
ELAN Microelectronics product in such applications is not supported and is prohibited.
NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY
ANY MEANS WITHOUT THE EXPRESS WRITTEN PERMISSION OF ELAN MICROELECTRONICS.
ELAN MICROELECTRONICS CORPORATION
Headquarters:
Hong Kong:
USA:
No. 12, Innovation 1st Road
Hsinchu Science Park
Elan (HK) Microelectronics
Corporation, Ltd.
Elan Information
Technology Group
Hsinchu, TAIWAN 30076
Tel: +886 3 563-9977
Fax: +886 3 563-9966
webmaster@emc.com.tw
http://www.emc.com.tw
Flat A, 19F., World Tech Centre 95 (U.S.A.)
How Ming Street, Kwun Tong
Kowloon, HONG KONG
Tel: +852 2723-3376
PO Box 601
Cupertino, CA 95015
U.S.A.
Fax: +852 2723-7780
Tel: +1 408 366-8225
Fax: +1 408 366-8225
Korea:
Shenzhen:
Shanghai:
Elan Korea Electronics
Company, Ltd.
Elan Microelectronics
Shenzhen, Ltd.
ELAN Microelectronics
Shanghai, Ltd.
301 Dong-A Building
632 Kojan-Dong, Namdong-ku Gaoxin South Road 6
8A Floor, Microprofit Building
6F, Ke Yuan Building
No. 5 Bibo Road
Incheon City, KOREA
Tel: +82 32 814-7730
Fax: +82 32 813-7730
Shenzhen Hi-tech Industrial Park
South Area, Shenzhen
CHINA 518057
Tel: +86 755 2601-0565
Fax: +86 755 2601-0500
elan-sz@elanic.com.cn
Zhangjiang Hi-Tech Park
Shanghai, CHINA 201203
Tel: +86 21 5080-3866
Fax: +86 21 5080-0273
elan-sh@elanic.com.cn
Contents
Contents
1
2
3
4
General Description.................................................................................................. 1
Features .....................................................................................................................1
Pin Assignment ......................................................................................................... 2
Pin Description.......................................................................................................... 4
4.1 Pin Description ................................................................................................... 4
Block Diagram........................................................................................................... 9
Functional Description ........................................................................................... 10
5
6
6.1 Operational Registers....................................................................................... 10
6.1.1 R0/IAR (Indirect Addressing Register) ..............................................................10
6.1.2 R1/TCC (Timer Clock Counter).........................................................................10
6.1.3 R2/PC (Program Counter).................................................................................10
6.1.3.1 Data Memory Configuration ...............................................................11
6.1.4 R3/SR (Status Register)...................................................................................12
6.1.5 R4/RSR (RAM Select Register) ........................................................................13
6.1.6 SBANK0 R5/Port 5 (Port 5 I/O Data and Page of Register Selection) .............13
6.1.7 SBANK0 R6/Port 6 (Port 6 I/O Data Register)..................................................13
6.1.8 SBANK0 R7/Port 7 (Port 7 I/O Data Register)..................................................14
6.1.9 SBANK0 R8/Port 8 (Port 8 I/O Data Register)..................................................14
6.1.10 SBANK0 R9/LCDCR (LCD Control Register) ...................................................14
6.1.11 SBANK0 RA/LCD_ADDR (LCD Address).........................................................15
6.1.12 SBANK0 RB/LCD_DB (LCD Data Buffer).........................................................15
6.1.13 SBANK0 RC/CNTER (Counter Enable Register) .............................................16
6.1.14 SBANK0 RD/SBPCR (System, Booster and PLL Control Register).................17
6.1.15 SBANK0 RE/IRCR (IR Control Register) ..........................................................20
6.1.16 SBANK0 RF/ISR (Interrupt Status Register).....................................................21
6.1.17 SBANK1 R5/TBRDH (TBRD High Address) .....................................................21
6.1.18 SBANK1 R6/TBRDL (TBRD Low Address).......................................................22
6.1.19 General Purpose Register (Address: 10h~3Fh; R10~R3F)..............................22
6.2 Special Purpose Register................................................................................. 22
6.2.1 A (Accumulator).................................................................................................22
6.2.2 IOC Page 0 (IOC50 ~ IOCF0, Bit 0 of R5 = “0”) ...............................................22
6.2.2.1 IOC50/P5CR (Port 5 I/O and Ports 7, 8 for LCD Segment
Control Register).................................................................................22
6.2.2.2 IOC60/P6CR (Port 6 I/O Control Register) ........................................23
6.2.2.3 IOC70/P7CR (Port 7 I/O Control Register) ........................................23
6.2.2.4 IOC80/P8CR (Port 8 I/O Control Register) ........................................23
6.2.2.5 IOC90/RAM_ADDR (128 Bytes RAM Address).................................24
Product Specification (V1.2) 11.30.2012
• iii
Contents
6.2.2.6 IOCA0/RAM_DB (128 Bytes RAM Data Buffer).................................24
6.2.2.7 IOCB0/CNT1PR (Counter 1 Preset Register)....................................24
6.2.2.8 IOCC0/CNT2PR (Counter 2 Preset Register)....................................24
6.2.2.9 IOCD0/HPWTPR (High-Pulse Width Timer Preset Register) ............25
6.2.2.10 IOCE0/LPWTPR (Low-Pulse Width Timer Preset Register)..............25
6.2.2.11 IOCF0/IMR (Interrupt Mask Register) ................................................26
6.2.3 IOC Page 1 (IOC61 ~ IOCE1)...........................................................................26
6.2.3.1 IOC61/WUCR (Wake-up and Sink Current of P5.7/IROUT
Control Register).................................................................................26
6.2.3.2 IOC71/TCCCR (TCC Control Register) .............................................27
6.2.3.3 IOC81/WDTCR (WDT Control Register)............................................28
6.2.3.4 IOC91/CNT12CR (Counters 1 and 2 Control Register).....................28
6.2.3.5 IOCA1/HLPWTCR (High/Low Pulse Width Timer Control Register)..29
6.2.3.6 IOCB1/P6PH (Port 6 Pull-high Control Register)...............................30
6.2.3.7 IOCC1/P6OD (Port 6 Open Drain Control Register)..........................30
6.2.3.8 IOCD1/P8PH (Port 8 Pull High Control Register) ..............................30
6.2.3.9 IOCE1/P6PL (Port 6 Pull Low Control Register)................................31
6.3 TCC and WDT Prescaler.................................................................................. 31
6.3.1 TCC Setting Flowchart......................................................................................33
6.3.2 WDT Setting Flowchart .....................................................................................33
6.4 I/O Ports ........................................................................................................... 34
6.5 Reset and Wake-up.......................................................................................... 34
6.5.1 Summary of Registers Initialized Values...........................................................35
6.5.2 Summary of Wake-up and Interrupt Modes ......................................................41
6.6 LVR (Low Voltage Reset) ................................................................................. 42
6.6.1 Low Voltage Reset ............................................................................................42
6.7 Oscillator .......................................................................................................... 42
6.7.1 Oscillator Modes................................................................................................42
6.7.2 Phase Lock Loop (PLL Mode)...........................................................................43
6.7.3 Crystal Oscillator/Ceramic Resonators (Crystal)...............................................43
6.7.4 RC Oscillator Mode with Internal Capacitor ......................................................45
6.8 Power-on Considerations................................................................................. 45
6.8.1 External Power-on Reset Circuit.......................................................................46
6.8.2 Residue-Voltage Protection...............................................................................46
6.9 Interrupt............................................................................................................ 47
6.10 LCD Driver........................................................................................................ 48
6.10.1 R9/LCDCR (LCD Control Register)..................................................................49
6.10.2 RA/LCD_ADDR (LCD Address) .......................................................................49
6.10.3 RB/LCD_DB (LCD Data Buffer) ........................................................................50
6.10.4 RD/SBPCR (System, Booster and PLL Control Registers) ..............................50
iv •
Product Specification (V1.2) 11.30.2012
Contents
6.11 Infrared Remote Control Application/PWM Waveform Generation................... 55
6.11.1 IROUT Output Waveforms ................................................................................56
6.11.2 IR/PWM Function Enable Flowchart .................................................................58
6.12 Code Options ................................................................................................... 59
6.12.1 Code Option Register (Word 0).........................................................................59
6.12.2 Code Option Register (Word 1).........................................................................60
6.12.3 Code Option Register (Word 2).........................................................................60
6.13 Instruction Set .................................................................................................. 61
6.13.1 Instruction Set Table.........................................................................................61
7
Timing Diagram ....................................................................................................... 64
7.1 AC Test Input/Output Waveform....................................................................... 64
7.2 Reset Timing .................................................................................................... 64
7.3 TCC Input Timing (CLKS = “0”) ........................................................................ 65
8
9
Absolute Maximum Ratings................................................................................... 65
Electrical Characteristics ....................................................................................... 66
9.1 DC Electrical Characteristics............................................................................ 66
9.2 AC Electrical Characteristics............................................................................ 68
APPENDIX
A
B
Package Type........................................................................................................... 69
A.1 Green Products Compliance ............................................................................ 69
Package Information............................................................................................... 70
B.1 QFP – 64.......................................................................................................... 70
B.2 LQFP – 64........................................................................................................ 71
B.3 LQFP – 44........................................................................................................ 72
B.4 QFP – 44.......................................................................................................... 73
Product Specification (V1.2) 11.30.2012
• v
Contents
Specification Revision History
Doc. Version
Revision Description
Date
1.0
Initial Release Version
2010/10/11
1. Modified the contents of the Features
2. Modified the contents of the Pin Description
3. Modified the form of each register in the Function
Description
1.1
2011/07/05
2012/11/30
4. Added an LVR function description
5. Modfiied the contents of the Code Option Register
6. Modified the contents of the Instruction Set Table
1. Modified the 44-pin package type name
2. Deleted the EM78P468NBQ64A package type on the
Features section and other related sections, as well as on
the Appendix section.
1.2
vi •
Product Specification (V1.2) 11.30.2012
EM78P468NB/P470N
8-Bit Microcontroller
1 General Description
The EM78P468NB/P470N is an 8-bit microprocessor designed and developed with low-power and
high-speed CMOS technology. It is integrated with Watchdog Timer (WDT), Data RAM, ROM,
programmable real time clock counter, internal/external interrupt, power-down mode, LCD driver, infrared
transmitter function, and tri-state I/O. The microprocessor is equipped with an on-chip 4K×13-bit Electrical
One Time Programmable Read Only Memory (OTP-ROM) and provides multi-protection bits to prevent
intrusion of user’s OTP memory code. Seven Code option bits are available for user requirements. Special
13 bits customer ID options are provided as well.
With its enhanced OTP-ROM feature, the EM78P468NB/P470N provides a convenient way of developing
and verifying user programs. Moreover, this OTP device offers the advantages of easy and effective
program updates with development and programming tools. User can take advantage of ELAN’s Writer to
easily program his development codes.
2 Features
CPU Configuration:
Peripheral Configuration:
• 4K×13 bits on-chip OTP-ROM
• 144 bytes general purpose register
• 128 bytes on-chip data RAM
• 272 bytes SRAM
•
•
8-bit real time clock/counter (TCC)
One infrared transmitter / PWM generator
• Four sets of 8-bit auto reload count-down timers
which can be used as interrupt sources:
◊
◊
Counter 1: Independent count-down timer
• 8 level stacks for subroutine nesting
Counter 2: High Pulse Width Timer (HPWT)
and Low Pulse Width Timer (LPWT) shared
with IR function.
• Four programmable Level Voltage Reset
(LVR) :4.0V, 3.5V, 2.7V, 1.7V(POR)
I/O Port Configuration:
◊
Programmable free running on-chip
Watchdog Timer (WDT). This function
operates under Normal, Green, and Idle
modes.
• Typically, 12 bidirectional tri-state I/O ports
• 16 bidirectional tri-state I/O ports shared
with LCD segment output pin
• Up to 28 bidirectional tri-state I/O ports
Operating Voltage and Temperature Range:
Eight Interrupt Sources: Three External and Five
Internal:
• Commercial: 2.1V ~ 5.5V (at 0°C ~ +70°C)
• Industrial: 2.3V ~ 5.5V (at -40°C ~ +85°C)
Operating Mode:
•
Internal interrupt source: TCC; Counters 1, 2;
and High/Low pulse width timer.
•
External interrupt source: INT0, INT1, and Pin
change wake-up (Port 6 and Port 8)
• Normal Mode: The CPU operates on main
oscillator frequency (Fm)
LCD Circuit:
• Green Mode: The CPU operates on
sub-oscillator frequency (Fs) and the main
oscillator (Fm) is stopped
•
•
•
•
Common driver pins: 4
Segment driver pins: 32
LCD Bias: 1/3, 1/2 bias
LCD Duty: 1/4, 1/3, 1/2 duty
• Idle Mode: CPU is idle, LCD display
remains working
Package Type:
• Sleep Mode: The whole chip stops working
•
•
•
•
•
Dice form: 59 pins
• Input port wake-up function (Port 6, Port 8).
Works under Idle and Sleep modes.
QFP 64-pin: EM78P468NBQ64 (14mm×20mm)
LQFP 64-pin: EM78P468NBL64 (7mm×7mm)
LQFP 44-pin: EM78P470NL44 (10mm×10mm)
QFP 44-pin: EM78P470NQ44 (10mm×10mm)
• Operation speed: DC ~ 10 MHz clock input
• Dual clock operation
Oscillation Mode:
• High frequency oscillator can be selected
from among Crystal, RC, or PLL (phase lock
loop)
Note: These are all Green Products which do not
contain hazardous substances.
• Low frequency oscillator can select
between Crystal and RC modes
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
• 1
EM78P468NB/P470N
8-Bit Microcontroller
3 Pin Assignment
Figure 3-1 64-Pin QFP EM78P468NBQ64 Pin Assignment
Figure 3-2 64-Pin LQFP EM78P468NBL64 Pin Assignment
Poduct Specification (V1.2) 11.30.2012
2 •
(This specification is subject to change without further notice)
EM78P468NB/P470N
8-Bit Microcontroller
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
SEG27/P83
SEG26/P82
SEG25/P81
SEG24/P80
SEG23/P77
SEG22/P76
SEG21/P75
SEG20/P74
SEG19/P73
SEG18/P72
SEG17/P71
34
35
36
37
38
39
40
41
42
43
44
22
21
20
19
18
17
16
15
14
13
12
P55/INT1 (DINCLK)
P54/INT0 (ACLK)
XOUT
XIN
VDD
EM78P470NQ44
EM78P470NL44
OSCO
R-OSCI
GND
/RESET
VLCD3
VLCD2
1
0
1
1
1
2
3
4
5
6
7
8
9
Figure 3-3 44-Pin QFP EM78470NQ44 / LQFP EM78P470NL44 Pin Assignment
Legend: The arrowheads shown on each pin in the above figures stand for the
following types of function:
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
• 3
EM78P468NB/P470N
8-Bit Microcontroller
4 Pin Description
4.1 Pin Description
Input
Type
Output
Type
Symbol
Function
Description
P54
ST
ST
CMOS Bidirectional I/O pin
External interrupt pin. INT0 interrupt source
can be set to falling or rising edge by IOC71
register Bit 7 (INT_EDGE).
P54/INT0
(ACLK)
INT0
−
Wakes up from Sleep mode and Idle mode
when the pin status changes.
(ACLK)
P55
ST
ST
−
ACLK pin for Writer programming
Bidirectional I/O pin
CMOS
External interrupt pin.
P55/INT1
(DINCK)
Interrupt source is a falling edge signal.
INT1
ST
−
Wakes up from Sleep mode and Idle mode
when the pin status changes.
(DINCK)
P56
ST
ST
−
DINCK pin for Writer programming
Bidirectional I/O pin. This pin works in Normal/
Green/Idle mode.
CMOS
P56/TCC
(DATAIN)
TCC
ST
ST
−
−
External input pin of TCC
(DATAIN)
DATAIN pin for Writer programming
Bidirectional I/O pin. This pin is capable of
sinking 20mA/5V.
P57
ST
ST
CMOS
P57/IROUT
IROUT
−
IR/PWM mode output pin
Programmable pull-high, pull-down and
P60
(OEB)
P61
ST
ST
ST
ST
CMOS open-drain. All pins wake up from Sleep and
Idle modes when the pin status changes.
P60
(OEB)
−
OEB pin for Writer programming
Programmable pull-high, pull-down and
CMOS open-drain. All pins wake up from Sleep and
Idle modes when the pin status changes
P61
(PGM)
(PGM)
−
PGM pin for Writer programming
Bidirectional I/O pin with programmable
pull-high, pull-down and open-drain. All pins
wake up from Sleep and Idle modes when the
pin status changes
P62
P63
P62
P63
ST
ST
CMOS
Bidirectional I/O pin with programmable
pull-high, pull-down and open-drain. All pins
wake up from Sleep and Idle modes when the
pin status changes
CMOS
4 •
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
EM78P468NB/P470N
8-Bit Microcontroller
Input
Type
Output
Type
Symbol
Function
Description
Bidirectional I/O pin with programmable
pull-high, pull-down and open-drain. All pins
wake up from Sleep and Idle modes when the
pin status changes
P64
P64
ST
ST
ST
ST
CMOS
CMOS
CMOS
CMOS
Bidirectional I/O pin with programmable
pull-high, pull-down and open-drain. All pins
wake up from Sleep and Idle modes when the
pin status changes
P65
P66
P67
P65
P66
P67
Bidirectional I/O pin with programmable
pull-high, pull-down and open-drain. All pins
wake up from Sleep and Idle modes when the
pin status changes
Bidirectional I/O pin with programmable
pull-high, pull-down and open-drain. All pins
wake up from Sleep and Idle modes when the
pin status changes
COM3~0
SEG0~15
COM3~0
SEG0~15
SEG16
−
−
−
AN
AN
AN
LCD common output pin
LCD segment output pin
LCD segment output pin
Bidirectional I/O pin . All pins wake up from
CMOS Sleep and Idle modes when the pin status
changes
SEG16/P70
SEG17/P71
SEG18/P72
SEG19/P73
SEG20/P74
SEG21/P75
P70
SEG17
P71
ST
−
AN
LCD segment output pin
Bidirectional I/O pin . All pins wake up from
CMOS Sleep and Idle modes when the pin status
changes
ST
−
SEG18
P73
AN
LCD segment output pin
Bidirectional I/O pin . All pins wake up from
CMOS Sleep and Idle modes when the pin status
changes
ST
−
SEG19
P73
AN
LCD segment output pin
Bidirectional I/O pin . All pins wake up from
CMOS Sleep and Idle modes when the pin status
changes
ST
−
SEG20
P74
AN
LCD segment output pin
Bidirectional I/O pin . All pins wake up from
CMOS Sleep and Idle modes when the pin status
changes
ST
−
SEG21
P75
AN
LCD segment output pin
Bidirectional I/O pin . All pins wake up from
CMOS Sleep and Idle modes when the pin status
changes
ST
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
• 5
EM78P468NB/P470N
8-Bit Microcontroller
Input
Type
Output
Type
Symbol
Function
Description
SEG22
−
ST
−
AN
LCD segment output pin
Bidirectional I/O pin . All pins wake up from
SEG22/P76
P76
SEG23
P77
CMOS Sleep and Idle modes when the pin status
changes
AN
LCD segment output pin
Bidirectional I/O pin . All pins wake up from
SEG23/P77
SEG24/P80
SEG25/P81
SEG26/P82
SEG27/P83
ST
−
CMOS Sleep and Idle modes when the pin status
changes
SEG24
P80
AN
LCD segment output pin
Bidirectional I/O pin with programmable
ST
−
CMOS pull-high. All pins wake up from Sleep and Idle
modes when the pin status changes
SEG25
P81
AN
LCD segment output pin
Bidirectional I/O pin with programmable
ST
−
CMOS pull-high. All pins wake up from Sleep and Idle
modes when the pin status changes
SEG26
P82
AN
LCD segment output pin
Bidirectional I/O pin with programmable
ST
−
CMOS pull-high. All pins wake up from Sleep and Idle
modes when the pin status changes
SEG27
P83
AN
LCD segment output pin
Bidirectional I/O pin with programmable
ST
−
CMOS pull-high. All pins wake up from Sleep and Idle
modes when the pin status changes
SEG28
P84
AN
CMOS
AN
LCD segment output pin
Bidirectional I/O pin with programmable
pull-high. All pins wake up from Sleep and Idle
modes when the pin status changes
SEG28/P84
SEG29/P85
SEG30/P86
SEG31/P87
ST
−
SEG29
P85
LCD segment output pin
Bidirectional I/O pin with programmable
ST
−
CMOS pull-high. All pins wake up from Sleep and Idle
modes when the pin status changes
SEG30
P86
AN
LCD segment output pin
Bidirectional I/O pin with programmable
ST
−
CMOS pull-high. All pins wake up from Sleep and Idle
modes when the pin status changes
SEG31
P87
AN
LCD segment output pin
Bidirectional I/O pin with programmable
ST
CMOS pull-high. All pins wake up from Sleep and Idle
modes when the pin status changes
6 •
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
EM78P468NB/P470N
8-Bit Microcontroller
Input
Type
Output
Type
Symbol
VB
Function
Description
VB
−
−
−
−
AN
AN
AN
AN
Connects capacitors for LCD bias voltage
Connects capacitors for LCD bias voltage
One of LCD bias voltage
VA
VA
VLCD2
VLCD3
VLCD2
VLCD3
One of LCD bias voltage
General-purpose Input only
Low active. If it remains at logic low, the device
will reset.
/RESET
VPP
ST
ST
−
−
/RESET
(VPP)
/RESET pin for writer programming
Vpp pin for Writer programming
In Crystal mode: crystal input
In RC mode: resistor pull high
In PLL mode: connect a 0.01μF capacitance to
R-OSCI
R-OSCI
AN
−
GND
Connect a 0.01 μF capacitor to GND and code
option selects PLL mode when high oscillator is
not used.
In Crystal mode: crystal input
OSCO
Xin
OSCO
Xin
−
XTAL
In RC mode: instruction clock output
In Crystal mode: Input pin for sub-oscillator.
Connect to a 32.768kHz crystal.
XTAL
−
In Crystal mode: Connect to a 32.768kHz
crystal.
Xout
Xout
−
XTAL
In RC mode: instruction clock output
NC
NC
−
−
−
−
No connection
Power
VDD
GND
VDD
GND
Power
Power
Ground
Legend: ST: Schmitt Trigger input
CMOS: CMOS output
AN: analog pin
XTAL: oscillation pin for crystal / resonator
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
• 7
EM78P468NB/P470N
8-Bit Microcontroller
Pin Status with Enabled Functions
I/O Status
Pin Control
Pull Low
Pin Function
Pin Change
I/O Direction
Pull High
O.D.
WK/Int.
General Input
General Output
TCC
Input
Output
Input
Input
Output
Input
Input
Input
Input
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
S/W
S/W
LCD Driver
TC-OUT
Reset
Disable
Init: Enable
S/W
Disable
S/W
S/W
EX_INT
S/W
S/W
OSCI
Disable
Disable
Disable
Disable
OSCO
NOTE
Disable: → It is always disabled
Enable: → It is always enabled
S/W: → It can be controlled by register. The initial status is disabled.
1. If the pin is not working as general I/O, it is a must to disable the Pin Change
Wake-up/Interrupt function.
2. Priority: Digital function output > digital function input > general I/O
8 •
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
EM78P468NB/P470N
8-Bit Microcontroller
5 Block Diagram
Figure 5-1 System Block Diagram
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
• 9
EM78P468NB/P470N
8-Bit Microcontroller
6 Functional Description
6.1 Operational Registers
6.1.1 R0/IAR (Indirect Addressing Register − Address: 00h)
R0 is not a physically implemented register. Its major function is to perform as an
indirect address pointer. Any instruction that uses R0 as a register, actually accesses
the data pointed by the RAM Select Register (R4).
6.1.2 R1/TCC (Timer Clock Counter − Address: 01h)
The Timer Clock Counter is incremented by an external signal edge applied to TCC, or
by the instruction cycle clock. It is written and read by the program as any other
register.
6.1.3 R2/PC (Program Counter − Address: 02h)
The R2 structure is depicted in Figure 6-1 shown below.
Figure 6-1 Program Counter Organization
The configuration structure generates 4K×13 bits on-chip ROM addresses to the
relative programming instruction codes.
The contents of R2 are all set to "0"s when a Reset condition occurs.
"JMP" instruction allows direct loading of the lower 10 program counter bits. Thus,
"JMP" allows the PC to jump to any location within a page.
"CALL" instruction loads the lower 10 bits of the PC, and PC+1 are pushed onto the
stack. Thus, the subroutine entry address can be located anywhere within a page.
10 •
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
EM78P468NB/P470N
8-Bit Microcontroller
"RET" ("RETL k", "RETI") instruction loads the program counter with the contents
of the top-level stack.
"ADD R2, A" allows a relative address to be added to the current PC, and the ninth
and above bits of the PC will increase progressively.
"MOV R2, A" allows loading of an address from the "A" register to the lower 8 bits of
the PC, and the ninth and tenth bits (A8 ~ A9) of the PC remain unchanged.
The most significant bits (A10~A11) are loaded with the contents of PS0~PS1 into
the Status Register (R3) upon execution of a "JMP" or "CALL" instruction.
6.1.3.1 Data Memory Configuration
SBANK0
SBANK1
ADDRESS
00
IOCPAGE0
IOCPAGE1
R0
01
R1 (TCC)
02
R2 (PC)
R3
03
(Status & ROM page)
04
R4 (RAM selection)
R5 (Port 5 & IOC page)
R6 (Port 6)
IOC50
(Port 5 IO control)
IOC60
(Port 6 IO control)
IOC 70
05
R5 (TBRDH)
R6 (TBRDL)
IOC51 (unused)
IOC61
(Wake-up register)
IOC71
06
07
R7 (Port 7)
(Port 7 IO control)
IOC80
(Port 8 IO control)
IOC90
(RAM Address)
IOCA0
(RAM Data)
(TCC control)
IOC81
(WDT control)
IOC91
(CNT1/2 control)
IOCA1
(H/L pulse time control)
08
R8 (Port 8)
09
R9 (LCD control)
RA
0A
(LCD contrast & addr.)
0B
RB (LCD data)
IOCB0 (CNT1 preset)
IOCB1 (Port 6 pull-high)
RC
IOCC1
(Port 6 open-drain)
0C
0D
0E
IOCC0 (CNT2 preset)
(Counter enable reg.)
RD
(System Clock control)
IOCD0 (High pulse timer
preset)
IOCE0
IOCD1 (Port 8 pull-high)
IOCE1
(Low pulse timer preset) (Port 6 pull down)
RE (IR control)
0F
RF (Interrupt status)
IOCF0 (interrupt mask ) IOCF1 (unused)
10
|
16 byte common register
1F
20
|
3F
Bank 0
Bank 1
Bank 2
Bank 3
32 byte common register 32 byte common register 32 byte common register 32 byte common register
Figure 6-2 Data Memory Configuration
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
• 11
EM78P468NB/P470N
8-Bit Microcontroller
6.1.4 R3/SR (Status Register)
(Address: 03h)
Bit 7
Bit 6
PS1
R/W
Bit 5
PS0
R/W
Bit 4
T
Bit 3
P
Bit 2
Z
Bit 1
DC
Bit 0
C
-
R/W
R/W
R/W
R/W
R/W
Bit 7: Unused bit
Bits 6 ~ 5 (PS1 ~ PS0): Page select bits
PS1
0
PS0
0
ROM Page (Address)
Page 0 (000H ~ 3FFH)
Page 1 (400H ~ 7FFH)
Page 2 (800H ~ BFFH)
Page 3 (C00H ~ FFFH)
0
1
1
0
1
1
PS0~PS1 are used to select a ROM page. You can use the “PAGE” instruction (e.g.,
“PAGE 1”) or set PS1~PS0 bits to change the ROM page. When executing a "JMP",
"CALL", or other instructions which causes the program counter to be changed (e.g.,
“MOV R2, A”), the PS0~PS1 are loaded into the 11th and 12th bits of the program
counter where it selects one of the available program memory pages. Note that “RET”
(“RETL”, “RETI”) instruction does not change the PS0~PS1 bits. That is, the return will
always be to the page from where the subroutine was called, regardless of the current
setting of PS0~PS1 bits.
Bit 4 (T): Time-out bit. Set to “1” by the "SLEP" and "WDTC" commands or during
power up and reset to “0” by WDT timeout.
Event
T
0
0
1
1
1
P
0
1
0
1
1
Remark
WDT wake-up from Sleep mode
WDT time out (not Sleep mode)
/RESET wake-up from Sleep
Power up
−
−
−
−
Low pulse on /RESET
×: don't care
Bit 3 (P): Power down bit. Set to “1” during power on or by a "WDTC" command and
reset to “0” by a "SLEP" command.
Bit 2 (Z): Zero flag
Bit 1 (DC): Auxiliary carry flag
Bit 0 (C): Carry flag
12 •
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
EM78P468NB/P470N
8-Bit Microcontroller
6.1.5 R4/RSR (RAM Select Register)
(Address: 04h)
Bit 7
RBS1
R/W
Bit 6
RBS0
R/W
Bit 5
RSR5
R/W
Bit 4
RSR4
R/W
Bit 3
RSR3
R/W
Bit 2
RSR2
R/W
Bit 1
RSR1
R/W
Bit 0
RSR0
R/W
Bits 7 ~ 6 (RBS1 ~ RBS0): Determine which bank among the four banks, is activated
(see the data memory configuration in Figure 6-2. Use the “BANK”
instruction (e.g., “Bank 1”) to change banks.
Bits 5 ~ 0 (RSR5 ~ RSR0): Used to select up to 64 registers (Address: 00~3F) under
indirect addressing mode. If no indirect addressing is used, the RSR is used
as an 8-bit general purpose read/writer register.
6.1.6 SBANK0 R5/Port 5 (Port 5 I/O Data and Page of Register
Selection)
(Address: 05h)
Bit 7
P57
Bit 6
P56
Bit 5
P55
Bit 4
P54
Bit 3
Bit 2
Bit 1
Bit 0
IOCPAGE
R/W
-
-
-
-
-
-
R/W
R/W
R/W
R/W
Bits 7 ~ 4 (P57 ~ P54):4-bit I/O registers of Port 5. Use the IOC50 register to define
each bit either as input or output.
Bits 3 ~ 1:Unused bits
Bit 0 (IOCPAGE): Switch Registers IOC5 ~ IOCF to another page
IOCPAGE = “0”: Page 0 (Registers IOC 50 to IOC F0) selected
IOCPAGE = “1”: Page 1 (Registers IOC 51 to IOC F1) selected
6.1.7 SBANK0 R6/Port 6 (Port 6 I/O Data Register)
(Address: 06h)
Bit 7
P67
Bit 6
P66
Bit 5
P65
Bit 4
P64
Bit 3
P63
Bit 2
P62
Bit 1
P61
Bit 0
P60
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits 7 ~ 0 (P67 ~ P60): 8-bit I/O registers of Port 6. Use the IOC60 register to define
each bit either as input or output.
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
• 13
EM78P468NB/P470N
8-Bit Microcontroller
6.1.8 SBANK0 R7/Port 7 (Port 7 I/O Data Register)
(Address: 07h)
Bit 7
Bit 6
P76
Bit 5
P75
Bit 4
P74
Bit 3
P73
Bit 2
P72
Bit 1
P71
Bit 0
P70
P77
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits 7 ~ 0 (P77 ~ P70):8-bit I/O registers of Port 7. Use the IOC70 register to define
each bit either as input or output.
6.1.9 SBANK0 R8/Port 8 (Port 8 I/O Data Register)
(Address: 08h)
Bit 7
P87
Bit 6
P86
Bit 5
P85
Bit 4
P84
Bit 3
P83
Bit 2
P82
Bit 1
P81
Bit 0
P80
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits 7 ~ 0 (P87 ~ P80): 8-bit I/O registers of Port 8. Use IOC80 register to define each
bit either as input or output.
6.1.10 SBANK0 R9/LCDCR (LCD Control Register)
(Address: 09h)
Bit 7
BS
Bit 6
DS1
R/W
Bit 5
DS0
R/W
Bit 4
LCDEN
R/W
Bit 3
Bit 2
LCDTYPE LCDF1
R/W R/W
Bit 1
Bit 0
LCDF0
R/W
-
-
R/W
Bit 7 (BS): LCD bias select bit
BS = “0”: 1/2 bias
BS = “1”: 1/3 bias
Bit 6 ~ 5 (DS1 ~ DS0): LCD duty select
DS1
DS0
LCD Duty
0
0
1
0
1
×
1/2 duty
1/3 duty
1/4 duty
Bit 4 (LCDEN): LCD enable bit
LCDEN = “0”: LCD circuit disabled. All common/segment outputs are set
to ground (GND) level.
LCDEN = “1”: LCD circuit enabled
Bit 3: Unused bit
14 •
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
EM78P468NB/P470N
8-Bit Microcontroller
Bit 2 (LCDTYPE): LCD drive waveform type select bit
LCDTYPE = “0”: A type waveform
LCDTYPE = “1”: B type waveform
Bits 1 ~ 0 (LCDF1 ~ LCDF0): LCD frame frequency control bits
LCD Frame Frequency (e.g., Fs=32.768kHz)
LCDF1
LCDF0
1/2 Duty
1/3 Duty
1/4 Duty
0
0
1
1
0
1
0
1
Fs/(256×2)=64.0
Fs/(280×2)=58.5
Fs/(304×2)=53.9
Fs/(232×2)=70.6
Fs/(172×3)=63.5
Fs/(188×3)=58.0
Fs/(204×3)=53.5
Fs/(156×3)=70.0
Fs/(128×4)=64.0
Fs/(140×4)=58.5
Fs/(152×4)=53.9
Fs/(116×4)=70.6
Fs: sub-oscillator frequency
6.1.11 SBANK0 RA/LCD_ADDR (LCD Address)
(Address: 0Ah)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
LCD_A4 LCD_A3 LCD_A2 LCD_A1 LCD_A0
R/W
R/W
R/W
R/W
R/W
Bits 7 ~ 5: Unused bits
Bits 4 ~ 0 (LCDA4 ~ LCDA0): LCD RAM addresses
RB (LCD Data Buffer)
RA
Segment
Bit 3
Bit 2
Bit 1
Bit 0
(LCD Address)
Bits 7 ~4
(LCD_D3) (LCD_D2) (LCD_D1) (LCD_D0)
00H
01H
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
SEG0
SEG1
SEG2
|
02H
|
|
1DH
1EH
−
−
−
×
−
−
−
−
SEG29
SEG30
SEG31
−
−
−
−
−
−
−
−
1FH
Common
COM3
COM2
COM1
COM0
6.1.12 SBANK0 RB/LCD_DB (LCD Data Buffer)
(Address: 0Bh)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
LCD_D3 LCD_D2 LCD_D1 LCD_D0
R/W R/W R/W R/W
Bits 7 ~ 4: Unused bits
Bits 3 ~ 0 (LCD_D3 ~ LCD_D0): LCD RAM data transfer register
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
• 15
EM78P468NB/P470N
8-Bit Microcontroller
6.1.13 SBANK0 RC/CNTER (Counter Enable Register)
(Address: 0Ch)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
LPWTEN HPWTEN CNT2EN CNT1EN
R/W R/W R/W R/W
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
Bits 7 ~ 4: Unused bits
Bit 3 (LPWTEN): Low pulse width timer enable bit
LPWTEN = “0”: Disable LPWT. Stop counting operation.
LPWTEN = “1”: Enable LPWT. Start counting operation.
Bit 2 (HPWTEN): High pulse width timer enable bit
HPWTEN = “0”: Disable HPWT. Stop counting operation.
HPWTEN = “1”: Enable HPWT. Start counting operation.
Bit 1 (CNT2EN): Counter 2 enable bit
CNT2EN = “0”: Disable Counter 2. Stop counting operation.
CNT2EN = “1”: Enable Counter 2. Start counting operation.
Bit 0 (CNT1EN): Counter 1 enable bit
CNT1EN = “0”: Disable Counter 1. Stop counting operation.
CNT1EN = “1”: Enable Counter 1. Start counting operation.
16 •
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
EM78P468NB/P470N
8-Bit Microcontroller
6.1.14 SBANK0 RD/SBPCR (System, Booster and PLL Control
Register)
(Address: 0Dh)
Bit 7
SBANK
R/W
Bit 6
CLK2
R/W
Bit 5
CLK1
R/W
Bit 4
CLK0
R/W
Bit 3
IDLE
R/W
Bit 2
BF1
R/W
Bit 1
BF0
R/W
Bit 0
CPUS
R/W
Bit 7 (SBANK): Special Register 0x05 ~ 0x06 bank select bit
0: SBANK 0
1: SBANK 1
Bits 6 ~ 4 (CLK2 ~ CLK0): Main clock select bits for PLL mode (code option select)
CLK2
CLK1
CLK0
Main Clock
Fs×130
Fs×65
Example Fs=32.768K
4.26 MHz
0
0
0
0
1
0
0
1
1
×
0
1
0
1
×
2.13 MHz
Fs×65/2
Fs×65/4
Fs×244
1.065 MHz
532kHz
8 MHz
Bit 3 (IDLE): Idle mode enable bit. This bit determines the intended mode of the SLEP
instruction.
Idle = ”0”+SLEP instruction → Sleep mode
Idle = ”1”+SLEP instruction → Idle mode
NOTE
NOP instruction must be added after SLEP instruction.
Example: Idle mode: Idle bit = “1” +SLEP instruction + NOP instruction
Sleep mode: Idle bit = “0” +SLEP instruction + NOP instruction
Bits 2, 1 (BF1, BF0): LCD booster frequency select bits to adjust VLCD 2, 3 driving.
BF1
0
BF0
0
Booster Frequency
Fs
0
1
Fs/4
Fs/8
Fs/16
1
0
1
1
Bit 0 (CPUS): CPU oscillator source select. When CPUS=0, the CPU oscillator selects
the Sub-oscillator and the Main oscillator is stopped.
CPUS = “0”: Sub-oscillator (Fs) is selected
CPUS = “1”: Main oscillator (Fm) is selected
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
• 17
EM78P468NB/P470N
8-Bit Microcontroller
CPU Operation Mode
Figure 6-3 CPU Operation Mode
Note
(*) If the watchdog function is enabled before going into sleep mode, some circuits like
the timer (its clock source is Fs) must stop counting.
If the watchdog function is enabled before going into sleep mode, some circuits like
timer (its clock source is the external pin) can still count and its interrupt flag can be
active at matching condition as corresponding interrupt is enabled. But the CPU
cannot be waken-up by this event.
(**)
Switching Operation Mode at Sleep → Normal,
Green → Normal:
If the clock source of timer is Fm, the timer/counter must stop counting at sleep or
green mode. Then, the timer can continue to count until the clock source is stable at
normal mode. That clock source is stable means the CPU starts to work at normal
mode.
Switching Operation Mode at Sleep → Green:
If the clock source of timer is Fs, the timer must stop counting at sleep mode. Then,
the timer can continue to count until the clock source is stable at green mode. That
clock source is stable means the CPU starts to work at green mode.
18 •
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
EM78P468NB/P470N
8-Bit Microcontroller
Switching Operation Mode at Sleep → Normal:
If the clock source of the timer is Fs, the timer must stop counting at sleep mode.
Then, the timer can continue to count until clock source is stable at normal mode.
That clock source is stable means the CPU starts to work at normal mode.
Pin-Reset
Power-on
WDT
Fmain Fsub
LVR
N / G / I
S
IRC 16ms + WSTO + 8*1/Fmain
WSTO + 8*1/Fmain
WSTO + 8*1/Fmain
WSTO + 510*1/Fsub
IRC
XT
XT 16ms + WSTO + 510*1/Fsub WSTO + 8*1/Fmain
IRC 16ms + WSTO + 510*1/Fmain WSTO + 510*1/Fmain WSTO + 510*1/Fmain
XT 16ms + WSTO + 510*1/Fsub WSTO + 510*1/Fmain WSTO + 510*1/Fsub
Fmain Fsub
G Æ N
I Æ N
S Æ N
IRC
WSTO + 8*1/Fmain
WSTO + 8*1/Fmain
WSTO + 510*1/Fmain
WSTO + 510*1/Fmain
WSTO + 8*1/Fmain
WSTO + 8*1/Fmain
WSTO + 8*1/Fmain
WSTO + 510*1/Fsub
IRC
XT
IRC
XT
XT
WSTO + 510*1/Fmain WSTO + 510*1/Fmain
WSTO + 510*1/Fmain WSTO + 510*1/Fsub
Fmain Fsub
I Æ G
S Æ G
WSTO + 8*1/Fsub
WSTO + 8*1/Fsub
IRC
IRC
XT
WSTO + 8*1/Fsub
WSTO + 510*1/Fsub
IRC
XT
WSTO + 8*1/Fsub
WSTO + 8*1/Fsub
WSTO + 8*1/Fsub
XT
WSTO + 510*1/Fsub
WSTO: Waiting Time from Start-to-Oscillation
N: Normal mode G: Green mode I: Idle mode S: Sleep mode
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
• 19
EM78P468NB/P470N
8-Bit Microcontroller
6.1.15 SBANK0 RE/IRCR (IR Control Register)
(Address: 0Eh)
Bit 7
IRE
Bit 6
HF
Bit 5
LGP
R/W
Bit 4
Bit 3
IROUTE
R/W
Bit 2
TCCE
R/W
Bit 1
EINT1
R/W
Bit 0
EINT0
R/W
-
-
R/W
R/W
Bit 7 (IRE): Infrared Remote Enable bit
IRE = “0”: Disable the IR/PWM function. The state of P5.7/IROUT pin
is determined by Bit 7 of IOC 50 if it is used as IROUT.
IRE = “1”: Enable IR or PWM function.
Bit 6 (HF): High carry frequency
HF = “0”: For PWM application, disable the H/W modulator function.
The IROUT waveform is generated according to high-pulse
and low-pulse time as determined by the respective high
pulse and low pulse width timers. Counter 2 is an
independent auto reload timer.
HF = “1”: For IR application mode, enable the H/W modulator function.
The low time section of the generated pulse is modulated with
the Fcarrier frequency. The Fcarrier frequency is provided by
Counter 2.
Bit 5 (LGP): IROUT for low pulse width timer
LGP = “0”: Both high-pulse width timer register and low-pulse width
timer are valid.
LGP = “1”: The high-pulse width timer register is ignored. So the
IROUT waveform is dependent on the low-pulse width timer
register only.
Bit 4: Unused bit
Bit 3 (IROUTE): Defines the function of the P57/IROUT pin
IROUTE = “0”: Defined as bidirectional general I/O pin
IROUTE = “1”: Defined as IR or PWM output pin. The P57 control bit
(Bit 7 of IOC50) must be set to “0.”
Bit 2 (TCCE): Defines the function of the P56/TCC pin.
TCCE = “0”: Defined as bidirectional general I/O pin
TCCE = “1”: Defined as external input pin of TCC. The P56 control bit
(Bit 6 of IOC50) must be set to “1.”
20 •
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
EM78P468NB/P470N
8-Bit Microcontroller
Bit 1 (EINT1): Defines the function of the P55/INT1 pin.
EINT1 = “0”: Defined as bidirectional general I/O pin.
EINT1 = “1”: Define as external interrupt pin of INT1. The P55 control
bit (Bit 5 of IOC50) must be set to “1.”
Bit 0 (EINT0): Defines the function of the P54/INT0 pin.
EINT0 = “0”: Defined as bidirectional general I/O pin.
EINT0 = “1”: Defined as external interrupt pin of INT0. The P54 control
bit (Bit 4 of IOC50) must be set to “1.”
6.1.16 SBANK0 RF/ISR (Interrupt Status Register)
(Address: 0Fh)
Bit 7
ICIF
F
Bit 6
LPWTF
F
Bit 5
HPWTF
F
Bit 4
CNT2F
F
Bit 3
CNT1F
F
Bit 2
INT1F
F
Bit 1
INT0F
F
Bit 0
TCIF
F
These bits are set to “1” when interrupt occurs respectively.
Bit 7 (ICIF): Port 6 and Port 8 input status change interrupt flag. Set when Port 6 and
Port 8 input status changes.
Bit 6 (LPWTF): Interrupt flag of the internal low-pulse width timer underflows.
Bit 5 (HPWTF): Interrupt flag of the internal high-pulse width timer underflows.
Bit 4 (CNT2F): Interrupt flag of the internal Counter 2 underflows.
Bit 3 (CNT1F): Interrupt flag of the internal Counter 1 underflows.
Bit 2 (INT1F): External INT1 pin interrupt flag
Bit 1 (INT0F): External INT0 pin interrupt flag
Bit 0 (TCIF): TCC timer overflow interrupt flag. Set when TCC timer overflows.
6.1.17 SBANK1 R5/TBRDH (TBRD High Address)
(Address: 05h)
Bit 7
HLB
R/W
Bit 6
Bit 5
Bit 4
Bit 3
RBit11
R/W
Bit 2
RBit10
R/W
Bit 1
RBit9
R/W
Bit 0
RBit8
R/W
-
-
-
-
-
-
Bit 7 (HLB): Take MLB or LSB at machine code
HLB = “0”: low 8 bits machine code
HLB = “1”: low 5 bits machine code
Bits 6 ~ 4: Not used
Bits 3 ~ 0 (RBit11 ~ RBit8): program ROM high address.
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
• 21
EM78P468NB/P470N
8-Bit Microcontroller
6.1.18 SBANK1 R6/TBRDL (TBRD Low Address)
(Address: 06h)
Bit 7
Bit 6
RBit6
R/W
Bit 5
RBit5
R/W
Bit 4
RBit4
R/W
Bit 3
RBit3
R/W
Bit 2
RBit2
R/W
Bit 1
RBit1
R/W
Bit 0
RBit0
R/W
RBit7
R/W
Bits 7 ~ 0 (RBit7~RBit0): Program ROM low address.
6.1.19 General Purpose Register (Address: 10h~3Fh; R10~R3F)
R10~R1F and R20~R3F (Banks 0~3) are general purpose registers.
6.2 Special Purpose Register
6.2.1 A (Accumulator)
Internal data transfer operation, or instruction operand holding usually involves the
temporary storage function of the Accumulator, which is not an addressable register.
6.2.2 IOC Page 0 (IOC50 ~ IOCF0, Bit 0 of R5 = “0”)
6.2.2.1 IOC50/P5CR (Port 5 I/O and Ports 7, 8 for LCD Segment Control Register)
(Address: 05h, Bit 0 of R5 = “0”)
Bit 7
IOC57
R/W
Bit 6
IOC56
R/W
Bit 5
IOC55
R/W
Bit 4
IOC54
R/W
Bit 3
P8HS
R/W
Bit 2
P8LS
R/W
Bit 1
P7HS
R/W
Bit 0
P7LS
R/W
Bits 7 ~ 4 (IOC57 ~ 54): Port 5 I/O direction control register
IOC5x = “0”: Set the relative P5x I/O pins as output
IOC5x = “1”: Set the relative P5x I/O pin into high impedance (input pin)
Bit 3 (P8HS): Switch to high nibble I/O of Port 8 or to LCD segment output while
sharing pins with SEGxx/P8x pins.
P8HS = “0”: Select high nibble of Port 8 as normal P84~P87
P8HS = “1”: Select LCD segment output as SEG 28~SEG 31 output
Bit 2 (P8LS): Switch to low nibble I/O of Port 8 or to LCD segment output while sharing
pins with SEGxx/P8.x pins.
P8LS = “0”: Select low nibble of Port 8 as normal P80~P83
P8LS = “1”: Select LCD Segment output as SEG 24~SEG 27 output
22 •
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
EM78P468NB/P470N
8-Bit Microcontroller
Bit 1 (P7HS): Switch to high nibble I/O of Port 7 or to LCD segment output while
sharing pins with SEGxx/P7x pins.
P7HS = “0”: Select high nibble of Port 7 as normal P74~P77
P7HS = “1”: Select LCD Segment output as SEG 20~SEG 23 output
Bit 0 (P7LS): Switch to low nibble I/O of Port 7 or to LCD segment output while sharing
pins with SEGxx/P7x pins.
P7LS = “0”: Select low nibble of Port 7 as normal P70~P73
P7LS = “1”: Select LCD segment output as SEG 16~SEG 19 output
6.2.2.2 IOC60/P6CR (Port 6 I/O Control Register)
(Address: 06h, Bit 0 of R5 = “0”)
Bit 7
IOC67
R/W
Bit 6
IOC66
R/W
Bit 5
IOC65
R/W
Bit 4
IOC64
R/W
Bit 3
IOC63
R/W
Bit 2
IOC62
R/W
Bit 1
IOC61
R/W
Bit 0
IOC60
R/W
Bits 7 ~ 4 (IOC67 ~ IOC60): Port 6 I/O direction control register
IOC6x = “0”: Set the relative Port 6x I/O pins as output
IOC6x = “1”: Set the relative Port 6x I/O pin into high impedance (input pin)
6.2.2.3 IOC70/P7CR (Port 7 I/O Control Register)
(Address: 07h, Bit 0 of R5 = “0”)
Bit 7
IOC77
R/W
Bit 6
IOC76
R/W
Bit 5
IOC75
R/W
Bit 4
IOC74
R/W
Bit 3
IOC73
R/W
Bit 2
IOC72
R/W
Bit 1
IOC71
R/W
Bit 0
IOC70
R/W
Bits 7 ~ 0 (IOC77 ~ IOC70): Port 7 I/O direction control register
IOC7x = “0”: Set the relative Port 7x I/O pins as output
IOC7x = “1”: Set the relative Port 7x I/O pin into high impedance (input pin)
6.2.2.4 IOC80/P8CR (Port 8 I/O Control Register)
(Address: 08h, Bit 0 of R5 = “0”)
Bit 7
IOC87
R/W
Bit 6
IOC86
R/W
Bit 5
IOC85
R/W
Bit 4
IOC84
R/W
Bit 3
IOC83
R/W
Bit 2
IOC82
R/W
Bit 1
IOC81
R/W
Bit 0
IOC80
R/W
Bits 7 ~ 0 (IOC 87 ~ IOC 80): Port 8 I/O direction control register
IOC8x = “0”: Set the relative Port 8x I/O pins as output
IOC8x = “1”: Set the relative Port 8x I/O pin into high impedance (input pin)
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
• 23
EM78P468NB/P470N
8-Bit Microcontroller
6.2.2.5 IOC90/RAM_ADDR (128 Bytes RAM Address)
(Address: 09h, Bit 0 of R5 = “0”)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
RAM_A6 RAM_A5 RAM_A4 RAM_A3 RAM_A2 RAM_A1 RAM_A0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 7: Unused bit, must be fixed to “0”.
Bits 6 ~ 0 (RAM_A6 ~ RAM_A0): 128 bytes RAM address
6.2.2.6 IOCA0/RAM_DB (128 Bytes RAM Data Buffer)
(Address: 0Ah, Bit 0 of R5 = “0”)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RAM_D7 RAM_D6 RAM_D5 RAM_D4 RAM_D3 RAM_D2 RAM_D1 RAM_D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits 7 ~ 0 (RAM_D7 ~RAM_D0): 128 bytes RAM data transfer register
6.2.2.7 IOCB0/CNT1PR (Counter 1 Preset Register)
(Address: 0Bh, Bit 0 of R5 = “0”)
Bit 7
Bit 7
R/W
Bit 6
Bit 6
R/W
Bit 5
Bit 5
R/W
Bit 4
Bit 4
R/W
Bit 3
Bit 3
R/W
Bit 2
Bit 2
R/W
Bit 1
Bit 1
R/W
Bit 0
Bit 0
R/W
Bit 7 ~ Bit 0: These are Counter 1 buffers which can be read and written to. Counter 1
is an 8-bit down-count timer with 8-bit prescaler used to preset the
counter and read the preset value. The prescaler is set by the IOC91
register. After an interrupt, the preset value will be auto-reloaded.
6.2.2.8 IOCC0/CNT2PR (Counter 2 Preset Register)
(Address: 0Ch, Bit 0 of R5 = “0”)
Bit 7
Bit 7
R/W
Bit 6
Bit 6
R/W
Bit 5
Bit 5
R/W
Bit 4
Bit 4
R/W
Bit 3
Bit 3
R/W
Bit 2
Bit 2
R/W
Bit 1
Bit 1
R/W
Bit 0
Bit 0
R/W
Bit 7 ~ Bit 0: These are Counter 2 buffers which can be read and written to. Counter 2
is an 8-bit down-count timer with 8-bit prescaler used to preset the
counter and read the preset value. The prescaler is set by IOC91
register. After an interrupt, the preset value will be auto-reloaded.
24 •
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
EM78P468NB/P470N
8-Bit Microcontroller
When IR output is enabled, this control register can obtain carrier
frequency output. If the Counter 2 clock source is equal to FT , then-
FT
Carrier frequency (Fcarrier) =
2 * (preset _ value +1) * prescaler
6.2.2.9 IOCD0/HPWTPR (High-Pulse Width Timer Preset Register)
(Address: 0Dh, Bit 0 of R5 = “0”)
Bit 7
Bit 7
R/W
Bit 6
Bit 6
R/W
Bit 5
Bit 5
R/W
Bit 4
Bit 4
R/W
Bit 3
Bit 3
R/W
Bit 2
Bit 2
R/W
Bit 1
Bit 1
R/W
Bit 0
Bit 0
R/W
Bit 7 ~ Bit 0: These are high-pulse width timer buffers which can be read and written
to. High-pulse width timer preset register is an 8-bit down-counter with
8-bit prescaler used as IOCD0 to preset the counter and read the preset
value. The prescaler is set by the IOCA1 register. After an interrupt, the
preset value will be auto-reloaded.
For PWM or IR application, this control register is set as high pulse width.
If the high-pulse width timer clock source is FT , then –
prescaler * (preset _ value +1)
High pulse time =
FT
6.2.2.10 IOCE0/LPWTPR (Low-Pulse Width Timer Preset Register)
(Address: 0Eh, Bit 0 of R5 = “0”)
Bit 7
Bit 7
R/W
Bit 6
Bit 6
R/W
Bit 5
Bit 5
R/W
Bit 4
Bit 4
R/W
Bit 3
Bit 3
R/W
Bit 2
Bit 2
R/W
Bit 1
Bit 1
R/W
Bit 0
Bit 0
R/W
Bit 7 ~ Bit 0: All are low-pulse width timer buffer that can be read and written to.
Low-pulse width timer preset is an eight-bit down-counter with 8-bit
prescaler that is used as IOCE0 to preset the counter and read preset
value. The prescaler is set by IOCA1 register. After an interrupt, it will
auto-reload the preset value.
For PWM or IR application, this control register is set as low pulse width.
If the low-pulse width timer clock source is FT , then –
prescaler * (preset _ value +1)
Low pulse time =
FT
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
• 25
EM78P468NB/P470N
8-Bit Microcontroller
6.2.2.11 IOCF0/IMR (Interrupt Mask Register)
(Address: 0Fh, Bit 0 of R5 = “0”)
Bit 7
ICIE
R/W
Bit 6
LPWTE
R/W
Bit 5
HPWTE
R/W
Bit 4
CNT2E
R/W
Bit 3
CNT1E
R/W
Bit 2
INT1E
R/W
Bit 1
INT0E
R/W
Bit 0
TCIE
R/W
Bit 7 ~ Bit 0: Interrupt enable bit. Enable the respective interrupt source.
“0”: Disable interrupt
“1”: Enable interrupt
IOCF0 register is readable and writable.
6.2.3 IOC Page 1 (IOC61 ~ IOCE1, Bit 0 of R5 = “1”)
6.2.3.1 IOC61/WUCR (Wake-up and Sink Current of P5.7/IROUT Control
Register)
(Address: 06h, Bit 0 of R5 = “1”)
Bit 7
IROCS
R/W
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
-
0
-
0
-
/WUE8H /WUE8L /WUE6H /WUE6L
R/W R/W R/W R/W
Bit 7 (IROCS): IROUT/Port 57 output sink current setting
P57/IROUT Sink Current Setting
IROCS
VDD=5V
VDD=3V
“0”
“1”
10 mA
6 mA
20 mA
12 mA
Bits 6, 5, 4: Unused bits, must be fixed to “0”
Bit 3 (/WUE8H): “0”/”1”→ Enable/disable Pins P84~P87 to change wake-up function
Bit 2 (/WUE8L): “0”/”1”→ Enable/disable Pins P80~P83 to change wake-up function
Bit 1 (/WUE6H): “0”/”1”→ Enable/disable Pins P64~P67 to change wake-up function
Bit 0 (/WUE6L): “0”/”1”→ Enable/disable Pins P60~P63 to change wake-up function
NOTE
Do not set Port 6 and Port 8 as input floating when wake-up function is enabled.
“Enable” is the default status of the wake-up function.
26 •
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
EM78P468NB/P470N
8-Bit Microcontroller
6.2.3.2 IOC71/TCCCR (TCC Control Register)
(Address: 07h, Bit 0 of R5 = “1”)
Bit 7
INT_EDGE
R/W
Bit 6
INT
F
Bit 5
TS
Bit 4
TE
Bit 3
PSRE
R/W
Bit 2
TCCP2
R/W
Bit 1
TCCP1
R/W
Bit 0
TCCP0
R/W
R/W
R/W
Bit 7 (INT_EDGE): Interrupt edge select bit
INT_EDGE = “0”: Interrupt on the rising edge of P54/INT0 pin
INT_EDGE = “1”: Interrupt on the falling edge of P54/INT0 pin
Bit 6 (INT): INT enable flag. This bit is read only.
INT = “0”: Interrupt masked by DISI or hardware interrupt
INT = “1”: Interrupt enabled by ENI/RETI instructions
Bit 5 (TS): TCC signal source
TS = “0”: Internal instruction cycle clock
TS = “1”: Transition on TCC pin, TCC period > internal instruction clock
period
Bit 4 (TE): TCC signal edge
TE = “0”: Incremented by TCC pin rising edge
TE = “1”: Incremented by TCC pin falling edge
Bits 3 ~ 0 (PSRE, TCCP2 ~ TCCP0): TCC prescaler bits
PSRE
TCCP2
TCCP1
TCCP0
TCC Rate
1:1
0
1
1
1
1
1
1
1
1
×
0
0
0
0
1
1
1
1
×
0
0
1
1
0
0
1
1
×
0
1
0
1
0
1
0
1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
• 27
EM78P468NB/P470N
8-Bit Microcontroller
6.2.3.3 IOC81/WDTCR (WDT Control Register)
(Address: 08h, Bit 0 of R5 = “1”)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
WDTE
R/W
Bit 2
WDTP2
R/W
Bit 1
WDTP1
R/W
Bit 0
WDTP0
R/W
-
-
-
-
-
-
-
-
Bits 7 ~ 4: Unused bits
Bit 3 (WDTE): Watchdog timer enable. This control bit is used to enable the Watchdog
timer
WDTE = “0”: Disable WDT function
WDTE = “1”: Enable WDT function
Bits 2 ~ 0 (WDTP2 ~ WDTP0): Watchdog Timer prescaler bits. The WDT clock source
is sub-oscillation frequency.
WDTP2
WDTP1
WDTP0
WDT Rate
1:1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
6.2.3.4 IOC91/CNT12CR (Counters 1 and 2 Control Register)
(Address: 09h, Bit 0 of R5 = “1”)
Bit 7
CNT2S
R/W
Bit 6
CNT2P2 CNT2P1 CNT2P0
R/W R/W R/W
Bit 5
Bit 4
Bit 3
CNT1S
R/W
Bit 2
CNT1P2 CNT1P1 CNT1P0
R/W R/W R/W
Bit 1
Bit 0
Bit 7 (CNT2S): Counter 2 clock source select
CNT2S = “0”: Fs (Fs: sub-oscillator clock)
CNT2S = “1”: Fm (Fm: main-oscillator clock)
Bits 6 ~ 4 (CNT2P2 ~ CNT2P0): Counter 2 prescaler select bits
CNT2P2
CNT2P1
CNT1P0
Counter 2 Scale
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
28 •
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
EM78P468NB/P470N
8-Bit Microcontroller
Bit 3 (CNT1S): Counter 1 clock source select bit
CNT1S = “0”: Fs (Fs: sub-oscillator clock)
CNT1S = “1”: Fm (Fm: main-oscillator clock)
Bits 2 ~ 0 (CNT1P2 ~ CNT1P0): Counter 1 prescaler select bits
CNT1P2
CNT1P1
CNT1P0
Counter 1 Scale
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
6.2.3.5 IOCA1/HLPWTCR (High/Low Pulse Width Timer Control Register)
(Address: 0Ah, Bit 0 of R5 = “1”)
Bit 7
LPWTS
R/W
Bit 6
LPWTP2 LPWTP1 LPWTP0 HPWTS HPWTP2 HPWTP1 HPWTP0
R/W R/W R/W R/W R/W R/W R/W
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7 (LPWTS): Low-pulse width timer clock source select bit
LPWTS = “0”: Fs (Fs: sub-oscillator clock)
LPWTS = “1”: Fm (Fm: main-oscillator clock)
Bits 6 ~ 4 (LPWTP2~ LPWTP0): Low-pulse width timer prescaler select bits
LPWTP2
LPWTP1
LPWTP0
Low-Pulse Width Timer Scale
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
Bit 3 (HPWTS): High-pulse width timer clock source select bit
HPWTS = “0”: Fs (Fs: sub-oscillator clock)
HPWTS = “1”: Fm (Fm: main-oscillator clock)
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
• 29
EM78P468NB/P470N
8-Bit Microcontroller
Bits 2 ~ 0 (HPWTP2 ~ HPWTP0): High-pulse width timer prescaler select bits
HPWTP2
HPWTP1
HPWTP0
High-Pulse Width Timer Scale
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
6.2.3.6 IOCB1/P6PH (Port 6 Pull-high Control Register)
(Address: 0Bh, Bit 0 of R5 = “1”)
Bit 7
PH67
R/W
Bit 6
PH66
R/W
Bit 5
PH65
R/W
Bit 4
PH64
R/W
Bit 3
PH63
R/W
Bit 2
PH62
R/W
Bit 1
PH61
R/W
Bit 0
PH60
R/W
Bit 7 ~ Bit 0 (PH67 ~ PH60): Port 6 pull high function enable bits
PH6x = “0”: Disable P6x pin internal pull-high resistor function
PH6x = “1”: Enable P6x pin internal pull-high resistor function
6.2.3.7 IOCC1/P6OD (Port 6 Open Drain Control Register)
(Address: 0Ch, Bit 0 of R5 = “1”)
Bit 7
OP67
R/W
Bit 6
OP66
R/W
Bit 5
OP65
R/W
Bit 4
OP64
R/W
Bit 3
OP63
R/W
Bit 2
OP62
R/W
Bit 1
OP61
R/W
Bit 0
OP60
R/W
Bit 7 ~ Bit 0 (OP67 ~ OP60): Port 6 open drain function enable bits
OD6x = “0”: Disable P6x pin open drain function
OD6x = “1”: Enable P6x pin open drain function
6.2.3.8 IOCD1/P8PH (Port 8 Pull High Control Register)
(Address: 0Dh, Bit 0 of R5 = “1”)
Bit 7
PH87
R/W
Bit 6
PH86
R/W
Bit 5
PH85
R/W
Bit 4
PH84
R/W
Bit 3
PH83
R/W
Bit 2
PH82
R/W
Bit 1
PH81
R/W
Bit 0
PH80
R/W
Bit 7 ~ Bit 0 (PH87 ~ PH80): Port 8 pull-high function enable bits
PH8x = “0”: Disable P8x pin internal pull-high resistor function
PH8x = “1”: Enable P8x pin pull-high resistor function
30 •
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
EM78P468NB/P470N
8-Bit Microcontroller
6.2.3.9 IOCE1/P6PL (Port 6 Pull Low Control Register)
(Address: 0Eh, Bit 0 of R5 = “1”)
Bit 7
PL67
R/W
Bit 6
PL66
R/W
Bit 5
PL65
R/W
Bit 4
PL64
R/W
Bit 3
PL63
R/W
Bit 2
PL62
R/W
Bit 1
PL61
R/W
Bit 0
PL60
R/W
Bit 7 ~ Bit 0 (PL67 ~ PL60): Port 6 pull low function enable bits
PL6x = “0”: Disable P6x pin internal pull-low resistor function
PL6x = “1”: Enable P6x pin internal pull-low resistor function
6.3 TCC and WDT Prescaler
Two 8-bit counters are available as prescalers for the TCC (Time Clock Counter) and
WDT (Watchdog Timer). The TCCP2~TCCP0 bits of the IOC71 register are used to
determine the ratio of the TCC prescaler. Likewise, the WDTP2~WDTP0 bits of the
IOC81 register are used to determine the WDT prescaler. The TCC prescaler (TCCP2
~TCCP0) is cleared by the instructions each time they are written into TCC, while the
WDT prescaler is cleared by the “WDTC” and “SLEP” instructions. Figures 6-4(a) and
6-4(b) depict the functional block diagrams of TCC and WDT respectively.
R1 (TCC) is an 8-bit timer/counter. The TCC clock source is selected from either
internal instruction clock or external signal input (edge selectable from the TCC control
register). If the TCC signal source is from the internal instruction clock, the TCC will be
incremented by “1” at every instruction cycle (without prescaler). If the TCC signal
source is from an external clock input, the TCC will be incremented by “1” at every
falling edge or rising edge of the TCC pin.
The Watchdog Timer (WDT) is a free running on-chip sub-oscillator. The WDT will
keep on running even after the oscillator driver has been turned off. During Normal
mode, Green mode or Idle mode operation, a WDT time-out (if enabled) will cause the
device to reset. The WDT can be enabled or disabled any time during Normal mode
and Green mode by software programming (see WDTE bit of IOC81 register in Section
6.4.3). The WDT time-out period is calculated using the following formula:
WDT Time-out Period = (prescaler × 256 / (Fs/2)).
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
• 31
EM78P468NB/P470N
8-Bit Microcontroller
Data Bus
TCC (R1)
Instruction Clock = Fosc /2
Fosc: CPU operate frequency
TCC
Pin
MUX
Pres c aler
8 to 1 MUX
PSRE TCCP2~0
(IOC71) (IOC71)
TCCoverflow interrupt
TE (IOC71)
TS (IOC71)
Figure 6-4(a) TCC Functional Block Diagram
WDT
8 bit counter
Fs/2
WDTE (IOC81)
8 to 1 MUX
Pres c aler
(Fs:Sub oscillator)
WDTP2~0
(IOC81)
WDT Time out
Figure 6-4(b) WDT Functional Block Diagram
32 •
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
EM78P468NB/P470N
8-Bit Microcontroller
6.3.1 TCC Setting Flowchart
START
from External Input
from Instruction Cycle
TCC clock source?
External/ instruction cycle
*set clock source from external TCC pin
(set bit 4 of IOC71 to "1")
*choose TCC clock source from instruction cycle
(set bit 4 of IOC71 to "0")
*set P5.6/TCC for TCC input Pin
*choose TCC prescaler
( set bit 2 of RE to "1" and set bit 6 of IOC 50 to "1")
(set by bit 0 to bit 3 of IOC71)
*choose TCC pin operation edge
(set by bit 4 of IOC71)
*choose TCC prescaler
(set by bit 0 to bit 3 of IOC71)
* Enable TCC interrupt Mask
(set bit 0 of IOCF0 to "1")
*Clear TCC interrupt Flag
(set bit 0 of RF to "0")
Enable TCC to start count
(use ENI instruction)
END
6.3.2 WDT Setting Flowchart
START
N
Use WDT function ?
Y
Enable WDT function : set bit 7 of
Code option Word 0 to "0"
Disable WDT function : set bit 7 of
Code option Word 0 to "1"
Setting WDT prescaler
(IOC81 register)
WDTtime= prescaler*256/Fs
Fs: sub-oscillator frequency
Enable WDT
(bit 3 of IOC81)
END
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
• 33
EM78P468NB/P470N
8-Bit Microcontroller
6.4 I/O Ports
The I/O registers (Port 5, Port 6, Port 7, and Port 8), are bidirectional tri-state I/O ports.
Port 6 and Port 8 are pulled-high internally by software while Port 6 is pulled-low
internally by software. Furthermore, Port 6 also has its open-drain output through
software. Port 6 and Port 8 features an input status changed interrupt (or wake-up)
function and are pulled-high by software. Each I/O pin can be defined as "input" or
"output" pin by the I/O control register (IOC50 ~ IOC80). The I/O registers and I/O
control registers are both readable and writable. The I/O interface circuits are as
shown in the following Figure 6-5.
Note: Open-drain, pull-high, and pull down are not shown in the figure.
Figure 6-5 I/O Port and I/O Control Register Circuit for Port 5 ~ 8
6.5 Reset and Wake-up
A reset can be activated by
POR (Power-on Reset)
WDT timeout. (if enabled)
LVR (if enabled)
/RESET pin goes to low
Note that the reset circuit is always enabled. It will reset the CPU at 1.9V. Once a reset
occurs, the following functions are performed:
The oscillator is running, or will be started
The program counter (R2/PC) is set to all "0"
All I/O port pins are configured as input mode (high-impedance state)
The TCC/Watchdog timer and prescaler are cleared
When power is on, the Bits 5 and 6 of R3 and the upper two bits of R4 are cleared.
Bits of the IOC71 register are set to all "1," except for Bit 6 (INT flag)
34 •
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
EM78P468NB/P470N
8-Bit Microcontroller
For other registers, see the following table.
6.5.1 Summary of Registers Initialized Values
Address
Name
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
Power-on
IOC57 IOC56 IOC55 IOC54 P8HS P8LS P7HS P7LS
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
IOC50
(P5CR)
/RESET and
WDT
0x05
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
Power-on
IOC67 IOC66 IOC65 IOC64 IOC63 IOC62 IOC61 IOC60
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IOC60
(P6CR)
/RESET and
WDT
0x06
0x07
0x08
0x09
0x0A
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
Power-on
IOC77 IOC76 IOC75 IOC74 IOC73 IOC72 IOC71 IOC70
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IOC70
(P7CR)
/RESET and
WDT
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
Power-on
IOC87 IOC86 IOC85 IOC84 IOC83 IOC82 IOC81 IOC80
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IOC80
(P8CR)
/RESET and
WDT
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
Power-on
0
0
RAM_A6 RAM_A5 RAM_A4 RAM_A3 RAM_A2 RAM_A1RAM_A0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IOC90
(RAM_ADDR)
/RESET and
WDT
0
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
Power-on
RAM_D7 RAM_D6 RAM_D5 RAM_D4 RAM_D3 RAM_D2 RAM_D1 RAM_D0
U
P
U
P
U
P
U
P
U
P
U
P
U
P
U
P
IOCA0
(RAM_DB)
/RESET and
WDT
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
• 35
EM78P468NB/P470N
8-Bit Microcontroller
(Continuation)
Address
Name
Reset Type
Bit Name
Bit 7
Bit 7
0
Bit 6
Bit 6
0
Bit 5
Bit 5
0
Bit 4
Bit 4
0
Bit 3
Bit 3
0
Bit 2
Bit 2
0
Bit 1
Bit 1
0
Bit 0
Bit 0
0
Power-on
IOCB0
/RESET and
WDT
0x0B
0
0
0
0
0
0
0
0
(CNT1PR)
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
Power-on
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
IOCC0
/RESET and
WDT
0x0C
0x0D
0x0E
0x0F
0x06
0
0
0
0
0
0
0
0
(CNT2PR)
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
Power-on
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
IOCD0
/RESET and
WDT
0
0
0
0
0
0
0
0
(HPWTPR)
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
Power-on
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
IOCE0
/RESET and
WDT
0
0
0
0
0
0
0
0
(LPWTPR)
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
Power-on
ICIE LPWTE HPWTE CNT2E CNT1E INT1E INT0E TCIE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IOCF0
(IMR)
/RESET and
WDT
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
Power-on
IROCS
0
0
0
0
0
0
0
/WUE8H /WUE8L /WUE6H /WUE6L
0
0
0
0
0
0
0
0
IOC61
/RESET and
WDT
0
0
0
0
(WUCR)
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
36 •
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
EM78P468NB/P470N
8-Bit Microcontroller
(Continuation)
Address
Name
Reset Type
Bit Name
Bit 7
Bit 6
INT
0
Bit 5
TS
1
Bit 4
TE
1
Bit 3
Bit 2
Bit 1
Bit 0
INT_EDGE
PSRE
TCCP2 TCCP1 TCCP0
Power-on
1
1
1
1
1
1
1
1
1
1
IOC71
0x07
/RESET & WDT
0
1
1
(TCCCR)
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
X
0
0
X
0
0
X
0
0
X
0
0
WDTE WDTP2 WDTP1 WDTP0
Power-on
0
0
1
1
1
1
1
1
IOC81
0x08
0x09
0x0A
0x0B
0x0C
0x0D
/RESET & WDT
(WDTCR)
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
CNT2S CNT2P2 CNT2P1 CNT2P0 CNT1S CNT1P2 CNT1P1 CNT1P0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IOC91
/RESET & WDT
(CNT12CR)
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
LPWTS LPWTP2 LPWTP1 LPWTP0 HPWTS HPWTP2 HPWTP1 HPWTP0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IOCA1
/RESET & WDT
(HLPWTCR)
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
PH67
PH66
PH65
PH64
PH63
PH62
PH61
PH60
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IOCB1
(P6PH)
/RESET & WDT
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
OP67
OP66
OP65
OP64
OP63
OP62
OP61
OP60
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IOCC1
/RESET & WDT
(P6OD)
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
PH87
PH86
PH85
PH84
PH83
PH82
PH81
PH80
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IOCD1
(P8PH)
/RESET & WDT
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
• 37
EM78P468NB/P470N
8-Bit Microcontroller
(Continuation)
Address
Name
Reset Type
Bit Name
Bit 7
PL67
0
Bit 6
PL66
0
Bit 5
PL65
0
Bit 4
PL64
0
Bit 3
PL63
0
Bit 2
PL62
0
Bit 1
PL61
0
Bit 0
PL60
0
Power-on
IOCE1
(P6PL)
0x0E
/RESET & WDT
0
0
0
0
0
0
0
0
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
Bit 7
U
Bit 6
U
Bit 5
U
Bit 4
U
Bit 3
U
Bit 2
U
Bit 1
U
Bit 0
U
Power-on
R0
0x00
0x01
0x02
0x03
0x04
0x05
/RESET & WDT
P
P
P
P
P
P
P
P
(IAR)
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R1
/RESET & WDT
(TCC)
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R2
/RESET & WDT
(PC)
Wake-up from
Pin Change
Jump to Address 0x0018 or continue to execute next instruction
Bit Name
X
0
0
PS1
0
PS0
0
T
1
t
P
1
t
Z
U
P
DC
U
C
U
P
Power-on
R3
/RESET & WDT
0
0
P
(SR)
Wake-up from
Pin Change
P
P
P
t
t
P
P
P
Bit Name
RBS1 RBS0 RSR5 RSR4 RSR3 RSR2 RSR1 RSR0
Power-on
0
0
0
0
U
P
U
P
U
P
U
P
U
P
U
P
R4
/RESET & WDT
(RSR)
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
P57
1
P56
1
P55
1
P54
1
X
0
0
X
0
0
X
0
0
IOCPAGE
Power-on
0
0
SBANK0
R5
/RESET & WDT
1
1
1
1
(Port 5)
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
38 •
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
EM78P468NB/P470N
8-Bit Microcontroller
(Continuation)
Address
Name
Reset Type
Bit Name
Bit 7
P67
1
Bit 6
P66
1
Bit 5
P65
1
Bit 4
P64
1
Bit 3
P63
1
Bit 2
P62
1
Bit 1
P61
1
Bit 0
P60
1
Power-on
SBANK0 R6
(Port 6)
0x06
/RESET & WDT
1
1
1
1
1
1
1
1
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
P77
1
P76
1
P75
1
P74
1
P73
1
P72
1
P71
1
P70
1
Power-on
SBANK0 R7
(Port 7)
0x07
0x08
0x09
0x0A
0x0B
0x0C
/RESET & WDT
1
1
1
1
1
1
1
1
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
P87
1
P86
1
P85
1
P84
1
P83
1
P82
1
P81
1
P80
1
Power-on
SBANK0 R8
(Port 8)
/RESET & WDT
1
1
1
1
1
1
1
1
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
BS
1
DS1
1
DS0 LCDEN
X
0
0
LCDTYPE LCDF1 LCDF0
Power-on
0
0
0
0
0
0
0
0
0
0
SBANK0 R9
(LCDCR)
/RESET & WDT
1
1
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
X
0
0
X
0
0
X
0
0
LCD_A4 LCD_A3 LCD_A2 LCD_A1 LCD_A0
Power-on
0
0
0
0
0
0
0
0
0
0
SBANK0
RA
/RESET & WDT
(LCD_ADDR)
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
X
0
0
X
0
0
X
0
0
X
0
0
LCD_D3 LCD_D2 LCD_D1 LCD_D0
Power-on
U
P
U
P
U
P
U
P
SBANK0
RB
/RESET & WDT
(LCD_DB)
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
X
0
0
X
1
1
X
0
0
X
0
0
LPWTEN HPWTEN CNT2EN CNT1EN
Power-on
0
0
0
0
0
0
0
0
SBANK0
RC
/RESET & WDT
(CNTER)
Wake-up from
Pin Change
P
P
0
P
P
P
P
P
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
• 39
EM78P468NB/P470N
8-Bit Microcontroller
(Continuation)
Address
Name
Reset Type
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
IDLE
1
Bit 2
BF1
0
Bit 1
BF0
0
Bit 0
CPUS
*1
SBANK CLK2 CLK1 CLK0
Power-on
0
0
0
0
0
0
0
0
SBANK0
RD
0x0D
/RESET & WDT
1
0
0
*1
(SBPCR)
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
IRE
0
HF
0
LGP
X
U
U
IROUTE TCCE EINT1 EINT0
Power-on
0
0
0
0
0
0
0
0
0
0
SBANK0
RE
0x0E
0x0F
0x05
0x06
/RESET & WDT
0
0
(IRCR)
Wake-up from
Pin Change
P
P
P
U
P
P
P
P
Bit Name
ICIF LPWTF HPWTF CNT2F CNT1F INT1F INT0F TCIF
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SBANK0 RF
(ISR)
/RESET & WDT
Wake-up from
Pin Change
N
P
P
P
P
P
P
P
Bit Name
HLB
0
0
0
0
0
0
0
0
0
0
RBit11 RBit10 RBit9
RBit8
Power-on
0
0
0
0
0
0
0
0
SBANK1 R5
(TBRDH)
/RESET & WDT
0
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
RBit7
RBit6
RBit5
RBit4
RBi3
RBit2
RBit1
RBit0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SBANK1 R6
(TBRDL)
/RESET & WDT
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
Bit 7
U
Bit 6
U
Bit 5
U
Bit 4
U
Bit 3
U
Bit 2
U
Bit 1
U
Bit 0
U
Power-on
0x10
~
0x3F
R10~R3F
/RESET & WDT
P
P
P
P
P
P
P
P
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Legend: “×” = Not used
“−” = Not defined
“P” = Previous value before reset
“t” = Check R3 register explanation
“u” = Unknown or don’t care
“N” = Monitors interrupt operation status
40 •
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
EM78P468NB/P470N
8-Bit Microcontroller
6.5.2 Summary of Wake-up and Interrupt Modes
All categories in Wake-up signals Interrupt modes are as follows:
Wake-up Signal
Sleep Mode
Idle Mode
Green Mode Normal Mode
TCC time out
IOCF0 Bit 0=1
Interrupt
Interrupt
Interrupt
Interrupt
×
×
Wake-up
+ interrupt
Wake-up
+ interrupt
INT0 pin
IOCF0 Bit 1=1
+ next instruction
+ next instruction
Wake-up
+ interrupt
Wake-up
+ interrupt
INT1 pin
IOCF0 Bit 2=1
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
+ next instruction
+ next instruction
Wake-up
+ interrupt
Counter 1
IOCF0 Bit 3=1
×
×
×
×
+ next instruction
Wake-up
+ interrupt
Counter 2
IOCF0 Bit 4=1
+ next instruction
Wake-up
High-pulse timer
IOCF0 Bit 5=1
+ interrupt
+ next instruction
Wake-up
+ interrupt
Low-pulse timer
IOCF0 Bit 6=1
+ next instruction
Port 6, Port 8
Wake-up
+ next instruction
Wake-up
+ next instruction
(input status
change wake-up)
×
×
×
×
Bit 7 of IOCF0 = “0”
Port 6, Port 8
(input status
change wake-up)
Wake-up
+ interrupt
Wake-up
+ interrupt
+ next instruction
+ next instruction
Bit 7 of IOCF0 = “1”
WDT time out
RESET
RESET
RESET
RESET
RESET
RESET
×
Low Voltage Reset
RESET
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
• 41
EM78P468NB/P470N
8-Bit Microcontroller
6.6 LVR (Low Voltage Reset)
6.6.1 Low Voltage Reset
LVR pin setting. The detailed operation mode is as follows:
LVR1
LVR0
VDD Reset Level
VDD Release Level
0
0
1
1
0
1
0
1
4.0V
3.5V
2.7V
4.2V
3.7V
2.9V
NA ( Power-on Reset )
If VDD < 2.7V and it is kept at 5 μs, the IC will be reset.
If VDD < 3.5V and it is kept at 5 μs, the IC will be reset.
If VDD < 4.0V and it is kept at 5 μs, the IC will be reset.
6.7 Oscillator
6.7.1 Oscillator Modes
The EM78P468NB/P470N operates in three different oscillator modes:
a) Main oscillator (R-OSCI, OSCO), such as RC oscillator with external resistor and
internal capacitor mode (ERIC).
b) Crystal oscillator mode
c) PLL operation mode (R-OSCI connected to Ground through a 0.01μF capacitor).
User can select which mode to use by programming FMMD1 and FMMD0 in the
Code Options Register (see Section 6.13). The sub-oscillator can operate in Crystal
mode and ERIC mode. The tables below show how these three modes are defined.
Oscillator Modes as defined by FSMD, FMMD1, and FMMD0:
FSMD
FMMD1
FMMD0
Main Clock
RC type (ERIC)
Crystal type
PLL type
Sub-clock
RC type (ERIC)
RC type (ERIC)
RC type (ERIC)
Crystal type
0
0
0
1
1
1
0
0
1
0
0
1
0
1
×
0
1
×
RC type (ERIC)
Crystal type
PLL type
Crystal type
Crystal type
Summary of maximum operating speeds:
VDD
2.3
Fxt Max. (MHz)
4
8
3.0
5.0
10
42 •
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
EM78P468NB/P470N
8-Bit Microcontroller
6.7.2 Phase Lock Loop (PLL Mode)
When operating in PLL mode, the high frequency is determined by the sub-oscillator.
You can use the RD register (see Section 6.1.14) to change the high oscillator
frequency. The relation between high frequency (Fm) and sub-oscillator is as shown in
the following figure.
Figure 6-6 PLL Mode Circuit Diagram
6.7.3 Crystal Oscillator/Ceramic Resonators (Crystal)
The EM78P468NB/P470N can be driven by an external clock signal through the
R-OSCI pin as shown in Figure 6-7(a) below.
Figure 6-7(a) External Clock Input Circuit Diagram
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
• 43
EM78P468NB/P470N
8-Bit Microcontroller
In most applications, the R-OSCI pin and the OSCO pin are connected with a crystal or
ceramic resonator to generate oscillation. The following figure depicts such circuit.
Figure 6-7(b) Crystal/Resonator Circuit Diagram
The following table provides the recommended values of C1 and C2. Since each
resonator has its own attribute, user should refer to its specification for appropriate
values of C1 and C2. RS, a serial resistor, may be necessary for AT strip cut crystal or
low frequency mode.
Capacitor Selection Guide for Crystal Oscillator or Ceramic Resonators
Oscillator Source
Oscillator Type
Frequency
455kHz
C1 (pF)
100~150
20~40
10~30
20~40
15~30
15
C2 (pF)
100~150
20~40
10~30
20~150
15~30
15
Ceramic Resonators
2.0 MHz
4.0 MHz
455kHz
Main Oscillator
1.0 MHz
2.0 MHz
4.0 MHz
32.768kHz
Crystal Oscillator
Crystal Oscillator
15
15
25
25
Sub-Oscillator
44 •
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
EM78P468NB/P470N
8-Bit Microcontroller
6.7.4 RC Oscillator Mode with Internal Capacitor
If both precision and cost are taken into consideration, this microcontroller also offers a
special oscillation mode, which has an on-chip internal capacitor and an external
resistor connected to VDD. The internal capacitor functions as temperature
compensator. In order to obtain more accurate frequency, a precise resistor is
recommended.
VDD
Rext
R-OSCI or Xin
EM78P468NB
Figure 6-8 Internal C Oscillator Mode Circuit
RC Oscillator Frequencies
°
°
Pin
Rext
51k
Average Fosc 5V, 25 C
Average Fosc 3V, 25 C
2.2221 MHz
1.1345 MHz
381.36kHz
32.768kHz
2.1972 MHz
1.1203 MHz
374.77kHz
32.768kHz
R-OSCI
100k
300k
2.2M
Xin
NOTE
1) Data measured from QFP packages with frequency drift of about ± 30%.
2) Values are provided for design reference only.
6.8 Power-on Considerations
Any microcontroller (as with EM78P468NB/P470N) is not warranted to start operating
properly before the power supply stabilizes in a steady state. This microcontroller has
an on-chip Power-on Reset (POR) with detection level range of 1.9V to 2.1V. The
circuitry eliminates the extra external reset circuit but will work well only if the VDD rises
fast enough (50 ms or less). However, under critical applications, extra devices are still
required to assist in solving power-on problems.
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
• 45
EM78P468NB/P470N
8-Bit Microcontroller
6.8.1 External Power-on Reset Circuit
The circuits shown below implements an external RC to generate reset pulse. The
pulse width (time constant) should be kept long enough to allow the VDD to reach
minimum operation voltage. This circuit is used when the power supply has a slow rise
time. Since current leakage from the /RESET pin is ± 5μA, it is recommended that R
should not be greater than 40KΩ in order for the voltage at Pin /RESET to remain below
0.2V. The diode (D) acts as a short circuit at power-down. The Capacitor, C, will
discharge rapidly and fully. The current-limited resistor Rin, will prevent high current
discharge or ESD (electrostatic discharge) from flowing into Pin /RESET.
Figure 6-9 External Power-on Reset Circuit
6.8.2 Residue-Voltage Protection
When battery is replaced, device power (VDD) is disconnected but residue-voltage
remains. The residue-voltage may trips below minimum VDD, but above zero. This
condition may cause poor power-on reset. The following figures show how to build a
proper protection circuit against residue-voltage.
Figure 6-10(a) Residue-Voltage Protection Circuit 1
46 •
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
EM78P468NB/P470N
8-Bit Microcontroller
Figure 6-10(b) Residue Voltage Protection Circuit 2
6.9 Interrupt
The EM78P468NB/P470N has eight interrupt sources as listed below:
TCC overflow interrupt
External interrupt P54/INT0 pin
External interrupt P55/INT1 pin
Counter 1 underflow interrupt
Counter 2 underflow interrupt
High-pulse width timer underflow interrupt
Low-pulse width timer underflow interrupt
Port 6, Port 8 input status change wake-up
This IC has internal interrupts which are falling edge triggered or as follows:
TCC timer overflow interrupt
Four 8-bit down counter/timer underflow interrupt
If these interrupt sources change signal from high to low, the RF register will generate a
“1” flag to the corresponding register if the IOCF0 register is enabled.
RF is the interrupt status register that records the interrupt request in the relative
flags/bits. IOCF0 is the interrupt mask register. The global interrupt is enabled by ENI
instruction and disabled by DISI instruction. When one of the interrupts (when
enabled) is generated, it will cause the next instruction to be fetched from Address
0003H~0018H according to the interrupt source.
Interrupt
occurs
Interrupt sources
ENI/DISI
STACKACC
STACKR3
ACC
R3
RETI
Figure 6-11 Interrupt Back-up Diagram
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
• 47
EM78P468NB/P470N
8-Bit Microcontroller
With this microcontroller, each individual interrupt source has its own interrupt vector as
depicted in the table below. Before the interrupt subroutine is executed, the contents of
the ACC and the R3 registers are initially saved by the hardware. After the interrupt
service routine is completed, the ACC and R3 registers are restored. The existing
interrupt service routine does not allow other interrupt service routine to be executed.
Hence, if other interrupts occur while an existing interrupt service routine is being
executed; the hardware will save the later interrupts. Only after the existing interrupt
service routine is completed that the next interrupt service routine is executed.
Interrupt Vector
Interrupt Vector
0003H
Interrupt Status
TCC overflow interrupt.
0006H
External interrupt P54/INT0 pin
0009H
External interrupt P55/INT1 pin
000CH
Counter 1 underflow interrupt
000FH
Counter 2 underflow interrupt
0012H
High-pulse width timer underflow interrupt
Low-pulse width timer underflow interrupt
Port 6, Port 8 input status change wake up
0015H
0018H
6.10 LCD Driver
The EM78P468NB/P470N can drive an LCD of up to 32 segments and 4 commons that
drive a total of 4×32 dots. The LCD block is made up of an LCD driver, display RAM,
segment output pins, common output pins, and LCD operating power supply pins. This
circuit works on Normal mode, Green mode, and Idle mode. The LCD duty; bias; the
number of segment; the number of common, and frame frequency are determined
through the LCD control register.
The basic structure contains a timing controller that uses a subsystem clock to
generate the proper timing for different duty and display accesses. The R9 register is a
command register for the LCD driver which includes LCD enable/disable, bias (1/2 and
1/3), duty (1/2, 1/3, 1/4), and LCD frame frequency control. The Register RA is an LCD
contrast and LCD RAM address control register. The Register RB is an LCD RAM data
buffer. LCD booster circuit can change the operation frequency to improve VLCD2 and
VLCD3 drive capability. The control register is described in the following sections.
48 •
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
EM78P468NB/P470N
8-Bit Microcontroller
6.10.1 R9/LCDCR (LCD Control Register)
Bit 7
BS
Bit 6
DS1
R/W
Bit 5
DS0
R/W
Bit 4
LCDEN
R/W
Bit 3
Bit 2
LCDTYPE LCDF1
R/W R/W
Bit 1
Bit 0
LCDF0
R/W
−
R/W
-
Bit 7 (BS): LCD bias select bit, “0” : 1/2 bias
“1” : 1/3 bias
Bits 6 ~ 5 (DS1 ~ DS0): LCD duty select
DS1
DS0
LCD Duty
0
0
1
0
1
×
1/2 duty
1/3 duty
1/4 duty
Bit 4 (LCDEN): LCD enable bit
LCDEN = “0”: Disable the LCD circuit
LCDEN = “1”: Enable the LCD circuit
When the LCD function is disabled, all common/segment outputs are set
to ground (GND) level.
Bit 3: Not used
Bit 2 (LCDTYPE): LCD drive waveform type select bit
LCDTYPE = “0”: “A” type waveform
LCDTYPE = “1”: “B” type waveform
Bits 1 ~ 0 (LCDF1 ~ LCDF0): LCD frame frequency control bits:
LCD Frame Frequency (e.g., Fs=32.768kHz)
LCDF1
LCDF0
1/2 Duty
1/3 Duty
1/4 Duty
0
0
1
1
0
1
0
1
Fs/(256×2)=64.0
Fs/(280×2)=58.5
Fs/(304×2)=53.9
Fs/(232×2)=70.6
Fs/(172×3)=63.5
Fs/(188×3)=58.0
Fs/(204×3)=53.5
Fs/(156×3)=70.0
Fs/(128×4)=64.0
Fs/(140×4)=58.5
Fs/(152×4)=53.9
Fs/(116×4)=70.6
Note: Fs: sub-oscillator frequency
6.10.2 RA/LCD_ADDR (LCD Address)
Bit 7
Bit 6
Bit 5
Bit 4
LCD_A4
R/W
Bit 3
LCD_A3
R/W
Bit 2
LCD_A2
R/W
Bit 1
LCD_A1
R/W
Bit 0
LCD_A0
R/W
0
-
0
-
0
-
Bits 7 ~ 5: Not used, fixed to “0”
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
• 49
EM78P468NB/P470N
8-Bit Microcontroller
Bits 4 ~ 0 (LCDA4 ~ LCDA0): LCD RAM address
RB (LCD Data Buffer)
Bit 3 Bit 2 Bit 1
(LCD_D3) (LCD_D2) (LCD_D1) (LCD_D0)
RA
Segment
Bit 0
(LCD Address)
Bits 7 ~4
00H
01H
SEG0
SEG1
SEG2
¦
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
02H
¦
¦
1DH
1EH
SEG29
SEG30
SEG31
-
−
−
−
X
−
−
−
−
−
−
−
−
−
−
−
−
1FH
Common
COM3
COM2
COM1
COM0
6.10.3 RB/LCD_DB (LCD Data Buffer)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LCD_D 3 LCD_D 2 LCD_D 1 LCD_D 0
R/W R/W R/W R/W
−
−
−
−
-
-
-
-
Bits 7 ~ 4: Not used
Bits 3 ~ 0 (LCD_D3 ~ LCD_D0): LCD RAM data transfer registers
6.10.4 RD/SBPCR (System, Booster and PLL Control Registers)
Bit 7
SBANK
R/W
Bit 6
CLK2
R/W
Bit 5
CLK1
R/W
Bit 4
CLK0
R/W
Bit 3
IDLE
R/W
Bit 2
BF1
R/W
Bit 1
BF0
R/W
Bit 0
CPUS
R/W
Bits 2 ~ 1 (BF1 ~ BF0): LCD booster frequency select bits
BF1
0
BF0
0
Booster Frequency
Fs
0
1
Fs/4
Fs/8
Fs/16
1
0
1
1
50 •
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
EM78P468NB/P470N
8-Bit Microcontroller
LCD function Initial setting flowchart
IC RESET occur
*Set Port 7 snd Port 8 for general I/O or LCD segment (IOC50)
*it must be set to output port w hen the pin of port 7 and the pin of port 8 for LCD
segemnt (IOC70 and IOC80)
Set LCD Type, duty, bias, LCD frame frequency (R9)
Set LCD Booster Frequency (RD)
Clear all LCD RAM (RA and RB)
Enable LCD function (R9)
Use LCD address and LCD data buffer to implment user's applications. (RA and RB)
END
Figure 6-12(a) LCD Function Initial Setting Flowchart
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
• 51
EM78P468NB/P470N
8-Bit Microcontroller
Booster circuit connection for LCD voltage
VDD
VLCD2(2*VDD/3)
VLCD3(1*VDD/3)
GND
VA
VB
External Circuit for 1/3 Bias
VDD
VLCD2(VDD/2)
VA
VLCD3(VDD/2)
GND
VB
External Circuit for 1/2 Bias
Figure 6-12(b) Charge Bump Circuit Connection ( Cext=0.1μf )
52 •
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
EM78P468NB/P470N
8-Bit Microcontroller
LCD Waveforms for 1/2 Bias
1frame
1frame
VDD
VDD
COM0
COM1
SEG N
VLCD2,3
GND
COM0
COM1
SEG N
VLCD2,3
GND
VDD
VDD
VLCD2,3
GND
VLCD2,3
GND
VDD
VDD
VLCD2,3
GND
VLCD2,3
GND
VDD
VDD
VLCD2,3
GND
VLCD2,3
GND
SEG N- COM0
ON
SEG N- COM0
ON
-VLCD2,3
-VDD
-VLCD2,3
-VDD
VDD
VDD
VLCD2,3
GND
VLCD2,3
GND
SEG N- COM1
OFF
SEG N- COM1
OFF
-VLCD2,3
-VDD
-VLCD2,3
-VDD
1/2 bias, 1/2 duty
A type
1/2 bias, 1/2 duty
B type
Figure 6-12(c) LCD Waveform for 1/2 Bias, 1/2 Duty
1frame
1frame
VDD
VDD
COM0
COM1
COM2
SEG N
VLCD2,3
GND
COM0
COM1
COM2
SEG N
VLCD2,3
GND
VDD
VDD
VLCD2,3
GND
VLCD2,3
GND
VDD
VDD
VLCD2,3
GND
VLCD2,3
GND
VDD
VDD
VLCD2,3
GND
VLCD2,3
GND
VDD
VDD
VLCD2,3
GND
VLCD2,3
GND
SEG N- COM0
ON
SEG N- COM0
ON
-VLCD2,3
-VDD
-VLCD2,3
-VDD
VDD
VDD
VLCD2,3
GND
VLCD2,3
GND
SEG N- COM1
OFF
SEG N- COM1
OFF
-VLCD2,3
-VDD
-VLCD2,3
-VDD
1/2 bias, 1/3 duty
B type
1/2 bias, 1/3 duty
A type
Figure 6-12(d) LCD Waveform for 1/2 Bias, 1/3 Duty
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
• 53
EM78P468NB/P470N
8-Bit Microcontroller
LCD Waveforms for 1/3 Bias
1frame
1frame
VDD
VDD
VLCD2
VLCD3
GND
VLCD2
VLCD3
GND
COM 0
COM 0
VDD
VDD
VLCD2
VLCD3
GND
VLCD2
VLCD3
GND
COM 1
COM 2
COM 1
COM 2
VDD
VDD
VLCD2
VLCD3
GND
VLCD2
VLCD3
GND
VDD
VDD
VLCD2
VLCD3
GND
VLCD2
VLCD3
GND
SEG N
SEG N
VDD
VDD
SEG N- COM0
ON
VLCD3
GND
SEG N- COM0
ON
VLCD3
GND
-VLCD3
-VDD
VDD
-VLCD3
-VDD
VDD
SEG N- COM1
OFF
VLCD3
GND
SEG N- COM1
OFF
VLCD3
GND
-VLCD3
-VDD
-VLCD3
-VDD
1/3 bias, 1/3 duty
B type
1/3 bias, 1/3 duty
A type
Figure 6-12(e) LCD Waveform for 1/3 Bias, 1/3 Duty
1frame
1frame
VDD
VDD
VLCD2
COM0
VLCD3
VLCD2
VLCD3
GND
COM0
GND
VDD
VDD
VLCD2
COM1
VLCD3
VLCD2
VLCD3
GND
COM1
COM2
GND
VDD
VDD
VLCD2
VLCD3
GND
COM2
VLCD2
VLCD3
GND
VDD
VDD
VLCD2
VLCD3
GND
VLCD2
VLCD3
GND
SEG N
SEG N
VDD
VDD
SEG N-
COM0
SEG N-
COM0
VLCD3
GND
VLCD3
GND
ON
ON
-VLCD3
-VDD
-VLCD3
-VDD
VDD
VDD
SEG N-
COM1
SEG N-
COM1
VLCD3
GND
VLCD3
GND
OFF
OFF
-VLCD3
-VDD
-VLCD3
-VDD
1/3 bias, 1/4 duty
A type
1/3 bias, 1/4 duty
B type
Figure 6-12(f) LCD Waveform for 1/3 Bias, 1/4 Duty
54 •
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
EM78P468NB/P470N
8-Bit Microcontroller
6.11 Infrared Remote Control Application/PWM
Waveform Generation
This microcontroller can output infrared carrier under user-friendly or PWM standard
waveform. The IR and PWM waveform generated functions include an 8-bit down
count timer/counter, high-pulse width timer, low-pulse width timer, and IR control
register. The IR system block diagram is shown below. The IROUT pin waveform is
determined by IR control register (RE), IOC90 (Counters 1 and 2 control register),
IOCA0 (high-pulse width timer, low-pulse width timer control register), IOCC0 (Counter
2 preset), IOCD0 (high-pulse width timer preset register), and IOCE0 (low-pulse width
timer preset register). Details on Fcarrier, high-pulse time, and low pulse time are
explained below.
If Counter 2 clock source is FT (this clock source can be set by IOC91), then -
FT
Fcarrier
=
2 × (1 + decimal of Counter 2 preset value (IOCC 0)) × prescaler
If the high-pulse width timer clock source is FT (this clock source can be set by IOCA1),
then-
prescaler × (1 + decimal of high pulse width timer value (IOCD 0))
Thigh
=
pulse time
FT
If the low-pulse width timer clock source is FT (this clock source can be set by IOCA1);
prescaler × (1 + decimal of low pulse width timer value (IOCE 0))
Tlow
=
pulse time
FT
Pre-scaler
(IOCA1)
High-Pulse Width Timer
(IOCD0)
Low -Pulse Width Timer
( IOCE0)
Fs Fm
8
8
Auto-reloadbuffer
Auto-reloadbuffer
Pre-scaler
(IOC A1)
8
8
Pre-scaler
(IOC91)
8 bit dow n counter
8
8 bit dow n counter
8
Fcarrier
8 bit dow n counter
H/W Modulator Circuit
IROUTpin
8
Auto-reloadbuffer
8
HF
LGP
IRE
REregister
Counter 2
(IOCC0)
Note: Fm: main oscillator frequency Fs: sub-oscillator frequency
Figure 6-13 IR/PWM System Block Diagram
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
• 55
EM78P468NB/P470N
8-Bit Microcontroller
6.11.1 IROUT Output Waveforms
The IROUT output waveform is further explained in the following figures:
Fcarrier
high-pulse width
low-pulse width
high-pulse width
low-pulse width
HF
IRE
start
IROUT
Figure 6-14(a) LGP=0, IROUT Pin Output Waveform
LGP=0, HF=1, the IROUT waveform can modulate Fcarrier waveform when in
low-pulse width time.
Fcarrier
high-pulse width
low-pulse width
high-pulse width
low-pulse width
HF
IRE
start
IROUT
Figure 6-14(b) LGP=0, IROUT Pin Output Waveform
LGP=0, HF=0, the IROUT waveform cannot modulate Fcarrier waveform when in
low-pulse width time. So IROUT waveform is determined by high-pulse time and
low-pulse time. This mode generates standard PWM waveform.
Fcarrier
high-pulse width
low-pulse width
high-pulse width
low-pulse width
HF
start
IR disable
IRE
IROUT
Always high-level
Figure 6-14(c) LGP=0, IROUT Pin Output Waveform
56 •
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
EM78P468NB/P470N
8-Bit Microcontroller
LGP=0, HF=1, the IROUT waveform can modulate Fcarrier waveform when in
low-pulse width time. When IRE goes from high to low, the output waveform of IROUT
will keep on transmitting until high-pulse width timer interrupt occurs.
Fcarrier
high-pulse width
low-pulse width
high-pulse width
low-pulse width
HF
IRE
start
IR disable
IROUT
Always high-level
Figure 6-14(d) LGP=0, IROUT Pin Output Waveform
LGP=0, HF=0, the IROUT waveform cannot modulate Fcarrier waveform when in
low-pulse width time. So IROUT waveform is determined by high-pulse time and
low-pulse time. This mode produces standard PWM waveform. When IRE goes from
high to low, the output waveform of IROUT will keep on transmitting until high-pulse
width timer interrupt occurs.
Fcarrier
high-pulse width
low-pulse width
Low-pulse width
low-pulse width
HF
start
IR disable
IRE
IROUT
Always high-level
Figure 6-14(e) LGP=1, IROUT Pin Output Waveform
LGP=1, when this bit is set to high level, the high-pulse width timer is ignored. So
IROUT waveform output from low-pulse width timer is established.
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
• 57
EM78P468NB/P470N
8-Bit Microcontroller
6.11.2 IR/PWM Function Enable Flowchart
ꢀ
Start
Start
SET P57 to Output state (IOC 50)
SET P57 to Output state (IOC 50)
SET P57 for IR/PWM Function Output Pin (RE)
SET Counter 2 clock source and prescaler (IOC91)
SET P57 for IR/PWM Function Output Pin (RE)
SET High pulse width timer, Low pulse width timer
clock source and prescaler (IOCA1)
SET High pulse width timer, Low pulse width timer
clock source and prescaler (IOCA1)
(IOD0)
High pulse width timer
, Low pulse width timer
(IOCE0) preset value
(IOC0)
SET Counter 2
, High pulse width timer
(IOD0)
, Low pulse width timer (IOCE0)preset value
Enable IR (RE)
HF="0", and IRE="1"
Enable IR (RE)
HF="1", and IRE="1"
Enable HPWT and LPWT Interrupt
Set IOCF0 and ENI instruction
Enable HPWT and LPWT Interrupt
Set IOCF0 and ENI instruction
Enable high pulse width timer and Low pulse width
Timer (RC)
Enable Counter 2, High pulse width timer and Low
pulse width timer (RC)
END
END
(a) IR Application
(b) PWM Application
Figure 6-15 IR/PWM Function Enable Flowchart
58 •
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
EM78P468NB/P470N
8-Bit Microcontroller
6.12 Code Options
The EM78P468NB/P470N has one Code Option word that is not part of the normal
program memory. The option bits cannot be accessed during normal program
execution.
Their respective Code Option Register and Customer ID Register arrangement
distribution are as follows:
Word 0
Word 1
Word 2
Bit 12~Bit 0
Customer ID
Bit 12~Bit 0
Word 0 and Word 2 of code options are for IC function setting. Word 1 is for customer
ID code application. The following are the settings for OTP IC programming.
6.12.1 Code Option Register (Word 0)
Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3 Bit Bit 1 Bit 0
Mnemonic
−
−
−
1
XTAL1 XTAL0
-
HLFS ENWDTB FSMD FMMD1 FMMD0 HLP PR2 PR1 PR0
1
0
High
Low
1
High
Low
1
-
High Disable
High
Low
1
High
Low
1
High Enable
Low Disable
Disable
Enable
1
-
Low
1
Enable
1
Default
0
1
1
1
1
Bit 12: Unused bit
Bits 11~10 (XTAL1 ~ XTAL0): Crystal range setting for main oscillator:
XTAL1
XTAL0
Crystal Range
Reserved
0
0
1
1
0
1
0
1
6 MHz~10 MHz (XXT_EN)
1 MHz~6 MHz (MXT_EN)
100kHz~1 MHz (LXT_EN)
Bit 9: Unused bit, default “0”
Bit 8 (HLFS): Main or sub-oscillator select bit
HLFS = “0”: CPU is set to select sub-oscillator when reset occurs.
HLFS = “1”: CPU is set to select main-oscillator when reset occurs.
Bit 7 (ENWDTB): Watchdog timer enable/disable bit
ENWDTB = “0”: Enable watchdog timer
ENWDTB = “1”: Disable watchdog timer
Bit 6 (FSMD): Sub-oscillator type selection
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
• 59
EM78P468NB/P470N
8-Bit Microcontroller
Bits 5 ~ 4 (FMMD1 ~ FMMD0): Main Oscillator Type Selection
FSMD FMMD1 FMMD0 Main Oscillator Type
Sub Oscillator Type
RC type
0
0
0
1
1
1
0
0
1
0
0
1
0
1
×
0
1
×
RC type
Crystal type
PLL type
RC type
RC type
RC type
Crystal type
Crystal type
Crystal type
Crystal type
PLL type
Bit 3 (HLP): Power consumption selection. If the system used to run in Green mode, it
must be set to low power consumption to help support the energy saving.
It is recommended that low power consumption mode is selected.
HLP = “0”: Low power consumption mode
HLP = “1”: High power consumption mode
Bits 2 ~ 0 (PR2 ~ PR0): Protect bit
PR2~PR0 are protect bits. Each protect status is as follows:
PR2
0
PR1
0
PR0
0
Protect
Enable
Disable
1
1
1
6.12.2 Code Option Register (Word 1)
Bit 12 Bit11 Bit10 Bit9 Bit8 Bit7
Bit6
Bit5 Bit4
Bit3
ID3
Bit2
ID2
Bit1
ID1
Bit0
ID0
Mnemonic ID12 ID11 ID11 ID9 ID8 ID7
ID6
ID5
ID4
1
0
High High
High High High High High High High High
High
Low
1
High
Low
1
High
Low
1
Low
1
Low
1
Low Low Low Low
Low
1
Low Low
Low
1
Default
1
1
1
1
1
1
Bits 12 ~ 0 (ID12 ~ ID0): Customer ID
6.12.3 Code Option Register (Word 2)
Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mnemonic
-
-
-
-
-
-
-
-
-
-
-
LVR1 LVR0
1
0
High High
High High High High High High High High
High
Low
1
High
Low
1
High
Low
1
Low
1
Low
1
Low Low Low Low
Low
1
Low Low
Low
1
Default
1
1
1
1
1
1
Bits 12 ~ 2: unused bits
Bits 1 ~ 0 (LVR1 ~ LVR0): Low voltage reset level selection.
LVR1
LVR0
VDD Reset Level
VDD Release Level
0
0
1
1
0
1
0
1
4.0V
3.5V
2.7V
4.2V
3.7V
2.9V
NA (Power-on Reset)
60 •
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
EM78P468NB/P470N
8-Bit Microcontroller
6.13 Instruction Set
Each instruction in the Instruction Set is a 13-bit word divided into an OP code and one
or more operands. Normally, all instructions are executed within one single instruction
cycle (one instruction consists of 2 oscillator periods), unless the program counter is
changed by Instructions "MOV R2,A", "ADD R2,A", or by instructions of arithmetic or
logic operation on R2 (e.g., "SUB R2,A", "BS(C) R2,6", "CLR R2", ⋅⋅⋅⋅). In this case, the
execution takes two instruction cycles.
If for some reasons, the specification of the instruction cycle is not suitable for certain
applications, try modifying the instruction as follows:
Execute within two instruction cycles the "JMP", "CALL", "RET", "RETL", and "RETI"
instructions, or the conditional skip instructions ("JBS", "JBC", "JZ", "JZA", "DJZ",
"DJZA") which were tested to be true. Also execute within two instruction cycles the
instructions that are written to the program counter.
Additionally, the instruction set offers the following features:
1) Every bit of any register can be set, cleared, or tested directly.
2) The I/O register can be regarded as general register. That is, the same instruction
can operate on I/O register.
6.13.1 Instruction Set Table
The following symbols are used with the Instruction Set table:
R = Register designator that specifies which one of the registers (including operation and general
purpose registers) is to be utilized by the instruction.
b = Bit field designator that selects the value for the bit located in the register R and which affects
the operation.
k = 8 or 10-bit constant or literal value
Mnemonic
Operation
No Operation
Status Affected
NOP
DAA
None
C
Decimal Adjust A
SLEP
WDTC
IOW
ENI
0 → WDT, Stop oscillator
T, P
0 → WDT
A → IOCR
T, P
R
None∗
None
None
None
Enable Interrupt
Disable Interrupt
[Top of Stack] → PC
[Top of Stack] → PC,
Enable Interrupt
IOCR → A
A → R
0 → A
0 → R
R-A → A
DISI
RET
RETI
None
IOR
R
None∗
None
Z
MOV
CLRA
CLR
SUB
SUB
R, A
R
Z
A,
R
Z,C,DC
Z,C,DC
R, A
R-A → R
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
• 61
EM78P468NB/P470N
8-Bit Microcontroller
(Continuation)
Mnemonic
DECA
Operation
Status Affected
R
R-1 → A
R-1 → R
Z
DEC
OR
R
Z
A,
R
A ∨ R → A
A ∨ R → R
A & R → A
A & R → R
A ⊕ R → A
A ⊕ R → R
A + R → A
A + R → R
R → A
Z
OR
R, A
A,
R, A
A,
R, A
A,
R, A
A,
Z
AND
AND
XOR
XOR
ADD
ADD
MOV
MOV
COMA
COM
INCA
INC
R
Z
Z
R
Z
Z
R
Z, C, DC
Z, C, DC
R
Z
R, R
R
R → R
Z
Z
/R → A
R
/R → R
Z
R
R+1 → A
Z
R
R+1 → R
Z
DJZA
DJZ
R
R-1 → A, skip if zero
R-1 → R, skip if zero
None
None
R
R(n) → A(n-1),
R(0) → C, C → A(7)
RRCA
RRC
R
R
R
R
R
C
C
R(n) → R(n-1),
R(0) → C, C → R(7)
R(n) → A(n+1),
R(7) → C, C → A(0)
RLCA
RLC
C
R(n) → R(n+1),
R(7) → (C), C → (R(0)
C
R(0-3) → ( A(4-7),
R(4-7) → ( A(0-3)
SWAPA
None
SWAP
JZA
JZ
R
R(0-3) → ( R(4-7)
R+1 → A, skip if zero
R+1 → R, skip if zero
0→ ( R(b)
None
None
None
None
None
None
None
R
R
BC
R, b
R, b
R, b
R, b
BS
1→ ( R(b)
JBC
JBS
if R(b)=0, skip
if R(b)=1, skip
62 •
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
EM78P468NB/P470N
8-Bit Microcontroller
(Continuation)
Mnemonic
Operation
PC+1 → [SP],
(Page, k) → (PC)
(Page, k) → (PC)
k → A
Status Affected
CALL
k
None
JMP
k
None
None
Z
MOV
OR
A,
A,
A,
A,
k
k
k
k
k
A v k → A
AND
XOR
RETL
SUB
A & k → A
Z
A ⊕ k → A
Z
k → A, [Top of Stack] → PC
k-A → A
None
Z, C, DC
Z, C, DC
None
None
None
A,
A,
k
k
k
ADD
PAGE
BANK
TBRD
k+A → A
K->R3(5:6)
k
K->R4(7:6)
R
If SBANK1 R5 Bit 7=0,
machine code(7:0) → R
Else machine code(12:8) →
R(4:0),
R(7:5)=(0,0,0)
∗
This instruction is applicable to IOC50~IOF0 and IOC61~IOCE1.
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
• 63
EM78P468NB/P470N
8-Bit Microcontroller
7 Timing Diagram
7.1 AC Test Input/Output Waveform
Note: AC Testing: Input are driven at 2.4V for logic “1,” and 0.4V for logic “0”
Timing measurements are made at 2.0V for logic “1,” and 0.8V for logic “0”
Figure 7-1(a) AC Test Timing Diagram
7.2 Reset Timing (CLK = “0”)
Instruction 1
NOP
Executed
CLK
/RESET
Tdrh
Figure 7-1(b) Reset Timing Diagram
64 •
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
EM78P468NB/P470N
8-Bit Microcontroller
7.3 TCC Input Timing (CLKS = “0”)
Tins
CLK
TCC
Ttcc
Ttrf
Ttrr
90%
90%
Port (n+1)
10%
*
10%
Tiod
Port (n)*
*n = 0 , 2 , 4 , 6
Figure 7-1(c) TCC Input Timing Diagram
8 Absolute Maximum Ratings
Rating
Items
Symbol
Condition
Unit
Min.
Max.
+7.0
Supply voltage
VDD
VI
−
GND-0.3
GND-0.3
GND-0.3
-40
V
V
Input voltage
Port 5 ~ Port 8
VDD+0.3
VDD+0.3
85
Output voltage
VO
Port 5 ~ Port 8
V
Operation temperature
Storage temperature
Power consumption
Operating Frequency
TOPR
TSTG
PD
−
−
−
−
°C
°C
mW
Hz
-65
150
−
500
−
32.768K
10M
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
• 65
EM78P468NB/P470N
8-Bit Microcontroller
9 Electrical Characteristics
9.1 DC Electrical Characteristics
Ta= -40°C ~85 °C, VDD= 5.0V, GND= 0V
Symbol
FXT
Parameter
Condition
Min.
Typ. Max. Unit
10M kHz
32.768 kHz
Crystal: VDD to 5V
Sub-oscillator
Two cycles with two clocks
Two cycles with two clocks
32.768 8M
Fs
−
−
External R, Internal C for
Sub-oscillator
270
384
500 kHz
R: 300KΩ, internal capacitance
R: 2.2MΩ, internal capacitance
VIN = VDD, GND
ERIC
External R, Internal C for
Sub-oscillator
22.9 32.768 42.6 kHz
Input Leakage Current for
Input pins
IIL
-1
0
1
μA
Input High Threshold
Voltage
VIH1
Ports 5, 6, 7, 8
2.0
V
−
−
(Schmitt Trigger)
Input High Threshold
Voltage (Schmitt Trigger)
VIL1
VIHT1
VILT1
VIHT2
VILT2
IOH1
IOL1
Ports 5, 6, 7, 8
0.8
−
V
V
−
2.0
−
−
−
−
−
−
−
−
−
Input High Threshold
Voltage (Schmitt Trigger)
/RESET
Input Low Threshold Voltage
(Schmitt Trigger)
/RESET
0.8
−
V
Input High Threshold
Voltage (Schmitt Trigger)
TCC, INT0, INT1
TCC, INT0, INT1
VOH = 2.4V, IROCS=”0”
VOL = 0.4V, IROCS=”0”
VOH = 2.4V, IROCS=”1”
2.0
−
V
Input Low Threshold Voltage
(Schmitt Trigger)
0.8
−
V
Output High Voltage
(Ports 5~8)
-10
−
mA
mA
mA
Output Low Voltage
(Ports 5~8)
10
Output high Voltage
(P5.7/IROUT Pin)
IOH2
-20
−
Output Low Voltage
(P5.7/IR OUT Pin)
IOL2
VOL = 0.4V, IROCS=”1”
20
mA
−
−
IPH
IPL
Pull-High Current
Pull-Low Current
Pull-high active, input pin at GND
Pull-low active, input pin at VDD
-55
55
-75
75
-95
95
μA
μA
All input and I/O pins at VDD,
Output pin floating,
WDT disabled
ISB
Sleep Mode Current
Idle Mode Current
0.5
14
1.5
18
−
−
μA
/RESET= 'High', CPU OFF,
Sub-oscillator clock (32.768kHz)
ON, output pin floating,
ICC1
μA
LCD enabled, no load
66 •
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
EM78P468NB/P470N
8-Bit Microcontroller
(Continuation)
Symbol
Parameter
Condition
Min.
Typ. Max. Unit
/RESET= 'High', CPU ON,
Sub-oscillator clock (32.768kHz),
Output pin floating,
ICC2
Green Mode Current
22
30
−
μA
WDT enabled, LCD enabled
/RESET= 'High', Fosc=4 MHz
(Crystal type, CLKS="0"),
Output pin floating
ICC3
ICC4
Normal Mode
Normal Mode
2.2
3.1
3
4
mA
mA
−
−
/RESET= 'High', Fosc=10 MHz
(Crystal type, CLKS="0"),
Output pin floating
Ta= -40°C ~85 °C, VDD= 3.0V, GND= 0V
Symbol
FXT
Parameter
Condition
Min.
Typ. Max. Unit
10M kHz
32.768 kHz
Crystal: VDD to 5V
Sub-Oscillator
Two cycles with two clocks
Two cycles with two clocks
32.768 8M
Fs
−
−
External R, Internal C for
Sub-Oscillator
270
384
500 kHz
R: 300KΩ, internal capacitance
R: 2.2MΩ, internal capacitance
VIN = VDD, GND
ERIC
External R, Internal C for
Sub-Oscillator
22.9 32.768 42.6 kHz
Input Leakage Current for
Input Pins
IIL
-1
0
1
μA
Input High Threshold
Voltage
VIH1
Ports 5, 6, 7, 8
1.8
V
−
−
(Schmitt Trigger)
Input High Threshold
Voltage (Schmitt Trigger)
VIL1
VIHT1
VILT1
VIHT2
VILT2
IOH1
Ports 5, 6, 7, 8
0.6
−
V
V
−
1.8
−
−
−
−
−
−
−
−
Input High Threshold
Voltage (Schmitt Trigger)
/RESET
Input Low Threshold
Voltage (Schmitt Trigger)
/RESET
0.6
−
V
Input High Threshold
Voltage (Schmitt Trigger)
TCC, INT0, INT1
TCC, INT0, INT1
VOH = 2.4V, IROCS=”0”
VOL = 0.4V, IROCS=”0”
1.8
−
V
Input Low Threshold
Voltage (Schmitt Trigger)
0.6
−
V
Output High Voltage (Ports
5~8)
-1.8
−
mA
mA
Output Low Voltage (Ports
5~8)
IOL1
6
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
• 67
EM78P468NB/P470N
8-Bit Microcontroller
(Continuation)
Symbol
Parameter
Condition
Min.
Typ. Max. Unit
Output high voltage
(P5.7/IROUT Pin)
IOH1
VOH = 2.4V, IROCS=”1”
-3.5
mA
mA
−
−
−
Output Low Voltage
(P5.7/IR OUT Pin)
IOL2
VOL = 0.4V, IROCS=”1”
12
−
IPH
IPL
Pull-High Current
Pull-Low Current
Pull-high active, input pin at GND -16
-23
23
-30
30
μA
μA
Pull-low active, input pin at VDD
16
All input and I/O pins at VDD,
Output pin floating,
WDT disabled
ISB
Sleep Mode Current
Idle Mode Current
0.1
4
1
8
−
μA
/RESET= 'High', CPU OFF,
Sub-oscillator clock (32.768kHz)
ON, output pin floating,
ICC1
−
μA
LCD enabled, no load
/RESET= 'High', CPU ON,
Sub-oscillator clock (32.768kHz),
Output pin floating,
ICC2
ICC3
Green Mode Current
Normal Mode
10
20
−
−
μA
WDT enabled, LCD enabled
/RESET= 'High', Fosc=4MHz
(Crystal type, CLKS="0"),
Output pin floating
0.73
1.2
mA
9.2 AC Electrical Characteristics
Ta=- 40°C ~ 85 °C, VDD=5V±5%, GND=0V
Symbol
Parameter
Conditions
Min
45
Typ
Max
Unit
%
Dclk
Input CLK duty cycle
−
Crystal type
RC type
−
50
−
55
DC
DC
−
100
500
ns
Instruction cycle time
(CLKS="0")
Tins
−
ns
Ttcc
Tdrh
Trst
TCC input period
(Tins+20)/N*
−
ns
°
Device reset hold time
/RESET pulse width
Watchdog timer period
Input pin setup time
Input pin hold time
Output pin delay time
Ta = 25 C
11.3
2000
11.3
−
16.2
−
21.6
−
ms
ns
°
Ta = 25 C
°
Twdt
Tset
Ta = 25 C
16.2
0
21.6
−
ms
ns
−
Thold
Tdelay
−
−
20
50
−
ns
Cload=20pF
−
−
ns
* N = Selected prescaler ratio
68 •
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
EM78P468NB/P470N
8-Bit Microcontroller
APPENDIX
A Package Type
Name
Package Type
Dice
Pin Count
Package Size
−
EM78P468NBH
EM78P468NBQ64
EM78P468NBL64
EM78P470NL44
EM78P470NQ44
59
64
64
44
44
QFP
14 mm × 20 mm
7 mm × 7 mm
10 mm × 10 mm
10 mm × 10 mm
LQFP
LQFP
QFP
A.1 Green Products Compliance
These MCUs are bona-fide Green products which do not contain hazardous
substances. They complied with the third edition of Sony SS-00259 standard.
The Pb contents are less the 100ppm and complied with Sony specifications.
Part No.
Electroplate type
Ingredient (%)
EM78P468NxS/xJ
Pure Tin
Sn: 100%
°
Melting point (°C)
Electrical resistivity (µΩ cm)
Hardness (hv)
232 C
11.4
8~10
>50%
Elongation (%)
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
• 69
EM78P468NB/P470N
8-Bit Microcontroller
B Package Information
B.1 QFP – 64
Symbal
Min
一
Normal
一
Max
3.40
一
A
A1
A2
D
D1
E
0.25
2.55
一
A1
2.72
3.05
25.00 BASIC
20.00 BASIC
19.00 BASIC
14.00 BASIC
E1
θ
0°
7°
3.5
0.15
c
0.11
1.15
0.23
1.45
L
1.3
2.50 REF
L1
b
0.35
0.50
0.4
1.00 BSC
e
TITLE:
QFP-64 L(14*20 MM) FOOTPRINT 5.0mm
PACKAGE OUTLINE DIMENSION
File :
QFP 64L
Edtion: A
Unit : mm
Scale: Free
Material:
Sheet:1 of 1
Figure B-1 EM78P468NBQ64 64-Pin QFP Package Type
70 •
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
EM78P468NB/P470N
8-Bit Microcontroller
B.2 LQFP – 64
DETAIL " A "
D
Symbal
A
A1
A2
D
D1
E
E1
e
c
c1
b
b1
L
L1
θ
Min
-
Normal
-
Max
1.60
0.15
1.45
9.10
7.10
9.10
7.100
D1
0.05
1.35
8.90
6.90
8.90
6.900
-
1.40
9.00
7.00
9.00
7.00
0.4 BSC
-
L
L1
0.09
0.09
0.13
0.13
0.45
0.20
0.16
0.23
0.19
0.75
-
0.18
0.16
0.60
1.00 REF.
3.5°
64
0°
7°
1
e
b
TITLE:
LQFP 64L ( 7*7 MM ) FOOTPRINT 2.0 mm
PACKAGE OUTLINE DIMENSION
A1
File :
Edtion:
A
DETAIL " B "
LQFP 64L
Unit : mm
Scale: Free
c1
c
b
Material:
b1
Sheet:1 of 1
Figure B-3 EM78P468NBL64 64-Pin LQFP Package Type
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
• 71
EM78P468NB/P470N
8-Bit Microcontroller
B.3 LQFP – 44
Symbal Min
A
Normal
Max
1.600
0.150
1.450
0.450
0.200
A1
A2
b
0.050
1.350
0.300
0.090
1.400
0.370
c
E1
E
L
L1
e
θ
12.00 BASIC
10.00 BASIC
0.600
c
0.450
0
0.750
7
1.0(BASIC)
0.8(BASIC)
3.5
TITLE:
LQFP-44L(10*10 MM) FOOTPRINT 2.0mm
PACKAGE OUTLINE DIMENSION
File :
LQFP44
Edtion: A
Unit : mm
Scale: Free
Material:
Sheet:1 of 1
Figure B-4 EM78P470NL44 44-Pin LQFP Package Type
72 •
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
EM78P468NB/P470N
8-Bit Microcontroller
B.4 QFP – 44
Symbal Min
A
Normal
Max
2.70
0.50
2.20
A1
A2
b
0.15
1.80
2.00
0.30(TYP)
0.15(TYP)
13.20
c
E1
E
L
L1
e
13.00
9.90
0.73
1.50
13.40
10.10
1.03
c
10.00
0.88
1.60
1.70
0.80(TYP)
θ
0
7
TITLE:
QFP-44L(10*10 MM) FOOTPRINT 3.2mm
PACKAGE OUTLINE DIMENSION
File :
QFP44
Edtion: A
Unit : mm
Scale: Free
Material:
Sheet:1 of 1
Figure B-5 EM78P470NQ44 44-Pin QFP Package Type
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
• 73
EM78P468NB/P470N
8-Bit Microcontroller
74 •
Product Specification (V1.2) 11.30.2012
(This specification is subject to change without further notice)
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