EM78P157NAAS [ELAN]
8-Bit Microcontroller with OTP ROM; 8位OTP微控制器
| 型号： | EM78P157NAAS |
| 厂家： | 
ELAN MICROELECTRONICS CORP |
| 描述： | 8-Bit Microcontroller with OTP ROM |
| 文件： | 总56页 (文件大小：495K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EM78P157N
8-Bit Microcontroller
with OTP ROM
Product
Specification
Doc. Version 1.0
ELAN MICROELECTRONICS CORP.
September 2005
Trademark Acknowledgments:
IBM is a registered trademark and PS/2 is a trademark of IBM.
Windows is a trademark of Microsoft Corporation
ELAN and ELAN logo
are trademarks of ELAN Microelectronics Corporation
Copyright © 2005 by ELAN Microelectronics Corporation
All Rights Reserved
Printed in Taiwan
The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes
no responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN
Microelectronics makes no commitment to update, or to keep current the information and material contained in
this specification. Such information and material may change to conform to each confirmed order.
In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or
other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not
be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information
or material.
The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and
may be used or copied only in accordance with the terms of such agreement.
ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of
ELAN Microelectronics product in such applications is not supported and is prohibited.
NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY
ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS.
ELAN MICROELECTRONICS CORPORATION
Headquarters:
Hong Kong:
USA:
No. 12, Innovation Road 1
Hsinchu Science Park
Elan (HK) Microelectronics
Corporation, Ltd.
Elan Information
Technology Group
Hsinchu, Taiwan 30077
Tel: +886 3 563-9977
Fax: +886 3 563-9966
http://www.emc.com.tw
Rm. 1005B, 10/F Empire Centre
68 Mody Road, Tsimshatsui
Kowloon , HONG KONG
Tel: +852 2723-3376
1821 Saratoga Ave., Suite 250
Saratoga, CA 95070
USA
Tel: +1 408 366-8223
Fax: +1 408 366-8220
Fax: +852 2723-7780
elanhk@emc.com.hk
Europe:
Shenzhen:
Shanghai:
Elan Microelectronics Corp. Elan Microelectronics
Elan Microelectronics
(Europe)
Shenzhen, Ltd.
Shanghai Corporation, Ltd.
Siewerdtstrasse 105
8050 Zurich, SWITZERLAND
Tel: +41 43 299-4060
Fax: +41 43 299-4079
http://www.elan-europe.com
SSMEC Bldg., 3F, Gaoxin S. Ave. 23/Bldg. #115 Lane 572, Bibo Road
Shenzhen Hi-Tech Industrial Park Zhangjiang Hi-Tech Park
Shenzhen, Guandong, CHINA
Tel: +86 755 2601-0565
Fax: +86 755 2601-0500
Shanghai, CHINA
Tel: +86 021 5080-3866
Fax: +86 021 5080-4600
Contents
Contents
1
2
3
General Description ......................................................................................1
Features .........................................................................................................1
Pin Assignments and Descriptions..............................................................2
3.1 Pin Assignments................................................................................................. 2
3.2 Pin Descriptions ................................................................................................. 3
3.2.1 EM78P157NBP and EM78P157NBM Pin Descriptions......................................3
3.2.2 EM78P157NAP and EM78P157NAM Pin Descriptions......................................3
3.2.3 EM78P157NAAS Pin Descriptions......................................................................4
3.2.4 EM78P157NAKM Pin Descriptions.....................................................................4
4
Function Description.....................................................................................5
4.1 Operational Registers......................................................................................... 5
4.1.1 Indirect Addressing (R0) Register .......................................................................6
4.1.2 Time Clock / Counter (R1) Register....................................................................6
4.1.3 Program Counter and Stack (R2) Register .........................................................6
4.1.4 Status (R3) Register............................................................................................7
4.1.5 RAM Select (R4) Register...................................................................................7
4.1.6 Port 5 ~ Port 6 (R5 ~ R6) Registers....................................................................8
4.1.7 Interrupt Status (RF) Register .............................................................................8
4.1.8 General Purpose (R10 ~ R3F) Registers............................................................8
4.2 Special Purpose Registers ................................................................................. 8
4.2.1 Accumulator (A) Register....................................................................................8
4.2.2 Control (CONT ) Register....................................................................................9
4.2.3 I/O Port Control (IOC5 ~ IOC6) Registers...........................................................9
4.2.4 Prescaler Counter (IOCA ) Register....................................................................9
4.2.5 Pull-Down Control (IOCB) Register...................................................................10
4.2.6 Open-Drain Control (IOCC ) Register ...............................................................10
4.2.7 Pull-High Control (IOCD) Register ....................................................................11
4.2.8 WDT Control (IOCE) Register...........................................................................11
4.2.9 IOCF (Interrupt Mask Register).........................................................................12
4.3 TCC/WDT & Prescaler ..................................................................................... 12
4.4 I/O Ports ........................................................................................................... 13
4.4.1 Port 6 Input Change Wake-up/Interrupt Function Usage..................................16
4.5 RESET and Wake-up ....................................................................................... 17
4.5.1 Summary of Initialized Values for Registers......................................................19
4.5.2 The Status of RST, T, and P of STATUS Register.............................................21
4.5.2.1 RST, T and P after RESET Values .....................................................21
4.5.2.2 Event Affecting T and P Status...........................................................21
4.6 Interrupt............................................................................................................ 22
Product Specification (V1.0) 09.22.2005
• iii
Contents
4.7 Oscillator .......................................................................................................... 23
4.7.1 Oscillator Modes................................................................................................23
4.7.1.1 Oscillator Modes Defined by OSC, HLF, and HLP.............................23
4.7.1.2 The Summary of Maximum Operating Speeds..................................23
4.7.2 Crystal Oscillator/Ceramic Resonators (XTAL).................................................23
4.7.2.1 Capacitor Selection Guide for Crystal Oscillator or
Ceramic Resonator ............................................................................24
4.7.3 External RC Oscillator Mode.............................................................................25
4.7.3.1 RC Oscillator Frequencies .................................................................26
4.8 CODE Option Register..................................................................................... 26
4.8.1 Code Option Register (Word 0).........................................................................26
4.8.2 Customer ID Register (Word 1).........................................................................27
4.9 Power-On Considerations ................................................................................ 28
4.10 External Power-On Reset Circuit .................................................................... 28
4.11 Residual-Voltage Protection............................................................................. 29
4.12 Instruction Set .................................................................................................. 30
4.13 Timing Diagrams .............................................................................................. 32
4.13.1 AC Test Input/Output Waveform........................................................................32
4.13.2 RESET Timing (CLK = ”0”)................................................................................32
4.13.3 TCC Input Timing (CLKS = ”0”).........................................................................32
5
6
Absolute Maximum Ratings........................................................................33
Electrical Characteristics............................................................................33
6.1 DC Electrical Characteristic.............................................................................. 33
6.2 AC Electrical Characteristics............................................................................ 34
6.3 Device Characteristics...................................................................................... 35
6.3.1 Port 6 Vih/Vil vs. VDD (Input Pin with Schmitt Inverter)....................................35
6.3.2 Port 5 Input Threshold Voltage (Vth) vs. VDD...................................................35
6.3.3 Ports 5 & Port 6 Voh vs. Ioh, VDD=5V and 3V .................................................36
6.3.4 Ports 5 & Port 6 Vol vs. Iol, VDD=5V and 3V....................................................36
6.3.5 WDT Time Out Period vs. VDD (Prescaler Set to 1:1)......................................37
6.3.6 Typical RC OSC Frequency vs. VDD (Cext = 100pF, Temp. = 25℃) ..............38
6.3.7 Typical RC OSC Frequency vs. VDD
(with R and C under Ideal Conditions)..............................................................38
6.3.8 Typical and Maximum Operating Current
(ICC1/2/3/4) vs. Temperature............................................................................39
6.3.9 Typical and Maximum Standby Current
(ISB1 and ISB2) vs. Temperature .....................................................................41
6.3.10 Operating Voltage under Temperature Range of 0°C to 70°C
and –40°C to 85°C ............................................................................................42
6.3.11 Operating Current Range (Based on High and Low Freq. @ =25℃)
vs. Voltage.........................................................................................................43
iv •
Product Specification (V1.0) 09.22.2005
Contents
APPENDIX
A
Package Types.............................................................................................44
A..1 Package Detailed Information .......................................................................... 44
A.1.1 14-Lead Plastic Dual in line (PDIP) — 300 Mil .................................................44
A.1.2 14-Lead Plastic Small Outline (SOP) — 150 Mil...............................................45
A.1.3 18-Lead Plastic Dual in Line (PDIP) — 300 Mil ................................................46
A.1.4 18-Lead Plastic Small Outline (SOP) — 300 Mil...............................................47
A.1.5 20-Lead Plastic Small Outline (SSOP) — 209 Mil ............................................48
B
C
Quality Assurance and Reliability..............................................................49
Address Trap Detect....................................................................................50
Product Specification (V1.0) 09.22.2005
• v
Contents
Specification Revision History
Doc. Version
Revision Description
Date
1.0
Initial version
09/22/2005
vi •
Product Specification (V1.0) 09.22.2005
EM78P157N
8-Bit Microcontroller with OTP ROM
1 General Description
EM78P157N is an 8-bit microprocessor designed and developed with low-power,
high-speed CMOS technology. It is equipped with 1K*13-bits Electrical One Time
Programmable Read Only Memory (OTP-ROM). It provides three PROTECTION bits
to prevent user’s code in the OTP memory from being intruded. Eight OPTION bits are
also provided to meet user’s additional requirements.
With its OTP-ROM feature, the EM78P157N is able to offer a convenient way of
developing and verifying user’s programs. Moreover, user can take advantage of
ELAN DWriter to easily program his development code.
2 Features
Operating voltage range: 2.5V~5.5V
Operating temperature range: -40°C~85°C
Operating frequency range (base on 2 clocks ):
• Crystal mode: DC~20MHz at 5V, DC~8MHz at 3V, DC~4MHz at 2.5V.
• ERC mode: DC~4MHz at 5V, DC~4MHz at 3V, DC~4MHz at 2.5V.
Low power consumption:
• Less then 2 mA at 5V/4MHz
• Typically 20 µA at 3V/32KHz
• Typically 1 µA during sleep mode
1K × 13 bits on chip ROM
One security register to prevent intrusion of OTP memory codes
One configuration register to accommodate user’s requirements
48× 8 bits on chip registers (SRAM, general purpose register)
2 bi-directional I/O ports
5 level stacks for subroutine nesting
8-bit real time clock/counter (TCC) with selective signal sources, trigger edges, and
overflow interrupt
Two clocks per instruction cycle
Power down (SLEEP) mode
Three available interruptions
• TCC overflow interrupt
• Input-port status changed interrupt (wake up from sleep mode)
• External interrupt
Product Specification (V1.0) 09.22.2005
• 1
(This specification is subject to change without further notice)
EM78P157N
8-Bit Microcontroller with OTP ROM
Programmable free running watchdog timer
8 programmable pull-high pins
7 programmable pull-down pins
8 programmable open-drain pins
2 programmable R-option pins
Package types:
• 14 pin DIP
300mil : EM78P157NBP
• 14 pin SOP 150mil : EM78P157NBM
• 18 pin DIP
300mil : EM78P157NAP
• 18 pin SOP 300mil : EM78P157NAM
• 20 pin SSOP 209mil : EM78P157NAAS
• 20 pin SSOP 209mil : EM78P157NAKM
99.9% single instruction cycle commands
The transient point of system frequency between HXT and LXT is around 400KHz
3 Pin Assignments and Descriptions
3.1 Pin Assignments
P52
18
17
16
15
14
13
12
11
10
P51
1
2
3
4
5
6
7
8
9
P50
P53
TCC
OSCI
OSCO
VDD
1
2
3
4
5
6
7
14
13
12
11
10
9
P51
P52
P53
/RESET
Vss
P50
TCC
/RESET
Vss
OSCI
P60/INT
P61
OSCO
VDD
P67
P67
P66
P65
P64
P60/INT
P61
P62
8
P66
P63
NC
20
19
18
17
16
15
14
13
12
11
NC
1
2
20
P52
1
2
P51
P52
P51
19
18
17
16
15
14
13
12
11
P50
P53
TCC
/RESET
Vss
3
P50
P53
TCC
3
OSCI
OSCO
VDD
VDD
OSCI
OSCO
VDD
4
4
/RESET
Vss
5
5
6
Vss
6
P60/INT
P61
7
P67
P66
P65
P64
P60/INT
P61
7
P67
P66
P65
P64
8
8
P62
9
P62
9
P63
10
P63
10
Fig. 1-1 Pin Assignments
2 •
Product Specification (V1.0) 09.22.2005
(This specification is subject to change without further notice)
EM78P157N
8-Bit Microcontroller with OTP ROM
3.2 Pin Descriptions
3.2.1 EM78P157NBP and EM78P157NBM Pin Descriptions
Symbol Pin No. Type
Function
VDD
10
–
Power supply
y
y
y
XTAL type: Crystal input terminal or external clock input pin
ERC type: RC oscillator input pin
OSCI
12
I
XTAL type: Output terminal for crystal oscillator or external clock input pin
RC type: Instruction clock output
External clock signal input
y
y
y
OSCO
11
I/O
The real time clock/counter (with Schmitt trigger input pin), must be tied
to VDD or VSS if not in use
y
TCC
3
4
I
I
Input pin with Schmitt trigger. If this pin remains at logic low, the controller
will also remain at reset condition.
y
/RESET
P50~P53 are bi-directional I/O pins
P50 and P51 can also be defined as the R-option pins
P50~P52 can be set as pull-down by software
y
y
y
13, 14,
1, 2
P50~P53
I/O
P60~P61 are bi-directional I/O pins
These pins can be set as pull-high, pull-down, or open-drain through
software programming
y
y
P60~P61
P66~P67
6~7
8~9
I/O
I/O
P66~P67 are bi-directional I/O pins
These pins can be set as pull-high or open-drain through software
programming
y
y
/INT
VSS
6
5
I
External interrupt pin triggered by falling edge
Ground
y
y
–
3.2.2 EM78P157NAP and EM78P157NAM Pin Descriptions
Symbol Pin No. Type
Function
VDD
14
–
Power supply
y
y
y
XTAL type: Crystal input terminal or external clock input pin
ERC type: RC oscillator input pin
OSCI
16
I
XTAL type: Output terminal for crystal oscillator or external clock input pin
RC type: Instruction clock output
External clock signal input
y
y
y
OSCO
15
I/O
The real time clock/counter (with Schmitt trigger input pin), must be tied to
VDD or VSS if not in use
y
TCC
3
4
I
I
Input pin with Schmitt trigger. If this pin remains at logic low, the controller
will also remain at reset condition.
y
/RESET
P50~P53 are bi-directional I/O pins
P50 and P51 can also be defined as the R-option pins
P50~P52 can be set as pull-down by software
y
y
y
17,18,
1, 2
P50~P53
P60~P67
I/O
I/O
P60~P67 are bi-directional I/O pins
These pins can be set as pull-high or open-drain through software
programming
y
y
6~13
P60~P63 can also be set as pull-down by software
y
y
y
/INT
VSS
6
5
I
External interrupt pin triggered by falling edge
Ground
–
Product Specification (V1.0) 09.22.2005
• 3
(This specification is subject to change without further notice)
EM78P157N
8-Bit Microcontroller with OTP ROM
3.2.3 EM78P157NAAS Pin Descriptions
Symbol Pin No. Type
Function
VDD
15
–
Power supply
y
y
y
XTAL type: Crystal input terminal or external clock input pin
ERC type: RC oscillator input pin
OSCI
17
I
XTAL type: Output terminal for crystal oscillator or external clock input pin
RC type: Instruction clock output
External clock signal input
y
y
y
OSCO
16
I/O
The real time clock/counter (with Schmitt trigger input pin), must be tied to
VDD or VSS if not in use
Input pin with Schmitt trigger. If this pin remains at logic low, the controller
will also remain at reset condition.
y
TCC
4
5
I
I
y
/RESET
P50~P53 are bi-directional I/O pins
P50 and P51 can also be defined as the R-option pins
P50~P52 can be set as pull-down by software
y
y
y
18, 19,
2, 3
P50~P53
P60~P67
I/O
I/O
P60~P67 are bi-directional I/O pins
These pins can be set as pull-high or open-drain through software
programming
y
y
7~14
P60~P63 can also be set as pull-down by software
y
y
y
/INT
VSS
7
6
I
External interrupt pin triggered by falling edge
Ground
–
3.2.4 EM78P157NAKM Pin Descriptions
Symbol Pin No. Type
Function
VDD
15,16
–
Power supply
y
y
y
y
y
y
y
XTAL type: Crystal input terminal or external clock input pin
ERC type: RC oscillator input pin
OSCI
18
I
XTAL type: Output terminal for crystal oscillator or external clock input pin
RC type: Instruction clock output
External clock signal input
OSCO
17
I/O
The real time clock/counter (with Schmitt trigger input pin), must be tied to
VDD or VSS if not in use
Input pin with Schmitt trigger. If this pin remains at logic low, the controller
will also remain at reset condition.
TCC
3
4
I
I
y
/RESET
P50~P53 are bi-directional I/O pins
P50 and P51 can also be defined as the R-option pins
P50~P52 can be set as pull-down by software
y
y
y
P50~P53 19, 20, 1, 2 I/O
P60~P67 are bi-directional I/O pins
These pins can be set as pull-high or open-drain through software
programming
y
y
P60~P67
7~14
I/O
P60~P63 can also be set as pull-down by software
y
y
y
/INT
VSS
7
I
External interrupt pin triggered by falling edge
Ground
5, 6
–
4 •
Product Specification (V1.0) 09.22.2005
(This specification is subject to change without further notice)
EM78P157N
8-Bit Microcontroller with OTP ROM
4 Function Description
OSCO
/RESET
OSCI
TCC /INT
WDT timer
Prescaler
Oscillator/Timing
Control
ROM
R2
Stack
ALU
IOCA
RAM
Interrupt
Controller
Instruction
Register
R3
R1(TCC)
R4
Instruction
Decoder
ACC
DATA & CONTROL BUS
P60//INT
P61
P62
IOC6
R6
IOC5
R5
P50
I/O
PORT 6
I/O
PORT 5
P63
P64
P65
P66
P67
P51
P52
P53
Fig. 4-1 Function Block Diagram
4.1 Operational Registers
The following is the operational registers’ data memory configuration.
Address
R PAGE Registers
IOC PAGE Registers
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
︰
R0
R1
R2
R3
R4
R5
R6
(IAR)
Reserve
CONT
Reserve
Reserve
Reserve
IOC5
(TCC)
(PC)
(Control Register)
(Status)
(RSR)
(Port5)
(Port6)
(I/O Port Control Register)
(I/O Port Control Register)
IOC6
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
RF
Reserve
Reserve
Reserve
IOCA
(Prescaler Control Register)
(Pull-down Register)
IOCB
IOCC
(Open-drain Control)
IOCD
(Pull-high Control Register)
(WDT Control Register)
(Interrupt Mask Register)
IOCE
(Interrupt Status)
IOCF
General Registers
3F
Product Specification (V1.0) 09.22.2005
• 5
(This specification is subject to change without further notice)
EM78P157N
8-Bit Microcontroller with OTP ROM
4.1.1 Indirect Addressing (R0) Register
R0 is not a physically implemented register. Its major function is to perform as an
indirect addressing pointer. Any instruction using R0 as a pointer actually accesses
data pointed by the RAM Select Register (R4).
4.1.2 Time Clock / Counter (R1) Register
Increased by an external signal edge, which is defined by TE bit (CONT-4) through
the TCC pin, or by the instruction cycle clock.
Writable and readable as any other registers.
Defined by resetting PAB (CONT-3).
The prescaler is assigned to TCC, if the PAB bit (CONT-3) is reset.
The contents of the prescaler counter will be cleared only when TCC register is
written with a value.
4.1.3 Program Counter and Stack (R2) Register
Depending on the device type, R2 and hardware stack are 10-bits wide. The R2
structure is depicted in Fig. 4-2 below.
Generates 1024×13 bits on-chip OTP ROM addresses to the relative programming
instruction codes. One program page is 1024 words long.
R2 is set as all “0” when under RESET condition.
"JMP" instruction allows direct loading of the lower 10 program counter bits. Thus,
"JMP" allows PC to go to any location within a page.
"CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into
the stack. Thus, the subroutine entry address can be located anywhere within a
page.
"RET" ("RETL k," "RETI") instruction loads the program counter with the contents
of the top-level stack.
"ADD R2, A" allows the contents of ‘A’ to be added to the current PC, and the ninth
and tenth bits of the PC are cleared.
"MOV R2, A" allows to load an address from the "A" register to the lower 8 bits of
the PC, and the ninth and tenth bits of the PC are cleared.
Any instruction that writes to R2 (e.g., "ADD R2,A," "MOV R2,A," "BC R2,6",⋅etc.)
will cause the ninth and tenth bits (A8~A9) of the PC to be cleared. Thus, the
computed jump is limited to the first 256 locations of a page.
All instructions are single instruction cycle (fclk/2 or fclk/4) except for the instruction
that would change the contents of R2. Such instruction will need one more
instruction cycle.
6 •
Product Specification (V1.0) 09.22.2005
(This specification is subject to change without further notice)
EM78P157N
8-Bit Microcontroller with OTP ROM
000H
008H
Reset Vector
Interrupt Vector
PC (A9 ~ A0)
On-chip Program
Memory
Stack Level 1
Stack Level 2
Stack Level 3
Stack Level 4
Stack Level 5
3FFH
Fig. 4-2 R2 (Program Counter) & Stack Organization
4.1.4 Status (R3) Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GP2
GP1
GP0
T
P
Z
DC
C
Bit 0 (C): Carry flag
Bit 1 (DC): Auxiliary carry flag
Bit 2 (Z): Zero flag
Set to "1" if the result of an arithmetic or logic operation is zero
Bit 3 (P): Power down bit
Set to “1” during power on or by a "WDTC" command
Reset to “0” by a "SLEP" command
Bit 4 (T): Time-out bit
Set to “1” with the "SLEP" and "WDTC" commands, or during power up
Reset to “0” by WDT time-out
Bit 5~7 (GP0 ~ 2): General-purpose read/write bits
4.1.5 RAM Select (R4) Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Not used (read only)
Select Registers
Z flag of R3 will set to “1” when R4 content is equal to “3F.” When R4=R4+1, R4
content will function as R0. See the data memory configuration shown in Section 4.1.
Bits 0~5: are used to select registers (Address: 00~06, 0F~3F) in indirect address
mode
Bits 6~7: are not used (read only)
Bits 6~7 are set to “1” all the time
Product Specification (V1.0) 09.22.2005
• 7
(This specification is subject to change without further notice)
EM78P157N
8-Bit Microcontroller with OTP ROM
4.1.6 Port 5 ~ Port 6 (R5 ~ R6) Registers
R5 and R6 are I/O registers. Only the lower 4 bits of R5 are available.
4.1.7 Interrupt Status (RF) Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
EXIF
ICIF
TCIF
RF can be cleared by instruction but cannot be set
IOCF is the interrupt mask register (see Section 4.2.9)
NOTE
The result of reading RF is the "logic AND" of RF and IOCF.
0: disable interrupt request
1: enable interrupt request
Bit 0 (TCIF): TCC overflow interrupt flag
Set when TCC overflows. Reset by software.
Bit 1 (ICIF): Port 6 input status change interrupt flag
Set when Port 6 input changes. Reset by software.
Bit 2 (EXIF): External interrupt flag
Set by falling edge on /INT pin. Reset by software.
Bits 3 ~ 7: Not used
4.1.8 General Purpose (R10 ~ R3F) Registers
R10 ~ R3F are all 8-bit general-purpose registers
4.2 Special Purpose Registers
4.2.1 Accumulator (A) Register
Internal data transfer, or instruction operand holding
It cannot be addressed
8 •
Product Specification (V1.0) 09.22.2005
(This specification is subject to change without further notice)
EM78P157N
8-Bit Microcontroller with OTP ROM
4.2.2 Control (CONT ) Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
/INT
TS
TE
PAB
PSR2
PSR1
PSR0
CONT register is both readable and writable
Bit 0 ~ Bit 2 (PSR0 ~ PSR2): TCC/WDT prescaler bits
PSR2
PSR1
PSR0
TCC Rate
1:2
WDT Rate
1:1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:4
1:8
1:16
1:32
1:64
1:128
1:256
1:2
1:4
1:8
1:16
1:32
1:64
1:128
Bit 3 (PAB): Prescaler assignment bit
0: TCC
1: WDT
Bit 4 (TE): TCC signal edge
0: increment if the transition from low to high takes place on TCC pin
1: increment if the transition from high to low takes place on TCC pin
Bit 5 (TS): TCC signal source
0: internal instruction cycle clock
1: transition on TCC pin
Bit 6 (/INT): Interrupt enable flag
0: masked by DISI or hardware interrupt
1: enabled by ENI/RETI instructions
Bit 7:
Not used
4.2.3 I/O Port Control (IOC5 ~ IOC6) Registers
0: defines the relative I/O pin as output
1: put the relative I/O pin into high impedance
Only the lower 4 bits of IOC5 can be defined.
IOC5 and IOC6 registers are both readable and writable
4.2.4 Prescaler Counter (IOCA ) Register
IOCA register is readable
The value of IOCA is equal to the contents of Prescaler counter
Down counter
Product Specification (V1.0) 09.22.2005
• 9
(This specification is subject to change without further notice)
EM78P157N
8-Bit Microcontroller with OTP ROM
4.2.5 Pull-Down Control (IOCB) Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/PD7
/PD6
/PD5
/PD4
-
/PD2
/PD1
/PD0
IOCB Register is both readable and writable.
Bit 0 (/PD0): Control bit is used to enable the P50 pin pull-down
0: Enable internal pull-down
1: Disable internal pull-down
Bit 1 (/PD1): Control bit is used to enable the P51 pin pull-down
Bit 2 (/PD2): Control bit is used to enable the P52 pin pull-down
Bit 3:
Not used
Bit 4 (/PD4): Control bit is used to enable the P60 pin pull-down
Bit 5 (/PD5): Control bit is used to enable the P61 pin pull-down
Bit 6 (/PD6): Control bit is used to enable the P62 pin pull-down
Bit 7 (/PD7): Control bit is used to enable the P63 pin pull-down
4.2.6 Open-Drain Control (IOCC ) Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
IOCC Register is both readable and writable.
Bit 0 (OD0): Control bit is used to enable the P60 pin open-drain
0: Disable open-drain output
1: Enable open-drain output
Bit 1 (OD1): Control bit is used to enable the P61 pin open-drain
Bit 2 (OD2): Control bit is used to enable the P62 pin open-drain
Bit 3 (OD3): Control bit is used to enable the P63 pin open-drain
Bit 4 (OD4): Control bit is used to enable the P64 pin open-drain
Bit 5 (OD5): Control bit is used to enable the P65 pin open-drain
Bit 6 (OD6): Control bit is used to enable the P66 pin open-drain
Bit 7 (OD7): Control bit is used to enable the P67 pin open-drain
10 •
Product Specification (V1.0) 09.22.2005
(This specification is subject to change without further notice)
EM78P157N
8-Bit Microcontroller with OTP ROM
4.2.7 Pull-High Control (IOCD) Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/PH7
/PH6
/PH5
/PH4
/PH3
/PH2
/PH1
/PH0
IOCD Register is both readable and writable
Bit 0 (/PH0): Control bit is used to enable the P60 pin pull-high
0: Enable internal pull-high
1: Disable internal pull-high
Bit 1 (/PH1): Control bit is used to enable the P61 pin pull-high
Bit 2 (/PH2): Control bit is used to enable the P62 pin pull-high
Bit 3 (/PH3): Control bit is used to enable the P63 pin pull-high
Bit 4 (/PH4): Control bit is used to enable the P64 pin pull-high
Bit 5 (/PH5): Control bit is used to enable the P65 pin pull-high
Bit 6 (/PH6): Control bit is used to enable the P66 pin pull-high
Bit 7 (/PH7): Control bit is used to enable the P67 pin pull-high
4.2.8 WDT Control (IOCE) Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WDTE
EIS
-
ROC
-
-
-
-
Bits 0~3, 5: Not used
Bit 4 (ROC): ROC is used for the R-option
Setting the ROC to "1" will enable the status of R-option pins (P50∼P51)
that are read by the controller. Clearing the ROC will disable the
R-option function. If the R-option function is selected, you must connect
the P51 pin or/and P50 pin to VSS with a 430KΩ external resistor (Rex).
If the Rex is connected or disconnected, the status of P50 (P51) is read
as "0" or "1" respectively Refer to Fig. 4-6 under Section 4.4.
Bit 6 (EIS): Control bit is used to define the P60 (/INT) pin function
0: P60, bi-directional I/O pin
1: /INT, external interrupt pin. In this case, the I/O control bit of P60
(bit 0 of IOC6) must be set to "1"
EIS is both readable and writable.
When EIS is "0," the path of /INT is masked. When EIS is "1,” the status
of /INT pin can also be read by way of reading Port 6 (R6). Refer to Fig.
4-5(a) under Section 4.4.
Bit 7 (WDTE):Control bit is used to enable Watchdog timer
0: Disable WDT
1: Enable WDT
WDTE is both readable and writable
Product Specification (V1.0) 09.22.2005
• 11
(This specification is subject to change without further notice)
EM78P157N
8-Bit Microcontroller with OTP ROM
4.2.9 IOCF (Interrupt Mask Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
EXIE
ICIE
TCIE
Individual interrupt is enabled by setting its associated control bit in the IOCF to "1."
Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction.
Refer to Fig. 4-8 under Section 4.6.
IOCF register is both readable and writable.
Bit 0 (TCIE): TCIF interrupt enable bit
0: disable TCIF interrupt
1: enable TCIF interrupt
Bit 1 (ICIE): ICIF interrupt enable bit
0: disable ICIF interrupt
1: enable ICIF interrupt
Bit 2 (EXIE): EXIF interrupt enable bit
0: disable EXIF interrupt
1: enable EXIF interrupt
Bits 3~7:
Not used.
4.3 TCC/WDT & Prescaler
An 8-bit counter available as prescaler for the TCC or WDT. The prescaler is available
for either the TCC or WDT only at any given time, and the PAB bit of the CONT register
is used to determine the prescaler assignment. The PSR0~PSR2 bits determine the
ratio. The prescaler is cleared each time the instruction is written to TCC under TCC
mode. The WDT and prescaler, when assigned to WDT mode, are cleared by the
“WDTC” or “SLEP” instructions. Fig. 4-3 below, depicts the circuit diagram of
TCC/WDT.
R1 (TCC) is an 8-bit timer/counter. The clock source of TCC can be internal or
external clock input (edge selectable from TCC pin). If TCC signal source is from
internal clock, TCC will increase by 1 at every instruction cycle (without prescaler).
Referring to Fig. 4-3 below, CLK=Fosc/2 or CLK=Fosc/4 application is determined
by the CODE Option bit CLK status. CLK=Fosc/2 is used when CLK bit is "0," and
CLK=Fosc/4 is used when CLK bit is "1." If TCC signal source comes from external
clock input, TCC is increased by 1 at every falling edge or rising edge of TCC pin.
12 •
Product Specification (V1.0) 09.22.2005
(This specification is subject to change without further notice)
EM78P157N
8-Bit Microcontroller with OTP ROM
The watchdog timer is a free running on-chip RC oscillator. The WDT will keep on
running even when the oscillator driver has been turned off (i.e., in sleep mode).
During normal operation or sleep mode, a WDT time-out (if enabled) will cause the
device to reset. The WDT can be enabled or disabled any time during normal
mode by software programming. Refer to WDTE bit of IOCE register. Without
prescaler, the WDT time-out period is approximately 18 ms1 (default).
Data Bus
CLK(=Fosc/2 or Fosc/4)
0
1
0
TCC
Pin
M
U
X
M
U
X
SYNC
2 cycles
TCC (R1)
1
TE
TCC overflow interrupt
TS
PAB
0
1
M
U
X
8-bit Counter
M
U
X
IOCA
WDT
WTE
PAB
PAB
(in IOCE)
8-to-1 MUX
Initial
value
PSR0~PSR2
0
1
MUX
WDT time-out
Fig. 4-3 TCC and WDT Block Diagram
PAB
4.4 I/O Ports
The I/O registers, both Port 5 and Port 6, are bi-directional tri-state I/O ports. Port 6 can
be set as pull-high internally by software. Furthermore, Port 6 can also be set as
open-drain output by software and supports input status change interrupt (or wake-up)
function. P50 ~ P52 and P60 ~ P63 pins can be pulled down by software. Each I/O pin
can be defined as "input" or "output" pin by the I/O control register (IOC5 ~ IOC6). P50
~ P51 are the R-option pins which are enabled by setting the ROC bit in the IOCE
register to “1.” When the R-option function is used, it is recommended that P50 ~ P51
are used as output pins. When R-option is in enabled state, P50 ~ P51 must be
programmed as input pins. Under R-option mode, the current/power consumption by
Rex should be taken into the consideration to promote energy conservation.
The I/O registers and I/O control registers are both readable and writable. The I/O
interface circuits for Port 5 and Port 6 are depicted in Figures 4-4, 4-5(a), 4-5(b), and
4-6 shown below.
1
Vdd = 5V, set up time period = 16.8ms ± 30%
Vdd = 3V, set up time period = 18ms ± 30%
Product Specification (V1.0) 09.22.2005
• 13
(This specification is subject to change without further notice)
EM78P157N
8-Bit Microcontroller with OTP ROM
PCRD
P
Q
D
R
PCWR
CLK
_
Q
C
L
P
IOD
PORT
Q
D
R
PDWR
CLK
_
Q
C
L
PDRD
0
1
M
U
X
NOTE: Pull-down is not shown in the figure
Fig. 4-4(a) I/O Port and I/O Control Register Port 5 Circuit Diagram
P C R D
P
Q
_
Q
D
R
P C W
R
R
C L K
C
L
P 6 0 / I N T
P O R T
I O D
P
Q
_
Q
D
R
P D W
C L K
C
L
B i t
6
o f I O C E
P
0
1
D
Q
R
M
U
X
_
Q
C L K
C
L
T 1 0
P D R D
P
D
Q
R
C L K
_
Q
C
L
I N T
NOTE: Pull-high/down and open-drain are not shown in the figure
Fig. 4-5(b) I/O Port and I/O Control Register P60 (/INT) Circuit Diagram
14 •
Product Specification (V1.0) 09.22.2005
(This specification is subject to change without further notice)
EM78P157N
8-Bit Microcontroller with OTP ROM
PCRD
P
Q
_
Q
D
CLK
R
PCWR
C
L
P61~P67
PORT
IOD
P
Q
D
R
PDWR
_
Q
CLK
C
L
0
1
M
U
X
TIN
PDRD
P
R
D
Q
CLK
_
Q
C
L
NOTE: Pull-high/down and open-drain are not shown in the figure
Fig. 4-5(c) I/O Port and I/O Control Register for P61~P67 Circuit Diagram
IOCE.1
P
Q
D
R
CLK
Interrupt
_
Q
C
L
RE.1
ENI Instruction
P
T10
T11
D
Q
R
P
CLK
Q
D
R
_
Q
C
CLK
L
_
Q
C
L
T17
DISI Instruction
Interrupt
(Wake-up from SLEEP)
/SLEP
Next Instruction
(Wake-up from SLEEP)
Fig. 4-5(d) Block Diagram on I/O Port 6 with Input Change Interrupt/Wake-up
Product Specification (V1.0) 09.22.2005
• 15
(This specification is subject to change without further notice)
EM78P157N
8-Bit Microcontroller with OTP ROM
4.4.1 Port 6 Input Change Wake-up/Interrupt Function Usage
(I) Wake-up from Port 6 Input Status Change
(II) Port 6 Input Status Change Interrupt
(a) Before SLEEP
1. Read I/O Port 6 (MOV R6,R6)
2. Execute "ENI"
1. Disable WDT* (using very carefully)
2. Read I/O Port 6 (MOV R6,R6)
3. Execute "ENI" or "DISI"
3. Enable interrupt (Set IOCF.1)
4. IF Port 6 change (interrupt)
→ Interrupt vector (008H)
4. Enable interrupt (Set IOCF.1)
5. Execute "SLEP" instruction
(b) After Wake-up
1. IF "ENI" → Interrupt vector (008H)
2. IF "DISI" → Next instruction
* Software disables WDT (watchdog timer) but hardware must be enabled before applying the Port 6 Change
Wake-Up function (CODE Option Register and Bit 11 (ENWDTB-) set to “1”).
PCRD
ROC
VCC
P
R
Q
Q
D
Weakly
Pull-up
CLK
PCWR
C
L
P
R
PORT
Q
Q
D
IOD
PDWR
C
L
PDRD
0
1
M
U
X
Rex*
*The Rex is a 430K ohm external
Fig. 4-6 I/O Port with R-option (P50,P51) Circuit Diagram
16 •
Product Specification (V1.0) 09.22.2005
(This specification is subject to change without further notice)
EM78P157N
8-Bit Microcontroller with OTP ROM
4.5 RESET and Wake-up
A RESET is initiated by one of the following events:
1. Power on reset
2. /RESET pin input "low," or
3. WDT time-out (if enabled)
The device is kept in a RESET condition for a period of approximately 18ms2 (one
oscillator start-up timer period) after the reset is detected. Once the RESET occurs, the
following functions are performed (see Fig. 4-7 under Section 4.5.2.1)
The oscillator is running, or will be started.
The Program Counter (R2) is set to all "0."
All I/O port pins are configured as input mode (high-impedance state).
The Watchdog timer and prescaler are cleared.
When power is switched on, the upper 3 bits of R3 are cleared.
All the CONT register bits are set to "1" except for the Bit 6 (INT flag).
All the IOCA register bits are set to "1."
All the IOCB register bits are set to "1."
The IOCC register is cleared.
All the IOCD register bits are set to "1."
Bit 7 of the IOCE register is set to "1," and Bits 4 and 6 are cleared.
Bits 0 ~2 of RF and bits 0 ~2 of IOCF registers are cleared.
The sleep (power down) mode is asserted by executing the “SLEP” instruction. While
entering sleep mode, WDT (if enabled) is cleared but keeps on running. The controller
can be awakened by:
1. External reset input on /RESET pin,
2. WDT time-out (if enabled), or
3. Port 6 input status changes (if enabled).
The first two cases will cause the EM78P157N to reset. The T and P flags of R3 can be
used to determine the source of the reset (wake-up). The last case is considered the
continuation of the program execution. The global interrupt ("ENI" or "DISI" being
executed) decides whether or not the controller branches to the interrupt vector
following wake-up. If ENI is executed before SLEP, the instruction will begin to execute
from the address 008H after wake-up. If DISI is executed before SLEP, the operation
will restart from the succeeding instruction right next to SLEP after wake-up.
2
Vdd = 5V, set up time period = 16.8ms ± 30%
Vdd = 3V, set up time period = 18ms ± 30%
Product Specification (V1.0) 09.22.2005
• 17
(This specification is subject to change without further notice)
EM78P157N
8-Bit Microcontroller with OTP ROM
Only one of Cases 2 and 3 can be enabled before entering into sleep mode, i.e.,
[a] if Port 6 Input Status Change Interrupt is enabled before SLEP, WDT must be
disabled by software. However, the WDT bit in the option register remains enabled.
Hence, the EM78P157N can be awakened only by either Case 1 or 3.
[b] if WDT is enabled before SLEP, Port 6 Input Status Change Interrupt must be
disabled. Hence, the EM78P157N can only be awakened by either Case 1 or 2.
Refer to the section (Section 4.6) on Interrupt.
If Port 6 Input Status Change Interrupt is used to wake-up the EM78P157N (Case [a]
above), the following instructions must be executed before SLEP:
MOV A, @xx000110b
CONTW
; Select internal TCC clock
CLR R1
; Clear TCC and prescaler
; Select WDT prescaler
MOV A, @xxxx1110b
CONTW
WDTC
; Clear WDT and prescaler
; Disable WDT
MOV A, @0xxxxxxxb
IOW RE
MOV R6, R6
MOV A, @00000x1xb
IOW RF
; Read Port 6
; Enable Port 6 input change interrupt
ENI (or DISI)
SLEP
; Enable (or disable) global interrupt
; Sleep
NOP
One problem you should be aware of is that after waking up from the sleep mode, WDT
is enabled automatically. The WDT operation (being enabled or disabled) should be
handled appropriately by software after waking up from the sleep mode.
18 •
Product Specification (V1.0) 09.22.2005
(This specification is subject to change without further notice)
EM78P157N
8-Bit Microcontroller with OTP ROM
4.5.1 Summary of Initialized Values for Registers
Legend:
U = Unknown or don’t care P = Previous value before reset t = Check with Section 4.5.2.1
Address
Name
Reset Type
Bit Name
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
X
U
U
X
U
U
X
U
U
X
U
U
C53
1
C52
1
C51
1
C50
1
Power-On
N/A
IOC5
/RESET and WDT
1
1
1
1
Wake-Up from Pin
Change
U
U
U
U
P
P
P
P
Bit Name
C67
1
C66
1
C65
1
C64 C63
C62
1
C61
1
C60
1
Power-On
1
1
1
1
N/A
N/A
IOC6
CONT
/RESET and WDT
1
1
1
1
1
1
Wake-Up from Pin
Change
Bit Name
P
P
P
P
P
P
P
P
X
1
1
/INT
0
TS
1
TE
1
PAB PSR2 PSR1 PSR0
Power-On
1
1
1
1
1
1
1
1
/RESET and WDT
0
1
1
Wake-Up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
-
-
-
-
-
-
-
-
Power-On
U
P
U
P
U
P
U
P
U
P
U
P
U
P
U
P
0x00
0x01
0x02
0x03
0x04
0x05
R0(IAR)
R1(TCC)
R2(PC)
R3(SR)
R4(RSR)
P5
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
P
P
P
P
P
P
P
P
-
-
-
-
-
-
-
-
Power-On
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
P
P
P
P
P
P
P
P
-
-
-
-
-
-
-
-
Power-On
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
*0/P *0/P *0/P *0/P *1/P *0/P *0/P *0/P
GP2 GP1 GP0
T
1
t
P
1
t
Z
U
P
DC
U
C
U
P
Power-On
0
0
0
0
0
0
/RESET and WDT
P
Wake-Up from Pin
Change
Bit Name
P
P
P
t
t
P
P
P
-
-
-
-
-
-
-
-
Power-On
1
1
1
1
U
P
U
P
U
P
U
P
U
P
U
P
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
1
1
P
P
P
P
P
P
X
0
0
X
0
0
X
0
0
X
0
0
P53
U
P52
U
P51
U
P50
U
Power-On
/RESET and WDT
P
P
P
P
Wake-Up from Pin
Change
0
0
0
0
P
P
P
P
* Jump to address 0x08, or execute the instruction following the “SLEP” instruction.
Product Specification (V1.0) 09.22.2005
• 19
(This specification is subject to change without further notice)
EM78P157N
8-Bit Microcontroller with OTP ROM
Address
Name
Reset Type
Bit Name
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
P67
U
P66
U
P65
U
P64
U
P63
U
P62
U
P61
U
P60
U
Power-On
0x06
P6
/RESET and WDT
P
P
P
P
P
P
P
P
Wake-Up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
X
U
U
X
U
U
X
U
U
X
U
U
X
U
U
EXIF ICIF TCIF
Power-On
0
0
0
0
0
0
0x0F
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
RF(ISR)
IOCA
IOCB
IOCC
IOCD
IOCE
IOCF
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
U
U
U
U
U
P
P
P
-
-
-
-
-
-
-
-
Power-On
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
P
P
P
P
P
P
P
P
/PD7 /PD6 /PD5 /PD4
X
U
U
/PD2 /PD1 /PD0
Power-On
1
1
1
1
1
1
1
1
1
1
1
1
1
1
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
P
P
P
P
U
P
P
P
OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0
Power-On
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
P
P
P
P
P
P
P
P
/PH7 /PH6 /PH5 /PH4 /PH3 /PH2 /PH1 /PH0
Power-On
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
P
P
P
P
P
P
P
P
WDTE EIS
X
U
U
ROC
X
U
U
X
U
U
X
U
U
X
U
U
Power-On
1
1
0
0
0
0
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
1
P
U
P
U
U
U
U
X
U
U
X
U
U
X
U
U
X
U
U
X
U
U
EXIE ICIE TCIE
Power-On
0
0
0
0
0
0
/RESET and WDT
Wake-Up from Pin
Change
U
U
U
U
U
P
P
P
Bit Name
-
-
-
-
-
-
-
-
Power-On
U
P
U
P
U
P
U
P
U
P
U
P
U
P
U
P
0x10~0x2F R10~R2F
/RESET and WDT
Wake-Up from Pin
Change
P
P
P
P
P
P
P
P
20 •
Product Specification (V1.0) 09.22.2005
(This specification is subject to change without further notice)
EM78P157N
8-Bit Microcontroller with OTP ROM
4.5.2 The Status of RST, T, and P of STATUS Register
A RESET condition is initiated by the following events:
1. A power-on condition
2. A high-low-high pulse on /RESET pin
3. Watchdog timer time-out
4.5.2.1 RST, T and P after RESET Values
The values of T (Time-out) and P (Power-down) as listed below are used to verify how
the processor wakes up.
Reset Type
T
P
Power on
1
*P
1
1
*P
0
/RESET during Operating mode
/RESET wake-up during SLEEP mode
WDT during Operating mode
0
*P
0
WDT wake-up during SLEEP mode
Wake-Up on pin change during SLEEP mode
0
1
0
*P = Previous status before reset
4.5.2.2 Event Affecting T and P Status
The table below shows the events that may affect the status of T (Time-out) and
P (Power-down).
Event
T
P
Power on
1
1
0
1
1
1
1
WDTC instruction
WDT time-out
SLEP instruction
*P
0
Wake-Up on pin change during SLEEP mode
0
*P = Previous status before reset
VDD
D
CLK
Q
CLK
Oscillator
CLR
Power-on
Reset
Voltage
Detector
WDTE
WDT Timeout
Setup Time
RESET
WDT
/RESET
Fig. 4-7 Controller Reset Block Diagram
Product Specification (V1.0) 09.22.2005
• 21
(This specification is subject to change without further notice)
EM78P157N
8-Bit Microcontroller with OTP ROM
4.6 Interrupt
The EM78P157N has three falling-edge interrupts as listed below:
1. TCC overflow interrupt
2. Port 6 Input Status Change Interrupt
3. External interrupt [(P60, /INT) pin].
Before the Port 6 Input Status Change Interrupt is enabled, reading Port 6 (e.g.,
"MOV R6,R6") is necessary. Each Port 6 pin of will have this feature when its status
changes. Any pin configured as output or P60 pin configured as “/INT,” is excluded
from this function. The Port 6 Input Status Change Interrupt can wake up the
EM78P157N from the sleep mode if Port 6 is enabled prior to going into the sleep mode
by executing SLEP instruction. When the chip wakes-up, the controller will continue to
execute the succeeding address if the global interrupt is disabled or branches to the
interrupt vector 008H if the global interrupt is enabled.
RF is the interrupt status register that records the interrupt requests in the relative
flags/bits. IOCF is an interrupt mask register. The global interrupt is enabled by the
ENI instruction and is disabled by the DISI instruction. When one of the enabled
interrupts occurs, the next instruction will be fetched from address 008H. Once in the
interrupt service routine, the source of an interrupt can be determined by polling the flag
bits in RF. The interrupt flag bit must be cleared by instructions before leaving the
interrupt service routine and before interrupts are enabled to avoid recursive interrupts.
The flag (except ICIF bit) in the Interrupt Status Register (RF) is set regardless of the
status of its mask bit or ENI execution. Note that the outcome of RF will be the logic
AND of RF and IOCF (refer to Fig. 4-7 above). The RETI instruction ends the interrupt
routine and enables the global interrupt (execution of ENI).
When an interrupt is generated by the INT instruction (enabled), the next instruction will
be fetched from address 001H.
VCC
P
D
Q
IRQn
R
/IRQn
CLK
INT
_
Q
IRQm
C
L
RFRD
RF
ENI/DISI
P
IOD
Q
D
R
CLK
_
Q
IOCFWR
C
L
IOCF
/RESET
IOCFRD
RFWR
Fig. 4-8 Interrupt Input Circuit
22 •
Product Specification (V1.0) 09.22.2005
(This specification is subject to change without further notice)
EM78P157N
8-Bit Microcontroller with OTP ROM
4.7 Oscillator
4.7.1 Oscillator Modes
The EM78P157N can be operated in three different oscillator modes, namely, External
RC oscillator mode (ERC), High XTAL oscillator mode (HXT), and Low XTAL oscillator
mode (LXT). User can select one of them by programming OSC, HLF, and HLP in the
CODE option register. The following table depicts how these three modes are defined.
4.7.1.1 Oscillator Modes Defined by OSC, HLF, and HLP
Mode
OSC
HLF
HLP
X2
1
X2
X2
0
ERC (External RC oscillator mode)
HXT (High XTAL oscillator mode)1
LXT (Low XTAL oscillator mode)1
0
1
1
0
1 The transient point of system frequency between HXT and LXY is around 400 kHz
2 X = Don’t care
4.7.1.2 The Summary of Maximum Operating Speeds
The maximum operational frequency of crystal/resonator under different VDDs is as
listed below.
Condition
VDD
Fxt Max Freq.
3.0
5.0
8.0 MHz
Two cycles with two clocks
20.0 MHz
4.7.2 Crystal Oscillator/Ceramic Resonators (XTAL)
EM78P157N can be driven by an external clock signal through the OSCI pin as
illustrated in the following figure.
OSCI
OSCO
Ext. Clock
EM78P157N
Fig. 4-9 External Clock Input Circuit
Product Specification (V1.0) 09.22.2005
• 23
(This specification is subject to change without further notice)
EM78P157N
8-Bit Microcontroller with OTP ROM
In most applications, Pin OSCI and Pin OSCO can connected with a crystal or ceramic
resonator to generate oscillation. The figure below depicts such circuit. The same
thing is applicable whether it is in the HXT mode or LXT mode. Table below provides
the recommended values of C1 and C2. Since each resonator has its own attribute,
you should refer to its specification for the appropriate values of C1 and C2. RS, a
serial resistor, may be necessary for AT strip cut crystal or low frequency mode.
C1
OSCI
EM78P157N
XTAL
OSCO
C2
RS
Fig. 4-10 Crystal/Resonator Circuit
4.7.2.1 Capacitor Selection Guide for Crystal Oscillator or Ceramic
Resonator
The table below provides the recommended values of C1 and C2. Since each
resonator has its own attribute, you should refer to its specification for the appropriate
values of C1 and C2. RS, a serial resistor, may be necessary for AT strip cut crystal or
low frequency mode.
Oscillator Type
Frequency Mode
Frequency
C1(pF)*
C2(pF)*
455 kHz
2.0 MHz
4.0 MHz
32.768kHz
100KHz
200KHz
455KHz
1.0MHz
2.0MHz
4.0MHz
100~150
20~40
10~30
25
100~150
20~40
10~30
15
Ceramic Resonators
HXT
LXT
HXT
25
25
25
25
Crystal Oscillator
20~40
15~30
15
20~150
15~30
15
15
15
* The values shown for capacitors C1 & C2 are for reference only.
24 •
Product Specification (V1.0) 09.22.2005
(This specification is subject to change without further notice)
EM78P157N
8-Bit Microcontroller with OTP ROM
4.7.3 External RC Oscillator Mode
For some applications that do not need a very precise timing calculation, the RC
oscillator (Fig. 4-11 below) offers a lot of cost savings. Nevertheless, it should be noted
that the frequency of the RC oscillator is influenced by the supply voltage, the values of
the resistor (Rext), the capacitor (Cext), and even by the operation temperature.
Moreover, the frequency also changes slightly from one chip to another due to the
manufacturing process variation.
In order to maintain a stable system frequency, the values of the Cext should not be
less than 20pF, and that the value of Rext should not be greater than 1 MΩ. If they
cannot be kept in this range, the frequency is easily affected by noise, humidity, and
leakage.
The smaller the Rext in the RC oscillator, the faster its frequency will be. On the
contrary, for very low Rext values, for instance, 1 KΩ, the oscillator will become
unstable because the NMOS cannot accurately discharge the current of the
capacitance.
Based on the above factors, it must be kept in mind that all of the supply voltage, the
operation temperature, the components of the RC oscillator, the package types, the
way the PCB is laid out, will affect the system frequency.
Vcc
Rext
OSCI
Cext
EM78P157N
Fig. 4-11 External RC Oscillator Mode Circuit
Product Specification (V1.0) 09.22.2005
• 25
(This specification is subject to change without further notice)
EM78P157N
8-Bit Microcontroller with OTP ROM
4.7.3.1 RC Oscillator Frequencies
Average Fosc
Average Fosc
Cext
Rext
5V, 25°C
3V, 25°C
3.3k
5.1k
10k
3.92 MHz
2.67 MHz
1.39MHz
149 KHz
1.39 MHz
940 KHz
480 KHz
52 KHz
3.65 MHz
2.60 MHz
1.40 MHz
156 KHz
1.33 MHz
920 KHz
475 KHz
50 KHz
20 pF
100k
3.3k
5.1k
10k
100 pF
300 pF
100k
3.3k
5.1k
10k
595 KHz
400 KHz
200 KHz
21 KHz
560 KHz
390 KHz
200 KHz
20 KHz
100k
NOTE: 1. Values derived and measured from DIP packages
2. Values are for design references only
3. The frequency drift is about ±30%
4.8 CODE Option Register
The EM78P157N has a CODE option word that is not a part of the normal program
memory. The option bits cannot be accessed during normal program execution.
The following is the Code Option Register and Customer ID Register arrangement
distribution:
Word 0
Word 1
Bit12~Bit0
Bit12~Bit0
4.8.1 Code Option Register (Word 0)
WORD 0
Bit12 Bit11 Bit10 Bit9
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
PR2
Bit1
Bit0
-
-
-
-
CLKS ENWDTB
-
HLF OSC HLP
PR1
PR0
Bit 9~Bit 12: Not used (reserved)
This bit is set to “1” all the time
Bit 8 (CLKS): Instruction period option bit
0: two oscillator periods
1: four oscillator periods
(Refer to Section 4-12, Instruction Set)
Bit 7 (ENWDTB): Watchdog timer enable bit
0: Enable
1: Disable
Bit 6:
Not used (reserved)
This bit is set to “1” all the time
26 •
Product Specification (V1.0) 09.22.2005
(This specification is subject to change without further notice)
EM78P157N
8-Bit Microcontroller with OTP ROM
Bit 5 (HLF): XTAL frequency selection
0: XTAL2 type (low frequency, 32.768KHz)
1: XTAL1 type (high frequency)
This bit will affect system oscillation only when Bit 4 (OSC) is “1.” When
OSC is”0,” HLF must be “0”.
NOTE
The transient point of system frequency between HXT and LXY is around 400 KHz.
Bit 4 (OSC): Oscillator type selection
0: RC type
1: XTAL type (XTAL1 and XTAL2)
Bit 3 (HLP): Power selection
0: Low power
1: High power
Bit 2 ~ Bit 0 (PR2 ~ PR0): Protect bits
PR2 ~ PR0 are protect bits that can be set as follows:
PR2
PR1
PR0
Protect
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Disable
4.8.2 Customer ID Register (Word 1)
Bit 12 ~ Bit 0
XXXXXXXXXXXXX
Bit 12 ~ Bit 0: Customer’s ID code
Product Specification (V1.0) 09.22.2005
• 27
(This specification is subject to change without further notice)
EM78P157N
8-Bit Microcontroller with OTP ROM
4.9 Power-On Considerations
Any microcontroller is not guaranteed to start to operate properly before the power
supply stays at its steady state.
EM78P157N POR voltage range is 1.2V~1.8V. Under customer application, when
power is OFF, Vdd must drop to below 1.2V and remains OFF for 10µs before power
can be switched ON again. This way, the EM78P157N will reset and works normally.
The extra external reset circuit will work well if Vdd can rise at very fast speed (50 ms or
less). However, under most cases where critical applications are involved, extra
devices are required to assist in solving the power-up problems.
4.10 External Power-On Reset Circuit
The circuit shown below implements an external RC to produce the reset pulse. The
pulse width (time constant) should be kept long enough for Vdd to reach the minimum
operation voltage. This circuit is used when the power supply has a slow rise time.
Because the current leakage from the /RESET pin is about ±5µA, it is recommended
that R should not be greater than 40K. In this way, the /RESET pin voltage is held
below 0.2V. The diode (D) acts as a short circuit at the moment of power down. The
capacitor C will discharge rapidly and fully. Rin, the current-limited resistor, will prevent
high current or ESD (electrostatic discharge) from flowing into /RESET pin.
Vdd
R
/RESET
D
EM78P157N
Rin
C
Fig. 4-12 External Power-Up Reset Circuit
28 •
Product Specification (V1.0) 09.22.2005
(This specification is subject to change without further notice)
EM78P157N
8-Bit Microcontroller with OTP ROM
4.11 Residual-Voltage Protection
When battery is replaced, device power (Vdd) is taken off but residual-voltage remains.
The residual-voltage may trips below Vdd minimum, but not to zero. This condition
may cause a poor power-on reset. Figures 4-13 and 4-14 illustrate how to build a
residual-voltage protection circuit.
Vdd
Vdd
33K
EM78P157N
Q1
10K
/RESET
40K
1N4684
Fig. 4-13 Circuit 1 for the Residue Voltage Protection
Vdd
Vdd
R1
EM78P157N
Q1
/RESET
R2
40K
Fig. 4-14 Circuit 2 for the Residue Voltage Protection
Product Specification (V1.0) 09.22.2005
• 29
(This specification is subject to change without further notice)
EM78P157N
8-Bit Microcontroller with OTP ROM
4.12 Instruction Set
Each instruction in the instruction set is a 13-bit word divided into an OP code and one
or more operands. Normally, all instructions are executed within one single instruction
cycle (one instruction consists of 2 oscillator periods), unless the program counter is
changed by instruction "MOV R2,A," "ADD R2,A," or by instructions of arithmetic or
logic operation on R2 (e.g., "SUB R2,A," "BS(C) R2,6," "CLR R2," etc.). In this case,
the execution takes two instruction cycles.
If for some reasons, the specification of the instruction cycle is not suitable for certain
applications, try modifying the instruction as follows:
1. Change one instruction cycle to consist of 4 oscillator periods.
2. "JMP,” "CALL," "RET," "RETL," and "RETI," or the conditional skip ("JBS," "JBC,"
"JZ," "JZA," "DJZ," and "DJZA") commands which were tested to be true, are
executed within two instruction cycles. The instructions that are written to the
program counter also take two instruction cycles.
Case (1) is selected by the CODE Option bit, called CLK. One instruction cycle
consists of two oscillator clocks if CLK is low, and four oscillator clocks if CLK is high.
Note that once the 4 oscillator periods within one instruction cycle is selected as in
Case (A), the internal clock source to TCC should be CLK=Fosc/4, instead of Fosc/2 as
indicated in Fig. 4-3 (TCC and WDT Block Diagram) in Section 4.3.
Furthermore, the instruction set has the following features:
1. Every bit of any register can be set, cleared, or tested directly.
2. The I/O register can be regarded as general register. That is, the same instruction
can operate on I/O register.
LEGEND: "R" represents a register designator that specifies which one of the registers (including operational registers
and general purpose registers) is to be utilized by the instruction.
"b" represents a bit field designator that selects the value for the bit which is located in the register "R" and
affects operation.
"k" represents an 8 or 10-bit constant or literal value.
Instruction Binary
Hex
Mnemonic
Operation
Status Affected
0 0000 0000 0000
0 0000 0000 0001
0 0000 0000 0010
0 0000 0000 0011
0 0000 0000 0100
0000
NOP
DAA
CONTW
SLEP
WDTC
No Operation
Decimal Adjust A
A → CONT
0 → WDT, Stop oscillator
0 → WDT
None
C
None
T,P
0001
0002
0003
0004
T,P
None1
None
None
None
0 0000 0000 rrrr
0 0000 0001 0000
0 0000 0001 0001
0 0000 0001 0010
000r
0010
0011
0012
IOW R
ENI
DISI
A → IOCR
Enable Interrupt
Disable Interrupt
[Top of Stack] → PC
RET
[Top of Stack] → PC, Enable
0 0000 0001 0011
0013
RETI
None
None
None1
None
Z
Interrupt
0 0000 0001 0100
0 0000 0001 rrrr
0 0000 01rr rrrr
0 0000 1000 0000
0014
001r
00rr
CONTR
IOR R
CONT → A
IOCR → A
A → R
MOV R,A
CLRA
0080
0 → A
30 •
Product Specification (V1.0) 09.22.2005
(This specification is subject to change without further notice)
EM78P157N
8-Bit Microcontroller with OTP ROM
Instruction Binary
Hex
Mnemonic
Operation
Status Affected
0 0000 11rr rrrr
0 0001 00rr rrrr
0 0001 01rr rrrr
0 0001 10rr rrrr
0 0001 11rr rrrr
0 0010 00rr rrrr
0 0010 01rr rrrr
0 0010 10rr rrrr
0 0010 11rr rrrr
0 0011 00rr rrrr
0 0011 01rr rrrr
0 0011 10rr rrrr
0 0011 11rr rrrr
0 0100 00rr rrrr
0 0100 01rr rrrr
0 0100 10rr rrrr
0 0100 11rr rrrr
0 0101 00rr rrrr
0 0101 01rr rrrr
0 0101 10rr rrrr
0 0101 11rr rrrr
00rr
CLR R
Z
0 → R
R-A → A
R-A → R
R-1 → A
R-1 → R
A ∨ R → A
A ∨ R → R
A & R → A
A & R → R
A ⊕ R → A
A ⊕ R → R
A + R → A
A + R → R
R → A
R → R
/R → A
/R → R
01rr
01rr
01rr
01rr
02rr
02rr
02rr
02rr
03rr
03rr
03rr
03rr
04rr
04rr
04rr
04rr
05rr
05rr
05rr
05rr
SUB A,R
SUB R,A
DECA R
DEC R
Z,C,DC
Z,C,DC
Z
Z
Z
Z
Z
Z
Z
Z
OR A,R
OR R,A
AND A,R
AND R,A
XOR A,R
XOR R,A
ADD A,R
ADD R,A
MOV A,R
MOV R,R
COMA R
COM R
Z,C,DC
Z,C,DC
Z
Z
Z
Z
Z
Z
INCA R
INC R
DJZA R
DJZ R
R+1 → A
R+1 → R
None
None
R-1 → A, skip if zero
R-1 → R, skip if zero
R(n) → A(n-1),
R(0) → C, C → A(7)
R(n) → R(n-1),
R(0) → C, C → R(7)
R(n) → A(n+1),
R(7) → C, C → A(0)
R(n) → R(n+1),
R(7) → C, C → R(0)
R(0-3) → A(4-7),
R(4-7) → A(0-3)
R(0-3) ↔ R(4-7)
R+1 → A, skip if zero
R+1 → R, skip if zero
0 0110 00rr rrrr
0 0110 01rr rrrr
0 0110 10rr rrrr
0 0110 11rr rrrr
0 0111 00rr rrrr
06rr
06rr
06rr
06rr
07rr
RRCA R
RRC R
C
C
RLCA R
RLC R
C
C
SWAPA R
None
0 0111 01rr rrrr
0 0111 10rr rrrr
0 0111 11rr rrrr
0 100b bbrr rrrr
07rr
07rr
07rr
0xxx
SWAP R
JZA R
JZ R
None
None
None
None2
BC R,b
0 → R(b)
None3
None
None
None
None
None
Z
0 101b bbrr rrrr
0 110b bbrr rrrr
0 111b bbrr rrrr
1 00kk kkkk kkkk
1 01kk kkkk kkkk
1 1000 kkkk kkkk
1 1001 kkkk kkkk
1 1010 kkkk kkkk
1 1011 kkkk kkkk
0xxx
0xxx
0xxx
1kkk
1kkk
18kk
19kk
1Akk
1Bkk
BS R,b
1 → R(b)
JBC R,b
JBS R,b
CALL k
JMP k
MOV A,k
OR A,k
AND A,k
XOR A,k
if R(b)=0, skip
if R(b)=1, skip
PC+1 → [SP], (Page, k) → PC
(Page, k) → PC
k → A
A ∨ k → A
A & k → A
A ⊕ k → A
Z
Z
k → A,
[Top of Stack] → PC
1 1100 kkkk kkkk
1Ckk
RETL k
None
1 1101 kkkk kkkk
1 1110 0000 0001
1 1111 kkkk kkkk
1Dkk
1E01
1Fkk
SUB A,k
INT
Z,C,DC
None
k-A → A
PC+1 → [SP], 001H → PC
k+A → A
ADD A,k
Z,C,DC
1This instruction is applicable to IOC5 ~ IOC6 and IOCB ~ IOCF only
2This instruction is not recommended for RF operation
3This instruction cannot operate under RF
Product Specification (V1.0) 09.22.2005
• 31
(This specification is subject to change without further notice)
EM78P157N
8-Bit Microcontroller with OTP ROM
4.13 Timing Diagrams
4.13.1 AC Test Input/Output Waveform
2.4
0.4
2.0
0.8
2.0
0.8
TEST POINTS
AC Testing : Input is driven at 2.4V for logic "1",and 0.4V for logic "0".Timing measurements are
made at 2.0V for logic "1",and 0.8V for logic "0".
Fig. 4-15 AC Test Input/Output Waveform Timing Diagram
4.13.2 RESET Timing (CLK = ”0”)
Instruction 1
Executed
NOP
CLK
/RESET
Tdrh
Fig. 4-16 RESET Timing (CLK = ”0”)Timing Diagram
4.13.3 TCC Input Timing (CLKS = ”0”)
Tins
CLK
TCC
Ttcc
Fig. 4-17 TCC Input Timing (CLKS = ”0”) Timing Diagram
32 •
Product Specification (V1.0) 09.22.2005
(This specification is subject to change without further notice)
EM78P157N
8-Bit Microcontroller with OTP ROM
5 Absolute Maximum Ratings
EM78P157N
Items
Rating
–40°C to 85°C
Temperature under bias
Storage temperature
Working voltage
–65°C to 150°C
2.5 to 5.5V
Working frequency
Input voltage
DC to 20MHz
Vss-0.3V to Vdd+0.5V
Vss-0.3V to Vdd+0.5V
Output voltage
6 Electrical Characteristics
6.1 DC Electrical Characteristic
(Ta=25 °C, VDD=5V±5%, VSS=0V)
Symbol
FXT
Parameter
Condition
Min
DC
Typ
Max Unit
XTAL: VDD to 3V
Two cycle with two clocks
Two cycle with two clocks
R: 5.1KΩ, C: 100 pF
8.0
MHz
MHz
XTAL: VDD to 5V
DC
20.0
ERC
IIL
ERC: VDD to 5V
F±30% 940 F±30% kHz
Input Leakage Current for input
pins
VIN = VDD, VSS
±1
µA
VIH1
VIL1
Input High Voltage (VDD=5V)
Input Low Voltage (VDD=5V)
Input High Threshold Voltage
(VDD=5V)
Ports 5, 6
Ports 5, 6
2.0
2.0
V
V
0.8
VIHT1
VILT1
VIHX1
VILX1
/RESET, TCC(Schmitt trigger)
V
V
V
V
Input Low Threshold Voltage
(VDD=5V)
/RESET, TCC(Schmitt trigger)
0.8
Clock Input High Voltage
(VDD=5V)
OSCI
OSCI
3.5
Clock Input Low Voltage
(VDD=5V)
1.5
0.4
VIH2
VIL2
Input High Voltage (VDD=3V)
Input Low Voltage (VDD=3V)
Input High Threshold Voltage
(VDD=3V)
Ports 5, 6
Ports 5, 6
1.5
1.5
V
V
VIHT2
VILT2
VIHX2
/RESET, TCC(Schmitt trigger)
/RESET, TCC(Schmitt trigger)
OSCI
V
V
V
Input Low Threshold Voltage
(VDD=3V)
0.4
0.9
Clock Input High Voltage
(VDD=3V)
2.1
Clock Input Low Voltage
(VDD=3V)
VILX2
VOH1
VOH1
VOL1
OSCI
V
V
V
V
Output High Voltage (Ports 5)
IOH = -12.0 mA
IOH = -12.0 mA
IOL = 12.0 mA
2.4
2.4
Output High Voltage (Ports 6)
(Schmitt trigger)
Output Low Voltage(Port5)
0.4
Product Specification (V1.0) 09.22.2005
• 33
(This specification is subject to change without further notice)
EM78P157N
8-Bit Microcontroller with OTP ROM
Symbol
Parameter
Condition
Min
Typ
Max Unit
Output Low Voltage (Ports 6)
(Schmitt trigger)
VOL1
IOL = 12.0 mA
0.4
–240
120
V
Pull-high active, input pin at
VSS
IPH
IPD
Pull-high current
Pull-down current
–50
25
–70
50
µA
µA
Pull-down active, input pin at
VDD
All input and I/O pins at VDD,
output pin floating, WDT
disabled
ISB1
ISB2
Power down current
Power down current
1
2
µA
µA
All input and I/O pins at VDD,
output pin floating, WDT
enabled
15
/RESET= 'High', Fosc=32KHz
(Crystal type,CLKS="0"),
output pin floating, WDT
disabled
Operating supply current
(VDD=3V)
at two cycles/four clocks
ICC1
ICC2
ICC3
ICC4
15
20
25
30
35
µA
µA
/RESET= 'High', Fosc=32KHz
(Crystal type,CLKS="0"),
output pin floating, WDT
enabled
Operating supply current
(VDD=3V)
at two cycles/four clocks
/RESET= 'High', Fosc=4MHz
(Crystal type, CLKS="0"),
output pin floating, WDT
enabled
Operating supply current
(VDD=5.0V)
at two cycles/two clocks
2.0
4.0
mA
mA
/RESET= 'High', Fosc=10MHz
(Crystal type, CLKS="0"),
output pin floating, WDT
enabled
Operating supply current
(VDD=5.0V)
at two cycles/four clocks
6.2 AC Electrical Characteristics
(Ta=25 °C, VDD=5V±5%, VSS=0V)
Symbol
Parameter
Conditions
Min
Typ
Max Unit
Dclk
Input CLK duty cycle
45
50
55
%
Crystal type
RC type
100
500
DC
DC
ns
ns
ns
ms
ns
ms
ns
ns
ns
Instruction cycle time
(CLKS="0")
Tins
Ttcc
TCC input period
(Tins+20)/N*
11.8
Tdrh
Trst
Device reset hold time
/RESET pulse width
Watchdog timer period
Input pin setup time
Input pin hold time
Output pin delay time
16.8
21.8
21.8
2000
Ta = 25°C
Ta = 25°C
Twdt
Tset
11.8
16.8
0
Thold
Tdelay
20
50
Cload=20pF
*N = selected prescaler ratio
34 •
Product Specification (V1.0) 09.22.2005
(This specification is subject to change without further notice)
EM78P157N
8-Bit Microcontroller with OTP ROM
6.3 Device Characteristics
The graphs provided in the following pages were derived based on a limited number of
samples and are shown herein for reference purposes only and are not guaranteed for
its accuracy. In some graphs, the data may be out of the specified warranted operating
range.
6.3.1 Port 6 Vih/Vil vs. VDD (Input Pin with Schmitt Inverter)
Vih/Vil (Input Pins with Schmitt Inverter)
2.5
Vih max (-40℃ to 85℃)
Vih typ 25℃
2
1.5
1
Vil max (-40℃ to 85℃)
0.5
Vil typ 25℃
0
2.5
3
3.5
4
4.5
5
5.5
VDD (Volt)
Fig. 6-1 Graph on Port 6 Vih/Vil vs. VDD
6.3.2 Port 5 Input Threshold Voltage (Vth) vs. VDD
Vth (Input Threshold Voltage) of I/O pins
2
Max(-40℃ to 85℃)
1.5
Typ 25℃
1
Min(-40℃ to 85℃)
0.5
0
2.5
3
3.5
4
4.5
5
5.5
VDD (Volt)
Fig. 6-2 Graph on Port 5 Input Threshold Voltage (Vth) vs. VDD
Product Specification (V1.0) 09.22.2005
• 35
(This specification is subject to change without further notice)
EM78P157N
8-Bit Microcontroller with OTP ROM
6.3.3 Ports 5 & Port 6 Voh vs. Ioh, VDD=5V and 3V
Voh/Ioh (5V)
Voh/Ioh (3V)
0
-2
0
-5
-4
-10
Min 85℃
Min 85℃
-6
-15
Typ 25℃
Typ 25℃
-8
-20
Max –40
Max –40
-10
-25
0
0.5
1
1.5
2
2.5
3
1.5
2
2.5
3
3.5
4
4.5
5
Voh (Volt)
Voh (Volt)
Fig. 6-3 Graph on Ports 5 & 6 Voh vs. Ioh, VDD=5V
Fig. 6-4 Graph on Ports 5 & 6 Voh vs. Ioh, VDD=3V
6.3.4 Ports 5 & Port 6 Vol vs. Iol, VDD=5V and 3V
Vol/Iol (5V)
Vol/Iol (3V)
45
100
90
80
70
60
50
40
30
20
10
0
Max -40
Max -40
40
35
30
25
20
15
10
5
Typ 25℃
Min 85℃
Typ 25℃
Min 85℃
0
0
0.5
1
1.5
2
2.5
3
0
0.5
1
1.5
2
2.5
3
Vol (Volt)
Vol (Volt)
Fig. 6-5 Graph on Ports 5 & 6 Vol vs. Ioh, VDD=5V
36 •
Fig. 6-6 Graph on Ports 5 & 6 Voh vs. Iol, VDD=3V
Product Specification (V1.0) 09.22.2005
(This specification is subject to change without further notice)
EM78P157N
8-Bit Microcontroller with OTP ROM
6.3.5 WDT Time Out Period vs. VDD (Prescaler Set to 1:1)
WDT Time out
45
40
35
30
25
20
15
10
5
Max 85℃
Max 70℃
Typ 25℃
Min 0℃
Min -40℃
0
2
3
4
5
6
VDD (Volt)
Fig. 6-7 Graph on WDT Time Out Period vs. VDD (Perscaler Set to 1:1)
Product Specification (V1.0) 09.22.2005
• 37
(This specification is subject to change without further notice)
EM78P157N
8-Bit Microcontroller with OTP ROM
6.3.6 Typical RC OSC Frequency vs. VDD
(Cext = 100pF, Temp. = 25℃)
Cext = 100pF, Typical RC Frequency vs. VDD
1.6
R = 3.3K
1.4
1.2
R = 5.1K
1
0.8
R = 10K
0.6
0.4
0.2
0
R = 100K
3
3.5
4
4.5
5
5.5
VDD (Volt)
Fig. 6-8 Graph on Typical RC OSC Frequency vs. VDD (Cext = 100pF, Temperature at 25℃)
6.3.7 Typical RC OSC Frequency vs. VDD
(with R and C under Ideal Conditions)
VDD = 5V
VDD = 3V
Fig. 6-9 Graph on Typical RC OSC Frequency vs. VDD (with R & C under Ideal Conditions)
38 •
Product Specification (V1.0) 09.22.2005
(This specification is subject to change without further notice)
EM78P157N
8-Bit Microcontroller with OTP ROM
6.3.8 Typical and Maximum Operating Current (ICC1/2/3/4) vs.
Temperature
The following four conditions exist with the Operating Current ICC1 to ICC4:
ICC1: VDD=3V, Fosc=32K Hz, 2 clocks, WDT disabled
ICC2: VDD=3V, Fosc=32K Hz, 2 clocks, WDT enabled
ICC3: VDD=5V, Fosc=4M Hz, 2 clocks, WDT enabled
ICC4: VDD=5V, Fosc=10M Hz, 2 clocks, WDT enabled
Typical ICC1 and ICC2 vs. Temperature
15
12
9
6
3
0
-40
-20
0
20
40
60
80
Temperature ( )
℃
Fig. 6-10 Graph on Typical Operating Current (ICC1 and ICC2) vs. Temperature
Maximum ICC1 and ICC2 vs. Temperature
21
18
15
12
9
6
-40
-20
0
20
40
60
80
Temperature ( )
℃
Fig. 6-11 Graph on Maximum Operating Current (ICC1 and ICC2) vs. Temperature
Product Specification (V1.0) 09.22.2005
• 39
(This specification is subject to change without further notice)
EM78P157N
8-Bit Microcontroller with OTP ROM
Typical ICC3 and ICC4 vs. Temperature
4
3.5
3
2.5
2
Typ ICC4
Typ ICC3
1.5
1
0.5
0
-40
-20
0
20
40
60
80
Temperature ( )
℃
Fig. 6-12 Graph on Typical Operating Current (ICC3 and ICC4) vs. Temperature
Maximum ICC3 and ICC4 vs. Temperature
4.5
Max ICC4
4
3.5
3
2.5
Max ICC3
2
1.5
1
-40
-20
0
20
40
60
80
Temperature ( )
℃
Fig. 6-13 Graph on Maximum Operating Current (ICC3 and ICC4) vs. Temperature
40 •
Product Specification (V1.0) 09.22.2005
(This specification is subject to change without further notice)
EM78P157N
8-Bit Microcontroller with OTP ROM
6.3.9 Typical and Maximum Standby Current (ISB1 and ISB2) vs.
Temperature
The following two conditions exist with the Standby Current ISB1 and ISB2:
ISB1: VDD=5V, WDT disabled
ISB2: VDD=5V, WDT enabled
Typical ISB1 and ISB2 vs. Temperature
12
10
8
Typ ISB2
6
4
Typ ISB1
2
0
-40
-20
0
20
40
60
80
Temperature ( )
℃
Fig. 6-14 Graph on Typical Standby Current (ISB1 and ISB2) vs. Temperature
Maximum ISB1 and ISB2 vs. Temperature
12
10
8
6
4
2
0
-40
-20
0
20
40
60
80
Temperature ( )
℃
Fig. 6-15 Graph on Maximum Standby Current (ISB1 and ISB2) vs. Temperature
Product Specification (V1.0) 09.22.2005
• 41
(This specification is subject to change without further notice)
EM78P157N
8-Bit Microcontroller with OTP ROM
6.3.10 Operating Voltage under Temperature Range of
0°C to 70°C and –40°C to 85°C
Fig. 6-16 Graph on Operating Voltage under Temperature Range of 0°C to 70°C
Fig. 6-17 Graph on Operating Voltage under Temperature Range of –40°C to 85°C
42 •
Product Specification (V1.0) 09.22.2005
(This specification is subject to change without further notice)
EM78P157N
8-Bit Microcontroller with OTP ROM
6.3.11 Operating Current Range (Based on High and
Low Freq. @ =25℃) vs. Voltage
EM78P157N HXT V-I
2.5
2.25
2
1.75
1.5
1.25
1
0.75
0.5
0.25
0
2.3
2.8
3.3
3.8
Voltage(V)
4.3
4.8
5.3
Fig. 34 Operating Current Range (Based on High Freq. @ =25℃) vs. Voltage
EM78P157N LXT V-I
40
35
30
25
20
15
10
5
0
2.3
2.8
3.3
3.8
4.3
4.8
5.3
Voltage(V)
Fig. 35 Operating Current Range (Based on Low Freq. @ =25℃) vs. Voltage
Product Specification (V1.0) 09.22.2005
• 43
(This specification is subject to change without further notice)
EM78P157N
8-Bit Microcontroller with OTP ROM
APPENDIX
A Package Types
OTP MCU
Package Type
DIP
Pin Count
Package Size
300 mil
EM78P157NBP
EM78P157NBM
EM78P157NAP
EM78P157NAM
EM78P157NAAS
EM78P157NAKM
14
14
18
18
20
20
SOP
DIP
150 mil
300 mil
SOP
SSOP
SSOP
300 mil
209 mil
209 mil
A.1 Package Detailed Information
A.1.1 14-Lead Plastic Dual in line (PDIP) — 300 Mil
44 •
Product Specification (V1.0) 09.22.2005
(This specification is subject to change without further notice)
EM78P157N
8-Bit Microcontroller with OTP ROM
A.1.2 14-Lead Plastic Small Outline (SOP) — 150 Mil
Product Specification (V1.0) 09.22.2005
• 45
(This specification is subject to change without further notice)
EM78P157N
8-Bit Microcontroller with OTP ROM
A.1.3 18-Lead Plastic Dual in Line (PDIP) — 300 Mil
46 •
Product Specification (V1.0) 09.22.2005
(This specification is subject to change without further notice)
EM78P157N
8-Bit Microcontroller with OTP ROM
A.1.4 18-Lead Plastic Small Outline (SOP) — 300 Mil
Product Specification (V1.0) 09.22.2005
• 47
(This specification is subject to change without further notice)
EM78P157N
8-Bit Microcontroller with OTP ROM
A.1.5 20-Lead Plastic Small Outline (SSOP) — 209 Mil
48 •
Product Specification (V1.0) 09.22.2005
(This specification is subject to change without further notice)
EM78P157N
8-Bit Microcontroller with OTP ROM
B Quality Assurance and Reliability
Test Category
Test Conditions
Remarks
Solder temperature=245±5℃，for 5 seconds up to the stopper
using a rosin-type flux
Solderability
For SMD IC(such as
SOP, QFP, SOJ, etc.)
Step1: TCT ，65℃(15mins)~150℃(15mins)，10 cycles
Step2: bake 125℃，TD(durance)=24 hrs
Step3:soak 30°C /60%，TD(durance)=192hrs
Pre-condition
Step4:IR flow 3cycles
(Pkg thickness≧2.5mm or Pkg volume≧350mm3 ----225±5℃)
(Pkg thickness≦2.5mm or Pkg volume≦350mm3 ----240±5℃)
–65℃(15mins)~150℃(15mins) , 200 cycles
Temperature cycle
test
Pressure cooker test
TA =121℃,RH=100%,pressure=2atm, TD(durance)= 96 Hrs
TA=85℃ , RH=85%，TD(durance)=168 ,500 Hrs
High temperature
/high humidity test
High-temperature
storage life
TA=150℃, TD(durance)=500,1000Hrs
High-temperature
operating life
TA=125 ℃ , VCC=Max. operating voltage, TD(durance)
=168,500,1000Hrs
Latch-up
TA=25℃, VCC=Max. operating voltage, 150mA/20V
TA=25℃, ≧∣±3KV∣
IP_ND,OP_ND,IO_ND
IP_NS,OP_NS,IO_NS
IP_PD,OP_PD,IO_PD,
IP_PS,OP_PS,IO_PS,
ESD(HBM)
ESD(MM)
TA=25℃, ≧∣±300V∣
VDD-VSS(+),VDD_V
SS(-)mode
Product Specification (V1.0) 09.22.2005
• 49
(This specification is subject to change without further notice)
EM78P157N
8-Bit Microcontroller with OTP ROM
C Address Trap Detect
An address trap detect is one of the fail-safe function that detects CPU malfunction
caused by noise or the like. If the CPU attempts to fetch an instruction from a part of
RAM, an internal recovery circuit will auto started. Until CPU got the correct function, it
will execute the next program that follows.
Vdd
Tvr
/Reset
Tvd
Internal POR
Tpor
Power on
Reset
Symbol
Tpor
Tvd
Parameter
Condition
Min.
Typ.
Max.
22
Unit
ms
us
Power on reset time
Vdd Voltage drop time
Vdd Voltage rise time
10.5
16.8
Vdd = 5V, -40℃ to 85℃
Vdd = 5V, -40℃ to 85℃
Vdd = 5V, -40℃ to 85℃
-
-
-
-
1*
Tvr
us
1**
* Tvd is the period of Vdd voltage less than POR voltage 1.9 volts.
** Tvr is the period of Vdd voltage higher than 5.5 volts.
50 •
Product Specification (V1.0) 09.22.2005
(This specification is subject to change without further notice)
相关型号：
EM78P173N
8-Bit Microcontroller with OTP ROM，台湾义隆8bit单片机EM78P173N--EM78P153S/EM78P153AB工业级版本 EM78P173N是一个采用低功耗、高速CMOS工艺制造的8位单片机，,其内部具有1K* 13位一次性可编程只读内存（OTP - ROM）,用户通过仿真器编写和调试正确的机器码文件通过编程器烧录进芯片,提供了一个保护位，以防止用户OTP存储器代码时的侵扰。同时有密码保护位防止程序数据读出. 可代客户开发，烧录。专业软件工程师设计指导，提供整套技术支持及疑难解答！ 深圳市美力科电子有限公司 业务部 手机： 13684932947 QQ：981734760 地 址：深圳市福田区彩田南路彩天名苑红荔轩10D 电 话：0755-82965828,82965533,82965118,82965566 传 真：0755-82964700 http://www.mlkdz.com E-mail:mlk_wqy@126.com
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