EM78F734NSO18 [ELAN]
8-Bit Microcontroller;
| 型号： | EM78F734NSO18 |
| 厂家： | 
ELAN MICROELECTRONICS CORP |
| 描述： | 8-Bit Microcontroller 微控制器 |
| 文件： | 总100页 (文件大小：3949K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EM78F734N
8-Bit
Microcontroller
Product
Specification
DOC. VERSION 1.4
ELAN MICROELECTRONICS CORP.
September 2019
Trademark Acknowledgments:
IBM is a registered trademark and PS/2 is a trademark of IBM.
Windows is a trademark of Microsoft Corporation.
ELAN and ELAN logo
are trademarks of ELAN Microelectronics Corporation.
Copyright © 2019 by ELAN Microelectronics Corporation
All Rights Reserved
Printed in Taiwan
The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no
responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics
makes no commitment to update, or to keep current the information and material contained in this specification.
Such information and material may change to conform to each confirmed order.
In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or
other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall
not be liable for direct, indirect, special incidental, or consequential damages arising from the use of such
information or material.
The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and
may be used or copied only in accordance with the terms of such agreement.
ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of
ELAN Microelectronics product in such applications is not supported and is prohibited.
NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY
ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS.
ELAN MICROELECTRONICS CORPORATION
Headquarters:
Hong Kong:
USA:
No. 12, Innovation Road 1
Hsinchu Science Park
Hsinchu, TAIWAN 308
Tel: +886 3 563-9977
Fax: +886 3 563-9966
webmaster@emc.com.tw
http://www.emc.com.tw
Elan (HK) Microelectronics
Corporation, Ltd.
Flat A, 19F., World Tech Centre
95 How Ming Street, Kwun Tong
Kowloon, HONG KONG
Tel: +852 2723-3376
Elan Information
Technology Group (U.S.A.)
PO Box 601
Cupertino, CA 95015
U.S.A.
Tel: +1 408 366-8225
Fax: +1 408 366-8225
Fax: +852 2723-7780
Shenzhen:
Shanghai:
Elan Microelectronics
Shenzhen, Ltd.
Elan Microelectronics
Shanghai, Ltd.
8A Floor, Microprofit Building
Gaoxin South Road 6
6F, Ke Yuan Building
No. 5 Bibo Road
Shenzhen Hi-tech Industrial Park
South Area, Shenzhen
CHINA 518057
Tel: +86 755 2601-0565
Fax: +86 755 2601-0500
elan-sz@elanic.com.cn
Zhangjiang Hi-Tech Park
Shanghai, CHINA 201203
Tel: +86 21 5080-3866
Fax: +86 21 5080-0273
elan-sh@elanic.com.cn
Contents
Contents
1 General Description··············································································1
2 Features ······························································································1
3 Pin Assignment····················································································3
4 Pin Description·····················································································5
5 Block Diagram······················································································7
6 Functional Description··········································································8
6.1 Operational Registers .......................................................................................8
6.1.1 R0 (Indirect Addressing Register) .......................................................................8
6.1.2 R1 (Timer Clock/Counter) ...................................................................................8
6.1.3 R2 (Program Counter) and Stack........................................................................8
6.1.4 R3 (Status Register)..........................................................................................11
6.1.5 R4 (RAM Select Register).................................................................................11
6.1.6 Bank 0 R5 ~ R8 (Port 5 ~ Port 8)......................................................................11
6.1.7 Bank 0 R9 TBPTL (Low byte of Table Pointer Register) ...................................11
6.1.8 Bank 0 RA (Wake- up Control Register) ...........................................................12
6.1.9 Bank 0 RB (EEPROM Control Register)...........................................................12
6.1.10 Bank 0 RC (EEPROM Address)........................................................................13
6.1.11 Bank 0 RD (EEPROM Data) .............................................................................13
6.1.12 Bank 0 RE (CPU Operating Control Register) ..................................................13
6.1.13 Bank 0 RF (Interrupt Status Register)...............................................................14
6.1.14 R10 ~ R3F.........................................................................................................15
6.1.15 Bank 1 R5 TC1CR (Timer 1 Control) ................................................................15
6.1.16 Bank 1 R6 TC1DA (Timer 1 Data Buffer A).......................................................18
6.1.17 Bank 1 R7 TC1DB (Timer 1 Data Buffer B).......................................................18
6.1.18 Bank 1 R8 OSCR (Oscillator Control)...............................................................18
6.1.19 Bank 1 R9 TC2DA (Timer 2 Data Buffer A).......................................................19
6.1.20 Bank 1 RA TC2DB (Timer 2 Data Buffer B) ......................................................19
6.1.21 Bank 1 RB ~RE .................................................................................................19
6.1.22 Bank 1 RF (Interrupt Status Register)...............................................................19
6.1.23 Bank 2 R5 AISR (ADC Input Select Register)...................................................20
6.1.24 Bank 2 R6 ADCON (A/D Control Register) .......................................................21
6.1.25 Bank 2 R7 ADOC (A/D Offset Calibration Register) .........................................22
6.1.26 Bank 2 R8 ADDH (AD High 8-Bit Data Buffer)..................................................22
6.1.27 Bank 2 R9 ADDL (AD Low 4-Bit Data Buffer) ...................................................22
6.1.28 Bank 2 RA ~ RE ................................................................................................23
6.1.29 Bank 2 RF (Pull-high Control Register 1)..........................................................23
6.1.30 Bank 3 R5..........................................................................................................23
6.1.31 Bank 3 R6 TBPTH (High Byte of Table Pointer Register) .................................23
Product Specification (V1.4) 09.05.2019
iii
Contents
6.1.32 Bank 3 R7~RC ..................................................................................................23
6.1.33 Bank 3 RD TC3CR (Timer 3 Control)................................................................23
6.1.34 Bank 3 RE TC3D (Timer 3 Data Buffer)............................................................26
6.1.35 Bank 3 RF (Pull-down Control Register 1)........................................................26
6.2 Special Function Registers .............................................................................27
6.2.1 A (Accumulator).................................................................................................27
6.2.2 CONT (Control Register)...................................................................................27
6.2.3 IOC5 ~ IOC8 (I/O Port Control Register) ..........................................................28
6.2.4 IOC9 ..................................................................................................................28
6.2.5 IOCA (WDT Control Register) ...........................................................................28
6.2.6 IOCB (Pull-down Control Register 2) ................................................................29
6.2.7 IOCC (Open-drain Control Register).................................................................29
6.2.8 IOCD (Pull-high Control Register 2)..................................................................29
6.2.9 IOCE (Interrupt Mask Register 2)......................................................................30
6.2.10 IOCF (Interrupt Mask Register 1)......................................................................30
6.3 TCC/WDT and Prescaler ................................................................................32
6.4 I/O Ports .........................................................................................................33
6.5 Reset and Wake-up ........................................................................................36
6.5.1 Reset .................................................................................................................36
6.5.2 Summary of Wake-up and Interrupt Modes Operation .....................................38
6.5.3 Summary of Register Initial Values ...................................................................39
6.5.4 Status of RST, T, and P of the Status Register .................................................44
6.6 Interrupt ..........................................................................................................45
6.7 Data EEPROM................................................................................................47
6.7.1 Data EEPROM Control Register.......................................................................47
6.7.1.1 RB (EEPROM Control Register) .........................................................................47
6.7.1.2 RC (128 Bytes EEPROM Address) .....................................................................48
6.7.1.3 RD (256 Bytes EEPROM Data)...........................................................................48
6.7.2 Programming Step / Example Demonstration...................................................48
6.7.2.1 Programming Step ..............................................................................................48
6.7.2.2 Example Demonstration Programs .....................................................................49
6.8 Analog-to-Digital Converter (ADC)..................................................................49
6.8.1 ADC Control Register (AISR/R5, ADCON/R6, ADOC/R7)................................50
6.8.2 Bank 2 R5 AISR (ADC Input Select Register)...................................................50
6.8.3 Bank 2 R6 ADCON (A/D Control Register) .......................................................51
6.8.4 Bank 2 R7 ADOC (A/D Offset Calibration Register) .........................................52
6.8.5 ADC Data Buffer (ADDH, ADDL/R8, R9) ..........................................................52
6.8.6 A/D Sampling Time............................................................................................52
6.8.7 A/D Conversion Time ........................................................................................53
6.8.8 A/D Operation during Sleep Mode ....................................................................53
6.8.9 Programming Steps/Considerations .................................................................54
6.8.9.1 Programming Steps ............................................................................................54
6.8.9.2 Sample Demonstration Programs .......................................................................54
6.9 Timer/Counter 1..............................................................................................56
6.10 Timer/Counter 3..............................................................................................58
iv
Product Specification (V1.4) 09.05.2019
Contents
6.11 Oscillator.........................................................................................................60
6.11.1 Oscillator Modes................................................................................................60
6.11.2 Crystal Oscillator/Ceramic Resonators (Crystal) ..............................................61
6.11.3 Internal RC Oscillator Mode ..............................................................................63
6.12 Code Option Register .....................................................................................64
6.12.1 Code Option Register (Word 0).........................................................................64
6.12.2 Code Option Register (Word 1).........................................................................66
6.12.3 Code Option Register (Word 2).........................................................................67
6.13 Power-on Considerations................................................................................68
6.14 External Power-on Reset Circuit.....................................................................68
6.15 Residue-Voltage Protection.............................................................................69
6.16 Instruction Set.................................................................................................70
7 Timing Diagrams ················································································ 73
8 Absolute Maximum Ratings ································································· 74
9 DC Electrical Characteristics ······························································· 75
9.1 Data EEPROM Electrical Characteristics........................................................77
9.2 Program Flash Memory Electrical Characteristics...........................................77
9.3 A/D Converter Characteristics.........................................................................78
10 AC Electrical Characteristics ······························································· 79
APPANDIX
A Ordering and Manufacturing Information··············································· 80
B Package Type····················································································· 81
C Package Information··········································································· 82
C.1 EM78F734ND16 300mil..................................................................................82
C.2 EM78F734NSO16 300mil...............................................................................83
C.3 EM78F734NSO16A 150mil.............................................................................84
C.4 EM78F734NSS16 150mil ...............................................................................85
C.5 EM78F734ND18 300mil..................................................................................86
C.6 EM78F734NSO18 300mil...............................................................................87
C.7 EM78F734ND20 300mil..................................................................................88
C.8 EM78F734NSO20 300mil...............................................................................89
C.9 EM78F734NSS20 209mil ...............................................................................90
C.10 EM78F734NSS20A 150mil .............................................................................91
C.11 EM78F734NQN20 4*4*0.8mm........................................................................92
D Quality Assurance and Reliability························································· 93
D.1 Address Trap Detect.......................................................................................93
Product Specification (V1.4) 09.05.2019
v
Contents
Specification Revision History
Doc. Version
Revision Description
Date
1.0
Initial version
2014/05/13
1. Added Channel ADC6 to ADC
2. Added package SSOP20
1.1
3. Modified TC1CR, TC2DA and TC2DB description.
4. Modified SSOP16 package type.
5.Added SOP16 150mil package type.
2015/08/10
1. Add User Application Notice
2. Added Word 0 Bit 12 HLP description.
1.2
2016/03/31
3. Added Appendix A “Ordering and Manufacturing
Information”
1.3
1.4
1. Added QFN20 package type.
2017/07/18
2019/09/05
1. Added SSOP20 150mil package type.
User Application Note
(Before using this chip, take a look at the following description note, it includes important messages.)
1.
2.
3.
The internal TCC will stop running when in sleep mode. However, during AD conversion, when
TCC is set to “SLEP” instruction, if the ADWE bit of the RE register is enabled, the TCC will
keep on running.
During ADC conversion, do not perform output instruction to maintain precision for all of the
pins. In order to obtain accurate values, it is necessary to avoid any data transition on I/O pins
during AD conversion
The noise rejection function is turned off in the Fs and sleep mode
vi
Product Specification (V1.4) 09.05.2019
EM78F734N
8-Bit Microcontroller
1 General Description
The EM78F734N is an 8-bit microprocessor designed and developed with low-power, high-speed CMOS technology
and high noise immunity. It has an on-chip 4K13-bit Electrical Flash Memory and 1288-bit In-system programmable
EEPROM. It provides three protection bits to prevent intrusion of user’s Flash memory code.
With its enhanced Flash-ROM feature, the EM78F734N provides a convenient way of developing and verifying user’s
programs. Moreover, this Flash-ROM device offers the advantages of easy and effective program updates, using
development and programming tools. Users can avail of the ELAN Writer to easily program their development codes.
2 Features
CPU Configuration
Eight available interrupts:
4K13 bits Flash memory
Internal interrupt: 4
External interrupt: 4
1448 bits on-chip registers (SRAM)
128 bytes In-system programmable EEPROM
8-level stacks for subroutine nesting
Eight channels Analog-to-Digital Converter with
12-bit resolution
Peripheral Configuration
I/O Port Configuration
8-bit real Timer Clock/Counter (TCC) with
selective signal sources, trigger edges, and
overflow interrupt
Three bidirectional I/O ports
Wake-up port : P6
12 Programmable pull-down I/O pins
8 programmable pull-high I/O pins
4 programmable open-drain I/O pins
External interrupt : P60
Power down (Sleep) mode
Four programmable Level Voltage Reset (LVR)
(LVR) : 3.3V, 3.0V, 2.6V, and 2.0V (POR)
Three security registers to prevent intrusion of
Flash memory codes
Operating Voltage Range:
2.2V~5.5V @ – 40°C ~85°C (Industrial)
2.2V~5.5V @ 0°C ~70°C (Commercial)
One configuration register to accommodate
user’s requirements
Operating frequency range (base on two clocks):
IRC Drift Rate (Vdd @ 3.3V)
Drift Rate
Two clocks per instruction cycle
High EFT immunity
Internal RC
Frequency
Two sub-frequencies; 128kHz and 16kHz,
the 16kHz is provided by dividing the 128kHz
Temperature
(-10°C+40°C)
Process
Total
Single instruction cycle commands
Four Crystal Range in Oscillator Mode
455kHz
1 MHz
4 MHz
8 MHz
±1%
±1%
±1%
±1%
±1%
±1%
±1%
±1%
±2%
±2%
±2%
±2%
Crystal Range
20 MHz ~ 12 MHz
12 MHz~6 MHz
6 MHz ~ 1 MHz
1 MHz ~ 100kHz
Oscillator Mode
HXT2
HXT1
XT
IRC Drift Rate (Temperature: -10°C+40°C)
Drift Rate
Internal RC
Frequency
LXT1
Voltage
(3.0~3.6V)
Process
Total
Programmable free running Watchdog Timer
Package Type:
455kHz
1 MHz
4 MHz
8 MHz
±1%
±1%
±1%
±1%
±1%
±1%
±1%
±1%
±2%
±2%
±2%
±2%
16-pin DIP 300mil
16-pin SOP 300mil
16-pin SOP 150mil
:
:
:
EM78F734ND16
EM78F734NSO16
EM78F734NSO16A
EM78F734NSS16
EM78F734ND18
EM78F734NSO18
EM78F734ND20
EM78F734NSO20
EM78F734NSS20
EM78F734NSS20A
EM78F734NQN20
16-pin SSOP 150mil :
One 16-bit Timer/Counter
TC1 : Timer/Counter/Capture
One 8-bit Timer/Counter
18-pin DIP 300mil
18-pin SOP 300mil
20-pin DIP 300 mil
20-pin SOP 300mil
:
:
:
:
TC3 : Timer/Counter/PDO (Programmable
Divider Output) / PWM (Pulse Width
Modulation)
20-pin SSOP 209mil :
20-pin SSOP 150mil :
20-pin QFN
:
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
1
EM78F734N
8-Bit Microcontroller
Note: These are Green Products which do not contain
hazardous substances.
2
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
EM78F734N
8-Bit Microcontroller
3 Pin Assignment
P52
P51
1
2
3
4
5
6
7
8
9
18
17
P52
P51
1
2
3
4
5
6
7
8
16
15
P53
P50/VREF
P55/OSCO
P53
P50/VREF
P55/OSCO
E
E
M
M
P77/TCC/AD5
7
16
15
14
13
12
11
10
P77/TCC/AD5
14
13
12
11
10
9
8
7
8
F
F
7
P83//RESET(RESET)
VSS(VSS)
P54/OSCI/RCOUT
VDD(VDD)
P70(DATA)
P71(CLK)
P72
7
3
P83//RESET(RESET)
VSS(VSS)
P54/OSCI/RCOUT
VDD(VDD)
P70(DATA)
P71(CLK)
3
4
4
N
N
-
-
1
1
6
8
P
P60/AD0//INT
P61/AD1
P
i
i
n
P60/AD0//INT
P61/AD1
n
P62/AD2
P62/AD2
P72
P73/AD4
P63/AD3
Figure 3-1 EM78F734ND16/SO16/SO16A/SS16
Figure 3-2 EM78F734ND18/SO18
1
2
3
4
5
6
7
8
9
20
19
P57/TC3/AD7
P51
P60/AD0//INT
P61/AD1
1
2
20
19
18
17
16
15
14
13
12
11
VSS(VSS)
P83//RESET(RESET)
P77/TCC/AD5
P53
P74/TC1/AD6
P52
P62/AD2
3
18
17
16
15
14
13
12
11
P53
P50/VREF
P55/OSCO
E
M
7
P63/AD3
4
P77/TCC/AD5
8
F
7
P73/AD4
5
P52
3
P83//RESET(RESET)
VSS(VSS)
P54/OSCI/RCOUT
VDD(VDD)
P70(DATA)
P71(CLK)
P72
4
N
P72
6
P74/TC1/AD6
P57/TC3/AD7
P50/VREF
P55/OSCO
VDD(VDD)
-
2
0
P
P71(CLK)
P70(DATA)
P51
7
i
n
P60/AD0//INT
P61/AD1
8
9
P62/AD2
P54/OSCI/RCOUT
10
10
P73/AD4
P63/AD3
Figure 3-4 EM78F734NSS20A
Figure 3-3 EM78F734ND20/SO20/SS20
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
3
EM78F734N
8-Bit Microcontroller
20 19 18 17 16
P74/TC1
P52
1
2
3
4
5
15
14
VDD(VDD)
P70(DATA)
P71(CLK)
P72
P53
EM78F734N-20Pin 13
P77/TCC/AD5
P83//RESET(RESET)
12
11
P73/AD4
6
7
8
9
10
Figure 3-5 EM78F734NQ20
4
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
EM78F734N
8-Bit Microcontroller
4 Pin Description
Table 1 EM78F734N Pin Description
Legend:
CMOS:
ST: Schmitt Trigger input
CMOS output
AN: analog pin
XTAL: Oscillation pin for crystal / resonator
Input Output
Name
Function
Description
Type
Type
P50
ST
AN
CMOS
Bidirectional I/O pin with programmable pull-down
ADC external voltage reference
P50/VREF
VREF
P51
P51
P52
P53
ST
CMOS
CMOS
CMOS
CMOS
Bidirectional I/O pin with programmable pull-down
Bidirectional I/O pin with programmable pull-down
Bidirectional I/O pin with programmable pull-down
Bidirectional I/O pin
P52
ST
P53
ST
P54
ST
XTAL
OSCI
External clock crystal resonator oscillator input pin
P54/OSCI/RCOUT
P55/OSCO
Clock output of internal RC oscillator
RCOUT
CMOS
Clock output of external RC oscillator (open-drain)
P55
ST
CMOS
XTAL
Bidirectional I/O pin
OSCO
P57
Clock output from crystal oscillator
Bidirectional I/O pin
ST
CMOS
Timer 3 input (Counter/Capture/Window)
TC3
ST
P57/TC3/AD7
Timer 3 output (PDO/PWM/Buzzer)
PDO
AD7
CMOS
Programmable divider output
ADC Input 7
AN
Bidirectional I/O pin with programmable pull-down,
pull-high, open-drain, and pin change wake-up
P60
ST
CMOS
P60/AD0//INT
P61/AD1
AD0
/INT
AN
ST
ADC Input 0
External interrupt pin
Bidirectional I/O pin with programmable pull-down,
pull-high, open-drain, and pin change wake-up
P61
AD1
ST
AN
CMOS
ADC Input 1
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
5
EM78F734N
8-Bit Microcontroller
(Continuation)
Input Output
Name
Function
Description
Type
Type
Bidirectional I/O pin with programmable pull-down,
pull-high, open-drain, and pin change wake-up
P62
AD2
P63
ST
AN
ST
CMOS
P62/AD2
P63/AD3
ADC Input 2
Bidirectional I/O pin with programmable pull-down,
pull-high, open-drain, and pin change wake-up
CMOS
AD3
P70
AN
ST
ADC Input 3
CMOS
CMOS
CMOS
Bidirectional I/O pin, pull-high
DATA pin for Writer programming
Bidirectional I/O pin, pull-high
CLOCK pin for Writer programming
Bidirectional I/O pin, pull-high
Bidirectional I/O pin, pull-high
ADC Input 4
P70
(DATA)
(DATA)
P71
ST
ST
P71
(CLK)
(CLK)
P72
ST
P72
ST
CMOS
CMOS
P73
ST
P73/AD4
AD4
AN
P74
ST
CMOS
Bidirectional I/O pin
P74/TC1/AD6
P77/TCC/AD5
TC1
ST
Timer 1 input (Counter/Capture)
ADC Input 6
AD6
AN
P77
ST
CMOS
Bidirectional I/O pin
TCC
ST
Real Time Clock/Counter clock input
ADC Input 5
AD5
AN
P83
ST
CMOS
Bidirectional I/O pin
P83//RESET
(/RESET)
/RESET
(/RESET)
VDD
VDD
VSS
ST
Internal pull-high reset pin
/RESET pin for Writer programming
Power
ST
Power
Power
Power
Power
VDD
(VDD)
VDD for Writer programming
Ground
VSS
(VSS)
VSS
VSS for Writer programming
6
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
EM78F734N
8-Bit Microcontroller
5 Block Diagram
Sub
IRC
WDT
ROM
PC
IRC
Reset
TCC
TC1
TCC
TC1
TC3
8 level
stack
Oscillator generator
P8
Instruction
register
TC3
P83
LVR
P7
Crystal
ADC
0~7
Instruction
decoder
P77
P74
P73
P72
P71
P70
ADC
EEPROM
Interrupt
control reg.
MUX
RAM
ALU
P6
R4
P63
P62
P61
P60
Interrupt
circuit
P5
P57
P55
P54
P53
P52
P51
P50
ACC
Status reg.
Ext INT
Figure 5-1 EM78F734N Functional Block Diagram
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
7
EM78F734N
8-Bit Microcontroller
6 Functional Description
6.1 Operational Registers
6.1.1 R0 (Indirect Addressing Register)
R0 is not a physically implemented register. It is used as an indirect addressing
pointer. Any instruction using R0 as a pointer actually accesses data pointed by the
RAM Select Register (R4).
6.1.2 R1 (Timer Clock/Counter)
R1 is incremented by an external signal edge, which is defined by TE bit (CONT-4)
through the TCC pin, or by the instruction cycle clock. It is writable and readable as
any other registers. It is defined by resetting PSTE (CONT-3).
The prescaler is assigned to TCC, if the PSTE bit (CONT-3) is reset. The contents of
the prescaler counter are cleared only when the TCC register is written with a value.
6.1.3 R2 (Program Counter) and Stack
Depending on the device type, R2 and hardware stack are 10-bit wide. The structure
is depicted in Figure 6-1.
The configuration structure generates 4K13 bits on-chip Flash ROM addresses to
the relative programming instruction codes. One program page is 1024 words long.
R2 is set as all “0”s when under a reset condition.
“JMP” instruction allows direct loading of the lower 10 program counter bits. Thus,
“JMP” allows PC to go to any location within a page (1K).
“CALL” instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into
the stack. Thus, the subroutine entry address can be located anywhere within a
page.
“LJMP” instruction allows direct loading of the program counter bits (A0~A11). Thus,
“LJMP” allows the PC to go to any location within 4K (212).
“LCALL” instruction loads the program counter bits (A0~A11), and PC+1 are pushed
onto the stack. Thus, the subroutine entry address can be located anywhere within
4K (212).
“RET” (“RETL k”, “RETI”) instruction loads the program counter with the contents of
the top-level stack.
“ADD R2, A” allows a relative address to be added to the current PC, and the ninth
and above bits of the PC will increase progressively.
8
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
EM78F734N
8-Bit Microcontroller
“MOV R2, A” allows loading an address from the “A” register to the lower 8 bits of the
PC, and the ninth and tenth bits of the PC remain unchanged.
Any instruction except “ADD R2,A” that is written to R2 (e.g. “MOV R2, A”, “BC R2, 6”)
will cause the ninth bit and the tenth bit (A8~A9) of the PC to remain unchanged.
All instructions are single instruction cycle (fclk/2) except for the instructions that
would change the contents of R2 and “LCALL”, “LJMP”, “TBRD” instruction. The
“LCALL”, “LJMP” and “TBRD” instructions need two instruction cycles.
A11 A10 A9 A8 A7
~
A0
PC
0000h
0003h
0006h
0009h
Reset vector
CALL
LCALL
RET
RETL
RETI
00 : PAGE0 0000~03FF
External INT pin interrupt vector
Port 6 pin status change interrupt vector
TCC overfolw
Store ACC, R3, R4
01 : PAGE1 0400~07FF
10 : PAGE2 0800~0BFF
11 : PAGE3 0C00~0FFF
Stack Level 1
0018h
0027h
0030h
Stack Level 2
Stack Level 3
Stack Level 4
Stack Level 5
Stack Level 6
Stack Level 7
Stack Level 8
TC1 interrupt vector
TC3 interrupt vector
AD interrupt vector
On-Chip Program memory
0FFFh
Figure 6-1 Program Counter Organization
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
9
EM78F734N
8-Bit Microcontroller
Register
Bank 0
Register
Bank 1
Register
Bank 2
Register
Bank 3
Control
Register
Address
R1 (TCC Buffer )
R2 (PC)
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
R3 (STATUS)
R4(7,6)
(0,1)
(1,0)
(1,1)
R4 (RSR,bank select)
R5 (Port 5 /IO data)
R6 (Port 6 I/O data)
R7 (Port 7 I/O data)
R8 (Port 8 I/O data)
R5 (ADC Input Select
Register)
R5 (Timer 1 Control)
R6 (Timer 1 data Buffer A)
R7 (Timer 1 data Buffer B)
R8 (Oscillator Control )
R5 (Reserve)
IOC5 (Port 5 I/O control)
IOC6 (Port 6 I/O control)
IOC7 (Port 7 I/O control)
IOC8(Port 8 I/O control)
IOC9 (Reserved)
R6 (ADC Control
Register)
R6 (TBHP: Table Point
Register)
R7 (ADC Offset
Calibration Register )
R7 (Reserve)
R8 (AD high 8-bits
data buffer)
R8 (Reserve)
R9 (Reserve)
R9 (TBLP: Table Point
Register)
R9 (AD low 4-bits
data buffer)
R9 (Timer 2 Data Buffer A)
RA (Wake control
Register)
RA (Reserve)
RA (Reserve)
IOCA (WDT control)
RA (Timer 2 Data Buffer B)
RB (Reserve)
RB (EEPROM control
Register)
RB (Reserve)
IOCB (Pull Down Control 2)
RB (Reserve)
RC (Reserve)
RD (Reserve)
RC (EEPROM address
Register)
IOCC (Open Drain
Control 1)
RC (Reserve)
RD (Reserve)
RE (Reserve)
RC (Reserve)
RD (EEPROM data
Register)
IOCD (Pull High Control 2)
IOCE (Interrupt Mask 2)
IOCF (Interrupt Mask 1)
RD (Timer 3 Control)
RE (Timer 3 data buffer)
RE (Mode Select
Register)
RE (Reserve)
RF (Interrupt Status
Flag 1)
RF (Interrupt Status
Flag 2)
RF (Pull High Control 1)
RF (Pull Down Control 1)
10
:
1F
16-Byte Common Register
20
:
3F
Bank 0
32x8
Bank 1
32x8
Bank 2
32x8
Bank 3
32x8
Figure 6-2 Data Memory Configuration
10
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
EM78F734N
8-Bit Microcontroller
6.1.4 R3 (Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
T
P
Z
DC
C
Bits 7 ~ 5: Not used, set to “0” at all time
Bit 4 (T): Time-out bit
Set to “1” with the “SLEP” and “WDTC” commands, or during power up and
reset to “0” by WDT time-out.
Bit 3 (P): Power down bit
Set to “1” during power on or by a “WDTC” command and reset to “0” by a
“SLEP” command.
Bit 2 (Z): Zero flag
Set to “1” if the result of an arithmetic or logic operation is zero.
Bit 1 (DC): Auxiliary carry flag
Bit 0 (C): Carry flag
6.1.5 R4 (RAM Select Register)
Bits 7 ~ 6: Used to select Bank 0 ~ Bank 3
Bits 5 ~ 0: Used to select registers (Address: 00~3F) in indirect addressing mode.
See the data memory configuration in Figure 6-2.
6.1.6 Bank 0 R5 ~ R8 (Port 5 ~ Port 8)
R5 ~ R7 are I/O registers.
6.1.7 Bank 0 R9 TBPTL (Low byte of Table Pointer Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RBit 7
RBit 6
RBit 5
RBit 4
RBit 3
RBit 2
RBit 1
RBit 0
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
11
EM78F734N
8-Bit Microcontroller
6.1.8 Bank 0 RA (Wake- up Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
ICWE
ADWE
EXWE
-
-
Bit 7: Not used, set to “0” at all time
Bit 6 (ICWE): Port 6 input status change wake-up enable bit
0 : Disable Port 6 input status change wake-up
1 : Enable Port 6 input status change wake-up
Bit 5 (ADWE): ADC wake-up enable bit
0 : Disable ADC wake-up
1 : Enable ADC wake-up
When ADC completed status is used to enter the interrupt vector or to wake
up the EM78F734N from sleep, with A/D conversion running, the ADWE bit
must be set to “Enable“.
Bit 4 (EXWE): External wake-up enable bit
0 : Disable External /INT pin wake-up
1 : Enable External /INT pin wake-up
Bits 3 ~ 0: Not used, set to “0” at all time
6.1.9 Bank 0 RB (EEPROM Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RD
WR
EEWE
EEDF
EEPC
-
-
-
Bit 7 (RD): Read control register
0 : Does not execute EEPROM read
1 : Read EEPROM content, (RD can be set by software, RD is cleared by
hardware after Read instruction is completed)
Bit 6 (WR): Write control register
0 : Write cycle to the EEPROM is completed.
1 : Initiate a write cycle, (WR can be set by software, WR is cleared by
hardware after Write cycle is completed)
Bit 5 (EEWE): EEPROM Write Enable bit.
0 : Prohibit write to the EEPROM
1 : Allows EEPROM write cycles
Bit 4 (EEDF): EEPROM Detective Flag
12
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
EM78F734N
8-Bit Microcontroller
0 : Write cycle is completed
1 : Write cycle is unfinished
Bit 3 (EEPC): EEPROM power-down control bit
0 : Switch off the EEPROM
1 : EEPROM is operating
Bits 2 ~ 0: Not used, set to “0” at all time
6.1.10 Bank 0 RC (EEPROM Address)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
EE_A6
EE_A5
EE_A4
EE_A3
EE_A2
EE_A1
EE_A0
Bits 6 ~ 0: EEPROM address
6.1.11 Bank 0 RD (EEPROM Data)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EE_D7
EE_D6
EE_D5
EE_D4
EE_D3
EE_D2
EE_D1
EE_D0
Bits 7 ~ 0: EEPROM data
6.1.12 Bank 0 RE (CPU Operating Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
TIMERSC
CPUS
IDLE-
-
Bit 7:
Not used, set to “0” at all time
Bit 6 (TIMERSC): TCC, TC1, TC3 clock source select
0 : Fs. Fs: sub frequency for WDT internal RC time base
1 : Fm. Fm: main-oscillator clock
CPU Oscillator Source Select
Bit 5 (CPUS):
0 = Sub-oscillator (fs)
1 = Main oscillator (fosc)
When CPUS=0, the CPU oscillator selects a sub-oscillator and the
main oscillator is stopped.
Bit 4 (IDLE):
Idle Mode Enable Bit. This bit determines the Idle mode status
under SLEP instruction.
0 : IDLE=”0”+SLEP instruction Sleep mode
1 : IDLE=”1”+SLEP instruction Idle mode
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
13
EM78F734N
8-Bit Microcontroller
CPU Operation Mode
RESET
Normal mode
Fm : oscillation
Fs : oscillation
CPU : using Fm
wakeup
wakeup
IDLE = 0
+ SLEP
IDLE = 1
+ SLEP
CPUS = 1
CPUS = 0
IDLE = 1
+ SLEP
(*)
wakeup
Sleep mode
Fm : stop
Fs : stop
Green mode
Fm : stop
Fs : oscillation
Idle mode
Fm : stop
Fs : oscillation
CPU : stop
CPU : using Fs
CPU : stop
wakeup
IDLE = 0
+ SLEP
(*) only as WDT IRC is Fs.
If watchdog function is enabled before into sleep mode, Fs does not stop.
Therefore, some circuits like timer/counter (Its clock source is Fs) must be disable
before into sleep mode especially as corresponding interrupt is enabled.
Figure 6-3 CPU Operation Mode
Bits 3 ~ 0: Not used, set to “0” at all time
6.1.13 Bank 0 RF (Interrupt Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADIF
-
-
-
EXIF
ICIF
TCIF
Note: “ 1 ” means with interrupt request
“ 0 ” means no interrupt occurs
Bit 7:
Not used, set to “0” at all time
Bit 6 (ADIF):
Interrupt flag for analog to digital conversion. Set when AD
conversion is completed, reset by software.
Bits 5 ~ 3:
Not used, set to “0” at all time
Bit 2 (EXIF):
External interrupt flag. Set by a falling edge on /INT pin, reset by
software.
Bit 1 (IC IF):
Bit 0 (TCIF):
Port 6 input status change interrupt flag. Set when Port 6 input
changes,reset by software.
TCC overflow interrupt flag. Set when TCC overflows, reset by
software.
Bank 0 RF can be cleared by instruction but cannot be set.
IOCF is the interrupt mask register.
NOTE
The result of reading Bank 0 RF is the "Logic AND" of Bank 0 RF and IOCF.
14
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
EM78F734N
8-Bit Microcontroller
6.1.14 R10 ~ R3F
These are all 8-bit general-purpose registers.
6.1.15 Bank 1 R5 TC1CR (Timer 1 Control)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TC1CAP
TC1S
TC1M
TC1ES TC1MOD TCK1CK2 TC1CK1 TC1CK0
Bit 7 (TC1CAP): Software capture control
0 : Software capture disable
1 : Software capture enable
Bit 6 (TC1S): Timer/Counter 1 start control
0 : Stop and clear the counter
1 : Start Timer/Counter 1
Bit 5 (TC1M): Timer/Counter 1 mode select
0 : Timer/Counter 1 mode
1 : Capture mode
Bit 4 (TC1ES): TC1 signal edge
0 : increment if the transition from low to high (rising edge) takes place
on the TC1 pin.
1 : increment if the transition from high to low (falling edge) takes place
on TC1 pin.
Bit 3 (TC1MOD): Timer Operation Mode Selection Bit
0: Two 8-bit timers
1: Timer 1 and 2 are cascaded as one 16-bit timer. The corresponding
control register of 16-bit timer is from timer 1. TC1DA and TC2DA
are low byte. TC1DB and TC2DB are high byte.
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
15
EM78F734N
8-Bit Microcontroller
Bit 2 ~ Bit 0 (TC1CK2 ~ TC1CK0): Timer/Counter 1 clock source select
Max. time
8 MHz
Max. time
16kHz
Clock
Source
Resolution
8 MHz
Resolution
16kHz
TC1CK2 TC1CK1 TC1CK0
Normal
FC=8M
FC=8M
FC=16K
FC=16K
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
FC/223
FC/213
FC/28
FC/23
FC/22
FC/2
1.05s
1.024ms
32μs
19.1hr
67.11s
145hr
512ms
16ms
9544hr
33554.432s
1048.576s
32768ms
16384ms
8192ms
2.097s
1μs
65.536ms
32.768ms
16.384ms
8.192ms
0.5ms
0.5s
0.25ms
125s
0.25s
125ns
FC
0.0625ms
4096ms
External
clock
1
1
1
-
-
-
-
(TC1 pin)
Bits 1 ~ 0: Not used, set to “0” at all time.
rising inhibit
edge
detector
capture
control
falling
TC1
interrupt
TC1ES
M
TC1M
TC1 pin
MUX
fc/212
overflow
fc/210
fc/27
8 or16 bit up counter
TC1S
TC1CAP
TC1CK
Comparator
2
capture
capture
TC1CR
TC1DB
TC2DB
TC1DA
TC2DA
TC1MOD
Figure 6-4 Timer/Counter 1 Configuration
In Timer mode, counting up is performed using the internal clock. When the
contents of the up-counter matched with the TC1DA, interrupt is generated and the
counter is cleared. Counting up resumes after the counter is cleared. The current
contents of the up-counter are loaded into TC1DB by setting TC1CAP to “1” and the
TC1CAP is automatically cleared to “0” after capture. The timer mode will operate
with 16bits by setting TC1MOD to “1”
16
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
EM78F734N
8-Bit Microcontroller
In Counter mode, counting up is performed using the external clock input pin (TC1
pin) and either rising or falling edge can be selected by TC1ES, but both edges
cannot be used. When the contents of the up-counter matched with the TC1DA,
interrupt is generated and the counter is cleared. Counting up resumes after the
counter is cleared. The current contents of the up-counter are loaded into the TC1DB
by setting TC1CAP to “1” and the TC1CAP is automatically cleared to “0” after
capture. The counter mode will operate with 16 bits by setting TC1MOD to “1”.
In Capture mode, the pulse width, period and duty of the TC1 input pin are
measured in this mode, which can be used to decode the remote control signal. The
counter is set as free running by the internal clock. On a rising (falling) edge of TC1
pin input, the contents of the counter is loaded into TC1DA, then the counter is
cleared and interrupt is generated. On a falling (rising) edge of the TC1 pin input, the
contents of the counter are loaded into TC1DB. The counter is still counting, on the
next rising edge of the TC1 pin input, the contents of the counter are loaded into
TC1DA, the counter is cleared and interrupt is generated again. If an overflow occurs
before an edge is detected, the FFH is loaded into TC1DA and the overflow interrupt
is generated. During interrupt processing, it can be determined whether there is an
overflow by checking if the TC1DA value is FFH. After an interrupt (capture to
TC1DA or overflow detection) is generated, capture and overflow detection are halted
until TC1DA is read out. The capture mode will operate with 16 bits by setting
TC1MOD to “1”.
Clock source
Up-counter
K 0
m m+1
K-2
K-1
1
m-1
n-1 n 0
1
2
3
FE FF0
1
2
3
TC1 pin input
TC1DA
K
n
FF (overflow)
overflow
m
FE
TC1DB
capture
capture
TC1 interrupt
Reading TC1DA
Figure 6-5 (a) Timing Chart of 8 bits Capture Mode
Clock source
Up-counter
K
0
m m+1
m-1
K-2
K-1
1
n-1 n 0
1
2
3
FFFE FFFF 0
1
2
3
TC1 pin input
TC2DA,TC1DA
TC2DB,TC1DB
K
n
FFFF (overflow)
FFFE
m
capture
overflow
capture
TC1 interrupt
Reading TC1DA
Figure 6-5 (b) Timing Chart of 16 bits Capture Mode
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
17
EM78F734N
8-Bit Microcontroller
6.1.16 Bank 1 R6 TC1DA (Timer 1 Data Buffer A)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TC1DA7 TC1DA6 TC1DA5 TC1DA4 TC1DA3 TC1DA2 TC1DA1 TC1DA0
Bit 7 ~ Bit 0 (TC1DA7 ~ TC1DA0): Data buffer of 8-bit Timer/Counter 1.
6.1.17 Bank 1 R7 TC1DB (Timer 1 Data Buffer B)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TC1DB7 TC1DB6 TC1DB5 TC1DB4 TC1DB3 TC1DB2 TC1DB1 TC1DB0
Bit 7 ~ Bit 0 (TC1DB7 ~ TC1DB0): Data buffer of 8-bit Timer/Counter 1.
6.1.18 Bank 1 R8 OSCR (Oscillator Control)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RCM1
RCM0
Bit 7 and Bit 6 (RCM1, RCM0): IRC mode select bits
Bank1 R8<7,6>
RCM1 RCM0
Writer Trim IRC
Frequency
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
4 MHz
1 MHz
8 MHz
455kHz
4 MHz
1 MHz
8 MHz
455kHz
4 MHz
1 MHz
8 MHz
455kHz
4 MHz
1 MHz
8 MHz
455kHz
4 MHz
1 MHz
8 MHz
455kHz
NOTE
Bank 1 R8<7, 6 > of the initialized values are kept the same as Word 1<3, 2>.
After A Frequency switches to B Frequency, EM78F734N needs to hold some
stable time on B frequency
Ex: Writer trim IRC 4 MHz Bank 1 R8<7,6> set to “10” holds 3 µs
EM78F734N works on 8 MHz ± 10%
18
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
EM78F734N
8-Bit Microcontroller
Code Option Word 1 COBS=0:
The R8<7, 6 > of the initialized values will remain the same as Word 1<3,
2>.
The R8<7, 6 > cannot change frequency.
Code Option Word 1 COBS=1:
The R8<7, 6 > of the initialized values will remain the same Word as 1<3,
2>.
The R8<7, 6> can change when user wants to work on other IRC
frequency.
6.1.19 Bank 1 R9 TC2DA (Timer 2 Data Buffer A)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TC2DA7 TC2DA6 TC2DA5 TC2DA4 TC2DA3 TC2DA2 TC2DA1 TC2DA0
Bits 7~0 (TC2DA7~ TC2DA0): Data buffer of 8-bit Timer/Counter 2 cascade with
Timer/Counter 1 at TC1MOD set to “1”
6.1.20 Bank 1 RA TC2DB (Timer 2 Data Buffer B)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TC2DB7 TC2DB6 TC2DB5 TC2DB4 TC2DB3 TC2DB2 TC2DB1 TC2DB0
Bit 7 ~ Bit 0 (TC2DB7 ~ TC2DB0): Data buffer of 8-bit Timer/Counter 2 cascade with
Timer/Counter 1 at TC1MOD set to “1” ..
6.1.21 Bank 1 RB ~RE
These are reserved registers.
6.1.22 Bank 1 RF (Interrupt Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
TCIF3
TCIF1
-
-
-
Note: “ 1 ” means with interrupt request
“ 0 ” means no interrupt occurs
Bits 7~6: Not used, set to “0” at all time
Bit 5 (TCIF3): 8-bit Timer/Counter 3 interrupt flag. The Interrupt flag is cleared by
software.
Bit 4: Not used, set to “0” at all time
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
19
EM78F734N
8-Bit Microcontroller
Bit 3 (TCIF1): 8-bit Timer/Counter 1 interrupt flag. The Interrupt flag is cleared by
software.
Bits 2~0: Not used, set to “0” at all time
Bank 1 RF can be cleared by instruction but cannot be set.
IOCE is the interrupt mask register.
NOTE
The result of reading Bank 1 RF is the "Logic AND" of Bank 1 RF and IOCE.
6.1.23 Bank 2 R5 AISR (ADC Input Select Register)
The AISR register for ADC pins act as analog input or digital I/O.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADE7
ADE6
ADE5
ADE4
ADE3
ADE2
ADE1
ADE0
Bit 7 (ADE7): AD converter enable bit of P57 pin.
0 : Disable ADC7, P57 functions as I/O pin.
1 : Enable ADC7 to function as analog input pin
Bit 6 (ADE6): AD converter enable bit of P74 pin.
0 : Disable ADC6, P74 functions as I/O pin.
1 : Enable ADC6 to function as analog input pin
Bit 5 (ADE5): AD converter enable bit of P77 pin
0 : Disable ADC5, P77 functions as I/O pin
1 : Enable ADC5 to function as analog input pin
Bit 4 (ADE4): AD converter enable bit of P73 pin
0 : Disable ADC4, P73 functions as I/O pin
1 : Enable ADC4 to function as analog input pin
Bit 3 (ADE3): AD converter enable bit of P63 pin.
0 : Disable ADC3, P63 functions as I/O pin
1 : Enable ADC3 to function as analog input pin
Bit 2 (ADE2): AD converter enable bit of P62 pin.
0 : Disable ADC2, P62 functions as I/O pin
1 : Enable ADC2 to function as analog input pin
Bit 1 (ADE1): AD converter enable bit of P61 pin
0 : Disable ADC1, P61 functions as I/O pin
1 : Enable ADC1 to function as analog input pin
Bit 0 (ADE0): AD converter enable bit of P60 pin
0 : Disable ADC0, P60 functions as I/O pin
20
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
EM78F734N
8-Bit Microcontroller
1 : Enable ADC0 to function as analog input pin
The following table shows the priority of P60/AD1//INT.
P60/AD0//INT Pin Priority
High
/INT
Medium
AD0
Low
P60
6.1.24 Bank 2 R6 ADCON (A/D Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VREFS
CKR1
CKR0
ADRUN
ADPD
ADIS2
ADIS1
ADIS0
Bit 7 (VREFS): The input source of the Vref of the ADC.
0 : Vref of the ADC is connected to the Internal reference which is
selected by Bank 2 R9<5,4>(default value), and the P50/VREF pin
carries out the function of P50
1 : Vref of the ADC is connected to P50/VREF
Bit 6 ~ Bit 5 (CKR1 ~ CKR0): The oscillator clock rate of ADC
CKR1/CKR0
Operation Mode
FOSC/4
Max. Operation Frequency
00
01
10
11
4 MHz
1 MHz
8 MHz
1 MHz
FOSC
FOSC/16
FOSC/2
RCM[1:0]*
Frequency (MHz)
Sample and Hold Timing
00
01
10
11
4
1
8 x TAD
4 x TAD
12 x TAD
2 x TAD
8
455k
*When using XT, LXT1, HXT1, HXT2 mode can also modify RCM[1:0] at Code Option Word 1
to set the Sample and Hold time.
Bit 4 (ADRUN): ADC starts to run
0 : Reset upon completion of AD conversion. This bit cannot be reset
by software.
1 : A/D conversion is started. This bit can be set by software.
Bit 3 (ADPD): ADC Power-down mode
0 : Switch off the resistor reference to save power even while the
CPU is operating.
1 : ADC is operating
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
21
EM78F734N
8-Bit Microcontroller
Bits 2~0 (ADIS2~ADIS0): AD Input Select Bits
AD Input Pin
AD0
ADIS2
ADIS1
ADIS0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
AD1
AD2
AD3
AD4
AD5
AD6
AD7
6.1.25 Bank 2 R7 ADOC (A/D Offset Calibration Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PDE
Reserved Reserved
Bits 7~3: Not used, set to “0” at all time
Bit 2 (PDE): 1/2 VDD Power Detect Enable bit
0 : Disable Power Detect (Default)
1 : Enable Power Detect
PDE
ADIS2
ADIS1
ADIS0
AD Input Select
1/2VDD
1
0
ADx
Bits 1~0: Reserved, must be set to “0” at all time
6.1.26 Bank 2 R8 ADDH (AD High 8-Bit Data Buffer)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADD11
ADD10
ADD9
ADD8
ADD7
ADD6
ADD5
ADD4
When the A/D conversion is completed, the result which is high 8-bit is loaded into the
ADDH. The ADRUN bit is cleared, and the ADIF is set. R8 is read only.
6.1.27 Bank 2 R9 ADDL (AD Low 4-Bit Data Buffer)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
IRVS1
IRVS0
ADD3
ADD2
ADD1
ADD0
Bits 7 ~ 6: Not used, set to “0” at all time
Bits 5 ~ 4 (IRVS1~IRVS0): Internal Reference Voltage Selection.
IRVS[1:0]
Reference Voltage
00
01
10
11
AVDD
4 V
3 V
2.5 V
Bits 3 ~ 0 (ADD3~ADD0): AD low 4-bit data buffer.
22
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
EM78F734N
8-Bit Microcontroller
6.1.28 Bank 2 RA ~ RE
These are reserved registers.
6.1.29 Bank 2 RF (Pull-high Control Register 1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
/PH73
/PH72
/PH71
/PH70
Bits 7 ~ 4:
Not used, set to “0” at all time.
Bit 3 (/PH73): Control bit used to enable pull-high of the P73 pin
0 : Enable internal pull-high
1 : Disable internal pull-high
Bit 2 (/PH72): Control bit used to enable pull-high of the P72 pin.
Bit 1 (/PH71): Control bit used to enable pull-high of the P71 pin.
Bit 0 (/PH70): Control bit used to enable pull-high of the P70 pin.
The RF Register is both readable and writable.
6.1.30 Bank 3 R5
Reserved Register
6.1.31 Bank 3 R6 TBPTH (High Byte of Table Pointer Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MLB
0
0
0
RBit 11
RBit 10
RBit 9
RBit 8
Bit 7 (MLB): Take MSB or LSB at machine code.
Bits 6 ~ 4:
Bits 3 ~ 0:
Not used. Set to “0” at all time.
Table Pointer Address Bits 11~8.
6.1.32 Bank 3 R7~RC
Reserved Registers
6.1.33 Bank 3 RD TC3CR (Timer 3 Control)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TC3FF1
TC3FF0
TC3S
TC3CK2 TC3CK1 TC3CK0
TC3M1
TC3M0
Bit 7 ~ Bit 6 (TC3FF1 ~ TC3FF0): Timer/Counter 3 flip-flop control
TC3FF1
TC3FF0
Operating Mode
Clear
0
0
1
1
0
1
0
1
Toggle
Set
Reserved
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
23
EM78F734N
8-Bit Microcontroller
Bit 5 (TC3S): Timer/Counter 3 start control
0 : Stop and clear the counter
1 : Start Timer/Counter 3
Bit 4 ~ Bit 2 (TC3CK2 ~ TC3CK0): Timer/Counter 3 Clock Source select
Clock Source
Resolution Max. Time
TC3CK2
TC3CK1
TC3CK0
Normal
Fc/211
Fc/27
Fc/25
Fc/23
Fc/22
Fc/21
Fc=8M
250 µs
16 µs
4 µs
Fc=8M
64 ms
4 ms
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1 ms
1 µs
255 µs
127.5 µs
63.8 µs
31.9 µs
-
500 ns
250 ns
125 ns
-
Fc
External clock (TC3 pin)
Bit 1 ~ Bit 0 (TC3M1 ~ TC3M0): Timer/Counter 3 operating mode select
TC3M1
TC3M0
Operating Mode
Timer/Counter
0
0
1
1
0
1
0
1
Reserved
Programmable Divider output
Pulse Width Modulation output
Figure 6-6 Timer / Counter 3 Configuration
In Timer mode, counting up is performed using internal clock (rising edge trigger).
When the contents of the up-counter match the TCR3, then interrupt is generated and
the counter is cleared. Counting up resumes after the counter is cleared.
24
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
EM78F734N
8-Bit Microcontroller
In Counter mode, counting up is performed using external clock input pin (TC3 pin).
When the contents of the up-counter match the TCR3, then interrupt is generated and
the counter is cleared. Counting up resumes after the counter is cleared.
In Programmable Divider Output (PDO) mode, counting up is performed using the
internal clock. The contents of TCR3 are compared with the contents of the up-
counter. The F/F output is toggled and the counter is cleared each time a match is
found. The F/F output is inverted and output to /PDO pin. This mode can generate
50% duty pulse output. The F/F can be initialized by the program and it is initialized
to “0” during reset. A TC3 interrupt is generated each time the /PDO output is
toggled.
Source clock
Up-counter
2
n
0
1
n-1
n
0
1
3
n-1
n
0
1
n-1
0
1
2
TCR3
n
F/F
/PDO Pin
TC3 Interrupt
Figure 6-7 PDO Mode Timing Chart
In Pulse Width Modulation (PWM) Output mode, counting up is performed using
internal clock. The contents of TCR3 are compared with the contents of the up-
counter and TCR3 should be greater than 1(including 1) . The F/F is toggled when a
match is found. The counter continues counting, the F/F is toggled again when the
counter overflows, after which the counter is cleared. The F/F output is inverted and
output to /PWM pin. A TC3 interrupt is generated each time an overflow occurs.
TCR3 is configured as a 2-stage shift register and, during output, will not switch until
one output cycle is completed even if TCR3 is overwritten. Therefore, the output can
be changed continuously. Also, the first time, TRC3 is shifted by setting TC3S to “1”
after data is loaded to TCR3.
Source Clock
n+2
m
Up-counter
TCR3
n
m-1
n
n+1 n+2
n-1
n+1
0
1
FE FF
0
n-1
FE FF
0
1
n/n
n/m
m/m
Shift
overflow
match
overflow
match
overwrite
F/F
/PWM
1 period
TC3 Interrupt
Figure 6-8 PWM Mode Timing Chart
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
25
EM78F734N
8-Bit Microcontroller
6.1.34 Bank 3 RE TC3D (Timer 3 Data Buffer)
Bit 7
TC3D7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TC3D6
TC3D5
TC3D4
TC3D3
TC3D2
TC3D1
TC3D0
Bit 7 ~ Bit 0 (TC3D7 ~ TC3D0): Data Buffer of 8-bit Timer/Counter 3
6.1.35 Bank 3 RF (Pull-down Control Register 1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
/PD73
/PD72
/PD71
/PD70
Bit 7~ Bit 4: Not used, set to “0” at all time
Bit 3 (/PD73): Control bit used to enable the P73 pull-down pin
0 : Enable internal pull-down
1 : Disable internal pull-down
Bit 2 (/PD72): Control bit used to enable the P72 pull-down pin
Bit 1 (/PD71): Control bit used to enable the P71 pull-down pin
Bit 0 (/PD70): Control bit used to enable the P70 pull-down pin
The RF Register is both readable and writable.
26
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
EM78F734N
8-Bit Microcontroller
6.2 Special Function Registers
6.2.1 A (Accumulator)
Internal data transfer operation, or instruction operand holding usually involves the
temporary storage function of the Accumulator, which is not an addressable register.
6.2.2 CONT (Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTE
/INT
TS
TE
PSTE
PST2
PST1
PST0
Bit 7 (INTE): INT signal edge
0 : interrupt occurs at the rising edge of the INT pin
1 : interrupt occurs at the falling edge of the INT pin
Bit 6 (/INT): Interrupt Enable flag
0 : masked by DISI or hardware interrupt
1 : enabled by ENI/RETI instructions
Bit 5 (TS): TCC signal source
0 : internal instruction cycle clock
1 : transition on the TCC pin
Bit 4 (TE): TCC signal edge
0 : increment if a transition from low to high takes place on the TCC pin
1 : increment if a transition from high to low takes place on the TCC pin
Bit 3 (PSTE): Prescaler enable bit for TCC
0 : prescaler disable bit, TCC rate is 1:1
1 : prescaler enable bit, TCC rate is set at Bit 2~Bit 0
Bit 2 ~ Bit 0 (PST 2 ~ PST0): TCC prescaler bits
PST2
PST1
PST0
TCC Rate
1:2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:4
1:8
1:16
1:32
1:64
1:128
1:256
The CONT register is both readable and writable.
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
27
EM78F734N
8-Bit Microcontroller
6.2.3 IOC5 ~ IOC8 (I/O Port Control Register)
A value “1” sets the relative I/O pin into high impedance, while “0” defines the relative
I/O pin as output.
IOC5, IOC6 IOC7 and IOC8 registers are both readable and writable.
6.2.4 IOC9
Reserved registers
6.2.5 IOCA (WDT Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WDTE
EIS
-
-
PSWE
PSW2
PSW1
PSW0
Bit 7 (WDTE): Control bit used to enable the Watchdog timer
0 : Disable WDT
1 : Enable WDT
WDTE is both readable and writable.
Bit 6 (EIS): Control bit used to define the function of P60 (INT) pin
0 : P60, bidirectional I/O pin
1 : INT, external interrupt pin. In this case, the I/O control bit of P60
(Bit 0 of IOC6) must be set to “1”.
When EIS is “0”, the path of /INT is masked. When EIS is “1”, the
status of the /INT pin can also be read by way of reading Port 6 (R6).
EIS is both readable and writable.
Bits 5~4:
Not used, set to “0” at all time
Bit 3 (PSWE): Prescaler enable bit for WDT
0 : prescaler disable bit, WDT rate is 1:1
1 : prescaler enable bit, WDT rate is set at Bit 0~Bit 2
Bit 2 ~ Bit 0 (PSW2 ~ PSW0): WDT prescaler bits
PSW2
PSW1
PSW0
WDT Rate
1:2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:4
1:8
1:16
1:32
1:64
1:128
1:256
28
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
EM78F734N
8-Bit Microcontroller
6.2.6 IOCB (Pull-down Control Register 2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/PD7
/PD6
/PD5
/PD4
/PD3
/PD2
/PD1
/PD0
Bit 7 (/PD7): Control bit used to enable pull-down of the of P63 pin
0 : Enable internal pull-down
1 : Disable internal pull-down
Bit 6 (/PD6): Control bit used to enable pull-down of the P62 pin
Bit 5 (/PD5): Control bit used to enable pull-down of the P61 pin
Bit 4 (/PD4): Control bit used to enable pull-down of the P60 pin
Bit 3 (/PD3): Control bit used to enable pull-down of the P53 pin
Bit 2 (/PD2): Control bit used to enable pull-down of the P52 pin
Bit 1 (/PD1): Control bit used to enable pull-down of the P51 pin
Bit 0 (/PD0): Control bit used to enable pull-down of the P50 pin
The IOCB Register is both readable and writable.
6.2.7 IOCC (Open-drain Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OD3
OD2
OD1
OD0
Bits 7 ~ 4: Not used, set to “0” at all time
Bit 3 (OD3): Control bit used to enable the open-drain output of P63 pin
0 : Disable open-drain output
1 : Enable open-drain output
Bit 2 (OD2): Control bit used to enable the open-drain output of P62 pin
Bit 1 (OD1): Control bit used to enable the open-drain output of P61 pin
Bit 0 (OD0): Control bit used to enable the open-drain output of P60 pin
The IOCC Register is both readable and writable.
6.2.8 IOCD (Pull-high Control Register 2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/PH3
/PH2
/PH1
/PH0
Bits 7~4:
Not used, set to “0” at all time
Bit 3 (/PH3): Control bit used to enable pull-high of the P63 pin.
0 : Enable internal pull-high
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
29
EM78F734N
8-Bit Microcontroller
1 : Disable internal pull-high
Bit 2 (/PH2): Control bit used to enable pull-high of the P62 pin.
Bit 1 (/PH1): Control bit used to enable pull-high of the P61 pin.
Bit 0 (/PH0): Control bit used to enable pull-high of the P60 pin.
The IOCD Register is both readable and writable.
6.2.9 IOCE (Interrupt Mask Register 2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TCIE3
TCIE1
Bits 7~6: Not used, set to “0” at all time
Bit 5 (TCIE3): Interrupt enable bit
0 : Disable TCIF3 interrupt
1 : Enable TCIF3 interrupt
Bit 4:
Bit 3 (TCIE1):Interrupt enable bit
0: Disable TCIF1 interrupt
Not used, set to “0” at all time
1: Enable TCIF1 interrupt
Bits 2~0:
Not used, set to “0” at all time
6.2.10 IOCF (Interrupt Mask Register 1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADIE
EXIE
ICIE
TCIE
Bit 7:
Not used, set to “0” at all time
Bit 6 (ADIE): ADIF interrupt enable bit
0 : Disable ADIF interrupt
1 : Enable ADIF interrupt
When the ADC Complete is used to enter an interrupt vector or enter
the next instruction, the ADIE bit must be set to “Enable“.
Bits 5 ~ 3: Not used, set to “0” at all time
Bit 2 (EXIE): EXIF interrupt enable bit
0 : Disable EXIF interrupt
1 : Enable EXIF interrupt
Perform the following steps from the EXINT, First set EXIE, and then set the EIS.
EXINT internal comparison value default is “0”. Then set the rising edge and the INT
30
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
EM78F734N
8-Bit Microcontroller
pin to high, since doing EXINT setting will cause immediate trigger signal and
generate an interrupt.
Bit 1 (ICIE): ICIF interrupt enable bit
0 : Disable ICIF interrupt
1 : Enable ICIF interrupt
Bit 0 (TCIE): TCIF interrupt enable bit
0 : Disable TCIF interrupt
1 : Enable TCIF interrupt
Individual interrupt is enabled by setting its associated control bit in the IOCF to “1”.
Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction.
The IOCF register is both readable and writable.
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
31
EM78F734N
8-Bit Microcontroller
6.3 TCC/WDT and Prescaler
There are two 8-bit counters available as prescalers for the TCC and WDT respectively.
The PST0~PST2 bits of the CONT register are used to determine the ratio of the
prescaler of TCC. Likewise, the PSW0~PSW2 bits of the IOCA register are used to
determine the WDT prescaler. The prescaler counter will be cleared by the
instructions each time they are written into TCC. The WDT and prescaler will be
cleared by the “WDTC” and “SLEP” instructions. Figure 6-9 depicts the circuit
diagram of TCC/WDT.
R1 (TCC) is an 8-bit timer/counter. The clock source of TCC can be the internal clock
or the external signal input (edge selectable from the TCC pin). If TCC signal source
is from the internal clock, TCC will be incremented by 1 at Fc clock (without
prescaler). As illustrated in Figure 6-9, selection of Fc depends on the bank 0 RE.6
<TIMERSC>. If TCC signal source is from external clock input, TCC will be
incremented by 1 at every falling edge or rising edge of the TCC pin. TCC pin input
time length (kept in High or low level) must be greater than 1CLK. The TCC will stop
running when sleep mode occurs.
The watchdog timer is a free running on-chip RC oscillator. The WDT will keep on
running even after the oscillator driver has been turned off (i.e. in sleep mode).
During normal operation or sleep mode, a WDT time-out (if enabled) will cause the
device to reset. The WDT can be enabled or disabled at any time during normal
mode by software programming. Refer to WDTE bit of IOCA register. With no
prescaler, the WDT time-out period is approximately 16.5 ms1 (one oscillator start-up
timer period).
0
8 Bit Counter
Data Bus
Fc (Fm/Fs)
MUX
1
TCC Pin
8 to 1 MUX
Prescaler
TCC(R1)
TE (CONT)
TCC overflow
interrupt
TS (CONT)
PSTE, PST2~PST0
(CONT)
8 Bit Counter
WDT
8 to 1 MUX
Prescaler
WDTE (IOCA)
WDT time out
PSWE, PSW2~PSW0
(IOCA)
Figure 6-9 TCC and WDT Block Diagram
1 VDD=5V, WDT time-out period = 16.5ms ± 5% VDD=3V
WDT time-out period = 16.5ms ± 5%.
32
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
EM78F734N
8-Bit Microcontroller
6.4 I/O Ports
The I/O registers, Ports 5, 6, 7 and 8, are bidirectional tri-state I/O ports. Port 6 / 7 can
be pulled high internally by software. In addition, Port 6 can also have open-drain
output by software. Input status change interrupt (or wake-up) function on Port 6 P50 ~
P53 and P60 ~ P63 and Port 7 pins can be pulled down by software. Each I/O pin can
be defined “in” or “out” pin by the I/O control register (IOC5 ~ IOC8).
The I/O registers and I/O control registers are both readable and writable. The I/O
interface circuits for Port 5, Port 6, Port 7 and Port 8 are shown in the following
Figures 6-10, 6-11 (a), 6-11 (b), and Figure 6-12.
PCRD
P
Q
D
R
PCWR
CLK
_
Q
C
L
P
R
IOD
PORT
Q
D
PDWR
CLK
_
Q
C
L
PDRD
0
1
M
U
X
Note: Pull-down is not shown in the figure.
Figure 6-10 I/O Port and I/O Control Register Circuit for Ports 5, 6, 7
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
33
EM78F734N
8-Bit Microcontroller
PCRD
P
Q
D
R
_
Q
PCWR
PDWR
CLK
C
L
INT
IOD
P
R
Q
PORT
D
_
Q
CLK
C
L
0
1
P
D
R
Q
M
U
X
_
Q
CLK
C
L
T10
PDRD
P
R
D
Q
CLK
_
Q
C
L
INT
Note: Pull-high (down) and Open-drain are not shown in the figure.
Figure 6-11 (a) I/O Port and I/O Control Register Circuit for P60 (INT)
PCRD
P
R
Q
D
_
Q
CLK
C
L
PCWR
PDWR
P60~P63
PORT
IOD
P
R
Q
D
_
Q
CLK
C
L
0
1
M
U
X
TIN
PDRD
P
R
D
Q
CLK
_
Q
C
L
Note: Pull-high (down) and Open-drain are not shown in the figure.
Figure 6-11 (b) I/O Port and I/O Control Register Circuit for P61~P63, P83
34
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
EM78F734N
8-Bit Microcontroller
IOCE.1
P
Q
D
R
CLK
Interrupt
_
Q
C
L
RE.1
ENI Instruction
P
R
T10
T11
D
Q
P
CLK
Q
D
R
_
Q
C
CLK
L
_
Q
C
L
T17
DISI Instruction
Interrupt
(Wake-up from SLEEP)
/SLEP
Next Instruction
(Wake-up from SLEEP)
Figure 6-12 Block Diagram of I/O Port 6 with Input Change Interrupt/Wake-up
Table 6-1 Usage of Port 6 Input Change Wake-up/Interrupt Function
Usage of Port 6 Input Status Changed Wake-up/Interrupt
(I) Wake-up Input Status Change
(a) Before Sleep
(II) Interrupt Input Status Change
1. Read I/O Port 6 (MOV R6,R6)
2. Execute “NI”
2
1. Disable WDT (use this very carefully)
2. Read I/O Port 6 (MOV R6,R6)
3. Enable interrupt (Set IOCF=1)
4. If Port 6 change (Interrupt)
3 a. Enable interrupt (Set IOCF=1), after
wake-up
Interrupt Vector (006H)
if “ENI” switch to interrupt vector
(006H),
if “DISI” excute next instruction
3 b. Disable interrupt (Set IOCF=1).
Always execute next instruction
4. Enable wake-up bit (Set RA=6)
5. Execute “SLEP” instruction
(b) After Wake-up
1. If “NI” Interrupt Vector (006H)
2. If “DSI” Next instruction
2 Software disables WDT (watchdog timer) but hardware must be enabled before applying
Port 6 Change Wake-up function (Code Option Register Word 0 Bit 6 (ENWDTB) is set to
“1”).
3 Vdd = 5V, set up time period = 16.5ms ± 5%
Vdd = 3V, set up time period = 16.5ms ± 5%
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
35
EM78F734N
8-Bit Microcontroller
6.5 Reset and Wake-up
6.5.1 Reset
A reset is initiated by one of the following events:
(1) Power-on reset
(2) /RESET pin input “low”
(3) WDT time-out (if enabled)
3
The device is kept in a reset condition for a period of approximately 18ms (one
oscillator start-up timer period) after the reset is detected. Once a reset occurs, the
following functions are performed.
The oscillator is running, or will be started.
The Program Counter (R2) is set to all “0”.
All I/O port pins are configured as input mode (high-impedance state).
The Watchdog timer and prescaler are cleared.
When power is switched on, the upper three bits of R3 are cleared.
The bits of the RB, RC, RD, RD, RE registers are set to their previous status.
The bits of the CONT register are set to all “0” except for Bit 6 (INT flag).
The bits of the Pull-high, Pull-down.
Bank 0 RF, IOCF registers are cleared.
Sleep (power down) mode is asserted by executing the “SLEP” instruction. While
entering sleep mode, WDT (if enabled) is cleared but keeps on running. After a
wake-up, in RC mode the wake-up time is 16 clocks.
The controller can be awakened by:
(1) External reset input on /RESET pin
(2) WDT time-out (if enabled)
(3) Port 6 input status changes (if enabled)
(4) External (P60 / INT) pin changes (if EXWE is enabled)
(5) A/D conversion completed (if ADWE is enabled)
3 Vdd = 5V, set up time period = 16.5ms ± 5%
Vdd = 3V, set up time period = 16.5ms ± 5%
36
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
EM78F734N
8-Bit Microcontroller
The first two events (1 & 2) will cause the EM78F734N to reset. The T and P flags of
R3 can be used to determine the source of the reset (wake-up). Events 3, 4, and 5
are considered the continuation of program execution and the global interrupt “NI” or
“DSI” (being executed) determines whether or not the controller branches to the
interrupt vector following wake-up. If ENI is executed before SLEP, the instruction
will begin to execute from Address 0x3, 0x6 0xF, 0x15 or 0X30, after wake-up. If
DISI is executed before SLEP, the execution will restart from the instruction right next
to SLEP after wake-up. All throughout the sleep mode, wake-up time is150 µs, no
matter what oscillation mode (except low Crystal mode). In low Crystal 2 mode,
wake-up time is 500ms.
One or more of the above Events 3 to 6 can be enabled before entering into sleep
mode but is awakened only by one of the events.
[a] If WDT is enabled before SLEP, all of the RE bit is disabled. Hence, the
EM78F734N can be awakened only by Event 1 or 2. Refer to Section 6.6
Interrupt for further details.
[b] If Port 6 Input Status Change is used to wake up the EM78F734N and the ICWE
bit
of the RA register is enabled before SLEP, WDT must be disabled. Hence, the
EM78F734N can be awakened only by Event 3. The following instructions must be
executed before SLEP:
MOV
A, @001110xxb ;Select WDT prescaler and disable WDT
IOW
IOCA
WDTC
;Clear WDT and prescaler
MOV
R6, R6
;Read Port 6
ENI (or DISI)
;Enable (or disable) global interrupt
MOV
MOV
MOV
IOW
SLEP
A, @010xxxxxb ;Enable Port 6 input change Wake-up bit
RA,A
A, @00000x1xb ;Enable Port 6 input change interrupt
IOCF
;Sleep
[c] If External (P60/INT) pin changes is used to wake-up the EM78F734N and
EXWE
bit of the RA register is enabled before SLEP, WDT must be disabled by
software. Hence, the EM78F734N can be awakened only by Event 4.
[d] If AD conversion completed is used to wake-up EM78F734N and ADWE bit of the
RA
register is enabled before SLEP, the WDT must be disabled by software. Hence,
the EM78F734N can be waken-up only by Event 5.
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
37
EM78F734N
8-Bit Microcontroller
6.5.2 Summary of Wake-up and Interrupt Modes Operation
All categories under Wake-up and Interrupt modes are summarized below.
The controller can be awakened from Sleep mode and Idle mode. The Wake-up
signals are listed as follows.
Wake-up Signal
Sleep Mode
Idle Mode
Green Mode
Normal Mode
If enable EXWE
bit
If enable EXWE
bit Wake-up
Interrupt (if
interrupt is
enabled)
Interrupt (if
interrupt is
enabled)
Wake-up
+ interrupt (if
interrupt is
enabled)
External interrupt
+ interrupt (if
interrupt is enablee)
or next instruction
or next instruction
+ next instruction
+ next instruction
If enable ICWE bit
Wake-up
If enable ICWE bit
Wake-up
Interrupt (if interrupt
is enabled)
Interrupt (if interrupt
is enabled)
+ interrupt (if
interrupt is
enabled)
Port 6 pin change
+ interrupt (if
interrupt is enabled)
or next instruction
or next instruction
+ next instruction
+ next instruction
Wake-up
Interrupt (if interrupt
is enabled)
Interrupt (if interrupt
is enabled)
+ interrupt (if
interrupt is
enabled)
TCC overflow
interrupt
x
or next instruction
or next instruction
+ next instruction
If enable ADWE
bit
If enable ADWE
bit Wake-up
Wake-up
Interrupt (if interrupt
is enabled)
+ interrupt (if
interrupt is
enabled)
Interrupt (if interrupt
is enabled)
AD conversion
complete
interrupt
+ interrupt (if
interrupt is
enabled)
or next instruction
Fs and Fm don’t
stop
or next instruction
+ next instruction
+ next instruction
Fs and Fm don’t
Fs and Fm don’t
stop
stop
Wake-up
Interrupt (if interrupt
is enabled)
Interrupt (if interrupt
is enabled)
+ interrupt (if
interrupt is
enabled)
TC2 interrupt
x
x
or next instruction
or next instruction
+ next instruction
Wake-up
Interrupt (if
interrupt is
enabled)
Interrupt (if
interrupt is
enabled)
+ interrupt (if
interrupt is
enabled)
TC3 interrupt
or next instruction
or next instruction
+ next instruction
RESET
WDT Time out
RESET
RESET
RESET
RESET
Low Voltage
Reset
RESET
RESET
RESET
After wake up:
1. If interrupt is enabled → interrupt+ next instruction
2. If interrupt is disabled → next instruction
38
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
EM78F734N
8-Bit Microcontroller
6.5.3 Summary of Register Initial Values
Legend: x: Not used
U: Unknown or don’t care
P: Previous value before reset
t: Check tables under Section 6.5.4
Addr Name
Reset Type
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
C53
1
Bit 2
Bit 1
Bit 0
C57
-
0
C55
1
C54
1
C52
1
C51
1
C50
1
Power-on
1
0x05 IOC5
/RESET and WDT
Wake-up from Pin Change
Bit Name
1
0
1
1
1
1
1
1
P
0
P
-
P
P
P
P
P
-
-
-
C63
1
C62
1
C61
1
C60
1
Power-on
0
0
0
0
0x06 IOC6
0x07 IOC7
/RESET and WDT
Wake-up from Pin Change
Bit Name
0
0
0
0
1
1
1
1
0
0
0
0
P
P
P
P
C77
-
-
C74
1
C73
1
C72
1
C71
1
C70
1
Power-on
1
0
0
/RESET and WDT
Wake-up from Pin Change
Bit Name
1
0
0
1
1
1
1
1
P
0
0
P
P
P
P
P
-
-
-
-
C83
1
-
-
-
Power-on
0
0
0
0
0
0
0
0
0x08
IOC8
/RESET and WDT
Wake-up from Pin Change
Bit Name
0
0
0
1
0
0
0
0
0
0
0
P
0
0
0
INTE
0
/INT
0
TS
0
TE
0
PSTE PST2 PST1 PST0
Power-on
0
0
0
0
0
0
0
0
N/A CONT
/RESET and WDT
Wake-up from Pin Change
Bit Name
0
0
0
0
P
P
IAR6
U
P
P
P
IAR5
U
P
P
P
P
P
P
P
IAR7
U
IAR4
U
P
IAR3
U
IAR2
U
IAR1
U
IAR0
U
Power-on
0x00 R0 (IAR)
/RESET and WDT
Wake-up from Pin Change
Bit Name
P
P
P
P
P
P
P
P
P
P
P
TCC7 TCC6 TCC5 TCC4 TCC3 TCC2 TCC1 TCC0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R1
0x01
(TCC)
/RESET and WDT
Wake-up from Pin Change
Bit Name
P
A7
0
P
A6
0
P
A5
0
P
A4
0
P
A3
0
P
A2
0
P
P
A0
0
A1
0
Power-on
0x02 R2 (PC)
0x03 R3 (SR)
/RESET and WDT
Wake-up from Pin Change
Bit Name
0
0
0
0
0
0
0
0
P
-
P
-
P
-
P
T
1
P
P
1
P
Z
P
P
C
U
P
P
DC
U
P
Power-on
0
0
0
U
P
P
/RESET and WDT
Wake-up from Pin Change
Bit Name
0
0
0
t
t
0
0
0
t
t
P
RSR7 RSR6 RSR5 RSR4 RSR3 RSR2 RSR1 RSR0
Power-on
U
P
P
U
P
P
U
P
P
U
P
P
U
P
P
U
P
P
U
P
P
U
P
P
R4
0x04
(RSR)
/RESET and WDT
Wake-up from Pin Change
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
39
EM78F734N
8-Bit Microcontroller
Addr Name
Reset Type
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
P53
1
Bit 2
P52
1
Bit 1
P51
1
Bit 0
P50
1
P57
1
-
P55
1
1
P
-
P54
1
Power-on
0
0
0
-
P5
(Bank 0)
0x05
/RESET and WDT
Wake-up from Pin Change
Bit Name
1
1
1
1
1
1
P
-
P
-
P
P
P
P
P63
1
P62
1
P61
1
P60
1
Power-on
0
0
0
0
-
0
0
0
-
0
P6
(Bank 0)
0x06
0x07
0x08
0X09
0x0A
0X0B
0X0C
0X0D
0X0E
/RESET and WDT
Wake-up from Pin Change
Bit Name
0
0
1
1
1
1
0
0
P
P
P
P
P77
1
P74
1
P73
1
P72
1
P71
1
P70
1
Power-on
0
0
0
-
0
0
0
-
P7
(Bank 0)
/RESET and WDT
Wake-up from Pin Change
Bit Name
1
1
1
1
1
1
P
-
P
-
P
P
P
P
P83
1
-
-
-
Power-on
0
0
0
0
0
0
0
0
0
0
0
P8
(Bank 0)
/RESET and WDT
Wake-up from Pin Change
Bit Name
0
0
1
0
0
0
0
0
P
0
0
0
RBit7 RBit6 RBit5 RBit4 RBit3 RBit2 RBit1 RBit0
Power-on
0
0
0
0
P
0
0
P
0
0
P
0
0
P
-
0
0
P
-
0
0
P
-
0
0
P
-
R9
(Bank 0)
/RESET and WDT
Wake-up from Pin Change
Bit Name
P
-
ICWE ADWE EXWE
Power-on
0
0
0
P
0
0
P
0
0
P
0
0
0
0
0
0
-
0
0
0
-
0
0
0
-
RA
(Bank 0)
/RESET and WDT
Wake-up from Pin Change
Bit Name
0
0
RD
0
WR EEWE EEDF EEPC
RB
(ECR)
(Bank 0)
Power-on
0
P
P
0
P
P
0
P
P
0
P
P
0
0
0
0
0
0
0
0
0
/RESET and WDT
Wake-up from Pin Change
Bit Name
P
P
-
EE_A6 EE_A5 EE_A4 EE_A3 EE_A2 EE_A1 EE_A0
Power-on
0
0
P
P
0
P
P
0
P
P
0
P
P
0
P
P
0
P
P
0
P
P
RC
(Bank 0)
/RESET and WDT
Wake-up from Pin Change
Bit Name
0
0
EE_D7 EE_D6 EE_D5 EE_D4 EE_D3 EE_D2 EE_D1 EE_D0
Power-on
0
P
P
-
0
P
P
0
P
P
0
P
P
0
P
P
-
0
P
P
-
0
P
P
-
0
P
P
-
RD
(Bank 0)
/RESET and WDT
Wake-up from Pin Change
Bit Name
TIMERSC CPUS IDLE
Power-on
0
0
0
1
1
P
1
1
P
1
1
P
0
0
0
0
0
0
0
0
0
0
0
0
RE
(Bank 0)
/RESET and WDT
Wake-up from Pin Change
40
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
EM78F734N
8-Bit Microcontroller
Addr Name
Reset Type
Bit Name
Bit 7
Bit 6
ADIF
0
Bit 5
Bit 4
Bit 3
Bit 2
EXIF
0
Bit 1
ICIF
0
Bit 0
TCIF
0
-
-
-
-
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
RF (ISR)
0x0F
(Bank 0)
/RESET and WDT
Wake-up from Pin Change
Bit Name
0
0
0
0
P
P
P
P
TC1AP TC1S TC1M TC1ES TC1MOD TCK1CK2 TC1CK1 TC1CK0
Power-on
0
0
0
0
0
0
P
0
0
P
0
0
P
0
0
P
0
0
P
0
0
P
R5
0x5
(Bank 1)
/RESET and WDT
Wake-up from Pin Change
P
P
TC1DA
1
Bit Name
TC1DA7 TC1DA6 TC1DA5 TC1DA4 TC1DA3 TC1DA2
TC1DA0
R6
0x6
Power-on
0
0
P
0
0
P
0
0
P
0
0
P
0
0
P
0
0
P
0
0
P
0
0
P
(Bank 1)
/RESET and WDT
Wake-up from Pin Change
TC1DB
1
Bit Name
TC1DB7 TC1DB6 TC1DB5 TC1DB4 TC1DB3 TC1DB2
TC1DB0
R7
0X7
Power-on
0
0
P
0
0
P
0
0
P
-
0
0
P
-
0
0
P
-
0
0
P
-
0
0
P
-
0
0
P
-
(Bank 1)
/RESET and WDT
Wake-up from Pin Change
Bit Name
RCM1 RCM0
Option Option
Power-on
0
0
0
0
0
0
RCM1
RCM0
R8
0x8
(Bank 1)
Option Option
/RESET and WDT
Wake-up from Pin Change
Bit Name
0
0
0
0
0
0
0
0
0
0
0
0
RCM1
P
RCM0
P
TC2DA
1
TC2DA7 TC2DA6 TC2DA5 TC2DA4 TC2DA3 TC2DA2
TC2DA0
R9
0x9
Power-on
0
0
P
0
0
P
0
0
P
0
0
P
0
0
P
0
0
P
0
0
P
0
0
P
(Bank 1)
/RESET and WDT
Wake-up from Pin Change
TC2DB
1
Bit Name
TC2DB7 TC2DB6 TC2DB5 TC2DB4 TC2DB3 TC2DB2
TC2DB0
RA
0XA
Power-on
0
0
P
-
0
0
P
-
0
0
0
P
-
0
0
0
P
-
0
0
P
-
0
0
P
-
(Bank 1)
/RESET and WDT
Wake-up from Pin Change
Bit Name
0
0
P
P
TCIF3
TCIF1
Power-on
0
0
0
0
0
0
0
0
P
0
0
0
0
0
P
0
0
0
0
0
0
0
0
0
RF
0XF
(Bank 1)
/RESET and WDT
Wake-up from Pin Change
Bit Name
ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0
Power-on
0
0
P
0
0
P
0
0
P
0
0
P
0
0
P
0
0
P
0
0
P
0
0
P
R5
0x05
(Bank 2)
/RESET and WDT
Wake-up from Pin Change
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
41
EM78F734N
8-Bit Microcontroller
Addr Name
Reset Type
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VREFS CKR1 CKR0 ADRUN ADPD ADIS2 ADIS1 ADIS0
Power-on
0
0
P
-
0
0
P
-
0
0
P
-
0
0
P
-
0
0
P
-
0
0
0
0
P
-
0
0
P
-
R6
(Bank 2)
0x06
/RESET and WDT
Wake-up from Pin Change
Bit Name
P
PDE
0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R7
(Bank 2)
0x7
0x8
/RESET and WDT
Wake-up from Pin Change
Bit Name
0
P
ADD11 ADD10 ADD9 ADD8 ADD7 ADD6 ADD5 ADD4
Power-on
0
0
0
0
P
-
0
0
P
0
0
P
0
0
P
0
0
P
0
0
P
0
0
P
R8
(Bank 2)
/RESET and WDT
Wake-up from Pin Change
Bit Name
P
-
IRVS1 IRVS0 ADD3 ADD2 ADD1 ADD0
Power-on
0
0
0
0
-
0
0
0
P
-
0
0
P
0
0
P
0
0
P
0
0
P
R9
(Bank 2)
0x9
/RESET and WDT
Wake-up from Pin Change
Bit Name
0
0
0
P
-
-
/PH73 /PH72 /PH71 /PH70
Power-On
0
0
0
0
-
0
0
0
0
-
1
1
P
1
1
P
1
1
P
1
1
P
RF
(Bank 2)
0x0F
0X06
0XD
0XE
0XF
/RESET and WDT
Wake-up from Pin Change
Bit Name
0
0
0
0
MLB
0
-
RBit 11 RBit 10 RBit 9 RBit 8
Power-On
0
0
0
0
0
0
0
0
0
P
0
0
P
0
0
P
0
0
P
R6
(Bank 3)
/RESET and WDT
Wake-up from Pin Change
Bit Name
0
0
P
0
TC3FF1 TC3FF0
TC3CK2 TC3CK1 TC3CK0
TC3M1 TC3M0
TC3S
Power-on
0
0
P
0
0
P
0
0
P
0
0
P
0
0
P
0
0
P
0
0
P
0
0
P
RD
(Bank 3)
/RESET and WDT
Wake-up from Pin Change
Bit Name
TC3D7 TC3D6 TC3D5 TC3D4 TC3D3 TC3D2 TC3D1 TC3D0
Power-on
0
0
P
-
0
0
P
-
0
0
P
-
0
0
P
-
0
0
P
0
0
P
0
0
P
0
0
P
RE
(Bank 3)
/RESET and WDT
Wake-up from Pin Change
Bit Name
/PD73 /PD72 /PD71 /PD70
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
1
1
P
1
1
P
1
1
P
1
1
P
RF
(Bank 3)
/RESET and WDT
Wake-up from Pin Change
42
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
EM78F734N
8-Bit Microcontroller
(Continuation)
Addr Name
Reset Type
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WDTE
EIS
-
-
0
PSWE PSW2 PSW1 PSW0
Power-on
0
0
0
0
0
0
0
0
0
0x0A IOCA
0x0B IOCB
0x0C IOCC
0x0D IOCD
0x0E IOCE
0x0F IOCF
/RESET and WDT
Wake-up from Pin Change
Bit Name
0
0
0
0
0
0
P
/PD7
1
P
0
0
P
P
P
P
/PD6
/PD5
/PD4
1
/PD3
/PD2
/PD1
1
/PD0
Power-on
1
1
1
1
1
1
1
1
/RESET and WDT
Wake-up from Pin Change
Bit Name
1
1
1
1
1
P
-
P
-
P
P
-
P
P
P
P
-
OD3
OD2
0
OD1
0
OD0
0
Power-on
0
0
0
0
0
/RESET and WDT
Wake-up from Pin Change
Bit Name
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
-
-
-
-
/PH3
/PH2
1
/PH1
1
/PH0
1
Power-on
0
0
0
0
1
/RESET and WDT
Wake-up from Pin Change
Bit Name
0
0
0
0
1
1
1
1
0
0
0
0
P
P
P
P
-
-
TCIE3
-
TCIE1
-
-
-
Power-on
0
0
0
0
0
0
0
0
0
0
/RESET and WDT
Wake-up from Pin Change
Bit Name
0
0
0
0
0
0
0
0
P
-
0
P
-
0
0
0
-
ADIE
0
-
EXIE
0
ICIE
0
TCIE
0
Power-on
0
0
0
0
/RESET and WDT
Wake-up from Pin Change
Bit Name
0
0
0
0
0
0
0
0
0
P
R6
U
P
P
0
0
0
P
P
P
R7
U
P
P
R5
U
P
P
R4
U
P
P
R3
U
P
P
R2
U
R1
U
R0
U
Power-on
R10~
R2F
0x10~
0x2F
/RESET and WDT
Wake-up from Pin Change
P
P
P
P
P
P
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
43
EM78F734N
8-Bit Microcontroller
6.5.4 Status of RST, T, and P of the Status Register
A reset condition is initiated by the following events:
1. Power-on condition
2. High-low-high pulse on /RESET pin
3. Watchdog timer time-out
The values of T and P, listed in the first table below are used to check how the
processor wakes up. The second table shows the events that may affect the status
of T and P.
Values of RST, T and P after Reset
Reset Type
Power on
T
1
P
1
/RESET during Operating mode
/RESET wake-up during Sleep mode
WDT during Operating mode
WDT wake-up during Sleep mode
Wake-up on pin change during Sleep mode
*P
1
*P
0
0
*P
0
0
1
0
*P: Previous status before reset
Status of T and P Being Affected by Events
Event
T
1
1
0
1
1
P
1
Power on
WDTC instruction
1
WDT time-out
*P
0
SLEP instruction
Wake-up on pin change during Sleep mode
0
*P: Previous value before reset
44
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
EM78F734N
8-Bit Microcontroller
VDD
D
Q
CLK
Oscillator
CLK
CLR
Power-On Reset
Low Voltage Reset
Setup time
WDTE
WDT
WDT Timeout
Reset
/RESET
Figure 6-13 Controller Reset Block Diagram
6.6 Interrupt
The EM78F734N has eight interrupts (four external, four internal) as listed below:
Interrupt Source
Enable Condition Int. Flag Int. Vector
Priority
Internal /
Reset
INT
-
-
0000
High 0
External
External
External
Internal
Internal
Internal
ENI + EXIE=1
EXIF
ICIF
0003
0006
0009
0018
0027
0030
1
2
3
4
5
6
Port 6 pin change ENI +ICIE=1
TCC
TC1
TC3
AD
ENI + TCIE=1
ENI + TCIE1=1
ENI + TCIE3=1
ENI + ADIE=1
TCIF
TCIF1
TCIF3
ADIF
Internal
RF is interrupt status register that records the interrupt requests in the relative flags/
bits. IOCF is interrupt mask register. The global interrupt is enabled by the ENI
instruction and is disabled by the DISI instruction. When one of the enabled
interrupts occur, the next instruction will be fetched from their individual address. The
interrupt flag bit must be cleared by instructions before leaving the interrupt service
routine and before interrupts are enabled to avoid recursive interrupts.
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
45
EM78F734N
8-Bit Microcontroller
The flag (except ICIF bit) in the Interrupt Status Register (RF) is set regardless of the
status of its mask bit or the execution of ENI. The RETI instruction ends the interrupt
routine and enables the global interrupt (the execution of ENI).
The external interrupt is equipped with an on-chip digital noise rejection circuit (input
pulse less than 8 system clock time is eliminated as noise). When an interrupt
(Falling edge) is generated by the External interrupt (when enabled), the next
instruction will be fetched from Address 003H.
Before the interrupt subroutine is executed, the contents of ACC and the R3 and R4
register will be saved by hardware. If another interrupt occurred, the ACC, R3 and
R4 will be replaced by the new interrupt. After the interrupt service routine is finished,
ACC, R3 and R4 will be pushed back.
VCC
IRQn
D
CLK
Q
_
Q
PR
/IRQn
INT
RFRD
IRQm
CL
RF
ENI/DISI
IOD
PR
Q
D
_
Q
CLK
CL
IOCFWR
IOCF
/RESET
IOCFRD
RFWR
Figure 6-14 Interrupt Input Circuit
Interrupt
Sources
Interrupt
occurs
ACC
Stack ACC
ENI/DISI
Stack R3
Stack R4
R3
R4
RETI
Figure 6-15 Interrupt Back-up Diagram
46
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
EM78F734N
8-Bit Microcontroller
6.7 Data EEPROM
The Data EEPROM is readable and writable during normal operation over the whole
Vdd range. The operation for Data EEPROM is based on a single byte. A write
operation makes an erase-then-write cycle to take place on the allocated byte.
The Data EEPROM memory provides high erase and write cycles. A byte write
automatically erases the location and writes the new value.
6.7.1 Data EEPROM Control Register
6.7.1.1 RB (EEPROM Control Register)
The EECR (EEPROM Control Register) is the control register for configuring and
initiating the control register status.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RD
WR
EEWE
EEDF
EEPC
-
-
-
Bit 7 (RD):
Bit 6 (WR):
Read control register
0 : Does not execute EEPROM read
1 : Read EEPROM content, (RD can be set by software, RD is
cleared by hardware after Read instruction is completed)
Write control register
0 : Write cycle to the EEPROM is completed.
1 : Initiate a write cycle, (WR can be set by software, WR is cleared
by hardware after Write cycle is completed)
Bit 5 (EEWE): EEPROM Write Enable bit
0 : Write to the EEPROM is prohibited.
1 : Allows EEPROM write cycles
Bit 4 (EEDF): EEPROM Detect Flag
0 : Write cycle is completed
1 : Write cycle is unfinished
Bit 3 (EEPC): EEPROM power-down control bit
0 : Switch off the EEPROM
1 : EEPROM is operating
Bits 2 ~ 0:
Not used, set to “0” at all time
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
47
EM78F734N
8-Bit Microcontroller
6.7.1.2 RC (128 Bytes EEPROM Address)
When accessing the EEPROM data memory, the RC (128 bytes EEPROM address
register) holds the address to be accessed. In accordance with the operation, the RD
(128 bytes EEPROM Data register) holds the data to be written, or the data read, at
the address in RC.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
EE_A6
EE_A5
EE_A4
EE_A3
EE_A2
EE_A1
EE_A0
Bit 7:
Bits 6 ~ 0:
Not used, set to “0” at all time.
128 bytes EEPROM address
6.7.1.3 RD (256 Bytes EEPROM Data)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EE_D7
EE_D6
EE_D5
EE_D4
EE_D3
EE_D2
EE_D1
EE_D0
Bits 7 ~ 0:
128 bytes EEPROM data
6.7.2 Programming Step / Example Demonstration
6.7.2.1 Programming Step
Follow these steps to write to or read data from the EEPROM:
Step 1 Set the RB.EEPC bit to “1” to enable the EEPROM power.
Step 2 Write the address to RC (128 bytes EEPROM address).
1. (a) Set the RB.EEWE bit to 1, if the write function is employed.
(b) Write the 8-bit data value to be programmed in the RD (256 bytes
EEPROM datI(c) Set the RB.WR bit to “1”, then execute the write
function.
2. Set the RB.READ bit to “1”, after which, execute the read function.
Step 3 Wait for the RB.EEDF or RB.WR to be cleared
Step 4 For the next conversion, go to Step 2 as required.
Step 5 If you want to save power, make sure the EEPROM data is not used by
clearing the RB.EEPC.
48
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
EM78F734N
8-Bit Microcontroller
6.7.2.2 Example Demonstration Programs
; Define the control register and write data to EEPROM
RC == 0x0C
RB == 0x0B
RD == 0x0D
Read == 0x07
WR == 0x06
EEWE == 0x05
EEDF == 0x04
EEPC == 0x03
BS RB, EEPC
MOV A,@0x0A
MOV RC,A
BS RB, EEWE
MOV A,@0x55
MOV RD,A
; Set the EEPROM power on
; Assign the address from EEPROM
; Enable the EEPROM write function
; Set the data for EEPROM
BS RB,WR
; Write value to EEPROM
JBC RB,EEDF
; Check whether the EEPROM bit is completed or
not
JMP $-1
6.8 Analog-to-Digital Converter (ADC)
The analog-to-digital circuitry consists of a 9-bit analog multiplexer, three control
registers (AISR/R5 (Bank 2), ADCON/R6 (Bank 2), ADOC/R7 (Bank 2), two data
registers (ADDH, ADDL/R8, R9) and an ADC with 12-bit resolution. The analog
reference voltage (Vref) and analog ground are connected via separate input pins.
The functional block diagram of the ADC is shown below.
The ADC module utilizes successive approximation to convert the unknown analog signal
into a digital value. The result is fed to the ADDH and ADDL. Input channels are
selected by the analog input multiplexer via the ADCON register Bits ADIS2, ADIS1 and
ADIS0.
1/2VDD
ADC7
ADC6
ADC5
ADC4
ADC3
Vref
Power-Down
ADC
ADC2
ADC1
ADC0
Start to Convert
(successive approximation)
Fsc
o
4 - 1
MUX
7 ~ 0
2
1
0
6
11 10
9
8
7
6
5
4
3
2
1
0
4
3
6
5
ADDL
ADDH
ADCON
RF
DATA BUS
ADCON
AISR
ADCON
Figure 6-16 Functional Block Diagram of Analog-to-Digital Conversion
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
49
EM78F734N
8-Bit Microcontroller
6.8.1 ADC Control Register (AISR/R5, ADCON/R6, ADOC/R7)
6.8.2 Bank 2 R5 AISR (ADC Input Select Register)
The AISR register defines the ADC pins as analog input or as digital I/O.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADE7
ADE6
ADE5
ADE4
ADE3
ADE2
ADE1
ADE0
Bit 7 (ADE7): AD converter enable bit of P57 pin.
0 : Disable ADC7, P57 functions as I/O pin.
1 : Enable ADC7 to function as analog input pin
Bit 6 (ADE6): AD converter enable bit of P74 pin.
0 : Disable ADC6, P74 functions as I/O pin.
1 : Enable ADC6 to function as analog input pin
Bit 5 (ADE5): AD converter enable bit of P77 pin
0 : Disable ADC5, P77 functions as I/O pin
1 : Enable ADC5 to function as analog input pin
Bit 4 (ADE4): AD converter enable bit of P73 pin
0 : Disable ADC4, P73 functions as I/O pin
1 : Enable ADC4 to function as analog input pin
Bit 3 (ADE3): AD converter enable bit of P63 pin.
0 : Disable ADC3, P63 functions as I/O pin
1 : Enable ADC3 to function as analog input pin
Bit 2 (ADE2): AD converter enable bit of P62 pin.
0 : Disable ADC2, P62 functions as I/O pin
1 : Enable ADC2 to function as analog input pin
Bit 1 (ADE1): AD converter enable bit of P61 pin
0 : Disable ADC1, P61 functions as I/O pin
1 : Enable ADC1 to function as analog input pin
Bit 0 (ADE0): AD converter enable bit of P60 pin
0 : Disable ADC0, P60 functions as I/O pin
1 : Enable ADC0 to function as analog input pin
The following table shows the priority of P60/AD0//INT.
P60/AD0//INT Pin Priority
Hight
/INT
Medium
AD0
Low
P60
50
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
EM78F734N
8-Bit Microcontroller
6.8.3 Bank 2 R6 ADCON (A/D Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VREFS
CKR1
CKR0
ADRUN
ADPD
ADIS2
ADIS1
ADIS0
Bit 7 (VREFS): Input source of the Vref of the ADC.
0 : Vref of the ADC is connected to the internal reference which is
selected by Bank 2 R9<5,4> (default value), and the P50/VREF
pin carries out the function of P50
1 : Vref of the ADC is connected to P50/VREF
Bit 6 ~ Bit 5 (CKR1 ~ CKR0): Prescaler of oscillator clock rate of ADC
CKR1/CKR0
Operation Mode
FOSC/4
Max. Operation Frequency
00
01
10
11
4 MHz
1 MHz
8 MHz
1 MHz
FOSC
FOSC/16
FOSC/2
Bit 4 (ADRUN): ADC starts to run
0 : Reset upon completion of AD conversion. This bit cannot be reset
by software.
1 : A/D conversion is started. This bit can be set by software.
Bit 3 (ADPD): ADC Power-down mode
0 : Switch off the resistor reference to save power even while the
CPU is operating
1 : ADC is operating
Bits 2~0 (ADIS2~ADIS0): AD Input Select Bits
ADIS2
ADIS1
ADIS0
AD Input Pin
AD0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
AD1
AD2
AD3
AD4
AD5
AD6
AD7
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
51
EM78F734N
8-Bit Microcontroller
6.8.4 Bank 2 R7 ADOC (A/D Offset Calibration Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
PDE
Reserved Reserved
Bits 7~3: Not used, set to “0” at all time.
Bit 2 (PDE): 1/2 VDD Power Detect Enable bit.
0: Disable Power Detect (Default)
1: Enable Power Detect.
PDE
ADIS2
ADIS1
ADIS0
AD Input Select
1
0
x
x
x
1/2VDD
ADx
Bits 1~0: Reserved, must be set to “0” at all time.
6.8.5 ADC Data Buffer (ADDH, ADDL/R8, R9)
When the A/D conversion is completed, the result is loaded to the ADDH, ADDL. The
ADRUN bit is cleared, and the ADIF is set.
6.8.6 A/D Sampling Time
The accuracy, linearity, and speed of the successive approximation A/D converter are
dependent on the properties of the ADC. The source impedance and the internal
sampling impedance directly affect the time required to charge the sample holding
capacitor. The application program controls the length of the sample time to meet the
specified accuracy. Generally speaking, the program should wait for 2µs for each K
of the analog source impedance and at least 2µs for the low- impedance source. The
maximum recommended impedance for analog source is 10K at Vdd=5V. After the
analog input channel is selected, this acquisition time must be done before the
conversion can be started.
Frequency (MHz)
RCM[1:0]*
Sample and Hold Timing
00
01
10
11
4
1
8 x TAD
4 x TAD
12 x TAD
2 x TAD
8
455k
*When using XT, LXT1, HXT1, HXT2 mode can also modify RCM[1:0] At Code Option Word 1
to set the Sample and Hold time.
52
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
EM78F734N
8-Bit Microcontroller
6.8.7 A/D Conversion Time
CKR0 and CKR1 select the conversion time (Tct), in terms of instruction cycles. This
allows the MCU to run at the maximum frequency without sacrificing the accuracy of
A/D conversion. For the EM78F734N, the conversion time per bit is 1µs. The table
below shows the relationship between Tct and the maximum operating frequencies.
Tct vs. Maximum Operation Frequency
CKR0: Operation Max. Operating Max. Conversion
Max. Conversion Rate (12bit)
CKR1
00
Mode
Fosc/4
Fosc
Frequency
4 MHz
Rate Per Bit
1 MHz (1 µs)
1 MHz (1µs)
(12+8)*1µs=20s (50kHz)
(12+4)*1µs=16s(62.5kHz)
(12+12)*2µs=48s (20.8kHz)
(12+4)*2µs=32s (31.25kHz)
01
1 MHz
10
Fosc/16
Fosc/2
8 MHz
0.5 MHz (2 µs)
0.5 MHz (2 µs)
11
1 MHz
NOTE
The pin that is not used as analog input can be used as regular input or output pin.
During conversion, do not perform output instruction to maintain precision for all of
the pins.
6.8.8 A/D Operation during Sleep Mode
In order to obtain a more accurate ADC value and reduced power consumption, the
A/D conversion remains operational during sleep mode. As the SLEP instruction is
executed, all the MCU operations will stop except for the Oscillator, TCC, TC1, TC3,
and A/D conversion.
The AD Conversion is considered completed when:
1
2
ADRUN Bit of R6 Register is cleared to “0”.
Wake-up from A/D Conversion remains in operation during Sleep Mode.
The result is fed to the ADDATA, ADOC when the conversion is completed. If the
ADWE is enabled, the device will wake up. Otherwise, the A/D conversion will be
shut off, no matter what the status of the ADPD bit is.
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
53
EM78F734N
8-Bit Microcontroller
6.8.9 Programming Steps/Considerations
6.8.9.1 Programming Steps
Follow the following steps to obtain data from the ADC:
1. Write to the 8 bits (ADE7~ ADE0) on the R5 (AISR) register to define the
characteristics of R6: Digital I/O, analog channels, and voltage reference pin.
2. Write to the R6/ADCON register to configure the AD module:
a. Select A/D input channel ( ADIS1 ~ ADIS0 ).
b. Define the A/D conversion clock rate ( CKR1 ~ CKR0 ).
c. Select the input source of the VREFS of the ADC.
d. Set the ADPD bit to “1” to begin sampling.
3. Set the ADWE bit, if the wake-up function is employed.
4. Set the ADIE bit, if the interrupt function is employed.
5. Put “ENI” instruction, if the interrupt function is employed.
6. Set the ADRUN bit to “1”.
7. Wait for wake-up or when ADRUN bit is cleared to “0”.
8. Read ADDATA, ADOC the conversion data register.
9. Clear the interrupt flag bit (ADIF) when A/D interrupt function occurs.
10. For the next conversion, repeat from Step 1 or Step 2 as required. At least 2 Tct
is required before the next acquisition starts.
NOTE
To obtain an accurate value, it is necessary to avoid any data transition on the I/O
pins during AD conversion.
6.8.9.2 Sample Demonstration Programs
; To define the General Registers
R_0 == 0
PSW == 3
PORT5 == 5
PORT6 == 6
RE== 0XE
RF== 0XF
; Indirect addressing register
; Status register
; Wake-up control resister
; Interrupt status register
; To define the Control Register
IOC50 == 0X5
IOC60 == 0X6
C_INT== 0XF
; Control Register of Port 5
; Control Register of Port 6
; Interrupt Control Register
; ADC Control Registers
ADDATA == 0x8
; The contents are the results of
ADC
54
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
EM78F734N
8-Bit Microcontroller
AISR == 0x08
ADCON == 0x6
; ADC output select register
; 7
VREFS CKR1 CKR0 ADRUN ADPD
ADIS1 ADIS0
6
5
4
3
2
1
0
; To define bits
; In ADCON
ADRUN == 0x4
ADPD == 0x3
; ADC is executed as the bit is set
; Power Mode of ADC
; Program Starts
ORG 0
JMP INITIAL
ORG 0x30
; Initial address
; Interrupt vector
(User program)
CLR RF
; To clear the ADIF bit
BS ADCON , ADRUN
; To start to execute the next AD
; conversion if necessary
RETI
INITIAL:
MOV A
, @0B00000001
; To define P60 as an analog input
MOV AISR
MOV A
, A
, @0B00001000
; To select P60 as an analog input
; channel, and AD power on
MOV ADCON , A
En_ADC:
; To define P60 as an input pin and
; set clock rate at fosc/16
MOV A
, @0BXXXXXXX1
; To define P60 as an input pin, and
; the others are dependent
; on applications
IOW PORT6
MOV A
, @0BXXXX1XXX
; Enable the ADWE wake-up function
; of ADC, “X” by application
MOV RE
MOV A
, A
, @0BXXXX1XXX
; Enable the ADIE interrupt function
; of ADC, “X” by application
IOW C_INT
ENI
BS ADCON
; Enable the interrupt function
; Start to run the ADC
, ADRUN
; If the interrupt function is ; employed, the following three
lines
; may be ignored
POLLING:
JBC ADCON , ADRUN
; To check the ADRUN bit ;
continuously
JMP
POLLING
; ADRUN bit will be reset as the AD
; conversion is completed
;
(User program)
;
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
55
EM78F734N
8-Bit Microcontroller
6.9 Timer/Counter 1
rising inhibit
edge
detector
capture
control
falling
TC1
interrupt
TC1ES
M
TC1M
TC1 pin
MUX
fc/212
overflow
fc/210
fc/27
8 or16 bit up counter
TC1S
TC1CAP
TC1CK
Comparator
2
capture
capture
TC1CR
TC1DB
TC2DB
TC1DA
TC2DA
TC1MOD
Figure 6-17 Timer / Counter 1 Configuration
In Timer mode, counting up is performed using an internal clock. When the contents
of the up-counter matched the TC1DA, then interrupt is generated and the counter is
cleared. Counting up resumes after the counter is cleared. The current contents of
the up-counter are loaded into TC1DB by setting TC1CAP to “1” and the TC1CAP is
automatically cleared to “0” after capture. The timer mode will operate with 16bits by
setting TC1MOD to “1”
In Counter mode, counting up is performed using an external clock input pin (TC1)
and either rising or falling edge can be selected by TC1ES but both edges cannot be
used. When the contents of the up-counter matched the TC1DA, then interrupt is
generated and the counter is cleared. Counting up resumes after the counter is
cleared. The current contents of the up-counter are loaded into TC1DB by setting
TC1CAP to “1” and the TC1CAP is automatically cleared to “0” after capture. The
counter mode will operate with 16bits by setting TC1MOD to “1”.
In Capture mode, the pulse width, period and duty of the TC1 input pin are
measured in this mode, which can be used to decode the remote control signal. The
counter is free running by the internal clock. On the rising (falling) edge of TC1 pin
input, the contents of counter is loaded into TC1DA, then the counter is cleared and
interrupt is generated. On a falling (rising) edge of TC1 pin input, the contents of the
counter are loaded into TC1DB. The counter is still counting, on the next rising edge
of TC1 pin input, the contents of the counter are loaded into TC1DA, the counter is
cleared and interrupt is generated again. If an overflow before the edge is detected,
the FFH is loaded into TC1DA and the overflow interrupt is generated. During
interrupt processing, it can be determined whether or not there is an overflow by
checking whether or not the TC1DA value is FFH.
56
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
EM78F734N
8-Bit Microcontroller
After an interrupt (capture to TC1DA or overflow detection) is generated, capture and
overflow detection are halted until TC1DA is read out. The capture mode will operate
with 16bits by setting TC1MOD to “1”.
Clock source
Up-counter
K
0
m m+1
K-2
K-1
1
m-1
n-1 n 0
1
2
3
FE FF0
1
2
3
TC1 pin input
TC1DA
K
n
FF (overflow)
overflow
m
FE
TC1DB
capture
capture
TC1 interrupt
Reading TC1DA
Figure 6-18 (a) Timing Chart of 8 bits Capture Mode
Clock source
Up-counter
K
0
m m+1
m-1
K-2
K-1
1
n-1 n 0
1
2
3
FFFE FFFF 0
1
2
3
TC1 pin input
TC2DA,TC1DA
TC2DB,TC1DB
K
n
FFFF (overflow)
FFFE
m
capture
overflow
capture
TC1 interrupt
Reading TC1DA
Figure 6-18 (b) Timing Chart of 16 bits Capture Mode
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
57
EM78F734N
8-Bit Microcontroller
6.10 Timer/Counter 3
Figure 6-19 Timer/Counter 3 Mode Configuration
Timer Mode
In Timer mode, counting up is performed using the internal clock (rising edge trigger).
When the contents of the up-counter matched with TCR3, interrupt is generated and
the counter is cleared. Counting up resumes after the counter is cleared.
Counter Mode
In Counter mode, counting up is performed using the external clock input pin (TC3
pin). When the contents of the up-counter matched with TCR3, interrupt is then
generated and the counter is cleared. Counting up resumes after the counter is
cleared.
Programmable Divider Output (PDO) Mode
In Programmable Divider Output (PDO) mode, counting up is performed using the
internal clock. The contents of TCR3 are compared with the contents of the up-
counter. The F/F output is toggled and the counter is cleared each time a match is
found. The F/F output is inverted and output to /PDO pin. This mode can generate
50% duty pulse output. The F/F can be initialized by program and it is initialized
to “0” during reset. A TC3 interrupt is generated each time the /PDO output is
toggled.
58
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
EM78F734N
8-Bit Microcontroller
Clock Source
Up-counter
2
n
0
1
n-1
n
0
1
3
n-1
n
0
1
n-1
0
1
2
n
TCR3
F/F
/PDO Pin
TC3 Interrupt
Figure 6-20 PDO Mode Timing Diagram
Pulse Width Modulation (PWM) Output Mode
In Pulse Width Modulation (PWM) Output mode, counting up is performed using the
internal clock. The contents of TCR3 are compared with the contents of the up-
counter. The F/F is toggled when a match is found. While the counter is counting,
the F/F is toggled again when the counter overflows, then the counter is cleared. The
F/F output is inverted and output to the /PWM pin. A TC3 interrupt is generated each
time an overflow occurs. TCR3 is configured as a 2-stage shift register and
during output, will not switch until one output cycle is completed even if TCR3
is overwritten. Hence, the output can be changed continuously. Also, on the first
time, TRC3 is shifted by setting TC3S to “1” after data is loaded to TCR3.
Source Clock
n+2
Up-counter
TCR3
n-1
n
n+1 n+2
n+1
m
m-1
0
1
n-1
FE
FF
0
n
FE
FF
0
1
n/n
n/m
m/m
overflow
match
match
overflow
Shift
overwrite
F/F
/PW M
1 period
TC3 Interrupt
Figure 6-21 PWM Mode Timing Diagram
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
59
EM78F734N
8-Bit Microcontroller
6.11 Oscillator
6.11.1 Oscillator Modes
The device can be operated in four different oscillator modes, such as Internal RC
oscillator mode (IRC), High Crystal oscillator mode (HXT), and Low Crystal oscillator
mode (LXT). You can select one of such modes by programming OSC2, OCS1, and
OSC0 in the Code Option register. The following table depicts how these four modes
are defined.
Oscillator Modes defined by OSC2 ~ OSC0
Mode
XT (Crystal oscillator mode)1
HXT1 (High Crystal 1 oscillator mode)2
LXT1 (Low Crystal 1 oscillator mode)3
Reserve
OSC2
OSC1
OSC0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
IRC mode, OSCO (P54) act as I/O pin
IRC mode, OSCO (P54) act as RCOUT pin
HXT2 (High Crystal 2 oscillator mode)4
Reserve
1
2
3
The Frequency range of HXT1 mode is 12 MHz ~ 6 MHz.
The Frequency range of XT mode is 6 MHz ~ 1 MHz.
The Frequency range of LXT1 mode is 1 MHz ~ 100kHz.
4
The Frequency range of HXT2 mode is 20 MHz ~ 12 MHz.
In LXT, XT, HXT modes, OSCI and OSCO are implemented. They cannot be used
as normal I/O pins.
60
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
EM78F734N
8-Bit Microcontroller
In IRC mode, P55 is used as normal I/O pin. The maximum operating frequency of
the crystal/resonator on the different VDD is shown below:
Summary of Maximum Operating Speeds
Conditions
VDD
2.2
Max Fxt. (MHz)
4.0
8.0
Two cycles with two clocks
4.0
5.0
20.0
6.11.2 Crystal Oscillator/Ceramic Resonators (Crystal)
The EM78F734N can be driven by an external clock signal through the OSCI pin as
illustrated below.
OSCI
Ext. Clock
OSCO
Figure 6-22 External Clock Input Circuit
In most applications, Pin OSCI and Pin OSCO can be connected with a crystal or
ceramic resonator to generate oscillation as depicted in the following figure. The
same thing applies to HXT mode or LXT mode.
C1
OSCI
Crystal
OSCO
C2
RS
Figure 6-23 Crystal/Resonator Circuit
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
61
EM78F734N
8-Bit Microcontroller
The following table provides the recommended values of C1 and C2. Since each
resonator has its own attributes, you should refer to its specification for appropriate
values of C1 and C2. A serial resistor RS, may be necessary for AT strip cut crystal
or low frequency mode.
Capacitor Selection Guide for Crystal Oscillator or Ceramic Resonator
Oscillator Type
Frequency Mode
Frequency
100kHz
200kHz
455kHz
1 MHz
C1(pF)
60pF
60pF
40pF
30pF
30pF
30pF
20pF
60pF
60pF
40pF
30pF
C2(pF)
60pF
60pF
40pF
30pF
30pF
30pF
20pF
60pF
60pF
40pF
30pF
LXT1
(100K~1 MHz)
Ceramic Resonators
1.0 MHz
2.0 MHz
4.0 MHz
100kHz
200kHz
455kHz
1 MHz
XT
(1M~6 MHz)
LXT1
(100K~1 MHz)
1.0 MHz
30pF
30pF
XT
2.0 MHz
4.0 MHz
6.0 MHz
6.0 MHz
8.0 MHz
12.0 MHz
12.0 MHz
16.0 MHz
30pF
20pF
30pF
30pF
20pF
30pF
30pF
20pF
30pF
20pF
30pF
30pF
20pF
30pF
30pF
20pF
Crystal Oscillator
(1~6 MHz)
HXT1
(6~12 MHz)
HXT2
(12~20 MHz)
62
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
EM78F734N
8-Bit Microcontroller
6.11.3 Internal RC Oscillator Mode
EM78F734N offers a versatile internal RC mode with default frequency value of 4
MHz. Internal RC oscillator mode has other frequencies (455kHz, 1 MHz and 8 MHz)
that can be set by Code Option (Word 1), RCM1 and RCM0 when COBS =0, or set
by Bank 1 R8 Bits 7, 6 when COBS=1 . All these four main frequencies can be
calibrated by programming the Code Option (Word 1) bits, C6~C0. The table
describes a typical instance of the calibration.
Internal RC Drift Rate (Ta=25 C, VDD=5 V ± 5%, VSS=0V)
Drift Rate
Internal RC
Temperature
(-40C~85C)
Voltage
(2.2V~5.5V)
Process
Total
455KHz
1 MHz
4 MHz
8 MHz
± 2%
± 2%
± 2%
± 2%
± 3.5%
± 3.5%
± 3.5%
± 3.5%
± 1%
± 1%
± 1%
± 1%
± 6.5%
± 6.5%
± 6.5%
± 6.5%
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
63
EM78F734N
8-Bit Microcontroller
6.12 Code Option Register
The EM78F734N has a Code Option Word that is not part of the normal program
memory. The option bits cannot be accessed during normal program execution.
Code Option Register and Customer ID Register arrangement distribution:
Word 0
Word 1
Word 2
Bit 12~Bit 0
Bit 12~Bit 0
Bit 12~Bit 0
6.12.1 Code Option Register (Word 0)
Word 0
Bit
Bit 12 Bit 11 Bit 10
Bit 9
RESETEN
Enable
Disable
0
Bit 8 Bit 7
Bit 6
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mnemonic HLP NRHL NRE
-
-
-
-
ENWDT OSC2 OSC1 OSC0 PR2
PR1
High
Low
0
PR0
High
Low
0
1
0
Low
8/fc Disable
Enable
Disable
0
High
Low
1
High
Low
0
High
Low
0
High
Low
0
High 32/fc Enable
-
-
default
0
0
0
0
0
Bit 12 (HLP): Power consumption selection. (High power consumption mode can
increase the anti-noise functionality. If the operating frequency is 1 MHz or less, and it
is necessary to enhance the anti-noise feature, user can select High power
consumption mode. But High power consumption mode will increase the power
consumption. Please refer to the ninth DC Electrical Characteristics power status
section.)
0: High power consumption, applies to working frequency above
1MHz (default)
1: Low power consumption, applies to working frequency at 1MHz or
below 1MHz
Bit 11 (NRHL): Noise rejection high/low pulse define bit. INT pin is falling edge
trigger.
1 : Pulses equal to 8/fc [s] is regarded as signal
0 : Pulses equal to 32/fc [s] is regarded as signal (default)
Bit 10 (NRE): Noise rejection enable. INT pin is falling edge trigger.
1: Disable noise rejection
0: Enable noise rejection (default)
Bit 9 (RESETEN): Reset Pin Enable Bit
1 : Enable, P83//RESET RESET pin.
0 : Disable, P83//RESET P83 (default)
Bits 8 ~ 7: Not used, always set to “0”
Bit 6 (ENWDT): Watchdog timer enable bit
1 : Enable
0 : Disable
64
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
EM78F734N
8-Bit Microcontroller
Bits 5 ~ 3 (OSC2 ~ OSC0): Oscillator Mode Selection bits
Mode
OSC2
OSC1
OSC0
XT (Crystal oscillator mode)1
HXT1 (High Crystal 1 oscillator mode)2
LXT1 (Low Crystal 1 oscillator mode)3
Reserve
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
IRC mode, OSCO (P54) act as I/O pin
IRC mode, OSCO (P54) act as RCOUT pin
HXT2 (High Crystal 2 oscillator mode)4
Reserve
1
2
3
The Frequency range of HXT1 mode is 12 MHz ~ 6 MHz.
The Frequency range of XT mode is 6 MHz ~ 1 MHz.
The Frequency range of LXT1 mode is 1 MHz ~ 100kHz.
4
The Frequency range of HXT2 mode is 20 MHz ~ 12 MHz.
Bits 2 ~ 0 (PR2 ~ PR0): Protect Bit. PR2~PR0 are protect bits, protect type is as
follows:
PR2
1
PR1
1
PR0
1
Protect
Enable
Disable
0
0
0
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
65
EM78F734N
8-Bit Microcontroller
6.12.2 Code Option Register (Word 1)
Word 1
Bit
Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mnemonic COBS TCEN
C6
C5
C4
C3
C2
C1
C0 RCM1 RCM0 LVR1 LVR0
1
0
High TCC High High High High High High High High High High High
Low
0
P77
0
Low
0
Low
0
Low
0
Low
0
Low
0
Low
0
Low
0
Low
0
Low
0
Low
0
Low
0
default
Bit 12 (COBS): Code Option Bit Selection
0 : IRC frequency select for code option (default)
1 : IRC frequency select internal register by Bank 1 R8(7,6)
Bit 11 (TCEN): TCC enable bit
0 : P77/TCC is set as P77
1 : P77/TCC is set as TCC
Bits 10 ~ 4 (C6 ~ C0): Internal RC mode calibration bits. (IRC frequency auto
calibration)
Bits 3 ~ 2 (RCM1 ~ RCM0): RC mode selection bits
RCM 1
RCM 0
*Frequency (MHz)
0
0
1
1
0
1
0
1
4
1
8
455k
Bits 1 ~ 0 (LVR1 ~ LVR0): Low voltage reset enable bits
LVR1 LVR0
Reset Level
NA
Release Level
0
0
1
1
0
1
0
1
NA
2.5V
2.6V
3.0V
3.3V
2.9V
3.2V
Note: LVR1, LVR0=“0, 0”: LVR disabled, power-on reset point of EM78F734N
is 1.9V.
LVR1, LVR0=“0, 1”: If Vdd < 2.5V, the EM78F734N will reset.
LVR1, LVR0=“1, 0”: If Vdd < 2.9V, the EM78F734N will reset.
LVR1, LVR0=“1, 1”: If Vdd < 3.2V, the EM78F734N will reset.
66
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
EM78F734N
8-Bit Microcontroller
6.12.3 Code Option Register (Word 2)
Word 2
Bit
Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Bit 7
SC2 SC1 SC0 EFTIM
High High High 20MHz
Low Low Low 10MHz
Bit 6 Bit 5 Bit 4
Bit 3
IRE
Bit 2 Bit 1 Bit 0
Mnemonic SC4 SC3
-
-
-
-
SFS
-
-
-
-
-
-
1
0
High High
Low Low
128kHz Enable
16kHz Disable
-
-
-
-
-
Default
0
0
0
0
0
1
0
0
0
0
0
0
0
Bits 12 ~ 8 (SC4 ~ SC0): Calibrator of sub frequency (WDT frequency auto
calibration)
Bit 7 (EFTIM): EFT improvement. If the MCU is at VDD=5V with working frequency
of <12 MHz, or at VDD=3V with working frequency of <6 MHz, enabling
this function can improve the performance of the electrical fast transient
(EFT) test. If the MCU is at VDD=5V and the working frequency is >12
MHz, choose EFTIM=1
0: 10 MHz
1: 20 MHz
Bits 6 ~ 5:
Not used, always set to “0”
Bits 4 (SFS): Sub-frequency select.
0: 16kHz (WDT frequency)
1: 128kHz
Bit 3 (IRE):
Bits 2 ~ 0:
IRC Regulator Enable bit
0: Disable regulator for saving power but more error of IRC.
1: Enable regulator for improving IRC accurately but more power
consumed.
Not used, always set to “0”
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
67
EM78F734N
8-Bit Microcontroller
6.13 Power-on Considerations
Any microcontroller is not guaranteed to start to operate properly before the power
supply stays has stabilized. The EM78F734N has an on-chip Power-on Voltage
Detector (POVD) with a detecting level of 2.0V. It will work well if Vdd can rise
quickly enough (50ms or less). In many critical applications, however, extra devices
are still required to assist in solving power-up problems.
6.14 External Power-on Reset Circuit
The circuit shown in Figure 6-24 uses an external RC to generate a reset pulse. The
pulse width (time constant) should be kept long enough for Vdd to reached minimum
operation voltage. This circuit is used when the power supply has slow rise time.
Because the current leakage from the /RESET pin is 5A, it is recommended that R
should not be greater than 40K. In this way, the /RESET pin voltage is held below
0.2V. The diode (D) functions as a short circuit at the moment of power down.
The capacitor C will discharge rapidly and fully. Rin, the current-limited resistor, will
prevent high current or ESD (electrostatic discharge) from flowing to pin /RESET.
Vdd
R
/RESET
D
Rin
C
Figure 6-24 External Power-up Reset Circuit
68
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
EM78F734N
8-Bit Microcontroller
6.15 Residue-Voltage Protection
When battery is replaced, device power (Vdd) is taken off but residue-voltage
remains. The residue-voltage may trip below Vdd minimum, but not to zero. This
condition may cause a poor power-on reset. Figure 6-25 and Figure 6-26 show how
to build a residue-voltage protection circuits.
Vdd
Vdd
33K
Q1
10K
/RESET
40K
1N4684
Figure 6-25 Circuit 1 for the Residue Voltage Protection
Vdd
Vdd
R1
Q1
/RESET
R2
40K
Figure 6-26 Circuit 2 for the Residue Voltage Protection
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
69
EM78F734N
8-Bit Microcontroller
6.16 Instruction Set
Each instruction in the instruction set is a 13-bit word divided into an OP code and
one or more operands. Normally, all instructions are executed within one single
instruction cycle (one instruction consists of two oscillator periods), unless the
program counter is changed by instru“tion "MO” R“,A", "AD” R2,A", or by instructions
of arithmetic or logic operation on R2 “e.g. "SU” R“,A", "BS(C” R“,6", "”LR R2", ). In
this case, the execution takes two instruction cycles.
(300)If for some reasons, the specification of the instruction cycle is not suitable for
certain applications, try modifying the instruction as fol“(A)” "“MP",”"C“LL"”
"“ET",”"R“TL",”"RETI" commands are executed with one instruction cycle, the
conditional “kip”("“BS"” "“BC”, “JZ"” "“ZA"” "“JZ",”"DJZA") commands which were
tested to be true, are executed within two instruction cycles. The instructions that
are written to the program counter also take two instruction cycles.
In addition, the instruction set has the following features:
(1) Every bit of any register can be set, cleared, or tested directly.
(2) The I/O register can be regarded as general register. That is, the same
instruction
can operate on the I/O register.
70
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
EM78F734N
8-Bit Microcontroller
Instruction Set Table:
The following symbols are used in the following table:
“R” Register designator that specifies which one of the registers (including operation and
general purpose registers) is to be utilized by the instruction.
“b” Bit field designator that selects the value for the bit located in the register R and which
affects the operation.
“K” 8 or 10-bit constant or literal value
Mnemonic
NOP
Operation
Status Affected
No Operation
Decimal Adjust A
A CONT
None
DAA
C
CONTW
SLEP
None
0 WDT, Stop oscillator
0 WDT
T, P
WDTC
T, P
IOW R
A IOCR
Enable Interrupt
Disable Interrupt
[Top of Stack] PC
[Top of Stack] PC, Enable Interrupt
CONT A
IOCR A
A R
None1
ENI
None
DISI
None
RET
None
RETI
None
CONTR
IOR R
None
None1
MOV R,A
CLRA
None
0 A
Z
CLR R
0 R
Z
SUB A,R
SUB R,A
DECA R
DEC R
OR A,R
OR R,A
AND A,R
AND R,A
XOR A,R
XOR R,A
ADD A,R
ADD R,A
MOV A,R
MOV R,R
COMA R
COM R
INCA R
INC R
R-A A
Z, C, DC
R-A R
Z, C, DC
R-1 A
Z
R-1 R
Z
A R A
A R R
A & R A
A & R R
A R A
A R R
A + R A
A + R R
R A
Z
Z
Z
Z
Z
Z
Z, C, DC
Z, C, DC
Z
Z
Z
Z
Z
Z
R R
/R A
/R R
R+1 A
R+1 R
1
This instruction is applicable to IOC5~IOC7, IOCA ~ IOCF only.
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
71
EM78F734N
8-Bit Microcontroller
Mnemonic
Operation
Status Affected
DJZA R
DJZ R
R-1 A, skip if zero
R-1 R, skip if zero
None
None
R(n) A(n-1),
RRCA R
RRC R
C
C
R(0) C, C A(7)
R(n) R(n-1),
R(0) C, C R(7)
R(n) A(n+1),
RLCA R
RLC R
C
R(7) C, C A(0)
R(n) R(n+1),
R(7) C, C R(0)
C
R(0-3) A(4-7),
R(4-7) A(0-3)
SWAPA R
None
SWAP R
JZA R
R(0-3) R(4-7)
R+1 A, skip if zero
R+1 R, skip if zero
0 R(b)
None
None
None
None2
None3
None
None
JZ R
BC R,b
BS R,b
JBC R,b
JBS R,b
1 R(b)
if R(b)=0, skip
if R(b)=1, skip
PC+1 [SP],
(Page, k) PC
CALL k
None
JMP k
(Page, k) PC
k A
None
MOV A,k
OR A,k
AND A,k
XOR A,k
None
A k A
A & k A
A k A
Z
Z
Z
k A,
[Top of Stack] PC
RETL k
None
SUB A,k
ADD A,k
BANK k
k-A A
Z, C, DC
Z, C, DC
None
k+A A
K R4(7:6)
Next instruction : k kkkk kkkk kkkk
PC+1[SP], kPC4
LCALL k
LJMP k
None
None
Next instruction : k kkkk kkkk kkkk
kPC4
If Bank 3 R6.7=0, machine code (7:0) R
Else machine code (12:8) R(4:0),
R(7:5)=(0,0,0)
TBRD R
None
2 This instruction is not recommended for interrupt status register operation.
3 This instruction cannot operate under interrupt status register.
72
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
EM78F734N
8-Bit Microcontroller
7 Timing Diagrams
AC Test Input/Output Waveform
2.4
2.0
0.8
2.0
0.8
TEST POINTS
.0.4
AC Testing: Input are driven at 2.4V for logic “1” and 0.4V for logic “0”.
Timing measurements are made at 2.0V for logic “1”, and 0.8V for logic “0”.
Figure 7-1 AC Test Timing Diagram
Reset Timing (CLK=“0”)
Instruction 1
NOP
Executed
CLK
/RESET
Tdrh
Figure 7-2 Reset Timing Diagram
TCC Input Timing (CLKS=”0”)
ins
CLK
TCC
tcc
Figure 7-3 TCC Input Timing Diagram
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
73
EM78F734N
8-Bit Microcontroller
8 Absolute Maximum Ratings
EM78F734N
Items
Rating
Temperature under bias
Storage temperature
Working voltage
-40C
-65C
2.2
to
to
to
to
to
to
85C
150C
5.5V
Working frequency
Input voltage
DC
20 MHz*
Vdd+0.5V
Vdd+0.5V
Vss-0.3V
Vss-0.3V
Output voltage
Note: *These parameters are theoretical values and have not been tested.
74
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
EM78F734N
8-Bit Microcontroller
9 DC Electrical Characteristics
VDD=5.0V, VSS=0V, Ta=25 C
Symbol
Parameter
Crystal: VDD to 3V
Condition
Min.
DC
Typ.
Max. Unit
MHz
-
-
4
Two cycles with two clocks
Fxt
Crystal: VDD to 5V
IRC: VDD to 5 V
DC
20 MHz
4 MHz, 455kHz, 1 MHz,,8 MHz F30
F
-
F30 Hz
Input Leakage Current for input
pins
-
1
A
IIL
VIN = VDD, VSS
Input High Threshold Voltage
(Schmitt Trigger )
VIHRC
VILRC
IIL
OSCI in RC mode
OSCI in RC mode
VIN = VDD, VSS
Ports 5, 6, 7, 8
3.9
4
1.8
0
4.1
V
V
Input Low Threshold Voltage
(Schmitt Trigger )
1.7
1.9
Input Leakage Current for input
pins
-1
-
1
-
-
-
-
-
-
A
V
Input High Voltage (Schmitt
trigge )
0.7VDD
(2.8V)
VIH1
VIL1
0.3VDD
(2.2V)
Input Low Voltage (Schmitt trigger) Ports 5, 6, 7, 8
-
V
Input High Threshold Voltage
/RESET
VIHT1
VILT1
VIHT2
VILT2
-
0.7VDD
0.3VDD
0.7VDD
0.3VDD
V
(Schmitt Trigger )
Input Low Threshold Voltage
/RESET
-
V
(Schmitt trigger )
Input High Threshold Voltage
TCC, INT
-
V
(Schmitt Trigger )
Input Low Threshold Voltage
TCC, INT
-
V
(Schmitt Trigger )
VIHX1 Clock Input High Voltage
VILX1 Clock Input Low Voltage
OSCI in crystal mode
OSCI in crystal mode
2.9
1.7
3.0
1.8
3.1
1.9
V
V
Note: * The parameters are theoretical and have not been tested or verified.
* Data in the Minimum, Typical, Maximum (“Min.”, “T“p.”, "Max.”) column are based on hypothetical
results at 25C. These data are for design guidance only.
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
75
EM78F734N
8-Bit Microcontroller
(Continuation)
Symbol
Parameter
Condition
VOH = 0.9VDD
Min.
Typ. Max. Unit
High Drive Current
(Ports 5, 6, 7, 8)
IOH1
IOL1
-2.5
-
-
-
-
mA
mA
Low Sink Current
(Ports 5, 6, 7, 8)
VOL = 0.1VDD
10
IPH
IPL
Pull-high current
Pull-low current
Pull-high active, input pin at VSS
Pull-low active, input pin at Vdd
Ta = 25C
-
-
-95
40
A
A
V
-
-
2.13
1.72
2.48
2.05
2.72
2.25
2.6
2.6
3.0
3.0
3.3
3.3
3.07
3.46
3.51
3.93
3.86
4.3
Low voltage reset level 1
(2.6V)
LVR1
LVR2
LVR3
Ta = -40C ~ 85C
Ta = 25C
V
V
Low voltage reset level 1
(3.0V)
Ta = -40C ~ 85C
Ta = 25C
V
V
Low voltage reset level 1
(3.3V)
Ta = -40C ~ 85C
V
All input and I/O pins at VDD, output
pin floating, WDT disabled
ISB1
ISB2
Power down current
Power down current
-
-
-
-
2
5
A
A
All input and I/O pins at VDD, output
pin floating, WDT enabled
/R‘SET=’'High', Fosc=455kHz (IRC
type), Voltage = 3V, output pin
floating, WDT enabled, HLP='High'
Operating supply current
at two clocks
ICC1
ICC5
ICC2
ICC6
ICC3
ICC4
-
-
-
-
-
-
96
-
-
-
-
-
-
µA
µA
µA
µA
mA
mA
/RESET= 'High', Fosc=455kHz (IRC
type), Voltage = 3V, output pin
Operating supply current
at two clocks
84.5
170
160
1.3
floating, WDT enabled, HLP='Low'
/R‘SET=’'High', Fosc=1MHz (IRC
type), Voltage = 3V, output pin
floating, WDT enabled, HLP='High'
Operating supply current
at two clocks
/RESET= 'High', Fosc=1 MHz (IRC
type), Voltage = 3V, output pin
floating, WDT enabled, HLP='Low'
Operating supply current
at two clocks
/R‘SET=’'High', Fosc=4 MHz (Crystal
type), output pin floating, WDT
enabled
Operating supply current
at two clocks
/R‘SET=’'High', Fosc=10 MHz (Crystal
type), output pin floating, WDT
enabled
Operating supply current
at two clocks
3.25
76
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
EM78F734N
8-Bit Microcontroller
NOTE
The above parameters are theoretical values only and have not been tested or
verified.
Data under the “Min.”, “Typ.”, and “Max.” (Minimum, Typical, and Maximum)
columns are based on hypothetical results at 25C. These data are for design
reference only.
9.1 Data EEPROM Electrical Characteristics
Symbol
Tprog
Parameter
Erase/Write cycle time
Data Retention
Condition
Min.
Typ.
-
Max.
Unit
ms
-
-
-
-
-
-
Vdd = 2.2V~ 5.5V
Treten
Tendu
10
Years
Cycles
Temperature = -40C ~ 85C
Endurance time
100K
9.2 Program Flash Memory Electrical Characteristics
Symbol
Tprog
Parameter
Erase/Write cycle time
Data Retention
Condition
Min.
Typ.
-
Max.
Unit
ms
-
-
-
-
-
-
Vdd = 5.0V
Temperature = -40C ~ 85C
Treten
Tendu
10
Years
Cycles
Endurance time
100K
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
77
EM78F734N
8-Bit Microcontroller
9.3 A/D Converter Characteristics
VDD=5.0V, VSS=0V, Ta=25 C
Type
Parameter
Symbol
Test Conditions
Unit
Min. Typ. Max.
For 5.5v Fs=100KHz, Fin=2KHz,
For 2.2v Fs=50KHz, Fin=1KHz
Vdd
2.2
2.2
-
-
5.5
V
V
Operating Range
VREFT
Vdd
Ivdd
Iref
-
-
-
-
0.5 mA
VREFT= Vdd=5.5v,
Fs=100KHz, Fin=2KHz
Current Consumption
50
uA
uA
Standby Current
ZAI
Isb
ZAI
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
10k ohm
dBc
-70 dBc
dBc
-73 dBc
dBc
VREFT= Vdd=3.3v,
Fs=100kHz, Fin=2kHz
SNR
SNR
THD
SNDR
WH
70
-
-
VREFT= Vdd=3.3v,
Fs=100kHz, Fin=2kHz
THD
VREFT= Vdd=3.3v,
Fs=100kHz, Fin=2kHz
SNDR
68
-
-
VREFT= Vdd=3.3v,
Fs=100kHz, Fin=2kHz
Worst Harmonic
SFDR
VREFT= Vdd=3.3V,
Fs=100kHz, Fin=2kHz
SFDR
OE
73
-
-
VREFT= Vdd=3.3V,
Offset Error
Gain Error
DNL
+/-4 LSB
+/-8 LSB
+/-1 LSB
+/-4 LSB
Fs=100kHz
VREFT= Vdd=3.3V,
GE
-
Fs=100kHz
VREFT= Vdd=3.3V,
Fs=100kHz, Fin=2kHz
DNL
INL
-
VREFT= Vdd=3.3V,
Fs=100kHz, Fin=2kHz
INL
-
K
SPS
Fs1
Vdd=2.7~5.5V, Fin=2kHz
100
50
-
-
Conversion Rate
Vdd=2.2~2.7V,
Fin=1kHz
K
SPS
Fs2
VREFT=2.2V,
SVREF=”0”or”1”, Vdd=2.2V ~ 5.5V,
Fs=50kHz, Vin=0V ~ 2.2V
Power Supply Rejection
Ratio
PSRR
-
-
2
LSB
Note: 1These parameters are hypothetical (not tested) and are provided for design reference only.
2There is no current consumption when ADC is off other than minor leakage current.
3The A/D conversion result will not decrease with an increase in the input voltage, and has
no missing code.
4These parameters are subject to change without prior notice.
78
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
EM78F734N
8-Bit Microcontroller
10 AC Electrical Characteristics
EM78F734N, 0 Ta 70 C, VDD=5V, VSS=0V
-40 Ta 85 C, VDD=5V, VSS=0V
Symbol
Parameter
Conditions
Min.
Typ.
50
Max.
55
DC
DC
Unit
%
Dclk
Input CLK duty cycle
45
Crystal type
100
ns
Instruction cycle time
Tins
”C”KS="0")
RC type
500
ns
Ttcc
TCC input period
(Tins+20)/N*
ns
Tdrh
Trst
Device reset hold time
/RESET pulse width
Watchdog timer period
Input pin setup time
Input pin hold time
Output pin delay time
Ta = 25C
Ta = 25C
11.8
2000
11.8
16.8
21.8
ms
ns
Twdt
Tset
16.8
0
21.8
ms
ns
Thold
Tdelay
20
50
ns
Cload=20pF
ns
Note: These parameters are theoretical values and have not been tested. Such parameters are for
design
reference only.
Data in the Minimum, Typical, Maximum (“Min.”, “Typ.”, ”Max.”) columns are based on
characterization results at 25C.
* N = selected prescaler ratio
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
79
EM78F734N
8-Bit Microcontroller
APPENDIX
A Ordering and Manufacturing Information
EM78F734ND20J
Material Type
J: RoHS complied
S: Sony SS-00259 complied
Contact Elan Sales for details
Pin Number
Package Type
D: DIP
SO: SOP
Check the following section
Specific Annotation
Product Number
Product Type
F: Flash
Elan 8-bit Product
For example:
EM78F734NSO20S
is EM78F734N with Flash program memory, product,
in 20-pin SOP 300mil package with Sony SS-00259 complied
IC Mark
‧‧‧‧‧‧‧
Elan Product Number / Package, Material Type
Batch Number
EM78Paaaaaa
1041c bbbbbb
Manufacture Date
“YYWW”
YY is year and WW is week
c is Alphabetical suffix code for Elan use only
‧‧‧‧‧‧‧
80
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
EM78F734N
8-Bit Microcontroller
Ordering Code
EM78F734ND20J
Material Type
Contact Elan Sales for details
Package Type / Pin Number
Check the following section
Elan IC Product Number
B Package Type
Flash MCU
EM78F734ND20
EM78F734NSO20
EM78F734NSS20
EM78F734NSS20A
EM78F734NQN20
EM78F734ND18
EM78F734NSO18
EM78F734ND16
EM78F734NSO16
EM78F734NSO16A
EM78F734NSS16
Package Type
Pin Count
Package Size
PDIP
SOP
20
20
20
20
20
18
18
16
16
16
16
300 mil
300 mil
209 mil
150 mil
4*4*0.8mm
300 mil
300 mil
300 mil
300 mil
150 mil
150 mil
SSOP
SSOP
QFN
PDIP
SOP
PDIP
SOP
SOP
SSOP
These are Green products which do not contain hazardous substances and comply
with the third edition of Sony SS-00259 standard.
Pb contents should be less than 100ppm and complies with Sony specifications.
Part No.
Electroplate type
EM78F734NS/J
Pure Tin
Sn:100%
232°C
Ingredient (%)
Melting point (°C)
Electrical resistivity (µ cm)
Hardness (hv)
11.4
8~10
Elongation (%)
>50%
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
81
EM78F734N
8-Bit Microcontroller
C Package Information
C.1 EM78F734ND16 300mil
Figure C-1 EM78F734N 16-Pin PDIP Package Type
82
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
EM78F734N
8-Bit Microcontroller
C.2 EM78F734NSO16 300mil
Figure C-2 EM78F734N 16-Pin SOP Package Type
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
83
EM78F734N
8-Bit Microcontroller
C.3 EM78F734NSO16A 150mil
b
e
c
TITLE:
SOP-16L(150MIL) PACKAGE OUTLINE
DIMENSION
File :
Edtion: A
NSO16
Unit : mm
Scale: Free
Material:
Sheet:1 of 1
Figure C-3 EM78F734N 16-Pin SOP Package Type
84
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
EM78F734N
8-Bit Microcontroller
C.4 EM78F734NSS16 150mil
Package Type : SSOP-16L
EMC(mm )
Symbal
Min
1.35
Normal
Max
1.75
0.25
1.50
0.30
0.28
0.25
0.23
5.00
6.20
3.99
1.27
1.63
A
A1
A2
b
0.10
-
0.18
-
0.20
0.20
0.18
0.18
4.80
5.79
3.81
0.41
-
b1
c
0.25
-
0.20
c1
D
E
4.90
5.99
E1
L
3.91
0.64
e
0.635BASIC
-
θ
0°
8°
TITLE:
SSOP 16L (150MIL)PACKAGE OUTLINE
DIMENSION
File :
SSOP 16L
Edtion: A
Unit : mm
Scale: Free
Material:
Sheet:1 of 1
Figure C-4 EM78F734N 16-Pin SSOP Package Type
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
85
EM78F734N
8-Bit Microcontroller
C.5 EM78F734ND18 300mil
Figure C-5 EM78F734N 18-Pin PDIP Package Type
86
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
EM78F734N
8-Bit Microcontroller
C.6 EM78F734NSO18 300mil
Symbal
Min
2.350
0.102
Normal
Max
2.650
0.300
A
A1
b
0.406(TYP)
c
E
0.230
7.400
0.320
7.600
H
D
L
10.000
11.350
0.406
10.650
11.750
1.270
0.838
1.27(TYP)
e
θ
0
8
b
e
c
TITLE:
SOP-18L(300MIL) PACKAGE
OUTLINE DIMENSION
File :
Edtion: A
SO18
Unit : mm
Scale: Free
Material:
Sheet:1 of 1
Figure C-6 EM78F734N 18-Pin SOP Package Type
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
87
EM78F734N
8-Bit Microcontroller
C.7 EM78F734ND20 300mil
Symbal Min Normal Max
E
A
A1
A2
c
4.450
0.381
3.175
3.302
3.429
0.203 0.254 0.356
D
25.883 26.060 26.237
E1
E
eB
B
B1
L
e
6.220
7.370
8.510
6.438
7.620
9.020
6.655
7.870
9.530
0.356 0.457 0.559
1.143 1.524 1.778
3.048 3.302 3.556
2.540(TYP)
θ
0
15
TITLE:
PDIP-20L 300MIL PACKAGE
OUTLINE DIMENSION
File :
Edtion: A
D20
Unit : mm
Scale: Free
Material:
Sheet:1 of 1
Figure C-7 EM78F734N 20-Pin PDIP Package Type
88
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
EM78F734N
8-Bit Microcontroller
C.8 EM78F734NSO20 300mil
Figure C-8 EM78F734N 20-Pin SOP Package Type
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
89
EM78F734N
8-Bit Microcontroller
C.9 EM78F734NSS20 209mil
Symbal
Min
Normal
Max
2.130
0.250
1.880
0.380
0.200
8.200
5.600
7.500
0.850
A
A1
A2
b
c
E
E1
D
L
0.050
1.620
0.220
0.090
7.400
5.000
6.900
0.650
1.750
7.800
5.300
7.200
0.750
L1
e
θ
1.250(REF )
0.650(TYP)
4
0
8
b
e
c
TITLE:
L1
SSOP-20L(209MIL) OUTLINE
PACKAGE PACKA OUTLINE
DIMENSION
File :
Edtion: A
SSOP20
Unit : mm
Scale: Free
Material:
Sheet:1 of 1
Figure C-9 EM78F734N 20-Pin SSOP Package Type
90
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
EM78F734N
8-Bit Microcontroller
C.10 EM78F734NSS20A 150mil
Figure C-10 EM78F734N 20-Pin SSOP Package Type
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
91
EM78F734N
8-Bit Microcontroller
C.11 EM78F734NQN20 4*4*0.8mm
Figure C-11 EM78F734N 20-Pin QFN Package Type
92
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
EM78F734N
8-Bit Microcontroller
D Quality Assurance and Reliability
Test Category
Test Conditions
Remarks
Solder temperature=2455°C, for 5 seconds up to the
stopper using a rosin-type flux
Solderability
–
Step 1: TCT, 65°C (15mins)~150°C (15mins), 10 cycles
Step 2: Bake at 125°C, TD (endurance)=24 hrs
Step 3: Soak at 30°C/60%，TD (endurance)=192 hrs
Step 4: IR flow 3 cycles
For SMD IC (such as
SOP, QFP, SOJ, etc)
Pre-condition
(Pkg thickness 2.5mm or
Pkg volume 350mm3 ----2255°C)
(Pkg thickness 2.5mm or
Pkg volume 350mm3 ----2405°C)
Temperature cycle test
Pressure cooker test
-65°C (15mins)~150°C (15mins), 200 cycles
–
–
TA =121°C, RH=100%, pressure=2 atm,
TD (endurance)= 96 hrs
High temperature /
High humidity test
TA=85°C , RH=85%，TD (endurance) = 168 , 500 hrs
–
–
High-temperature
storage life
TA=150°C, TD (endurance) = 500, 1000 hrs
High-temperature
operating life
TA=125°C, VCC = Max. operating voltage,
TD (endurance) = 168, 500, 1000 hrs
–
–
Latch-up
TA=25°C, VCC = Max. operating voltage, 150mA/20V
IP_ND,OP_ND,IO_ND
IP_NS,OP_NS,IO_NS
IP_PD,OP_PD,IO_PD,
IP_PS,OP_PS,IO_PS,
ESD (HBM)
TA=25°C, ∣ ± 3KV∣
ESD (MM)
TA=25°C, ∣ ± 300V∣
VDD-VSS(+),VDD_VSS
(-) mode
D.1 Address Trap Detect
An address trap detect is one of the MCU embedded fail-safe functions that detects
MCU malfunction caused by noise or the like. Whenever the MCU attempts to fetch
an instruction from a certain section of ROM, an internal recovery circuit is auto
started. If a noise-caused address error is detected, the MCU will repeat execution of
the program until the noise is eliminated. The MCU will then continue to execute the
next program.
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
93
EM78F734N
8-Bit Microcontroller
94
Product Specification (V1.4) 09.05.2019
(This specification is subject to change without prior notice)
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明