EM78569 [ELAN]
8-BIT MICRO-CONTROLLER; 8位微控制器
| 型号： | EM78569 |
| 厂家： | 
ELAN MICROELECTRONICS CORP |
| 描述： | 8-BIT MICRO-CONTROLLER |
| 文件： | 总53页 (文件大小：459K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EM78569
8-BIT MICRO-CONTROLLER
Version 4.0
ELAN MICROELECTRONICS CORP.
No. 12, Innovation 1st RD., Science-Based Industrial Park
Hsin Chu City, Taiwan, R.O.C.
TEL: (03) 5639977
FAX: (03) 5630118
Version History
Specification Revision History
Version
Content
Release Date
EM78569
1.0
3.1
3.2
Initial version
Modify Multiplier architecture
1. Move DARES bit from bit7 to bit3.
2. Change instruction “MUL” Æ “INT A”
3. Modify Sink/Driver current
2002/06/10
2003/3/10
2003/5/2
3.3
3.4
1. Update Application Note
2. Add 17.91MHz main CLK
2003/6/9
2003/8/1
1. Add data RAM address auto-increase function
2. Add mclk/2 signal output. (output shared with PC0)
3. Add carry bit calculation function.(ADD, SUB)
1. Modify code option define.
1. ADD the description about ADC’s offset voltage
1. Decrease stack from 16 to 12
3.5
3.6
3.7
2003/9/17
2003/10/22
2004/4/10
2. Modify the operating temperature
3. Modify Port9 sink/driver current
Add the OSC stable and reset timing diagram
Modify Normal mode power consumption
Remove IDLE mode
3.8
3.9
4.0
2004/7/2
2004/8/19
2004/8/31
Modify operating temperature
User Application Note
(Before using this chip, take a look at the following description note, it includes important messages.)
1. There are some undefined bits in the registers. The values in these bits are unpredicted. These bits are not allowed to
use. We use the symbol “-” in the spec to recognize them.
2. You will see some names for the register bits definitions. Some name will be appear very frequently in the whole spec.
The following describes the meaning for the register’s definitions such as bit type, bit name, bit number and so on.
RA
PAGE0
7
6
5
4
3
-
2
RAB2
R
1
0
RAB1
RAB7
R/W-0
RAB6
R/W-0
BAB5
R-1
RAB4
R/W-1
RAB0
R/W
R-0
read/write
(default value=1)
read/write
(w/o default value)
read/write
(default value=0)
read only
(w/o default value)
Bit type
Bit name
(undefined) not allowed to use
Bit number
read only
(default value=1)
read only
(default value=0)
Register name and its page
3. Please set 1 to RA page2 bit7 or LCD waveform will difference between mask and romless.
4. Please set IOCC PAGE1 bit0 to “1” otherwise partial ADC function cannot be used
5. For 8 bits resolution DAC, DAO pin will output corresponding voltage after write new data to DAC data buffer(RA
PAGE1). For 10 bits resolution, DAO pin will output constant after change DAC most significant 2 bits (R5 PAGE1
bit6~7). DAO will output correct voltage after write data to least significant 8 bits. That is to say, when using 10 bits
resolution DAC, user must write most significant 2 bits and least significant 8 bits in order.
6. Base on “VERSEL”(code option) equal 0 or 1, R8 page1 and RB page2’s define are different.
“VERSEL” = 0: R8 page1 defined to data RAM address buffer
RB page2 defined to multiplier’s Y data or Y address buffer (controlled by RA page2 bit5 “INDR”).
EM78569
8-bit Micro-controller
RA page2 bit4(PLUS) determine RAM address auto increase or not (only for multiplier’s addressing).
RA page2 bit7 is undefined.
“VERSEL” = 1: R8 page1 is undefined.
RA page2 bit4(PLUS) determine RAM address auto increase or not (for data RAM and multiplier’s
addressing).
RA page2 bit7(INS) determine
.
RB page2 defined to multiplier’s Y data, Y address or data RAM address buffer.
7. The carry bit’s initial value is un-know, please define the initial value before execute first ADD or SUB instruction that
include carry bit.(VERSEL =1 and INS = 1)
8. In EM78569’s developing tool, “VERSEL” and “PHO” are at RD page2 bit6 and bit5, but in mask chip, these two bits
will mapping to code option. Please set these two bits to fixed value at initial and do not change these two bit
among your program.
9. While switching main clock (regardless of high freq to low freq or on the other hand), adding 6 instructions delay (NOP)
is required.
10. Please do not switch MCU operation mode from normal mode to sleep mode directly. Before into sleep mode, please
switch MCU to green mode.
11. Offset voltage will effect ADC’s result, please refer to figure 20 to detail.
The differences between ICE569, EM78P569 and EM78569.
ICE569
EM78P569
EM78569
12
Stack
16
16
VERSEL, PHO
RD page0 bit5,6
Code option
Code option
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
1
8/31/2004 (V4.0)
EM78569
8-bit Micro-controller
I. General Description
The EM78569 is an 8-bit RISC type microprocessor with low power, high speed CMOS technology. This
integrated single chip has an on_chip watchdog timer (WDT), program ROM, data RAM, LCD driver, programmable
real time clock/counter, internal interrupt, power down mode, built-in three-wire SPI, dual PWM(Pulse Width
Modulation), 10-bit A/D converter, 10-bit DA converter and tri-state I/O.
II. Feature
CPU
· Operating voltage : 2.2V~5.5V at main CLK less then 3.58MHz.
Main CLK(Hz)
Under 3.58M
7.16M
10.74M
14.4M
3.6
17.9M
4V
Operating Voltage(min)
2.2
2.5
3
· 16k x 13 on chip Program ROM.
· 1k x 8 on chip data RAM
· Up to 51 bi-directional tri-state I/O ports(22 pin shared with LCD)
· 12 level stack for subroutine nesting
· 8-bit real time clock/counter (TCC)
· Two 8-bit counters : COUNTER1 and COUNTER2
· On-chip watchdog timer (WDT)
· 99.9％ single instruction cycle commands
‧ Three modes (Main clock can be programmed from 447.829k to 17.9MHz generated by internal PLL)
Mode
Sleep mode
Green mode
CPU status
Turn off
Turn on
Main clock
Turn off
Turn off
Turn on
32.768kHz clock status
Turn off
Turn on
Normal mode Turn on
Turn on
· 8 level Normal mode frequency : 447.8K , 895.7K , 1.79M , 3.58M , 7.16M , 10.75M , 14.3M , 17.9MHz.
· Input port interrupt function
· 10 interrupt source , 4 external , 6 internal
· Dual clocks operation (Internal PLL main clock , External 32.768KHz)
SPI
· Serial Peripheral Interface (SPI) : a kind of serial I/O interface
· Interrupt flag available for the read buffer full or transmitter buffer empty.
· Programmable baud rates of communication
· Three-wire synchronous communication. (shared with IO)
PWM
‧ Dual PWM (Pulse Width Modulation) with 10-bit resolution
‧ Programmable period (or baud rate)
‧ Programmable duty cycle
ADC
· Operating : 2.5V∼ 5.5V
· 6 channel 10-bit successive approximation A/D converter
· Internal (VDD) or external reference
DAC
· Operating : 2.5V∼ 5.5V under VDD reference, 2.8V ~ 5.5V under 2.5V reference
· 10-bit R-2R D/A converter
· Internal (VDD or 2.5V) reference
POR
· 2.0V Power-on voltage detector reset
Build-in LCD driver(4 X 32)
· Common driver pins : 4
· Segment driver pins : 32
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
2
8/31/2004 (V4.0)
EM78569
8-bit Micro-controller
· 1/3 bias
· 1/4 duty, 1/2 duty
· 16 Level LCD contrast control by software
Multiplication
· 8 x 8 multiplication
PACKAGE
· 73-pin die or 100-pin QFP
III. Application
Communication or general product.
IV. Pin Configuration
1
2
NC
NC
80
79
78
77
76
NC
NC
NC
NC
NC
NC
3
4
NC
5
NC
NC
6
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
SEG21/PB7
SEG22/PB6
SEG23/PB5
SEG24/PB4
SEG25/PB3
SEG26/PB2
SEG27/PB1
SEG28/PB0
SEG29/PC7
SEG30/PC6
SEG31/PC5
PC4
NC
7
8
NC
9
NC
SEG0
10
11
12
13
14
15
16
17
18
19
20
21
22
COM3
COM2
COM1
COM0
NC
NC
NC
NC
NC
PC3
PWM2/PC2
PWM1/PC1
PC0
NC
AVDD
NC
INT0/P70
INT1/P71
INT2/P72
INT3/P73
SDI/P74
NC
23
24
25
26
27
28
29
30
NC
NC
NC
NC
SDO/P75
SCK/P76
P77
NC
PLLC
AVSS
VDD
Fig 1 : 74-pin die or 100-pin QFP
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
3
8/31/2004 (V4.0)
EM78569
8-bit Micro-controller
V. Functional Block Diagram
DATA RAM
CONTROL REGISTER
CPU
LCD DRIVER
I/O PORT
TIMING
CONTROL
TIMER
TCC
COUNTER1
COUNTER2
WDT
SPI
PWM
10-bit A/D
10-bit D/A
ROM
RAM
Fig.2a Block diagram
XIN XOUT PLLC
WDT
timer
ROM
R2
STACK
Oscillator
timing control
Prescaler
Interrupt
control
Instruction
register
ALU
R1(TCC)
General
RAM
R3
R5
Control sleep
and wakeup
on I/O port
ACC
DATA
RAM
Instruction
decoder
R4
DATA & Control Bus
LCD RAM
LCD driver
IOCC
RC
IOC5
R5
IOC6
R6
IOC7
R7
IOC8
R8
IOC9
R9
IOCB
RB
SPI
PWM
10-bit A/D
10-bit D/A
PORTC
PORT5
PORT6
PORT7
PORT8
PORT9
PORTB
COM0~COM3
SEG0~SEG31
PC0~PC7
P55~P57
P60~P67
P70~P77
P80~P87
P90~P97
PB0~PB7
Fig.2b Block diagram
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
4
8/31/2004 (V4.0)
EM78569
8-bit Micro-controller
VI. Pin Descriptions
PIN
I/O
DESCRIPTION
POWER
VDD
POWER
POWER
Digital power
Analog power
Digital ground
Analog ground
AVDD
VSS
AVSS
CLOCK
XIN
I
Input pin for 32.768 kHz oscillator
Output pin for 32.768 kHz oscillator
XOUT
PLLC
LCD
O
I
Phase loop lock capacitor, connect a capacitor 0.01u to 0.047u to the ground.
COM0 ~ COM3 O
SEG0 ~ SEG9
Common driver pins of LCD drivers
Segment driver pins of LCD drivers
O
SEG10 ~ SEG12 O (I/O : PORT5) SEG10 to SEG31 are shared with IO PORT.
SEG13 ~ SEG20 O (I/O : PORT9)
SEG21 ~ SEG28 O (I/O : PORTB)
SEG29 ~ SEG31 O (I/O : PORTC)
10-bit 6 channel A/D
VREF
AD1
I (P66)
I (P60)
I (P61)
I (P62)
I (P63)
I(P64)
I(P65)
ADC reference input. Shared with PORT66
ADC input channel 1. Shared with PORT60()
ADC input channel 2. Shared with PORT61
ADC input channel 3. Shared with PORT62
ADC input channel 4. Shared with PORT63
ADC input channel 5. Shared with PORT64
ADC input channel 6. Shared with PORT65
AD2
AD3
AD4
AD5
AD6
10-bit D/A
DAO
O(P67)
DAO is 10 bit DA output shared with PORT67
SPI
SCK
SDO
SDI
IO (PORT76)
O (PORT75)
I (PORT74)
Master: output pin, Slave: input pin. This pin shared with PORT76.
Output pin for serial data transferring. This pin shared with PORT75.
Input pin for receiving data. This pin shared with PORT74.
PWM
PWM1
PWM2
IO
O
O
Pulse width modulation output channel 1
Pulse width modulation output channel 2
P55~P57
I/O
PORT5 can be INPUT or OUTPUT port each bit.
PORT5(7:5) are shared with LCD Segment signal.
PORT6 can be INPUT or OUTPUT port each bit.
PORT7 can be INPUT or OUTPUT port each bit.
PORT7(4~6) are shared with SPI interface pins
Internal Pull high function.
P60 ~P67
P70 ~ P77
I/O
I/O
Interrupt function.
P80 ~ P87
I/O
PORT8 can be INPUT or OUTPUT port each bit.
Internal pull high.
PORT85 ~ P87 are shared with ADC input
PORT8(0~3) have wake-up functions(set by RE PAGE0)
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
5
8/31/2004 (V4.0)
EM78569
8-bit Micro-controller
P90 ~ P97
PB0 ~ PB7
PC0 ~ PC7
INT0
I/O
PORT9 can be INPUT or OUTPUT port each bit.
PORT9 are shared with LCD Segment signal.
PORTB can be INPUT or OUTPUT port each bit.
PORTB are shared with LCD Segment signal.
PORTC can be INPUT or OUTPUT port each bit.
PORTC(7:5) are shared with LCD Segment signal.
I/O
I/O
PORT70
PORT71
PORT72
PORT73
I
Interrupt sources. Once PORT70 has a falling edge or rising edge signal
(controlled by CONT register), it will generate a interruption.
Interrupt sources which has the same interrupt flag. Any pin from PORT71
has a falling edge signal, it will generate a interruption.
Interrupt sources which has the same interrupt flag. Any pin from PORT72
has a falling edge signal, it will generate a interruption.
Interrupt sources which has the same interrupt flag. Any pin from PORT73
has a falling edge signal, it will generate a interruption.
Low reset
INT1
INT2
INT3
/RESET
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
6
8/31/2004 (V4.0)
EM78569
8-bit Micro-controller
VII. Functional Descriptions
VII.1 Operational Registers
Register configuration
R PAGE registers
R PAGE2
Addr R PAGE0
00 Indirect addressing
01 TCC
R PAGE1
R PAGE3
02 PC
03 Page, Status
04 RAM bank, RSR
05 Port5 I/O data,
Program ROM page
06 Port6 I/O data
07 Port7 I/O data
LCD RAM address SPI control
PWM control
LCD data buffer
Data RAM bank
SPI data buffer
Duty of PWM1
PWM1 control
Duty of PWM1
08 Port8 I/O data
09 Port9 I/O data
Data RAM address
Data RAM data
buffer
Period of PWM1
Duty of PWM2
Multiplier control
Multiplicant Y
MR(0~7)
0A PLL, Main clock, DAC input data
PWM2 control
Duty of PWM2
Period of PWM2
WDTE
buffer
0B PortB I/O data
ADC output data
buffer
0C PortC I/O data
Counter1 data
MR(8~15)
MR(16~23)
0D LCD control
0E Wake-up control,
Interrupt flag
Counter2 data
0F Interrupt flag
10 16 bytes
:
Common registers
1F
20 Bank0~Bank3
Common registers
:
3F (32x8 for each
bank)
IOC PAGE registers
Addr IOC PAGE0
IOC PAGE1
00
01
02
03
04
05 Port5 I/O control,
LCD bias control
06 Port6 I/O control
07 Port7 I/O control
08 Port8 I/O control
09 Port9 I/O control
0A
Port6 switches
Port7 pull high
Port8 pull high
Port9 switches
DAC control
0B PortB I/O control ADC control
0C PortC I/O control Port5,8,B,C switch
0D
Clock
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
7
8/31/2004 (V4.0)
EM78569
8-bit Micro-controller
source(CN1,CN2)
Prescaler(CN1,CN2
)
0E Interrupt mask
0F Interrupt mask
10
:
1F
20
:
3F
VII.2 Operational Register Detail Description
R0 (Indirect Addressing Register)
R0 is not a physically implemented register. It is used as indirect addressing pointer. Any instruction using R0
as register actually accesses data pointed by the RAM Select Register (R4).
Example:
Mov A, @0x20
Mov 0x04, A
Mov A, @0xAA
Mov 0x00, A
;store a address at R4 for indirect addressing
;write data 0xAA to R20 at bank0 through R0
R1 (TCC)
TCC data buffer. Increased by 16.384KHz or by the instruction cycle clock (controlled by CONT register).
Written and read by the program as any other register.
R2 (Program Counter)
The structure is depicted in Fig.3.
Generates 16k × 13 external ROM addresses to the relative programming instruction codes.
"JMP" instruction allows the direct loading of the low 10 program counter bits.
"CALL" instruction loads the low 10 bits of the PC, PC+1, and then push into the stack.
"RET'' ("RETL k", "RETI") instruction loads the program counter with the contents at the top of stack.
"MOV R2, A" allows the loading of an address from the A register to the PC, and the ninth and tenth bits are
cleared to "0''.
"ADD R2,A" allows a relative address be added to the current PC, and contents of the ninth and tenth bits are
cleared to "0''.
"TBL" allows a relative address added to the current PC, and contents of the ninth and tenth bits don't change.
The most significant bit (A10~A13) will be loaded with the contents of bit PS0~PS3 in the status register (R5
PAGE0) upon the execution of a "JMP'', "CALL'', "ADD R2, A'', or "MOV R2, A'' instruction.
If an interrupt is triggered, PROGRAM ROM will jump to address 0x08 at page0. The CPU will store ACC,
R3 status and R5 PAGE automatically, and they will be restored after instruction RETI.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
8
8/31/2004 (V4.0)
EM78569
8-bit Micro-controller
R5(PAGE)
CALL and
INTERRUPT
STACK1
STACK2
STACK3
STACK4
STACK5
STACK6
STACK7
STACK8
STACK9
STACK10
STACK11
STACK12
STACK13
STACK14
STACK15
STACK16
A13 A12 A11 A10
A9 A8
A7~A0
PC
RET
RETL
RETI
0000 PAGE0 0000~03FF
0001 PAGE1 0400~07FF
store
ACC,R3,R5(PAGE)
restore
0010 PAGE2 0800~0BFF
1110 PAGE14 3800~3BFF
1111 PAGE15 3C00~3FFF
Fig.3 Program counter organization
R3 (Status, Page selection)
(Status flag, Page selection bits)
7
6
5
4
T
R
3
P
R
2
Z
1
0
C
RPAGE1 RPAGE0 IOCPAGE
R/W-0 R/W-0 R/W-0
Bit 0(C) : Carry flag
DC
R/W
R/W
R/W
Bit 1(DC) : Auxiliary carry flag
Bit 2(Z) : Zero flag
Bit 3(P) : Power down bit
Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP" command.
Bit 4(T) : Time-out bit
Set to 1 by the "SLEP" and "WDTC" command, or during power up and reset to 0 by WDT timeout.
EVENT
T
P
REMARK
WDT wake up from sleep mode
WDT time out (not sleep mode)
/RESET wake up from sleep
Power up
0
0
1
1
x
0
1
0
1
Low pulse on /RESET
X
x : don't care
Bit 5(IOCPAGE) : change IOC5 ~ IOCE to another page
Please refer to Fig.4 control register configuration for details.
0/1 Î IOC page0 / IOC page1
Bit 6(RPAGE0 ~ RPAGE1) : change R5 ~ RE to another page
Please refer to VII.1 Operational registers for detail register configuration.
(RPAGE1,RPAGE0)
R page # selected
R page 0
(0,0)
(0,1)
(1,0)
(1,1)
R page 1
R page 2
R page 3
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
9
8/31/2004 (V4.0)
EM78569
8-bit Micro-controller
R4 (RAM selection for common registers R20 ~ R3F))
(RAM selection register)
7
6
5
4
3
2
1
0
RB1
RB0
RSR5
R/W
RSR4
R/W
RSR3
R/W
RSR2
R/W
RSR1
R/W
RSR0
R/W
R/W-0
R/W-0
Bit 0 ~ Bit 5 (RSR0 ~ RSR5) : Indirect addressing for common registers R20 ~ R3F
RSR bits are used to select up to 32 registers (R20 to R3F) in the indirect addressing mode.
Bit 6 ~ Bit 7 (RB0 ~ RB1) : Bank selection bits for common registers R20 ~ R3F
These selection bits are used to determine which bank is activated among the 4 banks for 32 register (R20 to
R3F)..
Please refer to VII.1 Operational registers for details.
R5 (PORT5 I/O data, Program page selection, LCD address, SPI control)
PAGE0 (PORT5 I/O data register, Program page register)
7
6
5
4
-
3
2
1
0
P57
R/W
P56
R/W
P55
R/W
PS3
PS2
PS1
PS0
R/W-0
R/W-0
R/W-0
R/W-0
Bit 0 ~ Bit 3 (PS0 ~ PS3) : Program page selection bits
PS3 PS2 PS1 PS0 Program memory page (Address)
0
0
0
0
:
0
0
0
0
:
0
0
1
1
:
0
1
0
1
:
Page 0
Page 1
Page 2
Page 3
:
:
:
:
:
:
1
1
1
1
1
1
0
1
Page 14
Page 15
User can use PAGE instruction to change page to maintain program page by user. Otherwise, user can use
far jump (FJMP) or far call (FCALL) instructions to program user's code. And the program page is
maintained by EMC's complier. It will change user's program by inserting instructions within program.
Bit 4 : unused
Bit 5 ~ Bit 7 (P55 ~ P57) : 8-bit PORT5(5~7) I/O data register
User can use IOC register to define input or output each bit.
PAGE1 (LCD address)
7
6
5
-
4
-
3
2
1
0
DA9
DA8
LCDA3 LCDA2 LCDA1 LCDA0
R/W-0 R/W-0 R/W-0 R/W-0
R/W-0
R/W-0
Bit 0 ~ Bit 3 (LCDA0 ~ LCDA3) : LCD address for LCD RAM read or write
The address of the LCD RAM correspond to the COMMON and SEGMENT signals as the table.
COM3 ~ COM0
LCD address
(LCDA3 ~ LCDA0)
SEG1, SEG0
SEG3, SEG2
SEG5, SEG4
SEG7, SEG6
SEG9, SEG8
SEG11, SEG10
SEG13, SEG12
SEG15, SEG14
00H
01H
02H
03H
04H
05H
06H
07H
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
10
8/31/2004 (V4.0)
EM78569
8-bit Micro-controller
SEG17, SEG16
SEG19, SEG18
SEG21, SEG20
SEG23, SEG22
SEG25, SEG24
SEG27, SEG26
SEG29, SEG28
SEG31, SEG30
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
Bit 4 ~ Bit 5 : unused
Bit 6 ~ Bit 7(DA8~DA9) : DA8 and DA9 are DAC MSB when R7 page1 bit 3(DARES) is set ,.or unused
when DAREF clear to 0. When using 10 bits resolution DAC, DAO output voltage will
unchanged after write data to these two bits. DAO pin will change after write new data to DAC
low 8 bits data buffer (RA PAGE1).
PAGE2 (SPI control)
7
6
5
4
3
2
1
0
RBF
SPIE
SRO
SE
SCES
SBR2
SBR1
SBR0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SDO
SDI
Master Device
Salve Device
R5 page1
SPIR register
SPIW register
SDI
SDO
SCK
SPI module
SPIS Reg
Bit 0
Bit7
SCK
Fig.4 Single SPI Master / Salve Communication
Fig. 4 shows how SPI to communicate with other device by SPI module. If SPI is a master controller, it
sends clock through the SCK pin. An 8-bit data is transmitted and received at the same time. If SPI,
however, is defined as a slave, its SCK pin could be programmed as an input pin. Data will continue to be
shifted on a basis of both the clock rate and the selected edge.
Bit 0 ~ Bit 2 (SBR0 ~ SBR2) : SPI baud rate selection bits
SBR2
SBR1
SBR0
Mode
Master
Master
Master
Master
Master
Master
Slave
Baud rate
Fsco
Fsco/2
Fsco/4
Fsco/8
Fsco/16
Fsco/32
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
1
0
Master
16.384k
<Note> Fsco = CPU instruction clock
For example :
If PLL is enabled and main clock is selected to 3.5826MHz, the instruction clock is 3.5826MHz/2
Î Fsco=3.5862MHz/2
If PLL is enabled and main clock is selected to 3.5826MHz, the instruction clock is 0.895MHz/2
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
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8-bit Micro-controller
Î Fsco=0.895MHz/2
If PLL is disabled, the instruction clock is 32.768kHz/2 Î Fsco=32.768kHz/2.
Bit 3 (SCES) : SPI clock edge selection bit
1ÎData shifts out on falling edge, and shifts in on rising edge. Data is hold during the high level.
0ÎData shifts out on rising edge, and shifts in on falling edge. Data is hold during the low level.
Bit 4 (SE) : SPI shift enable bit
1 Î Start to shift, and keep on 1 while the current byte is still being transmitted.
0 Î Reset as soon as the shifting is complete, and the next byte is ready to shift.
<Note> This bit has to be reset in software.
Bit 5 (SRO) : SPI read overflow bit
1 Î A new data is received while the previous data is still being hold in the SPIB register. In this situation,
the data in SPIS register will be destroyed. To avoid setting this bit, users had better to read SPIB
register even if the transmission is implemented only.
0 Î No overflow, <Note> This can only occur in slave mode.
Bit 6 (SPIE) : SPI enable bit
1 Î Enable SPI mode
0 Î Disable SPI mode
Bit 7 (RBF) : SPI read buffer full flag
1 Î Receive is finished, SPIB is full.
0 Î Receive is not finish yet, SPIB is empty.
Write
R5
Read
R5
RBF
RBFI
SPIWC
SPIR reg.
SPIW reg.
set to 1
SPIE
Buffer Full Detector
SDI
shift right
SDI/P74
SPIS reg.
MUX
PORT62
bit 7
bit 0
SDO
SPIC reg. (R4 page1)
SDO/P75
MUX
PORT61
Edge
Select
SPIE
0
3
Noise
Filter
SBR2~SBR0
SBR0 ~SBR2
2
3
Clock Select
Tsco
Prescaler
4, 8, 16, 32, 64, 128
SCK
Edge
SCK/P76
Select
MUX
PORT60
16.38kHz
SCK
SPIE
Fig.5 SPI structure
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
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8-bit Micro-controller
SPIC reg. : SPI control register
SDO/P61 : Serial data out
SDI/P62 : Serial data in
SCK/P60 : Serial clock
RBF : Set by buffer full detector, and reset in software.
RBFI : Interrupt flag. Set by buffer full detector, and reset in software.
Buffer Full Detector : Sets to 1, while an 8-bit shifting is complete.
SE : Loads the data in SPIW register, and begin to shift
SPIE : SPI control register
SPIS reg. : Shifting byte out and in.
The MSB will be shifted first. Both the SPIS register and the SPIW register are loaded at the same time.
Once data being written to, SPIS starts transmission / reception. The received data will be moved to the
SPIR register, as the shifting of the 8-bit data is complete. The RBF (Read Buffer Full ) flag and the
RBFI(Read Buffer Full Interrupt) flag are set.
SPIR reg. : Read buffer.
The buffer will be updated as the 8-bit shifting is complete. The data must be read before the next
reception is finished. The RBF flag is cleared as the SPIR register read.
SPIW reg. : Write buffer.
The buffer will deny any write until the 8-bit shifting is complete. The SE bit will be kept in 1 if the
communication is still under going. This flag must be cleared as the shifting is finished. Users can
determine if the next write attempt is available.
SBR2 ~ SBR0: Programming the clock frequency/rates and sources.
Clock select : Selecting either the internal instruction clock or the external 16.338KHz clock as the shifting
clock.
Edge Select : Selecting the appropriate clock edges by programming the SCES bit.
SCK
(SCES=0)
SCK
(SCES=1)
Bit7
Bit6
Bit5
Bit4
Bit1
Bit0
Bit2
Bit3
SDO
SDI
RBF
Shift data in
Shift data out
Clear by software
Fig.6 SPI timing
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
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EM78569
8-bit Micro-controller
PAGE3 (PWMCON)
7
6
5
4
3
2
1
0
PWM2E PWM1E
R/W-0 R/W-0
T2EN
R/W-0
T1EN
R/W-0
T2P1
R/W-0
T2P0
R/W-0
T1P1
R/W-0
T1P0
R/W-0
Bit 0 ~ Bit 1 ( T1P0 ~ T1P1 ): TMR1 clock prescale option bits.
T1P1
T1P0
Prescale
1:2(Default)
1:8
0
0
1
1
0
1
0
1
1:32
1:64
Bit 2 ~ Bit 3 ( T2P0 ~ T2P1 ): TMR2 clock prescale option bits.
T2P1
T2P0
Prescale
1:2(Default)
1:8
0
0
1
1
0
1
0
1
1:32
1:64
Bit 4 (T1EN): TMR1 enable bit
0 Î TMR1 is off (default value).
1 Î TMR1 is on.
Bit 5 (T2EN): TMR2 enable bit
0 Î TMR2 is off (default value).
1 Î TMR2 is on.
Bit 6 (PWM1E): PWM1 enable bit
0 Î PWM1 is off (default value), and its related pin carries out the PC1 function;
1 Î PWM1 is on, and its related pin will be set to output automatically.
Bit 7 (PWM2E): PWM2 enable bit
0 Î PWM2 is off (default value), and its related pin carries out the PC2 function.
1 Î PWM2 is on, and its related pin will be set to output automatically.
R6 (PORT6 I/O data, LCD data, SPI data buffer)
PAGE0 (PORT6 I/O data register)
7
6
5
4
3
2
1
0
P67
P66
P65
P64
P63
P62
P61
P60
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 0 ~ Bit 8 (P60 ~ P67) : 8-bit PORT6(0~7) I/O data register
User can use IOC register to define input or output each bit.
PAGE1 (LCD data)
7
6
5
4
3
2
1
0
LCDD7 LCDD6 LCDD5 LCDD4 LCDD3 LCDD2 LCDD1 LCDD0
R/W R/W R/W R/W R/W R/W R/W R/W
Bit 0 ~ Bit 7 (LCDD0 ~ LCDD7 ) : LCD data buffer for LCD RAM read or write
LCD data vs. COM-SEG LCD address
LCDD7 ~ LCDD4 LCDD3 ~ LCDD0 (LCDA3 ~ LCDA0)
COM3 ~ COM0
SEG1
COM3 ~ COM0
SEG0
00H
01H
02H
03H
04H
05H
SEG3
SEG5
SEG7
SEG9
SEG2
SEG4
SEG6
SEG8
SEG11
SEG10
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
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EM78569
8-bit Micro-controller
SEG13
SEG15
SEG17
SEG19
SEG21
SEG23
SEG25
SEG27
SEG29
SEG31
SEG12
SEG14
SEG16
SEG18
SEG20
SEG22
SEG24
SEG26
SEG28
SEG30
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
PAGE2 (SPI data buffer)
7
6
5
4
3
2
1
0
SPIB7
R/W
SPIB6
R/W
SPIB5
R/W
SPIB4
R/W
SPIB3
R/W
SPIB2
R/W
SPIB1
R/W
SPIB0
R/W
Bit 0 ~ Bit 7 (SPIB0 ~ SPIB7) : SPI data buffer
If you write data to this register, the data will write to SPIW register. If you read this data, it will read the
data from SPIR register. Please refer to figure7
PAGE3 (DT1L: the Least Significant Byte ( Bit 7 ~ Bit 0) of Duty Cycle of PWM1)
7
6
5
4
3
2
1
0
PWM1[7] PWM1[6] PWM1[5] PWM1[4] PWM1[3] PWM1[2] PWM1[1] PWM1[0]
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
A specified value keeps the output of PWM1 to stay at high until the value matches with TMR1.
R7 (PORT7 I/O data, Data RAM bank)
PAGE0 (PORT7 I/O data register)
7
6
5
4
3
2
1
0
P77
P76
P75
P74
P73
P72
P71
P70
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 0 ~ Bit 7 (P70 ~ P77) : 8-bit PORT7(0~7) I/O data register
User can use IOC register to define input or output each bit.
PAGE1 (Data RAM bank selection bits)
7
6
-
5
AD9
R
4
AD8
R
3
2
1
0
DARES
R/W-0
ADRES
R/W-0
RAM_B1
R/W-0
RAM_B0
R/W-0
Bit 0~Bit 1 (RAM_B0~RAM_B1) : Data RAM bank selection bits
Each bank has address 0 ~ address 255 which is total 256 (0.25k) bytes RAM size.
Data RAM bank selection : (Total RAM = 1K)
RAM_B1
RAM_B0
PAGE
PAGE0
PAGE1
PAGE2
PAGE3
0
0
1
1
0
1
0
1
Bit 2(ADRES): Resolution selection for ADC
0 Î ADC is 8-bit resolution
When 8-bit resolution is selected, the most significant(MSB) 8-bit data output of the internal 10-bit ADC
will be mapping to RB PAGE1 so R7 PAGE1 bit 4 ~5 will be of no use.
1 Î ADC is 10-bit resolution
When 10-bit resolution is selected, 10-bit data output of the internal 10-bit ADC will be exactly mapping
to RB PAGE1 and R7 PAGE1 bit 4 ~5.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
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EM78569
8-bit Micro-controller
Bit 3: Resolution selection for DAC
0 Î DAC is 8-bit resolution
When 8-bit resolution is selected, the most significant(MSB) 8-bit data output of the internal 10-bit DAC
will be mapping to RA PAGE1 so R5 PAGE1 bit 6 ~7 will be of no use.
1 Î DAC is 10-bit resolution
When 10-bit resolution is selected, 10-bit data output of the internal 10-bit DAC will be exactly mapping to
RA PAGE1 and R5 PAGE1 bit 6 ~7.
Bit 4 ~ Bit 5(AD8 ~ AD9): The most significant 2 bit of 10-bit ADC conversion output data
Combine there two bits and RB PAGE1 as complete 10-bit ADC conversion output data.
Bit 6~Bit7: Unused
PAGE2 (reserved)
(Unused register, not allowed to use)
PAGE3 (DT1H: the Most Significant Byte ( Bit 1 ~ Bit 0 ) of Duty Cycle of PWM1)
7
-
6
-
5
-
4
-
3
-
2
-
1
0
PWM1[9] PWM1[8]
R/W-0 R/W-0
Bit 0 ~ Bit 1 (PWM1[8] ~ PWM1[9]): The Most Significant Byte of PWM1 Duty Cycle
A specified value keeps the PWM1 output to stay at high until the value matches with TMR1.
Bit 2 Bit 7 : unused
R8 (PORT8 I/O data, Data RAM address)
PAGE0 (PORT8 I/O data register)
7
6
5
4
3
2
1
0
P87
R/W
P86
R/W
P85
R/W
P84
R/W
P83
R/W
P82
R/W
P81
R/W
P80
R/W
Bit 0 ~ Bit 7 (P80 ~ P87) : 8-bit PORT8(0~7) I/O data register
User can use IOC register to define input or output each bit.
PAGE1 (“VERSEL = 0” Æ Data RAM address register)
7
6
5
4
3
2
1
0
RAM_A7 RAM_A6 RAM_A5 RAM_A4 RAM_A3 RAM_A2 RAM_A1 RAM_A0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
Bit 0 ~ Bit 7 (RAM_A0 ~ RAM_A7) : data RAM address
The data RAM bank’s selection is from R7 PAGE1 bit0 ~ bit 1 (RAM_B0 ~ RAM_B1).
PAGE1 (“VERSEL = 1” Æ Un-defined)
When “VERSEL = 1”, Data RAM address buffer is mapping to RB page2 and R8 page1 is unused.
PAGE2 (reserved)
(undefined) not allowed to use
PAGE3 (PRD1: Period of PWM1)
7
6
5
4
3
2
1
0
PRD1[7] PRD1[6] PRD1[5] PRD1[4] PRD1[3] PRD1[2] PRD1[1] PRD1[0]
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
The content of this register is a period (time base) of PWM1. The frequency of PWM1 is the
reverse of the period.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
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EM78569
8-bit Micro-controller
R9 (PORT9 I/O data, Data RAM data buffer)
PAGE0 (PORT9 I/O data register)
7
6
5
4
3
2
1
0
P97
R/W
P96
R/W
P95
R/W
P94
R/W
P93
R/W
P92
R/W
P91
R/W
P90
R/W
Bit 0 ~ Bit 7 (P90 ~ P97) : 8-bit PORT9(0~7) I/O data register
User can use IOC register to define input or output each bit.
PAGE1 (Data RAM data register)
7
6
5
4
3
2
1
0
RAM_D7 RAM_D6 RAM_D5 RAM_D4 RAM_D3 RAM_D2 RAM_D1 RAM_D0
R/W R/W R/W R/W R/W R/W R/W R/W
Bit 0 ~ Bit 7 (RAM_D0 ~ RAM_D7) : Data RAM’s data
The address for data RAM is accessed from R8 PAGE1. The data RAM bank is selected by R7 PAGE1 Bit
0 ~ Bit 1 (RAM_B0 ~ RAM_B1).
PAGE2 (Unused; The page is not allow to use)
PAGE3 (DT2L: the Least Significant Byte ( Bit 7 ~ Bit 0 ) of Duty Cycle of PWM2)
7
6
5
4
3
2
1
0
PWM2[7] PWM2[6] PWM2[5] PWM2[4] PWM2[3] PWM2[2] PWM2[1] PWM2[0]
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
A specified value keeps the output of PWM2 to stay at high until the value matches with TMR2.
RA (PLL, Main clock selection, Watchdog timer)
PAGE0 (PLL enable bit, Main clock selection bits, Watchdog timer enable bit)
7
0
6
5
4
3
2
-
1
-
0
PLLEN
R/W-0
CLK2
R/W-0
CLK1
R/W-1
CLK0
R/W-1
WDTEN
R/W-0
R/W-0
Bit 0(WDTEN) : Watch dog control bit
User can use WDTC instruction to clear watch dog counter. The counter 's clock source is 32768/2 Hz. If
the prescaler assigns to TCC. Watch dog will time out by (1/32768 )*2 * 256 = 15.616mS. If the
prescaler assigns to WDT, the time of time out will be more times depending on the ratio of prescaler.
0/1 Î disable/enable
Bit 1~Bit 2 : Unused
Bit 3 ~ Bit 5 (CLK0 ~ CLK2) : MAIN clock selection bits
User can choose different frequency of main clock by CLK1 and CLK2. All the clock selection is list below.
PLLEN
CLK2
CLK1
CLK0
Sub clock
MAIN clock CPU clock
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
32.768kHz 447.829kHz 447.829kHz (Normal mode)
32.768kHz 895.658kHz 895.658kHz (Normal mode)
32.768kHz 1.791MHz
32.768kHz 3.582MHz
32.768kHz 7.165MHz
1.791MHz (Normal mode)
3.582MHz (Normal mode)
7.165MHz (Normal mode)
32.768kHz 10.747MHz 10.747MHz (Normal mode)
32.768kHz 14.331MHz 14.331MHz (Normal mode)
32.768kHz 17.91MHz
17.91MHz (Normal mode)
32.768kHz (Green mode)
Don’t care Don’t care Don’t care 32.768kHz don’t care
Bit 6(PLLEN) : PLL's power control bit which is CPU mode control register
0/1 Î disable PLL/enable PLL
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
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EM78569
8-bit Micro-controller
If enable PLL, CPU will operate at normal mode (high frequency). Otherwise, it will run at green mode
(low frequency, 32768 Hz).
447.8293kHz ~17.9132MHz
CLK2 ~ CLK0
PLL circuit
1
switch
System clock
0
ENPLL
Sub-clock
32.768kHz
Fig.7 The relation between 32.768kHz and PLL
Bit 7: Unused register. Always keep this bit to 0 or some un-expect error will happen!
The status after wake-up and the wake-up sources list as the table below.
Wakeup signal
SLEEP mode
RA(7,6)=(0,0)
+ SLEP
TCC time out
IOCF bit0=1
No function
COUNTER1 time out No function
IOCF bit1=1
COUNTER2 time out No function
IOCF bit2=2
WDT time out
Reset and jump to
address 0
PORT8(0~3)
Reset and Jump to
address 0
RE PAGE0 bit3 or
bit4 or bit5 or bit6 = 1
PORT7(0~3)
Reset and Jump to
address 0
IOCF bit3 or bit4 or
bit5 =1
<Note> PORT70 's wakeup function is controlled by IOCF bit 3. It's falling edge or rising edge trigger
(controlled by CONT register bit7).
PORT71 's wakeup function is controlled by IOCF bit 4. It’s falling edge trigger.
PORT72~PORT73 's wakeup function is controlled by IOCF. They are falling edge trigger.
PORT80~PORT83’s wakeup function are controlled by RE PAGE0 bit 0 ~ bit 3. They are falling
edge trigger.
PAGE1 (DAC output data register)
7
6
5
4
3
2
1
0
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
Bit 0 ~ Bit 7 (DA0 ~ DA7) : These 8 bit is full DAC data buffer when 8-bit resolution is selected(R7 page1 bit 7
DAREF = 0), or the least significant 8-bit data when 10 bit resolution(DAREF = 1) selected..
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
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EM78569
8-bit Micro-controller
PAGE2 (Multiplier control register)
7
INS
R/W-0
6
-
5
4
3
2
1
0
INDR
R/W-0
PLUS MROPT3 MROPT2 MROPT1 MROPT0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
Bit 0 ~ Bit 3 (MROPT0 ~ MROPT3) : Multiplier operation mode control
MROPT3 ~ MROPT0 Mode Description
0 0 0 0
MR = sign(X)*sign(Y)
Sign-sign multiplication
0 0 0 1
MR = sign(X)*unsign(Y)
Sign-unsign multiplication
0 0 1 0
MR = unsign(X)*sign(Y)
Unsign-sign multiplication
0 0 1 1
MR = unsign(X)*unsign(Y)
MR = MR + sign(X)*sign(Y)
MR = MR + sign(X)*unsign(Y)
MR = MR + unsign(X)*sign(Y)
Unsign-unsign multiplication
1 0 0 0
Sign-sign accumulated multiplication addition
Sign-unsign accumulated multiplication addition
Unsign-unsign accumulated multiplication addition
1 0 0 1
1 0 1 0
1 0 1 1
MR = MR + unsign(X)*unsign(Y) Unsign-unsign accumulated multiplication addition
1 1 0 0
MR = MR - sign(X)*sign(Y)
MR = MR - sign(X)*unsign(Y)
MR = MR - unsign(X)*sign(Y)
Sign-sign accumulated multiplication subtraction
Sign-unsign accumulated multiplication subtraction
Unsign-unsign accumulated multiplication subtraction
1 1 0 1
1 1 1 0
1 1 1 1
MR = MR - unsign(X)*unsign(Y) Unsign-unsign accumulated multiplication subtraction
unused
0 1 0 0 ~ 0 1 1 1
-
Bit 4 (PLUS) : Base on “VERSEL”, this bit’s defined is different. If VERSEL = 0, data RAM and multiplicant
Y’s address buffer is independent. When VERSEL = 1, both data RAM and multiplicant Y’s address are point
to RB page2.
VERSEL PLUS
Data RAM Multiplicant Y’s
address buffer address buffer
Effect
0
0
1
1
0
1
0
1
R8 page1
R8 page1
RB page2
RB page2
RB page2
RB page2
RB page2
RB page2
Data RAM’s address will not auto-increase after access,
Y’s address will not auto-increase after run instruction “INT A”
Data RAM’s address will not auto-increase after access,
Y’s address will auto-increase after run instruction “INT A”
Data RAM’s address will auto-increase after access,
Y’s address will not auto-increase after run instruction “INT A”
Data RAM’s address will auto-increase after access,
Y’s address will auto-increase after run instruction “INT A”
Bit 5 (INDR) : Indirect address pointer enable control
0/1 Î disable/enable
When (INDR,PLUS) = (1,1), the address pointer and address auto-increment functions are enabled. Under
the functions are enabled, RB PAGE1 acts as address pointer and it will automatically increase one after
“MUL” instruction execution. That is to say, RB PAGE2 = RB PAGE2 + 1. The multiplicant Y data is
stored in R9 PAGE1 data RAM buffer.
Bit 5 (INDR) Bit 4 (PLUS) Function
1
0
Enable indirect address pointer
RB PAGE2 acts as Multipliacnt Y data address pointer for multiplier
Multiplicant Y data is stored in R9 PAGE1 for multiplier
Disable Multiplicant Y data address auto-increment for multiplier
Enable indirect address pointer
1
1
RB PAGE2 acts as Multipliacnt Y data address pointer for multiplier
Multiplicant Y data is stored in R9 PAGE1 for multiplier
Enable Multiplicant Y data address auto-increment for multiplier
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
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EM78569
8-bit Micro-controller
0
x
Disable indirect address pointer
Disable Multiplicant Y data address auto-increment for multiplier
RB PAGE2 acts as Multipliacnt Y data buffer for multiplier
Multiplicant Y data is stored in RB PAGE1 for multiplier
Set
RA PAG2
(bit5,bit4)
(bit3..Bit0)
=(1,1)
= (0,0)or(0,1)
=(1,0)
Y_data= R9PAGE1
Y_addr= RB
PAGE2
Y_data= RB
PAGE2
Y_data=R9PAGE1
Y_addr= RB
PAGE2
Y_addr=0x0B
case1
case3
case2
movX_datatoACC
INT A
instruction
case3
case1
case2
Y_addr=
RB PAGE2 +1
Y_addr= RB
PAGE2
Y_addr=0x0B
Fig 8 :Multiplier control flow
Bit 6 : Unused. This bit is not allow to use.
Bit 7(INS) : Instruction ”ADD” and “DEC” calculation select . This bit is a write only bit.
.
This bit’s define is based on “VERSEL”. If “VERSEL” = 0, this bit is undefined. If
“VERSEL” = 1, this bit will effect the result after run “ADD” and “SUB” instruction.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
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EM78569
8-bit Micro-controller
VERSEL
(code option)
0
INS
(RA page2 bit7)
X
Instruction
Execute
ADD A , R
ADD R , A
ADD A , K
SUB A , R
SUB R , A
SUB A , K
A + R Æ A
A + R Æ R
A + K Æ A
R – A Æ A
R – A Æ R
K – A Æ A
1
1
0
1
ADD A , R
ADD R , A
A + R Æ A
A + R Æ R
ADD A , K
SUB A , R
SUB R , A
SUB A , K
A + K Æ A
R – A Æ A
R – A Æ R
K – A Æ A
ADD A , R
ADD R , A
ADD A , K
SUB A , R
SUB R , A
SUB A , K
A + R + C Æ A
A + R + C Æ R
A + K + C Æ A
R – A – /C Æ A
R – A – /C Æ R
K – A - /C Æ A
PAGE3 (DT2H: the Most Significant Byte ( Bit 1 ~ Bit 0 ) of Duty Cycle of PWM2)
7
-
6
-
5
-
4
-
3
-
2
-
1
0
PWM2[9] PWM2[8]
R/W-0 R/W-0
Bit 0 ~ Bit 1 (PWM2[8] ~ PWM2[9]): The Most Significant Byte of PWM1 Duty Cycle
A specified value keeps the PWM1 output to stay at high until the value matches with TMR1.
Bit 2 ~ Bit 7 : unused
RB (PORTB I/O data, ADC output data buffer)
PAGE0 (PORTB I/O data register)
7
6
5
4
3
2
1
0
PB7
R/W
PB6
R/W
PB5
R/W
PB4
R/W
PB3
R/W
PB2
R/W
PB1
R/W
PB0
R/W
Bit 0 ~ Bit 7 (PB0 ~ PB7) : 8-bit PORTB(0~7) I/O data register
User can use IOC register to define input or output each bit.
PAGE1 (ADC output data register)
7
6
5
4
3
2
1
0
AD7
R
AD6
R
AD5
R
AD4
R
AD3
R
AD2
R
AD1
R
AD0
R
Bit 0 ~ Bit 7 (AD0 ~ AD7) : These 8 bit is full ADC data buffer when 8-bit resolution is selected(R7 page1 bit 2
ADREF = 0), or the least significant 8-bit data when 10 bit resolution(ADREF = 1) selected..
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
21
8/31/2004 (V4.0)
EM78569
8-bit Micro-controller
PAGE2(Multiplicand Y Data buffer and Data RAM’s data buffer)
Base on “VERSEL”, this page’s defined is different.
For VERSEL = 0 :
7
6
5
4
3
2
1
0
MULY7 MULY6 MULY5 MULY4 MULY3 MULY2 MULY1 MULY0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
Bit 0 ~ Bit 7 (MULY0 ~ MULY7) : Multiplicand Y data buffer of multiplier
The multiplier can make a multiplication with X*Y. The multiplicator data buffer X is ACC and
the multiplicand data buffer Y is RB PAGE2 The maximum 24 bit multiplication result MR will be stored in RC
PAGE2 ~ RE PAGE2. That is to say, MR = X*Y.
For VERSEL = 1 :
At this status, RB page2 defined to multiplicand Y data buffer and Data RAM address buffer.
Example 1 : Read continue data from continuous data RAM address:
MOV A , @0b00111111
AND 0x03 , A
BS
CLR
BS
BC
BS
0x03 , 7 ; Set R register to page 2
0x0B ; Set RAM address = 0
0x0A , 4 ; Enable address auto-increase function
0x03 , 7
0x03 , 6 ; Set R register to page 1
MOV A , @0b11111100
AND 0x07 , A ; Set RAM bank 0
MOV A , 0x09 ; read Data RAM address 0x00’s data
MOV A , 0x09 ; read Data RAM address 0x01’s data
MOV A , 0x09 ; read Data RAM address 0x02’s data
:
:
Example 2 : Continuous multiplication and addition operation.
MOV A , @0b00111111
AND 0x03 , A
BS
0x03 , 7 ; Set R register to page 2
CLR
CLR
CLR
BS
BS
CLR
0x0C
0x0D
0x0E
; Clear MR = 0
0x0A , 5 ; enable multiplier’s indirect address mode
0x0A , 4 ; Enable address auto-increase function
0x0B ;Set address = 0
MOV A , @0x55
INT
INT
INT
A
A
A
; multiplication instruction, operate MR Å 0x55(A) x (address 0’ data)
; MR Å 0x55(A) x (address 1’ data) + MR
; MR Å 0x55(A) x (address 2’ data) + MR
PAGE3 (PRD2: Period of PWM2)
7
6
5
4
3
2
1
0
PRD2[7] PRD2[6] PRD2[5] PRD2[4] PRD2[3] PRD2[2] PRD2[1] PRD2[0]
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
The content of this register is a period (time base) of PWM2. The frequency of PWM2 is the reverse of the
period.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
22
8/31/2004 (V4.0)
EM78569
8-bit Micro-controller
RC (PORTC I/O data, Counter1 data)
PAGE0 (PORT9 I/O data register)
7
6
5
4
3
2
1
0
PC7
R/W
PC6
R/W
PC5
R/W
PC4
R/W
PC3
R/W
PC2
R/W
PC1
R/W
PC0
R/W
Bit 0 ~ Bit 7 (PC0 ~ PC7) : 8-bit PORTC(0~7) I/O data register
User can use IOC register to define input or output each bit.
PAGE1 (Counter1 data register)
Bit7
CN17
R/W-0
Bit6
CN16
R/W-0
Bit5
CN15
R/W-0
Bit4
CN14
R/W-0
Bit3
CN13
R/W-0
Bit2
CN12
R/W-0
Bit1
CN11
R/W-0
Bit0
CN10
R/W-0
Bit 0 ~ Bit 7 (CN10 ~ CN17) : Counter1's buffer that user can read and write.
Counter1 is a 8-bit up-counter with 8-bit prescaler that user can use RC PAGE1 to preset and read the
counter.(write Î preset) After a interruption , it will reload the preset value.
Example for writing :
MOV 0x0C, A ; write the data at accumulator to counter1 (preset)
Example for reading :
MOV A, 0x0C
; read the data at counter1 to accumulator
PAGE2(LSB 8-bit Multiplication result)
7
6
5
4
3
2
1
0
MR7
MR6
MR5
MR4
MR3
MR2
MR1
MR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 0 ~ Bit 7 (MR0 ~ MR7) : Multiplication result data
The multiplier can make a multiplication with X*Y. The multiplicator data buffer X is ACC(acculator) and
the multiplicand data buffer Y is RB PAGE2. The LSB 8-bit of maximum 24 bit multiplication result MR
will be stored in RC PAGE2.
RC PAGE2 = MR(0~7) = LSB 8-bit (X*Y)
PAGE3 (reserved)
(unused register)
RD (LCD control, Counter2 data)
PAGE0 (LCD driver control bits)
7
-
6
5
4
1
3
-
2
1
0
VERSEL
PHO
LCD_C1 LCD_C0 LCD_M
R/W-0
R/W-0
R/W-0
R/W-0 R/W-0 R/W-0
Bit 0 (LCD_M) : LCD operation method including duty and frame frequency
Bit 1 ~ Bit 2 (LCD_C0 ~ LCD_C1) : LCD display control
LCD_C1 LCD_C0
LCD Display Control
change duty
LCD_M
Duty
1/4
Bias
1/3
0
0
0
1
Disable(turn off LCD)
1/2
1/3
0
1
1
1
:
:
Blanking
LCD display enable
:
:
:
:
Ps. To change the display duty must set the "LCD_C1 ,LCD_C0" to "00".
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
23
8/31/2004 (V4.0)
EM78569
8-bit Micro-controller
The controller can drive LCD directly. The LCD block is made up of common driver, segment driver,
display LCD RAM, common output pins, segment output pins and LCD operating power supply. The basic
structure contains a timing control. This timing control uses the basic frequency 32.768KHz to generate the
proper timing for different duty and display access.
RD PAGE0 Bit 0 ~ Bit 2 are LCD control bits for LCD driver. These LCD control bits determine the duty,
the number of common and the frame frequency. The LCD display (disable, enable, blanking) is controlled
by Bit 1 and Bit 2. The driving duty is decided by Bit 0. The display data is stored in LCD RAM which
address and data access controlled by registers R5 PAGE1 and R6 PAGE1.
User can regulate the contrast of LCD display by IOC5 PAGE0 Bit 0 ~ Bit 3 (BIAS0 ~ BIAS3). Up to 16
levels contrast is convenient for better display.
Bit 3, Bit 7 : (undefined) not allowed to use
Bit5 and Bit6 are only exist in EM78569’s developing tool(ICE569). In OTP and mask chip, these
two bits will mapping to code option. Please set these two bits to fixed value at initial and do not change
these two bit among your program design. Besides, please set bit4 to 1 or AD function will difference
between ICE 569 and EM78P569
Bit 4: Always set this bit to 1.
Bit 5(PHO) : PCO status select.
0 Î PC0 defined to normal IO.
1 Î PC0 defined to phase1 output.(VERSEL must = 1)
Bit 6(VERSEL) : Version select.
VERSEL = 0
R8 page1
VERSEL = 1
RB page2
Enable
Data RAM address
Data ram address auto-
increase
Not support
“ADD” & “SUB”
include “carry“ bit
Phase CLK output
Not support
Not support
Determined by RA page2 bit7
Phase1 CLK out from PC0
(determined by PHO)
PAGE1 (Counter2 data register)
Bit7
CN27
R/W
Bit6
CN26
R/W
Bit5
CN25
R/W
Bit4
Bit3
CN23
R/W
Bit2
CN22
R/W
Bit1
CN21
R/W
Bit0
CN20
R/W
CN24
R/W
Bit 0 ~ Bit 7 (CN20 ~ CN27) : Counter2's buffer that user can read and write.
Counter2 is a 8-bit up-counter with 8-bit prescaler that user can use RD PAGE1 to preset and read the
counter.(write Î preset) After a interruption, it will reload the preset value.
Example for writing :
MOV 0x0D, A ; write the data at accumulator to counter2 (preset)
Example for reading :
MOV A, 0x0D ; read the data at counter2 to accumulator
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
24
8/31/2004 (V4.0)
EM78569
8-bit Micro-controller
PAGE2(MID 8-bit Multiplication result)
7
6
5
4
3
2
1
0
MR15
MR14
MR13
MR12
MR11
MR10
MR9
MR8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 0 ~ Bit 7 (MR8 ~ MR15) : Multiplication result data
The multiplier can make a multiplication with X*Y. The multiplicator data buffer X is ACC(acculator) and
the multiplicand data buffer Y is RB PAGE2. The MID 8-bit of maximum 24 bit multiplication result MR
will be stored in RD PAGE2.
RD PAGE2 = MR(8~15) = MID 8-bit (X*Y)
PAGE3 (reserved)
(unused register)
RE (Interrupt flag, Wake-up control)
PAGE0 (Interrupt flag, Wake-up control bits)
7
6
5
4
3
2
1
0
PWM2
R/W-0
RBF
R/W-0
ADI
R/W-0
PWM1 /WUP83 /WUP82 /WUP81 /WUP80
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
Bit 0 (/WUP80) : PORT80 wake-up control, 0/1 Î disable/enable P80 pin wake-up function
Bit 1 (/WUP81) : PORT81 wake-up control, 0/1 Î disable/enable P81 pin wake-up function
Bit 2 (/WUP82) : PORT82 wake-up control, 0/1 Î disable/enable P82 pin wake-up function
Bit 3 (/WUP83) : PORT83 wake-up control, 0/1 Î disable/enable P83 pin wake-up function
Bit 4(PWM1) : PWM1 one period reach interrupt flag.
Bit 5 (ADI) : ADC interrupt flag after a sampling
Bit 6 (RBF) : SPI data transfer complete interrupt
If SPI's RBF signal has a rising edge signal (RBF set to "1" when transfer data completely), CPU will set this bit.
Bit 7(PWM2) : PWM2 one period reach interrupt flag.
PAGE1 (reserved)
PAGE2 (MSB 8-bit Multiplication result)
7
6
5
4
3
2
1
0
MR23
MR22
MR21
MR20
MR19
MR18
MR17
MR16
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
Bit 0 ~ Bit 7 (MR23 ~ MR16) : Multiplication result data
The multiplier can make a multiplication with X*Y. The multiplicator data buffer X is ACC(acculator) and
the multiplicand data buffer Y is RB PAGE2. The MSB 8-bit of maximum 24 bit multiplication result MR
will be stored in RE PAGE2.
RE PAGE2 = MR(16~23) = MSB 8-bit (X*Y)
PAGE3 (reserved)
RF (Interrupt status)
(Interrupt status register)
7
6
-
5
4
3
2
1
0
INT3
R/W-0
INT2
R/W-0
INT1
R/W-0
INT0
R/W-0
CNT2
R/W-0
CNT1
R/W-0
TCIF
R/W-0
"1" means interrupt request, "0" means non-interrupt
Bit 0(TCIF) : TCC timer overflow interrupt flag
Set when TCC timer overflows.
Bit 1(CNT1) : counter1 timer overflow interrupt flag
Set when counter1 timer overflows.
Bit 2(CNT2) : counter2 timer overflow interrupt flag
Set when counter2 timer overflows.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
25
8/31/2004 (V4.0)
EM78569
8-bit Micro-controller
Bit 3(INT0) : external INT0 pin interrupt flag
If PORT70 has a falling edge/rising edge (controlled by CONT register) trigger signal, CPU will set this bit.
Bit 4(INT1) : external INT1 pin interrupt flag
If PORT71 has a falling edge trigger signal, CPU will set this bit.
Bit 5(INT2) : external INT2 pin interrupt flag
If PORT72 or PORT73 has a falling edge trigger signal, CPU will set this bit.
Bit 6 : (undefined) not allowed to use
Bit 7(INT3) : external INT3 pin interrupt flag
If PORT73 has a falling edge trigger signal, CPU will set this bit.
<Note> IOCF is the interrupt mask register. User can read and clear.
Trigger edge as the table
Signal
Trigger
TCC
Time out
COUNTER1
COUNTER2
INT0
Time out
Time out
Falling
Rising edge
Falling edge
Falling edge
Falling edge
INT1
INT2
INT3
R10~R3F (General Purpose Register)
R10~R3F (Banks 0 ~ 3) : all are general purpose registers.
VII.3 Special Purpose Registers
A (Accumulator)
Internal data transfer, or instruction operand holding
It's not an addressable register.
CONT (Control Register)
7
6
5
4
3
2
1
0
P70EG
INT
TS
RETBK
PAB
PSR2
PSR1
PSR0
Bit 0 ~ Bit 2 (PSR0 ~ PSR2) : TCC/WDT prescaler bits
PSR2
PSR1
PSR0
TCC rate
1:2
WDT rate
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:1
1:2
1:4
1:8
1:4
1:16
1:32
1:64
1:128
1:256
1:8
1:16
1:32
1:64
1:128
Bit 3(PAB) : Prescaler assignment bit
0/1 Î TCC/WDT
Bit 4(RETBK) : Return value backup control for interrupt routine
0/1 Î disable/enable
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
26
8/31/2004 (V4.0)
EM78569
8-bit Micro-controller
When this bit is set to 1, the CPU will store ACC,R3 status and R5 PAGE automatically after an interrupt is
triggered. And it will be restored after instruction RETI. When this bit is set to 0, the user need to store ACC,
R3 and R5 PAGE in user program.
Bit 5(TS) : TCC signal source
0 Î internal instruction cycle clock
1 Î 16.384kHz
Bit 6 (INT) : INT enable flag
0 Î interrupt masked by DISI or hardware interrupt
1 Î interrupt enabled by ENI/RETI instructions
Bit 7(P70EG) : interrupt edge type of P70
0 Î P70 's interruption source is a rising edge signal.
1 Î P70 's interruption source is a falling edge signal.
CONT register is readable (CONTR) and writable (CONTW).
TCC and WDT :
There is an 8-bit counter available as prescaler for the TCC or WDT. The prescaler is available for the TCC
only or WDT only at the same time.
An 8 bit counter is available for TCC or WDT determined by the status of the bit 3 (PAB) of the CONT
register.
See the prescaler ratio in CONT register.
Fig.9 depicts the circuit diagram of TCC/WDT.
Both TCC and prescaler will be cleared by instructions which write to TCC each time.
The prescaler will be cleared by the WDTC and SLEP instructions, when assigned to WDT mode.
The prescaler will not be cleared by SLEP instructions, when assigned to TCC mode.
16.38KHz
Fig.9 Block diagram of TCC WDT
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
27
8/31/2004 (V4.0)
EM78569
8-bit Micro-controller
IOC5 (PORT5 I/O control, LCD bias control)
PAGE0 (LCD bias control bits)
7
6
5
4
-
3
2
1
0
BIAS3
BIAS2
BIAS1
BIAS0
R/W-0
IOC57
R/W-1
IOC56 IOC55
R/W-1 R/W-1
R/W-0
R/W-0
R/W-0
Bit 0 ~ Bit 3 (BIAS0 ~ BIAS3) : LCD operation voltage selection. V1 = VDD * (1 - n/60)
BIAS3 BIAS2 BIAS1 BIAS0
Vop (=VDD-VLCD)
VDD * (1-0/60)
VDD * (1-1/60)
VDD * (1-2/60)
VDD * (1-3/60)
VDD * (1-4/60)
:
Example (VDD = 3V)
0
0
0
0
0
:
0
0
0
0
1
:
0
0
1
1
0
:
0
1
0
1
0
:
3V
2.95V
2.90V
2.85V
2.80V
:
1
1
1
1
1
1
0
1
1
1
0
1
VDD * (1-13/60)
VDD * (1-14/60)
VDD * (1-15/60)
2.35V
2.30V
2.25V
Bit 4 : unused
Bit 5 ~ Bit 7 (IOC55 ~ IOC57) : PORT5(5~7) I/O direction control register
0 Î put the relative I/O pin as output
1 Î put the relative I/O pin into high impedance
1111
R15
1110
R14
1100
MUX
R
R
R13
R1
R
VDD
0001
0000
VLCD
V2
V1
4
BIAS3 to BIAS0
Fig.10 LCD driver bias circuit
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
28
8/31/2004 (V4.0)
EM78569
8-bit Micro-controller
Frame
VDD
V1
COM0
COM1
V2
VLCD
VDD
V1
V2
VLCD
VDD
V1
COM2
COM3
V2
VLCD
VDD
V1
V2
VLCD
VDD
V1
SEG
SEG
V2
VLCD
dark
VDD
V1
V2
VLCD
light
Fig.11 LCD waveform for 1/3 bias, 1/4 duty
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
29
8/31/2004 (V4.0)
EM78569
8-bit Micro-controller
Frame
VDD
V1
COM0
COM1
V2
VLCD
VDD
V1
V2
VLCD
VDD
V1
SEG
SEG
V2
VLCD
dark
VDD
V1
V2
VLCD
light
Fig.12 LCD waveform for 1/3 bias, 1/2 duty
PAGE1 (Reserved)
IOC6 (PORT6 I/O control, P6* pins switch control)
PAGE0 (PORT6 I/O control register)
7
6
5
4
3
2
1
0
IOC67
R/W-1
IOC66
R/W-1
IOC65
R/W-1
IOC64
R/W-1
IOC63
R/W-1
IOC62
R/W-1
IOC61
R/W-1
IOC60
R/W-1
Bit 0 ~ Bit 7 (IOC60 ~ IOC67) : PORT6(0~7) I/O direction control register
0 Î put the relative I/O pin as output
1 Î put the relative I/O pin into high impedance
PAGE1 (P6* pins switch control register)
7
-
6
5
4
3
2
1
0
P66S
R/W-0
P65S
R/W-0
P64S
R/W-0
P63S
R/W-0
P62S
R/W-0
P61S
P60S
R/W-0
R/W-0
Bit 0(P60S) : Select normal I/O PORT60 pin or channel 1 input AD1 pin of ADC
0 Î P60 (I/O PORT60) pin is selected
1 Î AD1 (Channel 1 input of ADC) pin is selected
Bit 1(P61S) : Select normal I/O PORT61 pin or channel 2 input AD2 pin of ADC
0 Î P61 (I/O PORT61) pin is selected
1 Î AD2 (Channel 2 input of ADC) pin is selected
Bit 2(P62S) : Select normal I/O PORT62 pin or channel 3 input AD3 pin of ADC
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
30
8/31/2004 (V4.0)
EM78569
8-bit Micro-controller
0 Î P62 (I/O PORT62) pin is selected
1 Î AD3 (Channel 3 input of ADC) pin is selected
Bit 3(P63S) : Select normal I/O PORT63 pin or channel 4 input AD4 pin of ADC
0 Î P63 (I/O PORT63) pin is selected
1 Î AD4 (Channel 4 input of ADC) pin is selected
Bit 4(P64S) : Select normal I/O PORT64 pin or channel 5 input AD5 pin of ADC
0 Î P64 (I/O PORT64) pin is selected
1 Î AD5 (Channel 5 input of ADC) pin is selected
Bit 5(P65S) : Select normal I/O PORT65 pin or channel 6 input AD6 pin of ADC
0 Î P65 (I/O PORT65) pin is selected
1 Î AD5 (Channel 6 input of ADC) pin is selected
Bit 6(P66S) : Select modulation transmitting output pin of AD or I/O PORT66 pin
0 Î P66 (I/O PORT66) pin is selected and ADC reference voltage come from internal VDD
1 Î VREF (External reference voltage input of ADC) pin is selected
Bit 7 : (undefined) not allowed to use
IOC7 (PORT7 I/O control, PORT7 pull high control)
PAGE0 (PORT7 I/O control register)
7
6
5
4
3
2
1
0
IOC77
R/W-1
IOC76
R/W-1
IOC75
R/W-1
IOC74
R/W-1
IOC73
R/W-1
IOC72
R/W-1
IOC71
R/W-1
IOC70
R/W-1
Bit 0 ~ Bit 7 (IOC70 ~ IOC77) : PORT7(0~7) I/O direction control register
0 Î put the relative I/O pin as output
1 Î put the relative I/O pin into high impedance
PAGE1 (PORT7 pull high control register)
7
6
5
4
3
2
1
0
PH77
R/W-0
PH76
R/W-0
PH75
R/W-0
PH74
R/W-0
PH73
R/W-0
PH72
R/W-0
PH71
R/W-0
PH70
R/W-0
Bit 0 ~ Bit 7 (PH70 ~ PH77) : PORT7 bit0~bit7 pull high control register
0 Î disable pull high function.
1 Î enable pull high function
IOC8 (PORT8 I/O control, PORT8 pull high control)
PAGE0 (PORT8 I/O control register)
7
6
5
4
3
2
1
0
IOC87
R/W-1
IOC86
R/W-1
IOC85
R/W-1
IOC84
R/W-1
IOC83
R/W-1
IOC82
R/W-1
IOC81
R/W-1
IOC80
R/W-1
Bit 0 ~ Bit 7 (IOC80 ~ IOC87) : PORT8(0~7) I/O direction control register
0 Î put the relative I/O pin as output
1 Î put the relative I/O pin into high impedance
PAGE1 (PORT8 pull high control register)
7
6
5
4
3
2
1
0
PH87
R/W-0
PH86
R/W-0
PH85
R/W-0
PH84
R/W-0
PH83
R/W-0
PH82
R/W-0
PH81
R/W-0
PH80
R/W-0
Bit 0 ~ Bit 7 (PH80 ~ PH87) : PORT8 bit0~bit7 pull high control register
0 Î disable pull high function.
1 Î enable pull high function
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
31
8/31/2004 (V4.0)
EM78569
8-bit Micro-controller
IOC9 (PORT9 I/O control, PORT9 switches)
PAGE0 (PORT9 I/O control register)
7
6
5
4
3
2
1
0
IOC97
R/W-1
IOC96
R/W-1
IOC95
R/W-1
IOC94
R/W-1
IOC93
R/W-1
IOC92
R/W-1
IOC91
R/W-1
IOC90
R/W-1
Bit 0 ~ Bit 7 (IOC90 ~ IOC97) : PORT9(0~7) I/O direction control register
0 Î put the relative I/O pin as output
1 Î put the relative I/O pin into high impedance
PAGE1 (PORT9 switches)
7
6
5
4
3
2
1
0
P97S
R/W-0
P96S
R/W-0
P95S
R/W-0
P94S
R/W-0
P93S
R/W-0
P92S
R/W-0
P91S
R/W-0
P90S
R/W-0
Bit 0(P90S) : Switch I/O PORT90 or LCD segment signal
0 Î (P90 pin is selected) : normal PORT90
1 Î (SEG20 pin) : SEGMENT output
Bit 1(P91S) : Switch I/O PORT91 or LCD segment signal
0 Î (P91 pin is selected) : normal PORT91
1 Î (SEG19 pin) : SEGMENT output
Bit 2(P92S) : Switch I/O PORT92 or LCD segment signal
0 Î (P92 pin is selected) : normal PORT92
1 Î (SEG18 pin) : SEGMENT output
Bit 3(P93S) : Switch I/O PORT93 or LCD segment signal
0 Î (P93 pin is selected) : normal PORT93
1 Î (SEG17 pin) : SEGMENT output
P90~P93 are shared with AD input channel. P90~P93 are defined to AD input when
Bit 4(P94S) : Switch I/O PORT94 or LCD segment signal
0 Î (P94 pin is selected) : normal PORT94
1 Î (SEG16 pin) : SEGMENT output
Bit 5(P95S) : Switch I/O PORT95 or LCD segment signal
0 Î (P95 pin is selected) : normal PORT95
1 Î (SEG15 pin) : SEGMENT output
Bit 6(P96S) : Switch I/O PORT96 or LCD segment signal
0 Î (P96 pin is selected) : normal PORT96
1 Î (SEG14 pin) : SEGMENT output
Bit 7(P97S) : Switch I/O PORT97 or LCD segment signal
0 Î (P97 pin is selected) : normal PORT97
1 Î (SEG13 pin) : SEGMENT output
IOCA (Reserved)
PAGE0(Unused)
PAGE1 DAC control
7
-
6
5
-
4
-
3
2
1
0
VREF
R/W-0
DAST/P67
R/W-0
R/W-0
R/W-0
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
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8-bit Micro-controller
Bit0~Bit1 : Undefined.
Bit 3(DAST/P67) : DAC enable control or P67 switch
0 Î switch DAO/P67 pin as normal I/O P67
1 Î enable DAC, enable DAC output buffer B1 and DAC output to DAO/P67 pin
When this bit is set by software, the DA converter will start converting and output to DAO/P67 pin. If user
clean this bit, DA converter will stop and DAO/P67 pin will be become normal I/O P67.
Bit 4 ~ Bit 5 : Unused
Bit 6(VREF) : Reference voltage selection bit for DA converter circuit
DAC reference setting is shown as following. Also see Fig.13.
VREF DAST/P67 Function
x
1
0
1
disable 2.5V, disable DAC
select 2.5V ref, enable 2.5V ref, enable DAC, enable output to
DAO/P67 pin
0
1
select VDD, disable 2.5V, enable DAC, enable output to DAO/P67
pin
VDD
2.5V
REF
M UX
VREF
DAOUT
2R
buffer
R
R
10-bit
D/A
ref.
o
2R
2R
volt.
DAST
P67
2R
DARES
Fig.13 D/A converter (DAC)
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
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8-bit Micro-controller
IOCB (PORTB I/O control, ADC control)
PAGE0 (PORTB I/O control register)
7
6
5
4
3
2
1
0
IOCB7
R/W-1
IOCB6
R/W-1
IOCB5
R/W-1
IOCB4
R/W-1
IOCB3
R/W-1
IOCB2
R/W-1
IOCB1
R/W-1
IOCB0
R/W-1
Bit 0 ~ Bit 7 (IOCB0 ~ IOCB7) : PORTB(0~7) I/O direction control register
0 Î put the relative I/O pin as output
1 Î put the relative I/O pin into high impedance
PAGE1 (ADC control bits)
7
6
5
4
3
2
1
-
0
IN2
IN1
IN0
ADCLK1 ADCLK0 ADPWR
R/W-0 R/W-0 R/W-0
ADST
R/W-0
R/W-0
R/W-0
R/W-0
Bit 0(ADST) : AD converter start to sample
By setting to “1”, the AD will start to sample data. This bit will be cleared by hardware automatically after a
sampling.
Bit 1 : Undefined. This bit is not allow to use.
Bit 2(ADPWR) : AD converter power control, 1/0 Î enable/disable
Bit 3 ~ Bit 4 (ADCLK0 ~ ADCLK1) : AD circuit ‘s sampling clock source.
For PLL clock = 895.658kHz ~ 17.9MHz (CLK2~CLK0 = 001 ~ 110)
ADCLK1 ADCLK0
Sampling rate
74.6K
Operation voltage
>=3.5V
0
0
1
1
0
1
0
1
37.4K
>=3.0V
18.7K
>=2.5V
9.3K
>=2.5V
For PLL clock = 447.829kHz (CLK2~CLK0 = 000)
ADCLK1 ADCLK0
Sampling rate
37.4K
Operation voltage
>=3.0V
0
0
1
1
0
1
0
1
18.7K
>=3.0V
9.3K
>=2.5V
4.7K
>=2.5V
This is a CMOS multi-channel 10-bit successive approximation A/D converter.
Features
74.6kHz maximum conversion speed at 5V.
Adjusted full scale input
External reference voltage input or internal(VDD) reference voltage
6 analog inputs multiplexed into one A/D converter
Power down mode for power saving
A/D conversion complete interrupt
Interrupt register, A/D control and status register, and A/D data register
Programmable
divider
ADC output
fpll
fadc
Divider
Nx
10-bit
ADC
fs
PLL
1/Mx
ADCLK1~ADCLK0
ENPLL
CLK2 ~ CLK0
Fig.14 ADC voltage control logic
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
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8-bit Micro-controller
fpll
Mx
fs
fadcon = fadc / 12
Nx = 1
Nx = 2
Nx = 4
Nx = 8
14.331MHz
10.747MHz
7.165MHz
3.582MHz
1.791MHz
895.658kHz
447.829kHz
16
12
8
4
2
895.658kHz
895.658kHz
895.658kHz
895.658kHz
895.658kHz
895.658kHz
74.638kHz
74.638kHz
74.638kHz
74.638kHz
74.638kHz
74.638kHz
37.391kHz
37.391kHz
37.391kHz
37.391kHz
37.391kHz
37.391kHz
18.659khz
18.659khz
18.659khz
18.659khz
18.659khz
18.659khz
18.659khz
9.329kHz
9.329kHz
9.329kHz
9.329kHz
9.329kHz
9.329kHz
9.329kHz
4.665kHz
1
1
447.829kHz 37.391kHz
Bit 5 ~ Bit 7(IN0~ IN2) : Input channel selection of AD converter
These two bits can choose one of three AD input.
IN2
IN1
IN0
Input
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
AD1
AD2
AD3
AD4
AD5
AD6
IOCC (PORTC I/O control, ADC control)
PAGE0 (PORTC I/O control register)
7
6
5
4
3
2
1
0
IOCC7
R/W-1
IOCC6
R/W-1
IOCC5
R/W-1
IOCC4
R/W-1
IOCC3
R/W-1
IOCC2
R/W-1
IOCC1
R/W-1
IOCC0
R/W-1
Bit 0 ~ Bit 7 (IOCC0 ~ IOCC7) : PORTC(0~7) I/O direction control register
0 Î put the relative I/O pin as output
1 Î put the relative I/O pin into high impedance
PAGE1 (PORT switch)
7
6
5
4
3
2
1
0
PC5S
PBSH
PBSL
P5SH
X
MS
PC7S
R/W-0
PC6S
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
-
R/W/0
Bit 0(MS) : P6* switch mode selection
0 Î (default unknown)
1 Î ADC input mode selection
(Always set this bit to “1” otherwise partial ADC function cannot be used)
Bit 1 : Unused. Not allowed to use.
Bit 2(P5SH) : Switch I/O PORT5 high nibble(5~7) or LCD segment signal
0 Î (P55 ~ P57 pins are selected) : normal PORT5 high nibble(5~7)
1 Î (SEG10 ~ SEG12 pins are selected) : SEGMENT output
Bit 3(PBSL) : Switch I/O PORTB low nibble(0~3) or LCD segment signal
0 Î (PB0 ~ PB3 pins are selected) : normal PORTB low nibble(0~3)
1 Î (SEG28 ~ SEG25 pins are selected) : SEGMENT output
Bit 4(PBSH) : Switch I/O PORTB high nibble(4~7) or LCD segment signal
0 Î (PB5 ~ PB7 pins are selected) : normal PORTB high nibble(4~7)
1 Î (SEG24 ~ SEG21 pins are selected) : SEGMENT output
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
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8-bit Micro-controller
Bit 5(PC5S) : Switch I/O PORTC5 or LCD segment signal
0 Î (PC5 pin is selected) : normal PORTC5
1 Î (SEG31 pin) : SEGMENT output
Bit 6(PC6S) : Switch I/O PORTC6 or LCD segment signal
0 Î (PC6 pin is selected) : normal PORTC6
1 Î (SEG30 pin) : SEGMENT output
Bit 7(PC7S) : Switch I/O PORTC7 or LCD segment signal
0 Î (PC7 pin is selected) : normal PORTC7
1 Î (SEG29 pin) : SEGMENT output
IOCD (Clock source, Prescaler of CN1 and CN2)
PAGE0 (Reserved)
PAGE1 (Clock source and prescaler for COUNTER1 and COUNTER2)
7
6
5
4
3
2
1
0
CNT2S
C2_PSC2 C2_PSC1 C2_PSC0
CNT1S
C1_PSC2 C1_PSC1 C1_PSC0
R/W-0
R/W-0 R/W-0 R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Bit 0 ~ Bit 2 (C1_PSC0 ~ C1_PSC2) : COUNTER1 prescaler ratio
C1_PSC2
C1_PSC1
C1_PSC0
COUNTER1
1:2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:4
1:8
1:16
1:32
1:64
1:128
1:256
Bit 3(CNT1S) : COUNTER1 clock source
0/1 Î 16.384kHz/system clock
Bit 4 ~ Bit 6 (C2_PSC0 ~ C2_PSC2) : COUNTER2 prescaler ratio
C2_PSC2
C2_PSC1
C2_PSC0
COUNTER2
1:2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:4
1:8
1:16
1:32
1:64
1:128
1:256
Bit 7(CNT2S) : COUNTER2 clock source
0/1 Î 16.384kHz/system clock
IOCE (Interrupt mask,)
PAGE0 (Interrupt mask)
7
6
5
4
3
2
1
0
-
PWM2
RBF
ADI
PWM1
R/W-0
-
-
-
R/W-0
R/W-0
R/W-0
Bit 0 ~ Bit 3 : unused
Bit 4(PWM1) : PWM1 one period reach interrupt mask.
Bit 5 (ADI) : ADC conversion complete interrupt mask
0/1 Î disable/enable interrupt
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
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EM78569
8-bit Micro-controller
There are four registers for A/D converter. Use one bit of interrupt control register (IOCE PAGE0 Bit5) for
A/D conversion complete interrupt. The status and control register of A/D (IOCB PAGE1 and RE PAGE0
Bit5) responses the A/D conversion status or takes control on A/D. The A/D data register (RB PAGE1)
stores A/D conversion result.
ADI bit in IOCE PAGE0 register is end of A/D conversion complete interrupt enable/disable. It
enables/disables ADI flag in RE register when A/D conversion is complete. ADI flag indicates the end of an
A/D conversion. The A/D converter sets the interrupt flag, ADI in RE PAGE0 register when a conversion is
complete. The interrupt can be disabled by setting ADI bit in IOCE PAGE0 Bit5 to ‘0’.
The A/D converter has four analog input channels AD1~AD3 multiplexed into one sample and hold to A/D
module. Reference voltage can be driven from VREF pin or internal power. The A/D converter itself is of
an 8-bit successive approximation type and produces an 8-bit result in the RB PAGE1 data register. A
conversion is initiated by setting a control bit ADST in IOCB PAGE1 Bit0. Prior to conversion, the
appropriate channel must be selected by setting IN0~IN1 bits in RE register and allowed for enough time to
sample data. Every conversion data of A/D need 10-clock cycle time. The minimum conversion time
required is 20 us (50K sample rate). ADST Bit in IOCB PAGE1 Bit0 must be set to begin a conversion.
It will be automatically reset in hardware when conversion is complete. At the end of conversion, the
START bit is cleared and the A/D interrupt is activated if ADI in IOCE PAGE0 Bit5 = 1. ADI will be set
when conversion is complete. It can be reset in software.
If ADI = 0 in IOCE PAGE0 Bit5, when A/D start conversion by setting ADST(IOCB PAGE1 Bit0) = 1 then
A/D will continue conversion without stop and hardware won’t reset ADST bit. In this condition, ADI is
deactived. After ADI in IOCE PAGE0 bit5 is set, ADI in RE PAGE0 bit5 will activate again.
To minimum operating current , all biasing circuits in the A/D module that consume DC current are power
down when ADPWR bit in IOCB PAGE1 Bit2 register is a ’0’. When ADPWR bit is a ‘1’, A/D converter
module is operating.
User has to set PORT86, PORT87, PORT60, PORT61as AD converter input pin or bi-direction IO PORT.
1
2
3
4
5
6
7
8
9
10
START
SAMPLE
ADI(IOCE PAGE0 bit5 ) =1
ADI(RE PAGE0 bit 5)
Clear by software
DATA
Fig.15 A/D converter timing
Bit 6 (RBF) : SPI’s RBF interrupt mask
0/1 Î disable/enable interrupt
Bit 7(PWM2) : PWM2 one period reach interrupt mask.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
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EM78569
8-bit Micro-controller
IOCF (Interrupt mask)
(Interrupt mask register)
Bit7
INT3
Bit6
0
Bit5
INT2
Bit4
INT1
Bit3
INT0
Bit2
CNT2
R/W-0
Bit1
CNT1
R/W-0
Bit0
TCIF
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Bit 0 ~ 5 : interrupt enable bit
0 Î disable interrupt
1 Î enable interrupt
Bit 6 : (remain these values to “0”othwise it will generate unpredicted interrupts)
Bit 7 : interrupt enable bit
0 Î disable interrupt
1 Î enable interrupt
The status after interrupt and the interrupt sources list as the table below.
Interrupt signal
GREEN mode
NORMAL mode
RA(7,6)=(x,0)
no SLEP
RA(7,6)=(x,1)
no SLEP
TCC time out
IOCF bit0=1
And "ENI"
Interrupt
Interrupt
(jump to address 8 at
page0)
(jump to address 8 at
page0)
COUNTER1 time out Interrupt
Interrupt
IOCF bit1=1
And "ENI"
(jump to address 8 at
page0)
(jump to address 8 at
page0)
COUNTER2 time out Interrupt
Interrupt
IOCF bit2=2
And "ENI"
(jump to address 8 at
(jump to address 8 at
page0)
page0)
PORT7(0~3)
IOCF bit3 or bit4 or
bit5 =1
Interrupt
Interrupt
(jump to address 8 at
page0)
(jump to address 8 at
page0)
And "ENI"
RBF
Interrupt <ps>
(jump to address 8 at
page0)
Interrupt
IOCE bit6 = 1
And “ENI
ADI
(jump to address 8 at
page0)
No function
Interrupt
IOCE bit5 = 1
And “ENI
PWM1
(jump to address 8 at
page0)
Interrupt <ps>
(jump to address 8 at
page0)
Interrupt
IOCE bit4 = 1
And “ENI
PWM2
(jump to address 8 at
page0)
Interrupt <ps>
(jump to address 8 at
page0)
Interrupt
IOCE bit7 = 1
And “ENI
(jump to address 8 at
page0)
<Note> PORT70 's interrupt function is controlled by IOCF bit 3. It's falling edge or rising edge trigger
(controlled by CONT register bit7).
PORT7(1~3) 's wakeup functions are controlled by IOCF bit (4,5,7). They are falling edge trigger.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
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EM78569
8-bit Micro-controller
ADI interrupt source function is controlled by RE PAGE0 bit 5. It is rising edge trigger after ADC
sample complete.
<ps> It only happens when master and 16.386kHz mode is selected.
VII.4 I/O Port
The I/O registers are bi-directional tri-state I/O ports. The I/O ports can be defined as "input" or "output" pins by
the I/O control registers under program control. The I/O data registers and I/O control registers are both readable
and writable. The I/O interface circuit is shown in Fig.16.
PCRD
P
R
Q
Q
D
CLK
PCWR
C
L
P
R
PORT
Q
Q
D
IOD
CLK
PDWR
PDRD
C
L
0
1
M
U
X
Fig.16_1 The circuit of I/O port and I/O control register
VDD
VDD
VDD
pull
high
PIN
120
ohm
Fig.16_2 The input/output circuit of EM78569 input/output ports
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
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8-bit Micro-controller
VII.5 RESET
The RESET can be caused by
(1) Power on reset
(2) WDT timeout. (if enabled and in GREEN or NORMAL mode)
(3) /RESET pin pull low
Once the RESET occurs, the following functions are performed.
•The oscillator is running, or will be started.
•The Program Counter (R2) is set to all "0".
•When power on, the upper 3 bits of R3 and the upper 2 bits of R4 are cleared.
•The Watchdog timer and prescaler counter are cleared.
•The Watchdog timer is disabled.
•The CONT register is set to all "1"
•The other register (bit 7 ~ bit 0) default values are as follows.
Operation registers :
Address
R register
PAGE0
R register
PAGE1
R register
PAGE2
R register
PAGE3
IOC register
IOC register
PAGE1
PAGE0
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
00xxxxxx
xxxx0000
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
00011xx0
xxxxxxxx
xxxxxxxx
xxxxx000
00000000
00000000
xxxx0000
xxxxxxxx
xxxx0000
00000000
xxxxxxxx
11111111
xxxxxxxx
00000000
00000000
00000000
xxxxxxxx
00000000
00000000
xxxxxx00
00000000
00000000
xxxxxx00
00000000
111x0000
11111111
11111111
11111111
11111111
xxxxxxxx
11111111
11111111
xxxxxxxx
0000xxxx
00000000
00000000
00000000
00000000
00000000
x0xx0xx
0x000000
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
000000x0
00000000
00000000
xxxxxxxx
VII.6 Wake-up
The controller provided sleep mode for power saving :
SLEEP mode, RA(7) = 0 + "SLEP" instruction
The controller will turn off all the CPU and crystal. Other circuit with power control like key tone control or
PLL control (which has enable register), user has to turn it off by software.
Wake-up from SLEEP mode
(1) WDT time out
(2) External interrupt
(3) /RESET pull low
All these cases will reset controller , and run the program at address zero. The status just like the power on reset.
VII.7 Interrupt
RF is the interrupt status register which records the interrupt request in flag bit. IOCF is the interrupt mask
register. Global interrupt is enabled by ENI instruction and is disabled by DISI instruction. When one of the
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
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EM78569
8-bit Micro-controller
interrupts (when enabled) generated, will cause the next instruction to be fetched from address 008H. Once in the
interrupt service routine, the source of the interrupt can be determined by polling the flag bits in the RF register.
The interrupt flag bit must be cleared in software before leaving the interrupt service routine and enabling
interrupts to avoid recursive interrupts.
VII.8 Instruction Set
Instruction set has the following features:
(1) Every bit of any register can be set, cleared, or tested directly.
(2) The I/O register can be regarded as general register. That is, the same instruction can operates on I/O
register.
The symbol "R" represents a register designator which specifies which one of the 64 registers (including
operational registers and general purpose registers) is to be utilized by the instruction. Bits 6 and 7 in R4
determine the selected register bank. "b'' represents a bit field designator which selects the number of the bit,
located in the register "R'', affected by the operation. "k'' represents an 8 or 10-bit constant or literal value.
INSTRUCTION BINARY
STATUS
Instruction
HEX
0000
0001
0002
0003
0004
000r
0010
0011
0012
0013
MNEMONIC OPERATION
AFFECTED cycle
0
0
0
0
0
0
0
0
0
0
0000 0000 0000
0000 0000 0001
0000 0000 0010
0000 0000 0011
0000 0000 0100
0000 0000 rrrr
0000 0001 0000
0000 0001 0001
0000 0001 0010
0000 0001 0011
NOP
No Operation
None
C
1
1
1
1
1
1
1
1
2
2
DAA
CONTW
SLEP
WDTC
IOW R
ENI
Decimal Adjust A
A → CONT
None
T,P
0 → WDT, Stop oscillator
0 → WDT
T,P
A → IOCR
None
None
None
None
None
Enable Interrupt
Disable Interrupt
[Top of Stack] → PC
[Top of Stack] → PC
Enable Interrupt
CONT → A
DISI
RET
RETI
0
0
0
0000 0001 0100
0000 0001 rrrr
0000 0010 0000
0014
001r
0020
CONTR
IOR R
TBL
None
None
1
1
2
IOCR → A
R2+A → R2 bits 9,10 do not Z,C,DC
clear
0
0000 0011 0000
0030
INT A
(MR)(+/-)(s/us X)*(s/us
Y)ÆMR
None
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0000 01rr rrrr
0000 1000 0000
0000 11rr rrrr
0001 00rr rrrr
0001 01rr rrrr
0001 10rr rrrr
0001 11rr rrrr
0010 00rr rrrr
0010 01rr rrrr
0010 10rr rrrr
0010 11rr rrrr
0011 00rr rrrr
0011 01rr rrrr
00rr
0080
00rr
01rr
01rr
01rr
01rr
02rr
02rr
02rr
02rr
03rr
03rr
MOV R,A
CLRA
A → R
None
1
1
1
1
1
1
1
1
1
1
1
1
1
0 → A
Z
CLR R
0 → R
Z
SUB A,R
SUB R,A
DECA R
DEC R
R-A → A
Z,C,DC
R-A → R
Z,C,DC
R-1 → A
Z
Z
Z
Z
Z
Z
Z
Z
R-1 → R
OR A,R
OR R,A
AND A,R
AND R,A
XOR A,R
XOR R,A
A ∨ R → A
A ∨ R → R
A & R → A
A & R → R
A ⊕ R → A
A ⊕ R → R
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
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EM78569
8-bit Micro-controller
0
0
0
0
0
0
0
0
0
0
0
0011 10rr rrrr
0011 11rr rrrr
0100 00rr rrrr
0100 01rr rrrr
0100 10rr rrrr
0100 11rr rrrr
0101 00rr rrrr
0101 01rr rrrr
0101 10rr rrrr
0101 11rr rrrr
0110 00rr rrrr
03rr
03rr
04rr
04rr
04rr
04rr
05rr
05rr
05rr
05rr
06rr
ADD A,R
ADD R,A
MOV A,R
MOV R,R
COMA R
COM R
A + R → A
Z,C,DC
1
A + R → R
Z,C,DC
1
R → A
Z
1
R → R
Z
1
/R → A
Z
1
/R → R
Z
1
INCA R
INC R
R+1 → A
Z
1
R+1 → R
Z
1
DJZA R
DJZ R
R-1 → A, skip if zero
R-1 → R, skip if zero
R(n) → A(n-1)
R(0) → C, C → A(7)
R(n) → R(n-1)
R(0) → C, C → R(7)
R(n) → A(n+1)
R(7) → C, C → A(0)
R(n) → R(n+1)
R(7) → C, C → R(0)
R(0-3) → A(4-7)
R(4-7) → A(0-3)
R(0-3) ↔ R(4-7)
R+1 → A, skip if zero
R+1 → R, skip if zero
0 → R(b)
None
None
C
2 if skip
2 if skip
1
RRCA R
0
0
0
0
0110 01rr rrrr
0110 10rr rrrr
0110 11rr rrrr
0111 00rr rrrr
06rr
06rr
06rr
07rr
RRC R
C
1
1
1
1
RLCA R
RLC R
C
C
SWAPA R
None
0
0
0
0
0
0
0
1
0111 01rr rrrr
0111 10rr rrrr
0111 11rr rrrr
100b bbrr rrrr
101b bbrr rrrr
110b bbrr rrrr
111b bbrr rrrr
00kk kkkk kkkk
07rr
SWAP R
JZA R
None
None
None
None
None
None
None
None
1
07rr
2 if skip
07rr
JZ R
2 if skip
0xxx
0xxx
0xxx
0xxx
1kkk
BC R,b
BS R,b
JBC R,b
JBS R,b
CALL k
1
1 → R(b)
1
if R(b)=0, skip
if R(b)=1, skip
PC+1 → [SP]
(Page, k) → PC
(Page, k) → PC
k → A
2 if skip
2 if skip
2
1
1
1
1
1
1
1
1
01kk kkkk kkkk
1000 kkkk kkkk
1001 kkkk kkkk
1010 kkkk kkkk
1011 kkkk kkkk
1100 kkkk kkkk
1101 kkkk kkkk
1110 0000 0001
1kkk
18kk
19kk
1Akk
1Bkk
1Ckk
1Dkk
1E01
JMP k
None
None
Z
2
1
1
1
1
2
1
1
MOV A,k
OR A,k
AND A,k
XOR A,k
RETL k
SUB A,k
INT
A ∨ k → A
A & k → A
Z
A ⊕ k → A
Z
k → A, [Top of Stack] → PC None
k-A → A
Z,C,DC
PC+1 → [SP]
001H → PC
K->R5(4:0)
k+A → A
None
1
1
1110 100k kkkk
1111 kkkk kkkk
1E8k
1Fkk
PAGE
k
None
1
1
ADD A,k
Z,C,DC
** About execute instruction ADD and SUB, please reference to RA page2 bit 7
** Instruction cycle = 2 main CLK
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* This specification is subject to be changed without notice.
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8/31/2004 (V4.0)
EM78569
8-bit Micro-controller
VII.9 Code Option
CODE Option Register
13 12
11
10
9
1
8
7
-
6
5
4
3
2
1
0
PHO VERSEL
MER
Bit 3(MER) : Memory error recover function
0 Î disable memory error recover function
1 Î enable memory error recovery function
If user enable memory error recovery function, MCU will improve effect from environment noise.
Bit 9: This bit must set to 1.
Bit 10(VERSEL) : Version select.
VERSEL = 0
R8 page1
VERSEL = 1
RB page2
Enable
Data RAM address
Data ram address auto-
increase
Not support
“ADD” & “SUB”
include “carry“ bit
Phase CLK output
Not support
Determined by RA page2 bit7
Determined by PHO
Determined by PHO
Bit 11(PHO) : PORTCO status select.
0 Î PORTC0 defined to normal IO.
1 Î PORTC0 defined to phase1 output, next figure show the relative of main CLK and Phase1 CLK.
M ainCLK
PH1output
InstructionCycle
The relative between main CLK and PH1 output
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* This specification is subject to be changed without notice.
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8/31/2004 (V4.0)
EM78569
8-bit Micro-controller
VII.10 Dual sets of PWM (Pulse Width Modulation)
(1) Overview
In PWM mode, both PWM1 and PWM2 pins produce up to a 10-bit resolution PWM output (see. Fig.17
for the functional block diagram). A PWM output has a period and a duty cycle, and it keeps the output in
high. The baud rate of the PWM is the inverse of the period. Fig.18 depicts the relationships between a
period and a duty cycle.
latch
To PWM1IF
DL1H + DL1L
DT1H
+
Fosc
DT1L
Duty Cycle
Match
1:2
1:8
1:32
1:64
Comparator
PWM1
MUX
R
S
Q
TMR1H + TMR1L
reset
IOC6
Comparator
T1P0 T1P1 T1EN
Period
Match
PRD1
Data Bus
Data Bus
latch
To PWM2IF
DL2H + DL2L
DT2H
+
DT2L
Duty Cycle
Match
T2P0 T2P1 T2EN
Comparator
PWM2
Fosc
R
S
Q
TMR2H + TMR2L
1:2
1:8
1:32
1:64
reset
MUX
IOC6
Comparator
Period
Match
PRD2
Fig.17 The Functional Block Diagram of the Dual PWMs
Period
Duty Cycle
PRD1 = TMR1
DT1 = TMR1
Fig.18 The Output Timing of the PWM
(2) Increment Timer Counter ( TMRX: TMR1H/TWR1L or TMR2H/TWR2L )
TMRX are ten-bit clock counters with programmable prescalers. They are designed for the PWM module
as baud rate clock generators. TMRX can be read, written, and cleared at any reset conditions. If
employed, they can be turned down for power saving by setting T1EN bit [PWMCON<4>] or T2EN bit
[PWMCON<5>] to 0.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
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8/31/2004 (V4.0)
EM78569
8-bit Micro-controller
(3) PWM Period ( PRDX : PRD1 or PRD2 )
The PWM period is defined by writing to the PRDX register. When TMRX is equal to PRDX, the
following events occur on the next increment cycle:
• TMRX is cleared.
• The PWMX pin is set to 1.
• The PWM duty cycle is latched from DT1/DT2 to DTL1/DTL2.
< Note > The PWM output will not be set, if the duty cycle is 0;
• The PWMXIF pin is set to 1.
The following formula describes how to calculate the PWM period:
PERIOD = (PRDX + 1) * 4 * (1/Fosc) * (TMRX prescale value )
Where Fosc is system clock
(4) PWM Duty Cycle ( DTX: DT1H/ DT1L and DT2H/ DT2L; DTL: DL1H/DL1L and DL2H/DL2L )
The PWM duty cycle is defined by writing to the DTX register, and is latched from DTX to DLX while
TMRX is cleared. When DLX is equal to TMRX, the PWMX pin is cleared. DTX can be loaded at any
time. However, it cannot be latched into DTL until the current value of DLX is equal to TMRX.
The following formula describes how to calculate the PWM duty cycle:
Duty Cycle = (DTX) * (1/Fosc) * (TMRX prescale value )
(5) PWM Programming Procedures/Steps
Load PRDX with the PWM period.
(1) Load DTX with the PWM Duty Cycle.
(2) Enable interrupt function by writing IOCF PAFE0, if required.
(3) Set PWMX pin to be output by writing a desired value to IOCC PAGE0.
(4) Load a desired value to R5 PAGE3 with TMRX prescaler value and enable both PWMX and TMRX.
(6) Timer
Timer1 (TMR1) and Timer2 (TMR2) (TMRX) are 10-bit clock counters with programmable prescalers,
respectively. They are designed for the PWM module as baud rate clock generators. TMRX can be read,
written, and cleared at any reset conditions.
The figure in the next page shows TMRX block diagram. Each signal and block are described as follows:
Fosc
1:2
To PWM1IF
1:8
1:32
1:64
MUX
reset
Period
TMR1X
Match
Comparator
T1P0 T1P1
T1EN
PRD1
PRD2
Data Bus
Data Bus
T2P0 T2P1 T2EN
Comparator
reset
Period
Match
Fosc
1:2
TMR2X
1:8
1:32
1:64
MUX
To PWM2IF
*TMR1X = TMR1H + TMR1L;
*TMR2X = TMR2H +TMR2L
Fig.19 TMRX Block Diagram
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* This specification is subject to be changed without notice.
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8/31/2004 (V4.0)
EM78569
8-bit Micro-controller
• Fosc: Input clock.
• Prescaler ( T1P0 and T1P1/T2P1 and T2P0 ): Options of 1:2, 1:8, 1:32, and 1:64 are defined by TMRX. It is
cleared when any type of reset occurs.
• TMR1X and TMR2X (TMR1H/TWR1L and TMR2H/TMR2L ):Timer X register; TMRX is increased until
it matches with PRDX, and then is reset to 0. TMRX cannot be read.
• PRDX ( PRD1 and PRD2 ): PWM period register.
When defining TMRX, refer to the related registers of its operation as shown in prescale register. It must be
noted that the PWMX bits must be disabled if their related TMRXs are employed. That is, bit 7 and bit 6 of
the PWMCON register must be set to ‘0’.
Related Control Registers(R5 PAGE3) of TMR1 and TMR2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3 Bit 2
Bit 1 Bit 0
T1P1 T1P0
PWM2E PWM1E T2EN T1EN T2P1 T2P0
Timer programming procedures/steps
(1) Load PRDX with the TIMER period.
(2) Enable interrupt function by writing IOCF PAGE0, if required
(3) Load a desired value to PWMCON with the TMRX prescaler value and enable both TMRX and disable
PWMX.
VIII. Absolute Operation Maximum Ratings
RATING
SYMBOL
VDD
Vin
VALUE
-0.3 To 6
UNIT
DC SUPPLY VOLTAGE
INPUT VOLTAGE
V
V
-0.5 to VDD +0.5
0 to 70
℃
OPERATING TEMPERATURE RANGE
Ta
IX. DC Electrical Characteristic
(Ta = 25°C, VDD=5V±5%, VSS=0V)
Parameter
Symbol Condition
Min Typ Max
Unit
Input leakage current for
input pins
IIL1
VIN = VDD, VSS
±1
µA
Input leakage current for bi-
directional pins
IIL2
VIN = VDD, VSS
±1
µA
Input high voltage
Input low voltage
Input high threshold voltage
Input low threshold voltage
Clock input high voltage
Clock input low voltage
Output high voltage for
PORT5,B,C,
VIH
VIL
2.5
0.8
2.0
0.8
3.5
1.5
2.4
V
V
V
V
V
V
V
VIHT /RESET, TCC
VILT /RESET, TCC
VIHX OSCI
VILX OSCI
VOH1 IOH = -6mA
Output high voltage for
PORT6,7,8
Output high voltage for
PORT9
Output low voltage for
PORT5,B,C
Output low voltage for
PORT6,7,8
Output low voltage for
PORT9
LCD drive reference voltage
Pull-high current
VOH2 IOH = -12mA
VOH3 IOH = -15mA
VOL1 IOH = 6mA
2.4
2.4
0.4
0.4
0.4
V
V
V
V
V
VOL2 IOH = 12mA
VOL3 IOH = 15mA
VLCD VDD=5V, Contrast adjust
4 ~ 5
-10 -15
V
µA
IPH
Pull-high active input pin at
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
46
8/31/2004 (V4.0)
EM78569
8-bit Micro-controller
VSS
Power down current
(SLEEP mode)
ISB1
ISB2
ICC1
All input and I/O pin at VDD,
output pin floating, WDT
disabled
CLK=32.768KHz, All analog
circuits disabled, All input
and I/O pin at VDD, output
/RESET=High,
CLK=3.582MHz, All analog
circuits disabled, output pin
floating
4
35
1
8
50
2
µA
µA
mA
Low clock current
(GREEN mode)
Operating supply current
(Normal mode)
Operation current for DAC
I_DA
0.65 0.9
mA
XI. AC Electrical Characteristic
CPU instruction timing (Ta = 25°C, VDD=5V, VSS=0V)
Parameter
Symbol Condition
Dclk
Min
45
Typ
50
Max
55
Unit
Input CLK duty cycle
Instruction cycle time
%
us
Tins
32.768kHz
3.582MHz
60
550
16
ns
Device delay hold time
TCC input period
Tdrh
Ttcc
Twdt
Tda
ms
ns
Note 1
(Tins+20)/N
Watchdog timer period
DAC output delay
Ta = 25°C
16
50
ms
uS
Note 1: N= selected prescaler ratio.
ADC characteristic (VDD = 5V, Ta = +25°C, for internal reference voltage)
Parameter
Symbol
Vofh
Condition
Min
Typ
44
Max
52.8
38.4
Unit
mV
mV
Upper bound offset voltage
Lower bound offset voltage
Vofl
32
*These parameters are characterized but not tested.
* About ADC characteristic, please refer to next page.
Timing characteristic (AVDD=VDD=5V,Ta=+25°C)
Symbol
Description
Min Typ Max Unit
Oscillator timing characteristic
OSC start up
32.768kHz
Toscs
400
1500 ms
10 us
3.579MHz PLL
5
SPI timing characteristic (CPU clock 3.58MHz and Fsco = 3.58Mhz /2)
/SS set-up time
/SS hold time
SCLK high time
SCLK low time
SCLK rising time
SCLK falling time
SDI set-up time to the reading edge of SCLK
SDI hold time to the reading edge of SCLK
SDO disable time
Tcss
Tcsh
Thi
Tlo
Tr
560
250
250
250
ns
ns
ns
ns
ns
ns
ns
15
15
30
30
Tf
Tisu
Tihd
Tdis
25
25
560 ns
Timing characteristic of reset
The minimum width of reset low pulse
The delay between reset and program start
Trst
Tdrs
3
uS
mS
18
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* This specification is subject to be changed without notice.
47
8/31/2004 (V4.0)
EM78569
8-bit Micro-controller
Embedded LCD driver
Symbol
Ron
Parameter
LCD driver ON resistance
LCD frame frequency
Condition
LCD function enable
1/2 , 1/4 duty
Min Typ Max Unit
2
4
kΩ
Frame
64
Hz
VDD
OSC
Toscs
Power
onreset
Trst
/RESET
Tdrs
Tdrs
Program
Active
The relative between OSC stable time and power on reset.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
48
8/31/2004 (V4.0)
EM78569
8-bit Micro-controller
EM78569 operation voltage(X axis Æ min VDD ; Y axis Æ main CLK):
M Hz
17.91
14.33
10.74
7.16
3.58
1.79
V
2.2 2.5
3.0
3.6
4
5.5
Fig.19 The relative between operating voltage and main CLK
EM78569 10 bit ADC characteristic
EM78569 build in 10 bit resolution, multi channel ADC function. In ideal, if ADC’s reference voltage is 5V, the
ADC’s LSB will be 5V/1024. But in practical, for some physics or circuit’s character, some un-ideal will effect the converter
result. As the next figure, offset voltage will reduce AD’s converter range. If AD’s input voltage less than VOFL, ADC will
output 0; in opposition, if input voltage is larger than (VDD-VOFH), ADC will output 1023. That is to say the physics AD
converter range will replace by (VDD-VOFH+LSB-VOFL+LSB). If we defined that VRB = VOFL – LSB and VRT = VDD-
VOFH+LSB, the physics LSB is:
LSB = (VRT - VRB) / 1024
= (VDD – (VOFH+VOFL) ) / 1022
For real operating, please think about the effect of AD’s offset voltage. If converter the range of (VRT - VRB), the AD
converter’s opposite result will be précised.
10-bit ADC
VDD
VRT
VOFH
Min. input for ADC output = 1023
(For 10-bit ADC, internally it takes this range to
average 1024 steps)
Min. input for ADC output = 1
VOFL
VRB
0V
Fig.20 The relative between ADC and offset voltage
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
49
8/31/2004 (V4.0)
EM78569
8-bit Micro-controller
XII. Timing Diagrams
ins
Fig.21 AC timing
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
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8/31/2004 (V4.0)
EM78569
8-bit Micro-controller
Appendix: Notice about EM78569 developing tool. (ICE569)
In mask EM78569, user can switch some function by set code option. But code option is un-exist on ICE569.
For ICE569, these 2 bits are mapping to RD page0 bit5~bit6. During developing program on ICE569, please fix these 2
bit on initial and do not change them among program.
RD page0
7
-
6
5
4
1
3
-
2
1
0
VERSEL
PHO
R/W-0
R/W-0
R/W-0
About the describe of bit5~bit6, please refer to EM78569’s code option.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
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8/31/2004 (V4.0)
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